README.md

Selected circuits

• Circuit: 16-bit unsigned multipliers
• Selection criteria: pareto optimal sub-set wrt. WCED [%] and # LUTs parameters

Parameters of selected circuits

Circuit name	MAE%	WCE%	EP%	MRE%	MSE	PowerW	Delayns	LUTs	Download
mul16u_HFD	0.00	0.00	0.00	0.00	0	3.4	15	292	[Verilog] [VerilogPDK45] [C]
mul16u_3UT	0.000073	0.00042	99.85	0.0064	15325.312e3	5.1	16	274	[Verilog] [VerilogPDK45] [C]
mul16u_FD6	0.00045	0.0026	99.98	0.034	59461.42e4	4.4	15	239	[Verilog] [VerilogPDK45] [C]
mul16u_5KN	0.0018	0.01	99.99	0.11	94085.355e5	3.2	15	195	[Verilog] [VerilogPDK45] [C]
mul16u_89C	0.004	0.023	99.99	0.20	44931.821e6	2.5	14	154	[Verilog] [VerilogPDK45] [C]
mul16u_6NY	0.048	0.20	100.00	1.34	61508.569e8	1.5	13	89	[Verilog] [VerilogPDK45] [C]
mul16u_H6P	0.16	0.63	100.00	3.06	55158.891e9	1.1	12	66	[Verilog] [VerilogPDK45] [C]
mul16u_G8D	0.88	3.51	100.00	11.81	17642.903e11	0.56	10	26	[Verilog] [VerilogPDK45] [C]
mul16u_HEN	3.03	12.11	100.00	26.79	23887.935e12	0.36	8.0	15	[Verilog] [VerilogPDK45] [C]
mul16u_G9P	15.62	62.50	100.00	79.49	71651.74e13	0.25	6.5	1.0	[Verilog] [VerilogPDK45] [C]

Parameters

References

PRABAKARAN B. S., MRAZEK V., VASICEK Z., SEKANINA L., SHAFIQUE M. ApproxFPGAs: Embracing ASIC-based Approximate Arithmetic Components for FPGA-Based Systems. DAC 2020.