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Selected circuits

Circuit: 8-bit unsigned multipliers
Selection criteria: pareto optimal sub-set wrt. MED [%] and # LUTs parameters

Parameters of selected circuits

Circuit name	MAE_%	WCE_%	EP_%	MRE_%	MSE	Power_W	Delay_ns	LUTs	Download
mul8u_1JD3	0.00	0.00	0.00	0.00	0	1.3	12	74	[Verilog] [Verilog_PDK45] [C]
mul8u_589	0.0085	0.049	64.97	0.25	65	1.2	12	72	[Verilog] [Verilog_PDK45] [C]
mul8u_5E8	0.018	0.066	84.96	0.62	233	1.2	11	65	[Verilog] [Verilog_PDK45] [C]
mul8u_6LH	0.051	0.25	84.76	1.28	2005	1.0	11	63	[Verilog] [Verilog_PDK45] [C]
mul8u_GT4	0.16	0.73	96.25	3.68	17466	0.85	9.7	48	[Verilog] [Verilog_PDK45] [C]
mul8u_176X	0.47	2.06	98.93	9.37	145132	0.64	10	34	[Verilog] [Verilog_PDK45] [C]
mul8u_7T1	1.17	5.18	99.17	18.02	903134	0.42	8.4	16	[Verilog] [Verilog_PDK45] [C]
mul8u_19SM	3.39	13.56	99.21	36.51	79737.894e2	0.31	6.4	5.0	[Verilog] [Verilog_PDK45] [C]
mul8u_17A6	7.51	25.01	99.22	59.60	38114.505e3	0.26	6.2	1.0	[Verilog] [Verilog_PDK45] [C]
mul8u_199Z	24.81	99.22	99.22	100.00	47164.981e4	0.24	0	0	[Verilog] [Verilog_PDK45] [C]

Parameters

References

PRABAKARAN B. S., MRAZEK V., VASICEK Z., SEKANINA L., SHAFIQUE M. ApproxFPGAs: Embracing ASIC-based Approximate Arithmetic Components for FPGA-Based Systems. DAC 2020.