Fixed synthesis reporting for Single- and Multi-FPGA

Author: bwintermann

src/finn/builder/build_dataflow_config.py

@@ -451,7 +451,7 @@ def _fix_path(p: Path | None) -> Path | None:
 
     #: Which output(s) to generate from the build flow.  See documentation of
     #: DataflowOutputType for available options.
-    generate_outputs: Optional[list[DataflowOutputType]] = field(
+    generate_outputs: list[DataflowOutputType] = field(
         default_factory=lambda: [
             DataflowOutputType.STITCHED_IP,
             DataflowOutputType.ESTIMATE_REPORTS,

src/finn/builder/build_dataflow_steps.py

@@ -141,7 +141,12 @@
 from finn.transformation.streamline import Streamline
 from finn.transformation.streamline.reorder import MakeMaxPoolNHWC
 from finn.transformation.streamline.round_thresholds import RoundAndClipThresholds
-from finn.util.basic import get_liveness_threshold_cycles, get_rtlsim_trace_depth
+from finn.util.basic import (
+    get_liveness_threshold_cycles,
+    get_metadata_prop_path,
+    get_metadata_prop_safe,
+    get_rtlsim_trace_depth,
+)
 from finn.util.config import extract_model_config_consolidate_shuffles, extract_model_config_to_json
 from finn.util.exception import FINNMultiFPGAUserError, FINNUserError
 from finn.util.execution import execute_parent
@@ -1604,59 +1609,94 @@ def step_vivado_power_estimation(model: ModelWrapper, cfg: DataflowBuildConfig):
 def step_synthesize_bitfile(model: ModelWrapper, cfg: DataflowBuildConfig):
     """Synthesize a bitfile for the using the specified shell flow, using either
     Vivado or Vitis, to target the specified board."""
+    if DataflowOutputType.BITFILE not in cfg.generate_outputs:
+        log.warning(
+            "DataflowOutputType.BITFILE not in requested outputs, skipping step_synthesize_bitfile."
+        )
+        return model
 
-    if DataflowOutputType.BITFILE in cfg.generate_outputs:
-        bitfile_dir = cfg.output_dir + "/bitfile"
-        os.makedirs(bitfile_dir, exist_ok=True)
-        report_dir = cfg.output_dir + "/report"
-        os.makedirs(report_dir, exist_ok=True)
-        partition_model_dir = cfg.output_dir + "/intermediate_models/kernel_partitions"
-        if cfg.shell_flow_type == ShellFlowType.VIVADO_ZYNQ:
-            model = model.transform(
-                ZynqBuild(
-                    cfg.board,
-                    cfg.synth_clk_period_ns,
-                    cfg.enable_hw_debug,
-                    cfg.enable_instrumentation,
-                    cfg.instrumentation_no_dma,
-                    cfg.live_fifo_sizing,
-                    partition_model_dir=partition_model_dir,
-                )
-            )
-
-            bitfile_path = os.path.join(bitfile_dir, "finn-accel.bit")
-            copy(model.get_metadata_prop("bitfile"), bitfile_path)
-            copy(model.get_metadata_prop("hw_handoff"), bitfile_dir + "/finn-accel.hwh")
-            copy(
-                model.get_metadata_prop("vivado_synth_rpt"),
-                report_dir + "/post_synth_resources.xml",
-            )
-
-            model.set_metadata_prop("bitfile_output", os.path.abspath(bitfile_path))
-
-            post_synth_resources = model.analysis(post_synth_res)
-            with open(report_dir + "/post_synth_resources.json", "w") as f:
-                json.dump(post_synth_resources, f, indent=2)
+    # Create some directories for later
+    bitfile_dir = Path(cfg.output_dir) / "bitfile"
+    bitfile_dir.mkdir(exist_ok=True)
+    report_dir = Path(cfg.output_dir) / "report"
+    report_dir.mkdir(exist_ok=True)
+    partition_model_dir = Path(cfg.output_dir) / "intermediate_models/kernel_partitions"
 
-            vivado_pynq_proj_dir = model.get_metadata_prop("vivado_pynq_proj")
-            timing_rpt = (
-                "%s/finn_zynq_link.runs/impl_1/top_wrapper_timing_summary_routed.rpt"
-                % vivado_pynq_proj_dir
+    # The actual synthesis step!
+    if cfg.shell_flow_type == ShellFlowType.VIVADO_ZYNQ:
+        model = model.transform(
+            ZynqBuild(
+                cfg.board,
+                cfg.synth_clk_period_ns,
+                cfg.enable_hw_debug,
+                cfg.enable_instrumentation,
+                cfg.instrumentation_no_dma,
+                cfg.live_fifo_sizing,
+                partition_model_dir=partition_model_dir,
             )
-            copy(timing_rpt, report_dir + "/post_route_timing.rpt")
-
-        elif cfg.shell_flow_type == ShellFlowType.VITIS_ALVEO:
-            # TODO: Rework missing parts here
-            model = model.transform(VitisBuild(cfg))
-
+        )
+    elif cfg.shell_flow_type == ShellFlowType.VITIS_ALVEO:
+        model = model.transform(VitisBuild(cfg))
+    else:
+        raise Exception("Unrecognized shell_flow_type: " + str(cfg.shell_flow_type))
+
+    # Store bitstreams into the output directory. This is the same regardless of flow.
+    bitfile_json = json.loads(get_metadata_prop_safe(model, "bitfile"))
+    suffix = ""
+    if cfg.shell_flow_type == ShellFlowType.VIVADO_ZYNQ:
+        suffix = ".bit"
+    elif cfg.shell_flow_type == ShellFlowType.VITIS_ALVEO:
+        suffix = ".xclbin"
+
+    # If only one device, omit the device suffix
+    if len(list(bitfile_json.keys())) == 1:
+        bitfile_path = bitfile_dir / f"finn-accel{suffix}"
+        copy(bitfile_json[0], bitfile_path)
+        # For the single-fpga case, store in bitfile_output
+        # TODO: Also adapt this for Multi-FGPA
+        model.set_metadata_prop("bitfile_output", str(bitfile_path.absolute()))
+    else:
+        for device, path in bitfile_json.items():
+            copy(path, bitfile_dir / f"finn-accel-{device}{suffix}")
+
+    # Store synth reports
+    rpt_json = json.loads(get_metadata_prop_safe(model, "vivado_synth_rpt"))
+    if len(list(rpt_json.keys())) == 1:
+        res_report = Path(rpt_json[0])
+        if res_report.exists():
+            copy(res_report, report_dir / "post_synth_resources.xml")
         else:
-            raise Exception("Unrecognized shell_flow_type: " + str(cfg.shell_flow_type))
-        log.info(f"Bitfile written into {bitfile_dir}")
-
+            log.warning(f"Resource report XML not found: {res_report}")
     else:
-        log.info(
-            "DataflowOutputType.BITFILE not in requested outputs, skipping step_synthesize_bitfile."
+        for device, path in rpt_json.items():
+            if path.exists():
+                copy(path, report_dir / f"post_synth_resources_{device}.xml")
+            else:
+                log.warning(f"Resource report XML not found: {path}")
+
+    # Store artifacts, depending on flow
+    if cfg.shell_flow_type == ShellFlowType.VIVADO_ZYNQ:
+        # Store synthesis artifacts
+        hw_handoff = get_metadata_prop_path(model, "hw_handoff", must_exist=True)
+        copy(hw_handoff, bitfile_dir / "finn-accel.hwh")
+
+        # Log post synthesis resource as a JSON file
+        post_synth_resources = model.analysis(post_synth_res)
+        (report_dir / "post_synth_resources.json").write_text(
+            json.dumps(post_synth_resources, indent=2)
+        )
+
+        # Store the post-route timing report
+        timing_report = (
+            get_metadata_prop_path(model, "vivado_pynq_proj", must_exist=True)
+            / "finn_zynq_link.runs"
+            / "impl_1"
+            / "top_wrapper_timing_summary_routed.rpt"
         )
+        copy(timing_report, report_dir / "post_route_timing.rpt")
+
+    elif cfg.shell_flow_type == ShellFlowType.VITIS_ALVEO:
+        pass
 
     return model
 

src/finn/templates/vitis_link/vitis_gen_report_xml.tcl.jinja

@@ -0,0 +1,3 @@
+open_project {{ VITIS_PROJ_PATH }}/_x/link/vivado/vpl/prj/prj.xpr
+open_run impl_1
+report_utilization -hierarchical -hierarchical_depth 5 -file {{ VITIS_PROJ_PATH }}/synth_report.xml -format xml

src/finn/transformation/fpgadataflow/make_zynq_proj.py

@@ -588,8 +588,10 @@ def apply(self, model):
             )
         deploy_bitfile_name = vivado_pynq_proj_dir + "/resizer.bit"
         copy(bitfile_name, deploy_bitfile_name)
-        # set bitfile attribute
-        model.set_metadata_prop("bitfile", deploy_bitfile_name)
+
+        # set bitfile attribute (device - path mapping to be in sync with the alveo flow,
+        # which needs to support multiple bitstream output files due to Multi-FPGA
+        model.set_metadata_prop("bitfile", json.dumps({0: deploy_bitfile_name}))
         hwh_name_alts = [
             vivado_pynq_proj_dir + "/finn_zynq_link.srcs/sources_1/bd/top/hw_handoff/top.hwh",
             vivado_pynq_proj_dir + "/finn_zynq_link.gen/sources_1/bd/top/hw_handoff/top.hwh",
@@ -608,7 +610,8 @@ def apply(self, model):
         model.set_metadata_prop("hw_handoff", deploy_hwh_name)
         # filename for the synth utilization report
         synth_report_filename = vivado_pynq_proj_dir + "/synth_report.xml"
-        model.set_metadata_prop("vivado_synth_rpt", synth_report_filename)
+        # Stored as a json for Multi-FPGA support (on the alveo side)
+        model.set_metadata_prop("vivado_synth_rpt", json.dumps({0: synth_report_filename}))
         return (model, False)
 
 

src/finn/transformation/fpgadataflow/multifpga/aurora/metadata.py

@@ -11,6 +11,7 @@
 from typing import TYPE_CHECKING, cast
 
 from finn.transformation.fpgadataflow.multifpga.metadata import DataDirection, NetworkMetadata
+from finn.util.basic import get_metadata_prop_path
 from finn.util.exception import FINNInternalError, FINNMultiFPGAConfigError
 
 if TYPE_CHECKING:
@@ -60,15 +61,15 @@ class AuroraNetworkMetadata(NetworkMetadata, DataClassYAMLMixin):
     @staticmethod
     def from_model(model: ModelWrapper) -> AuroraNetworkMetadata:
         """Load metadata from the model."""
-        p = model.get_metadata_prop("network_metadata")
-        if p is None:
-            raise FINNInternalError(
+        p = get_metadata_prop_path(
+            model,
+            "network_metadata",
+            must_exist=True,
+            custom_error=(
                 "Cannot load metadata from model, since no 'network_metadata' prop was set. "
                 "Did you forget to run the 'AssignMetadata' transformation before this?"
-            )
-        p = Path(p)
-        if not p.exists():
-            raise FINNInternalError(f"Cannot load metadata. File not found: {p}.")
+            ),
+        )
         meta = AuroraNetworkMetadata.load(p)
         meta.loaded_from_path = p
         return meta

src/finn/transformation/fpgadataflow/multifpga/create_multi_sdp.py

@@ -10,12 +10,8 @@
 
 from finn.builder.build_dataflow_config import MFVerbosity
 from finn.transformation.fpgadataflow.create_dataflow_partition import CreateDataflowPartition
-from finn.transformation.fpgadataflow.multifpga.utils import (
-    get_device_id,
-    get_submodel,
-    set_device_id,
-)
 from finn.util.exception import FINNMultiFPGAUserError
+from finn.util.fpgadataflow import get_device_id, get_submodel, set_device_id
 from finn.util.logging import log
 
 if TYPE_CHECKING:
@@ -127,7 +123,7 @@ def apply(self, model: ModelWrapper) -> tuple[ModelWrapper, bool]:  # noqa
 
         # Set the SDP's device_id
         for node in model.graph.node:
-            device_id = get_device_id(get_submodel(node).graph.node[0])
+            device_id = get_device_id(get_submodel(node)[0].graph.node[0])
             assert device_id is not None
             set_device_id(node, device_id)
         return model, False

src/finn/transformation/fpgadataflow/multifpga/metadata.py

@@ -10,9 +10,9 @@
 from typing import TYPE_CHECKING, Any
 
 from finn.builder.build_dataflow_config import MFVerbosity
-from finn.transformation.fpgadataflow.multifpga.utils import get_device_id
 from finn.util.basic import make_build_dir
 from finn.util.exception import FINNMultiFPGAError
+from finn.util.fpgadataflow import get_device_id
 from finn.util.logging import log
 
 if TYPE_CHECKING:

src/finn/transformation/fpgadataflow/multifpga/partition_model.py

@@ -22,7 +22,6 @@
     is_single_in_out_model,
 )
 from finn.transformation.fpgadataflow.multifpga.partitioner import Partitioner
-from finn.transformation.fpgadataflow.multifpga.utils import set_device_id
 from finn.util.basic import make_build_dir
 from finn.util.exception import (
     FINNInternalError,
@@ -31,6 +30,7 @@
     FINNMultiFPGANoPartitionerSolutionError,
     FINNMultiFPGAUserError,
 )
+from finn.util.fpgadataflow import set_device_id
 from finn.util.logging import LogDisabledConsole, log
 from finn.util.platforms import platforms
 from finn.util.resources import available_resources, get_estimated_model_resources

src/finn/transformation/fpgadataflow/vitis_build.py

@@ -78,6 +78,17 @@ def link(self, config: VitisLinkConfiguration) -> Path:
                 f"at {config.run_script_path.parent}.",
                 config.run_script_path.parent / "v++_a.log",
             )
+
+        # Try to generate resource reports, but don't raise an exception if this fails
+        gen_result = subprocess.run(
+            shlex.split(f"vivado -mode batch -source {config.gen_report_xml_path}"),
+            cwd=config.gen_report_xml_path.parent,
+        )
+        if gen_result.returncode != 0:
+            log.error(
+                f"Could not create post-synthesis resource report in "
+                f"{config.gen_report_xml_path.parent}. Continuing now."
+            )
         return config.run_script_path.parent / "a.xclbin"
 
     def apply(self, model: ModelWrapper) -> tuple[ModelWrapper, bool]:  # noqa
@@ -105,16 +116,19 @@ def apply(self, model: ModelWrapper) -> tuple[ModelWrapper, bool]:  # noqa
         results = {}
         for i, future in futures.items():
             result = cast("Path", future.result())
-            results[i] = str(result)
+            results[i] = str(result.absolute())
             if not result.exists():
                 log.critical(
                     f"XCLBIN for device {i} not found. Check "
                     f"synthesis logs at {configs[i].run_script_path.parent}"
                 )
 
         # Store paths for usage in driver generation, etc.
-        # TODO: Find a better way to do this
-        model.set_metadata_prop("bitfile_output", json.dumps(results))
+        model.set_metadata_prop("bitfile", json.dumps(results))
+        model.set_metadata_prop(
+            "vivado_synth_rpt",
+            json.dumps({device: Path(p).parent / "synth_report.xml" for device, p in results}),
+        )
         return model, False
 
 
@@ -168,5 +182,4 @@ def apply(self, model: ModelWrapper) -> tuple[ModelWrapper, bool]:  # noqa
         # Run the synthesis
         log.info("Starting synthesis...")
         model = model.transform(ParallelVitisSynthesis(self.cfg))
-
         return model, False

src/finn/transformation/fpgadataflow/vitis_linking_configuration.py

@@ -17,7 +17,7 @@
 
 from finn.builder.build_dataflow_config import FpgaMemoryType, VitisOptStrategy
 from finn.templates import get_jinja_environment
-from finn.util.basic import make_build_dir
+from finn.util.basic import get_metadata_prop_path, make_build_dir
 from finn.util.exception import FINNInternalError, FINNUserError, FINNVitisLinkConfigError
 from finn.util.fpgadataflow import (
     check_all_sdp_nodes,
@@ -54,6 +54,7 @@ class VitisLinkConfiguration(DataClassYAMLMixin):
     optimization_level: str
     platform: str
     run_script_path: Path = field(init=False, default_factory=lambda: Path())
+    gen_report_xml_path: Path = field(init=False, default_factory=lambda: Path())
     cu: list[str] = field(default_factory=list)
     nk: list[tuple[str, str]] = field(default_factory=list)
     sc: dict[str, list[str]] = field(default_factory=dict)
@@ -68,6 +69,7 @@ def __post_init__(self) -> None:  # noqa
         self.config_path.parent.mkdir(exist_ok=True, parents=True)
         self.run_script_path = self.config_path.parent / "run_link.sh"
         self.run_script_path.parent.mkdir(exist_ok=True, parents=True)
+        self.gen_report_xml_path = self.config_path.parent / "vitis_gen_report_xml.tcl"
 
     def store(self, p: Path) -> None:
         """Store the config as a YAML file, so that it can be loaded
@@ -94,18 +96,16 @@ def load_from_model(model: ModelWrapper) -> dict[int, VitisLinkConfiguration]:
             dict[int, VitisLinkConfiguration]: Maps device-IDs to their respective
                 linking configurations.
         """
-        storage_path = model.get_metadata_prop("vitis_link_configs")
-        if storage_path is None:
-            raise FINNVitisLinkConfigError(
+        storage_path = get_metadata_prop_path(
+            model,
+            "vitis_link_configs",
+            must_exist=True,
+            custom_error=(
                 "Cannot load VitisLinkConfig from model, "
                 "since the metadata prop "
                 "'vitis_link_configs' was not found!"
-            )
-        storage_path = Path(storage_path)
-        if not storage_path.exists():
-            raise FINNVitisLinkConfigError(
-                f"Cannot load VitisLinkConfigs from invalid path: {storage_path}"
-            )
+            ),
+        )
 
         configs = {}
         for device_path in storage_path.iterdir():
@@ -469,6 +469,15 @@ def generate_config(self) -> None:
         )
         self.config_path.write_text(rendered)
 
+    def generate_report_tcl_script(self) -> None:
+        """Generate a tcl script to output a resource report as an XML. Stored
+        in the link directory as "vitis_gen_report_xml.tcl".
+        """
+        env = get_jinja_environment()
+        template = env.get_template("vitis_link/vitis_gen_report_xml.tcl.jinja")
+        rendered = template.render(VITIS_PROJ_PATH=str(self.config_path.parent.absolute()))
+        self.gen_report_xml_path.write_text(rendered)
+
     def generate_run_script(self) -> None:
         """Generate a shell script to start v++ with the correct parameters.
         Produces the shell script next to the path of the config file
@@ -661,4 +670,5 @@ def apply(self, model: ModelWrapper) -> tuple[ModelWrapper, bool]:  # noqa
         for config in configs.values():
             config.generate_config()
             config.generate_run_script()
+            config.generate_report_tcl_script()
         return model, False