Make averaging window size configurable

Author: fpjentzsch

custom_hls/instrumentation.template.cpp

@@ -291,6 +291,7 @@
                  ts1 = cnt_clk;	// mark completion ^
 
                  // Sliding-window average update
+                 // TODO: II=1 but depth is ~70 cycles, can we optimize this?
                  ap_uint<32>  win = (avg_n == 0 || avg_n > AVG_N) ? ap_uint<32>(AVG_N) : avg_n;
                  if(prev_avg_n != win) {
                      avg_head = 0;

src/finn/builder/build_dataflow_config.py

@@ -538,6 +538,10 @@ def _fix_path(p: Path | None) -> Path | None:
     #: If enable_instrumentation is True, one can disable the DMA with this flag
     instrumentation_no_dma: Optional[bool] = False
 
+    #: (Only relevant if enable_instrumentation is True) Size of the averaging window
+    #: (number of frames) used by the instrumentation wrapper for throughput measurement.
+    instrumentation_avg_n: int = 64
+
     #: Whether pdb postmortem debugging will be launched when the build fails.
     enable_build_pdb_debug: bool = False
 

src/finn/builder/build_dataflow_steps.py

@@ -1515,6 +1515,7 @@ def step_synthesize_bitfile(model: ModelWrapper, cfg: DataflowBuildConfig):
                     cfg.enable_hw_debug,
                     cfg.enable_instrumentation,
                     cfg.instrumentation_no_dma,
+                    cfg.instrumentation_avg_n,
                     cfg.live_fifo_sizing,
                     partition_model_dir=partition_model_dir,
                 )

src/finn/templates/python_driver/driver.py

@@ -601,7 +601,7 @@ def reset_accelerator(self):
             offset=self.ip_dict["axi_gpio_0"]["registers"]["GPIO_DATA"]["address_offset"], value=0
         )
 
-    def start_accelerator(self, throttle_interval=0):
+    def start_accelerator(self, throttle_interval=0, avg_window_size=64):
         """
         Start the accelerator. Input is throttled to the specified interval (in cycles)
         by pausing after each FM transmission. A throttle_interval of 0 means no throttling.
@@ -610,8 +610,9 @@ def start_accelerator(self, throttle_interval=0):
         lfsr_seed = (self.seed << 16) & 0xFFFF0000  # upper 16 bits
         self.instrumentation_write("seed", lfsr_seed)
 
-        # Set average measurement window size (in frames)
-        self.instrumentation_write("avg_n", 65536)  # max window size
+        # Set average measurement window size (in frames),
+        # maximum is configured in build config, default value = 64
+        self.instrumentation_write("avg_n", avg_window_size)
 
         # Start operation
         self.instrumentation_write("cfg", (throttle_interval << 1) | 1)  # bit 0 = start

src/finn/transformation/fpgadataflow/instrumentation.py

@@ -43,12 +43,14 @@ def __init__(
         self,
         fpga_part,
         clk_period_ns,
+        avg_n=64,
         format="ip",  # "ip" for Vivado (Zynq) or "xo" for Vitis (Alveo/Versal)
     ):
         """Initialize instrumentation IP generation with FPGA part and clock settings."""
         super().__init__()
         self.fpga_part = fpga_part
         self.clk_period_ns = clk_period_ns
+        self.avg_n = avg_n
         self.format = format
 
     def apply(self, model):
@@ -86,8 +88,7 @@ def apply(self, model):
         ) as f:
             instrwrp_cpp = f.read()
         instrwrp_cpp = instrwrp_cpp.replace("@PENDING@", str(pending))
-        # Fixed max average window size for now:
-        instrwrp_cpp = instrwrp_cpp.replace("@AVG_N@", str(65536))
+        instrwrp_cpp = instrwrp_cpp.replace("@AVG_N@", str(self.avg_n))
         instrwrp_cpp = instrwrp_cpp.replace("@ILEN@", str(ilen))
         instrwrp_cpp = instrwrp_cpp.replace("@OLEN@", str(olen))
         instrwrp_cpp = instrwrp_cpp.replace("@TI@", str(ti))

src/finn/transformation/fpgadataflow/make_zynq_proj.py

@@ -625,6 +625,7 @@ def __init__(
         enable_debug=False,
         enable_instrumentation=False,
         instrumentation_no_dma=False,
+        instrumentation_avg_n=64,
         live_fifo_sizing=False,
         partition_model_dir=None,
     ):
@@ -637,6 +638,7 @@ def __init__(
         self.enable_debug = enable_debug
         self.enable_instrumentation = enable_instrumentation
         self.instrumentation_no_dma = instrumentation_no_dma
+        self.instrumentation_avg_n = instrumentation_avg_n
         self.live_fifo_sizing = live_fifo_sizing
         self.partition_model_dir = partition_model_dir
 
@@ -652,14 +654,18 @@ def apply(self, model):
         if self.enable_instrumentation:
             if self.instrumentation_no_dma is True or self.live_fifo_sizing is True:
                 prep_transforms = [
-                    GenerateInstrumentationIP(self.fpga_part, self.period_ns),
+                    GenerateInstrumentationIP(
+                        self.fpga_part, self.period_ns, self.instrumentation_avg_n
+                    ),
                     Floorplan(),
                     CreateDataflowPartition(partition_model_dir=self.partition_model_dir),
                 ]
             else:
                 # DMA & Instrumentation Wrapper Case
                 prep_transforms = [
-                    GenerateInstrumentationIP(self.fpga_part, self.period_ns),
+                    GenerateInstrumentationIP(
+                        self.fpga_part, self.period_ns, self.instrumentation_avg_n
+                    ),
                     InsertIODMA(self.axi_port_width),
                     InsertDWC(),
                     SpecializeLayers(self.fpga_part),