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Implement a full binary search / bisection instead of the current two-phase algorithm
Implement an optimized RTL implementation of the virtual FIFO. This could save LUTs (current HLS variant uses ~ 300 LUT per virtual FIFO) and reduce the FIFO depth offset and thus the minimal FIFO depth the algorithm is able to determine (currently 9, ideally 2 or even 0 (no FIFO needed at all))
Switch to a better control mechanism, i.e., a ring/chain/stream based virtual FIFO configuration interface instead of AXI-Lite
Support Alveo/Versal platforms in addition to Zynq
Live FIFO-Sizing was first introduced here: #46
Some improvements remain: