wip(chip,robot): post-merge background churn — npu/asap7 evidence, robot bridge backends

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

Author: lalalune

packages/chip/docs/arch/npu.md

@@ -827,7 +827,7 @@ executing; it rejects sequences whose GEMM preamble, descriptor submission, or
 and rejects completion metadata that does not require the done
 bit or reject the error bit. `stage_prepared_descriptor_batch` validates an
 `eliza.e1_npu_prepared_descriptor_batch.v1` package, checks `descriptor_base`,
-`arena_base`, `arena_total_bytes`, `arena_alignment_bytes`,
+`batch_index`, `arena_base`, `arena_total_bytes`, `arena_alignment_bytes`,
 `required_runtime_steps`, `descriptor_memory_writes`, and
 `mmio_preamble_writes` against the packaged `descriptor_image` and
 `op_mmio_preamble`, then returns
@@ -839,7 +839,7 @@ returns `eliza.e1_npu_prepared_descriptor_execution_batches_stage_result.v1`.
 Before writing descriptor memory or MMIO, it checks every descriptor image base
 and `DESC_BASE` submission value against the package-level `descriptor_base +
 execution_batch_index * descriptor_stride_bytes` contract, checks
-`arena_base consistency` and arena sizing across the outer package, inner packages, and
+`batch_index`/`execution_batch_index` identity, `arena_base consistency` and arena sizing across the outer package, inner packages, and
 descriptor images, checks `required_runtime_steps` on the outer and inner packages, and checks
 `descriptor_memory_writes` exactly match the packaged `descriptor_image`.
 It also checks `mmio_preamble_writes` match `op_mmio_preamble`, including op

packages/chip/docs/evidence/process/asap7/big_core_shell_shape.json

@@ -14,7 +14,7 @@
     "mapper": "abc",
     "memory_inference": true,
     "param_overrides": [],
-    "wall_clock_s": 22.52
+    "wall_clock_s": 18.04
   },
   "abc_target_period_ps": 4000,
   "gate_count_total": 63814,

packages/chip/docs/npu/2028-targets.md

@@ -91,7 +91,7 @@ the done bit, requires the done bit, and rejects the error bit. The
 `stage_prepared_descriptor_batch` helper validates
 `eliza.e1_npu_prepared_descriptor_batch.v1` packages and returns
 `eliza.e1_npu_prepared_descriptor_batch_stage_result.v1` after checking
-`arena_base`, `arena_total_bytes`, `arena_alignment_bytes`,
+`batch_index`, `arena_base`, `arena_total_bytes`, `arena_alignment_bytes`,
 `required_runtime_steps`, `descriptor_base`, `descriptor_memory_writes`, and
 `mmio_preamble_writes` against the packaged `descriptor_image` and
 `op_mmio_preamble`. The
@@ -100,7 +100,8 @@ the done bit, requires the done bit, and rejects the error bit. The
 `eliza.e1_npu_prepared_descriptor_execution_batches_stage_result.v1` after
 checking each descriptor image and `DESC_BASE` submission against
 `descriptor_base + execution_batch_index * descriptor_stride_bytes`, and
-checking `arena_base consistency`, arena sizing, `required_runtime_steps`, and
+checking `batch_index`/`execution_batch_index` identity, `arena_base consistency`,
+arena sizing, `required_runtime_steps`, and
 `descriptor_memory_writes` exactly match the packaged
 `descriptor_image`. It also checks `mmio_preamble_writes` match
 `op_mmio_preamble` before staging. The

packages/chip/docs/spec-db/e1-npu-runtime-contract.json

@@ -796,7 +796,7 @@
     "descriptor_type": "NpuStreamDescriptor",
     "max_entries": 7,
     "descriptor_bytes": 16,
-    "staging": "CommandBuffer.descriptor_image returns a deterministic word-addressed descriptor image and CommandBuffer.stage writes that image through a caller-provided 32-bit memory writer before submit arms the existing descriptor ring; stage_host_runtime_sequence validates GEMM preamble, descriptor submission, and completion_poll register metadata labels/addresses plus completion_poll requires_done_bit/rejects_error_bit metadata, replays a prepared-batch host_runtime_sequence through caller-provided MMIO and descriptor-memory writers, and returns eliza.e1_npu_host_runtime_sequence_stage_result.v1 without polling or executing; stage_prepared_descriptor_batch validates an eliza.e1_npu_prepared_descriptor_batch.v1 package, checks arena_base, arena_total_bytes, arena_alignment_bytes, required_runtime_steps, descriptor_base, descriptor_memory_writes, and mmio_preamble_writes against descriptor_image/op_mmio_preamble metadata, and returns eliza.e1_npu_prepared_descriptor_batch_stage_result.v1; stage_prepared_descriptor_execution_batches validates eliza.e1_npu_prepared_descriptor_execution_batches.v1 packages, checks arena_base consistency and arena sizing across the outer package, inner batches, and descriptor images, checks required_runtime_steps, checks descriptor_base plus execution_batch_index times descriptor_stride_bytes against each descriptor image and DESC_BASE submission write, checks descriptor_memory_writes match descriptor_image, checks mmio_preamble_writes match op_mmio_preamble before staging, stages each ordered execution-batch host_runtime_sequence, and returns eliza.e1_npu_prepared_descriptor_execution_batches_stage_result.v1",
+    "staging": "CommandBuffer.descriptor_image returns a deterministic word-addressed descriptor image and CommandBuffer.stage writes that image through a caller-provided 32-bit memory writer before submit arms the existing descriptor ring; stage_host_runtime_sequence validates GEMM preamble, descriptor submission, and completion_poll register metadata labels/addresses plus completion_poll requires_done_bit/rejects_error_bit metadata, replays a prepared-batch host_runtime_sequence through caller-provided MMIO and descriptor-memory writers, and returns eliza.e1_npu_host_runtime_sequence_stage_result.v1 without polling or executing; stage_prepared_descriptor_batch validates an eliza.e1_npu_prepared_descriptor_batch.v1 package, checks batch_index, arena_base, arena_total_bytes, arena_alignment_bytes, required_runtime_steps, descriptor_base, descriptor_memory_writes, and mmio_preamble_writes against descriptor_image/op_mmio_preamble metadata, and returns eliza.e1_npu_prepared_descriptor_batch_stage_result.v1; stage_prepared_descriptor_execution_batches validates eliza.e1_npu_prepared_descriptor_execution_batches.v1 packages, checks batch_index/execution_batch_index identity, arena_base consistency and arena sizing across the outer package, inner batches, and descriptor images, checks required_runtime_steps, checks descriptor_base plus execution_batch_index times descriptor_stride_bytes against each descriptor image and DESC_BASE submission write, checks descriptor_memory_writes match descriptor_image, checks mmio_preamble_writes match op_mmio_preamble before staging, stages each ordered execution-batch host_runtime_sequence, and returns eliza.e1_npu_prepared_descriptor_execution_batches_stage_result.v1",
     "completion": "Submit arms DESC_BASE/DESC_HEAD/DESC_TAIL once through submit_descriptors and waits for one descriptor completion proof for the staged batch",
     "claim_boundary": "command_buffer_descriptor_batching_smoke_only_not_scheduler_iommu_or_production_dma_runtime",
     "not_claimed": "No graph scheduler, dependency tracking, coherent IOMMU staging, production DMA allocator, Android delegate command stream, or queue-depth proof beyond the current 3-bit local RTL ring is implemented"

packages/chip/pd/asap7/README.md

@@ -40,34 +40,41 @@ project those shapes to TSMC N2P / A14 / Intel 14A class using
 
 Two flow modes coexist in this lane:
 
-1. **ORFS post-route** (full PnR) — drives `big_core_shell`, `npu_tile`,
-   `slc_slice`, `npu_tile_rf_leaf`. Gated by an ORFS local checkout or docker
-   image. The operator runs ORFS for the block and copies the post-route
-   shape JSON into `docs/evidence/process/asap7/<block>_shape.json`.
-2. **Yosys + ABC synth-only** (no ORFS dependency) — drives `tage_table` and
-   any other leaf block whose `config.asap7.yaml` entry sets
-   `flow_mode: yosys_abc_synth_only`. The runner invokes
-   `scripts/run_asap7_leaf_synth.py`, which:
+1. **Yosys + ABC synth-only** (no ORFS dependency, default) — drives every
+   block currently declared in `config.asap7.yaml`: `tage_table`,
+   `npu_tile_rf_leaf`, `npu_tile`, `big_core_shell`, `slc_slice`. The runner
+   invokes `scripts/run_asap7_leaf_synth.py`, which:
      1. unpacks the ASAP7 7p5t RVT TT NLDM libraries from
         `external/pdks/asap7/asap7sc7p5t_27/LIB/NLDM/*.lib.7z` into
         `build/asap7/lib/` (via `scripts/extract_asap7_libs.py` + the
         bundled `py7zr`),
      2. runs `yosys 0.64 + slang` with the per-block `synth_params`
-        overrides,
+        overrides and the per-block `rtl_top` as the SystemVerilog top,
      3. ABC-maps the design with `abc -fast` and the ORFS-published
         `DONT_USE_CELLS` exclusion set
         (`*x1p*_ASAP7*`, `*xp*_ASAP7*`, `SDF*`, `ICG*`),
      4. emits a shape JSON tagged
         `evidence_class: predictive_finfet_shape_only_not_signoff` that the
         downstream `scripts/project_ppa_to_n2p.py` ingests verbatim.
+2. **ORFS post-route** (full PnR, opt-in) — available for any block whose
+   `config.asap7.yaml` entry omits `flow_mode: yosys_abc_synth_only`. Gated
+   by an ORFS local checkout or docker image. The operator runs ORFS for the
+   block and copies the post-route shape JSON into
+   `docs/evidence/process/asap7/<block>_shape.json`. No block currently
+   ships with this mode by default; it is the upgrade path once full PnR
+   is required for a leaf.
 
 ```sh
-make -C pd/asap7 check                          # preflight: PDK reachable?
-make -C pd/asap7 clone-asap7                    # one-shot ASAP7 PDK clone
-make -C pd/asap7 clone-orfs                     # one-shot ORFS clone (tier-1 blocks)
-make -C pd/asap7 all                            # run every ORFS block
-make -C pd/asap7 leaf-shape MODULE=tage_table   # yosys+ABC synth-only leaf shape
-make ppa-projection                             # project all shapes to N2P/A14/Intel-14A/SF2P
+make -C pd/asap7 check                              # preflight: PDK reachable?
+make -C pd/asap7 clone-asap7                        # one-shot ASAP7 PDK clone
+make -C pd/asap7 clone-orfs                         # one-shot ORFS clone (opt-in PnR)
+make -C pd/asap7 leaf-shape MODULE=tage_table       # yosys+ABC synth-only leaf shape
+make -C pd/asap7 leaf-shape MODULE=npu_tile_rf_leaf # NPU weight-buffer SRAM leaf shape
+make -C pd/asap7 leaf-shape MODULE=npu_tile         # full e1_npu monolithic tile shape
+make -C pd/asap7 leaf-shape MODULE=big_core_shell   # CPU subsystem stub leaf shape
+make -C pd/asap7 leaf-shape MODULE=slc_slice        # SLC bank slice shape (shrunk geom)
+make -C pd/asap7 big_core_shell-shape               # equivalent per-block target
+make ppa-projection                                 # project all shapes to N2P/A14/Intel-14A/SF2P
 ```
 
 The block list is defined in `config.asap7.yaml` and mirrors the OpenLane
@@ -105,14 +112,30 @@ tional logic area.
 
 ### Block tiers
 
-- **Tier 1 — Wrapper blocks** (`big_core_shell`, `npu_tile`, `slc_slice`)
-  drive the existing module tops and emit a `*_shape.json` post-route shape
-  report under `docs/evidence/process/asap7/`.
-- **Tier 2 — Leaf sub-blocks** (`npu_tile_rf_leaf`) characterize a single
-  representative sub-block (the first 64-entry NPU register-file slice
-  inside `e1_npu`). Outputs are tagged `leaf_only` so they are not aggregated
-  into top-level NPU area. The intent is to land a first sub-block shape
-  before the full tile closes.
+Every block currently uses the yosys + ABC synth-only flow. The block list
+mirrors the per-domain leaf shape needed for advanced-node area projection:
+
+- **`tage_table`** — BPU TAGE tagged-table primitive (128-entry leaf-shape
+  proxy of the production 4096-entry geometry).
+- **`npu_tile_rf_leaf`** — NPU weight-staging register file
+  (`e1_weight_buffer_sram`, 512x32-bit + write-mask, behavioral path). The
+  hard-macro swap point under `E1_HAVE_HARD_SRAM`.
+- **`npu_tile`** — full `e1_npu` monolithic NPU tile (16x32-bit scratch RF,
+  16 opcodes including INT8/INT4/INT2/FP8 dot products, GEMM/vector engines,
+  AXI-Lite descriptor engine, perf counters) at production geometry.
+- **`big_core_shell`** — `e1_cpu_subsystem_stub`, the self-contained
+  32x64-bit RV64I subset in-order microcontroller stub (decoder + ALU +
+  architectural RF + AXI4-Lite master FSM). Substitutes for the
+  Ascalon / Kunminghu / CVA6 big-core RTL until those land.
+- **`slc_slice`** — shrunk `e1_slc` (2 KiB, 2-way, 2 banks, 64 B line)
+  covering the cache lookup/install FSM, BDI compression form classifier,
+  QoS-aware victim selection, and display-RT reservation counter.
+
+For every block, the storage cost in the leaf shape is the flat-flop cost.
+Production silicon swaps storage for vendor SRAM macros at vendor density
+(38.1 Mb/mm² HD at N2 per TSMC) — `scripts/project_ppa_to_n2p.py` carries
+the logic-only band; reviewers must add macro area separately when sizing
+real cache or scratch arrays.
 
 ### Fail-closed contract
 

packages/chip/research/alpha_chip_macro_placement/01_sources/ai_eda_automation_readiness.yaml

@@ -1058,6 +1058,8 @@ stages:
       - sigrok-cli
       - ml-boot-failure-debug
       - llm4sechw-debug
+      - llm4sechw-oshd
+      - chipbench-ai-aided-design
     local_lane: p1-post-silicon-validation-target-capture
     current_artifacts:
       - scripts/ai_eda/capture_post_silicon_validation_targets.py
@@ -1067,9 +1069,10 @@ stages:
       Post-silicon and lab automation is essential but cannot be simulated into
       existence. RISC-V compliance tests, riscv-dv, QED-style tests,
       trace-debug methods, cross-target on-device tests, RISC-V debug/OpenOCD
-      flows, sigrok lab capture, and ML boot-failure triage can guide future
+      flows, sigrok lab capture, ML boot-failure triage, LLM hardware-debug
+      datasets, and tougher LLM chip-debug benchmarks can guide future
       bring-up, but E1 currently has no silicon, no lab trace corpus, no
-      executed compliance suite, and no approved hardware action workflow. Keep
-      this lane as target capture until QEMU/Renode, FPGA, board/package,
-      debug-policy, manufacturing, real-world, benchmark, and lab evidence
-      exists.
+      executed compliance suite, no approved external debug corpus, and no
+      approved hardware action workflow. Keep this lane as target capture until
+      QEMU/Renode, FPGA, board/package, debug-policy, manufacturing,
+      real-world, benchmark, corpus-governance, and lab evidence exists.

packages/chip/research/alpha_chip_macro_placement/01_sources/ai_eda_integration_backlog.yaml

@@ -1627,20 +1627,25 @@ work_items:
       - sigrok-cli
       - ml-boot-failure-debug
       - llm4sechw-debug
+      - llm4sechw-oshd
+      - chipbench-ai-aided-design
     target_area:
       - post_silicon_validation
       - silicon_bringup
       - fpga_bringup
       - riscv_compliance
       - lab_debug
       - boot_failure_triage
+      - hardware_debug_benchmark
+      - debug_dataset_governance
     owner_scope: dry-run target capture only; no hardware actions, generated lab scripts, test binaries, FPGA bitstreams, or compliance claims
     objective: >
       Track post-silicon debug methods, QED/trace-analysis approaches, RISC-V
       compatibility tests, random-instruction validation, cross-target
-      on-device tests, RISC-V debug/lab capture tooling, and ML/XAI
-      boot-failure triage while tying any future E1 use to QEMU/Renode, FPGA,
-      manufacturing, real-world, and lab evidence.
+      on-device tests, RISC-V debug/lab capture tooling, ML/XAI boot-failure
+      triage, LLM hardware-debug datasets, and LLM chip-debug benchmarks while
+      tying any future E1 use to QEMU/Renode, FPGA, manufacturing, real-world,
+      corpus-governance, benchmark, and lab evidence.
     deliverables:
       - scripts/ai_eda/capture_post_silicon_validation_targets.py
       - build/ai_eda/post_silicon_validation_targets/<run-id>/targets_report.json
@@ -1663,6 +1668,7 @@ work_items:
       - No trace schema for reset, boot, UART, JTAG, power, thermal, FPGA, or board observations
       - No pinned OpenOCD board configuration, RISC-V debug module transcript, probe inventory, or sigrok acquisition profile
       - No labeled boot-failure, post-silicon debug, or lab anomaly corpus for ML/XAI triage
+      - No approved LLM hardware-debug dataset or benchmark import with pinned revisions, licenses, task manifests, non-overlap review, replay logs, and reviewer disposition
       - No approved workflow for AI-generated lab scripts, test binaries, FPGA bitstreams, or hardware actions
     acceptance_criteria:
       - Report hashes local RISC-V compliance, QEMU/Renode, FPGA, package, board, benchmark, and release-gate inputs.

packages/chip/research/alpha_chip_macro_placement/01_sources/ai_eda_provenance_matrix.yaml

@@ -935,6 +935,24 @@ entries:
     license_status: review_required
     release_use: blocked_pending_dataset_license_snapshot_and_non_overlap_review
     allowed_current_use: dataset_governance_reference_only
+  - source_id: llm4sechw-debug
+    asset_type: hardware_debug_llm_framework
+    asset_url: https://arxiv.org/abs/2401.16448
+    license_status: paper_assets_review_required
+    release_use: blocked_pending_model_dataset_defect_patch_and_review_harness
+    allowed_current_use: hardware_debug_method_reference_only
+  - source_id: llm4sechw-oshd
+    asset_type: open_source_hardware_debug_dataset
+    asset_url: https://huggingface.co/datasets/KSU-HW-SEC/LLM4SecHW-OSHD
+    license_status: review_required
+    release_use: blocked_pending_dataset_snapshot_license_and_contamination_review
+    allowed_current_use: dataset_governance_reference_only
+  - source_id: chipbench-ai-aided-design
+    asset_type: llm_chip_design_debug_reference_model_benchmark
+    asset_url: https://github.com/zhongkaiyu/ChipBench
+    license_status: review_required
+    release_use: blocked_pending_benchmark_license_split_overlap_and_replay_review
+    allowed_current_use: benchmark_governance_reference_only
   - source_id: archgym
     asset_type: architecture_dse_framework
     asset_url: https://github.com/srivatsankrishnan/oss-arch-gym