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1 | | -/** |
2 | | - * @file pci_enum.c |
3 | | - * @brief PCI/PCIe bus enumeration and device discovery |
4 | | - */ |
5 | | - |
6 | | -#include "eos_pci.h" |
7 | | -#include <string.h> |
8 | | -#include <stdio.h> |
9 | | - |
10 | | -/* ECAM config space access (memory-mapped) */ |
11 | | -static volatile uint32_t *pci_ecam_addr(uint32_t ecam_base, |
12 | | - uint8_t bus, uint8_t dev, uint8_t func, |
13 | | - uint16_t reg) |
14 | | -{ |
15 | | - uint32_t addr = ecam_base |
16 | | - | ((uint32_t)bus << 20) |
17 | | - | ((uint32_t)dev << 15) |
18 | | - | ((uint32_t)func << 12) |
19 | | - | (reg & 0xFFC); |
20 | | - return (volatile uint32_t *)(uintptr_t)addr; |
21 | | -} |
22 | | - |
23 | | -static uint32_t pci_read32(uint32_t ecam, uint8_t bus, uint8_t dev, |
24 | | - uint8_t func, uint16_t reg) |
25 | | -{ |
26 | | - volatile uint32_t *p = pci_ecam_addr(ecam, bus, dev, func, reg); |
27 | | - return *p; |
28 | | -} |
29 | | - |
30 | | -int eos_pci_init(eos_pci_bus_t *bus, uint32_t ecam_base) |
31 | | -{ |
32 | | - if (!bus) return -1; |
33 | | - memset(bus, 0, sizeof(*bus)); |
34 | | - bus->ecam_base = ecam_base; |
35 | | - return 0; |
36 | | -} |
37 | | - |
38 | | -int eos_pci_enumerate(eos_pci_bus_t *bus) |
39 | | -{ |
40 | | - if (!bus || !bus->ecam_base) return -1; |
41 | | - |
42 | | - bus->count = 0; |
43 | | - |
44 | | - for (uint8_t b = 0; b < 4 && bus->count < EOS_PCI_MAX_DEVICES; b++) { |
45 | | - for (uint8_t d = 0; d < 32 && bus->count < EOS_PCI_MAX_DEVICES; d++) { |
46 | | - uint32_t id = pci_read32(bus->ecam_base, b, d, 0, 0); |
47 | | - if (id == 0xFFFFFFFF || id == 0) continue; |
48 | | - |
49 | | - eos_pci_device_t *dev = &bus->devices[bus->count]; |
50 | | - dev->vendor_id = (uint16_t)(id & 0xFFFF); |
51 | | - dev->device_id = (uint16_t)(id >> 16); |
52 | | - dev->bus = b; |
53 | | - dev->dev = d; |
54 | | - dev->func = 0; |
55 | | - |
56 | | - uint32_t class_rev = pci_read32(bus->ecam_base, b, d, 0, 0x08); |
57 | | - dev->class_code = (uint16_t)(class_rev >> 16); |
58 | | - |
59 | | - uint32_t hdr = pci_read32(bus->ecam_base, b, d, 0, 0x0C); |
60 | | - dev->header_type = (uint8_t)((hdr >> 16) & 0x7F); |
61 | | - dev->is_bridge = (dev->header_type == 1); |
62 | | - |
63 | | - for (int i = 0; i < 6; i++) { |
64 | | - dev->bar[i] = pci_read32(bus->ecam_base, b, d, 0, |
65 | | - (uint16_t)(0x10 + i * 4)); |
66 | | - } |
67 | | - |
68 | | - uint32_t irq = pci_read32(bus->ecam_base, b, d, 0, 0x3C); |
69 | | - dev->irq_line = (uint8_t)(irq & 0xFF); |
70 | | - |
71 | | - bus->count++; |
72 | | - } |
73 | | - } |
74 | | - return bus->count; |
75 | | -} |
76 | | - |
77 | | -const eos_pci_device_t *eos_pci_find_device(const eos_pci_bus_t *bus, |
78 | | - uint16_t vendor, uint16_t device) |
79 | | -{ |
80 | | - for (int i = 0; i < bus->count; i++) { |
81 | | - if (bus->devices[i].vendor_id == vendor && |
82 | | - bus->devices[i].device_id == device) |
83 | | - return &bus->devices[i]; |
84 | | - } |
85 | | - return NULL; |
86 | | -} |
87 | | - |
88 | | -const eos_pci_device_t *eos_pci_find_class(const eos_pci_bus_t *bus, |
89 | | - uint16_t class_code) |
90 | | -{ |
91 | | - for (int i = 0; i < bus->count; i++) { |
92 | | - if (bus->devices[i].class_code == class_code) |
93 | | - return &bus->devices[i]; |
94 | | - } |
95 | | - return NULL; |
96 | | -} |
97 | | - |
98 | | -void eos_pci_dump(const eos_pci_bus_t *bus) |
99 | | -{ |
100 | | - printf("PCI: %d devices (ECAM @ 0x%08x)\n", bus->count, bus->ecam_base); |
101 | | - for (int i = 0; i < bus->count; i++) { |
102 | | - const eos_pci_device_t *d = &bus->devices[i]; |
103 | | - printf(" %02x:%02x.%x %04x:%04x class=%04x IRQ=%d%s\n", |
104 | | - d->bus, d->dev, d->func, |
105 | | - d->vendor_id, d->device_id, d->class_code, |
106 | | - d->irq_line, d->is_bridge ? " [bridge]" : ""); |
107 | | - } |
108 | | -} |
| 1 | +/** |
| 2 | + * @file pci_enum.c |
| 3 | + * @brief PCI/PCIe bus enumeration and device discovery |
| 4 | + */ |
| 5 | + |
| 6 | +#include "eos_pci.h" |
| 7 | +#include <string.h> |
| 8 | +#ifdef EBOOT_ENABLE_PRINTF |
| 9 | +#include <stdio.h> |
| 10 | +#endif |
| 11 | + |
| 12 | +/* ECAM config space access (memory-mapped) */ |
| 13 | +static volatile uint32_t *pci_ecam_addr(uint32_t ecam_base, |
| 14 | + uint8_t bus, uint8_t dev, uint8_t func, |
| 15 | + uint16_t reg) |
| 16 | +{ |
| 17 | + uint32_t addr = ecam_base |
| 18 | + | ((uint32_t)bus << 20) |
| 19 | + | ((uint32_t)dev << 15) |
| 20 | + | ((uint32_t)func << 12) |
| 21 | + | (reg & 0xFFC); |
| 22 | + return (volatile uint32_t *)(uintptr_t)addr; |
| 23 | +} |
| 24 | + |
| 25 | +static uint32_t pci_read32(uint32_t ecam, uint8_t bus, uint8_t dev, |
| 26 | + uint8_t func, uint16_t reg) |
| 27 | +{ |
| 28 | + volatile uint32_t *p = pci_ecam_addr(ecam, bus, dev, func, reg); |
| 29 | + return *p; |
| 30 | +} |
| 31 | + |
| 32 | +int eos_pci_init(eos_pci_bus_t *bus, uint32_t ecam_base) |
| 33 | +{ |
| 34 | + if (!bus) return -1; |
| 35 | + memset(bus, 0, sizeof(*bus)); |
| 36 | + bus->ecam_base = ecam_base; |
| 37 | + return 0; |
| 38 | +} |
| 39 | + |
| 40 | +int eos_pci_enumerate(eos_pci_bus_t *bus) |
| 41 | +{ |
| 42 | + if (!bus || !bus->ecam_base) return -1; |
| 43 | + |
| 44 | + bus->count = 0; |
| 45 | + |
| 46 | + for (uint8_t b = 0; b < 4 && bus->count < EOS_PCI_MAX_DEVICES; b++) { |
| 47 | + for (uint8_t d = 0; d < 32 && bus->count < EOS_PCI_MAX_DEVICES; d++) { |
| 48 | + uint32_t id = pci_read32(bus->ecam_base, b, d, 0, 0); |
| 49 | + if (id == 0xFFFFFFFF || id == 0) continue; |
| 50 | + |
| 51 | + eos_pci_device_t *dev = &bus->devices[bus->count]; |
| 52 | + dev->vendor_id = (uint16_t)(id & 0xFFFF); |
| 53 | + dev->device_id = (uint16_t)(id >> 16); |
| 54 | + dev->bus = b; |
| 55 | + dev->dev = d; |
| 56 | + dev->func = 0; |
| 57 | + |
| 58 | + uint32_t class_rev = pci_read32(bus->ecam_base, b, d, 0, 0x08); |
| 59 | + dev->class_code = (uint16_t)(class_rev >> 16); |
| 60 | + |
| 61 | + uint32_t hdr = pci_read32(bus->ecam_base, b, d, 0, 0x0C); |
| 62 | + dev->header_type = (uint8_t)((hdr >> 16) & 0x7F); |
| 63 | + dev->is_bridge = (dev->header_type == 1); |
| 64 | + |
| 65 | + for (int i = 0; i < 6; i++) { |
| 66 | + dev->bar[i] = pci_read32(bus->ecam_base, b, d, 0, |
| 67 | + (uint16_t)(0x10 + i * 4)); |
| 68 | + } |
| 69 | + |
| 70 | + uint32_t irq = pci_read32(bus->ecam_base, b, d, 0, 0x3C); |
| 71 | + dev->irq_line = (uint8_t)(irq & 0xFF); |
| 72 | + |
| 73 | + bus->count++; |
| 74 | + } |
| 75 | + } |
| 76 | + return bus->count; |
| 77 | +} |
| 78 | + |
| 79 | +const eos_pci_device_t *eos_pci_find_device(const eos_pci_bus_t *bus, |
| 80 | + uint16_t vendor, uint16_t device) |
| 81 | +{ |
| 82 | + for (int i = 0; i < bus->count; i++) { |
| 83 | + if (bus->devices[i].vendor_id == vendor && |
| 84 | + bus->devices[i].device_id == device) |
| 85 | + return &bus->devices[i]; |
| 86 | + } |
| 87 | + return NULL; |
| 88 | +} |
| 89 | + |
| 90 | +const eos_pci_device_t *eos_pci_find_class(const eos_pci_bus_t *bus, |
| 91 | + uint16_t class_code) |
| 92 | +{ |
| 93 | + for (int i = 0; i < bus->count; i++) { |
| 94 | + if (bus->devices[i].class_code == class_code) |
| 95 | + return &bus->devices[i]; |
| 96 | + } |
| 97 | + return NULL; |
| 98 | +} |
| 99 | + |
| 100 | +void eos_pci_dump(const eos_pci_bus_t *bus) |
| 101 | +{ |
| 102 | +#ifdef EBOOT_ENABLE_PRINTF |
| 103 | + printf("PCI: %d devices (ECAM @ 0x%08x)\n", bus->count, bus->ecam_base); |
| 104 | + for (int i = 0; i < bus->count; i++) { |
| 105 | + const eos_pci_device_t *d = &bus->devices[i]; |
| 106 | + printf(" %02x:%02x.%x %04x:%04x class=%04x IRQ=%d%s\n", |
| 107 | + d->bus, d->dev, d->func, |
| 108 | + d->vendor_id, d->device_id, d->class_code, |
| 109 | + d->irq_line, d->is_bridge ? " [bridge]" : ""); |
| 110 | + } |
| 111 | +#else |
| 112 | + (void)bus; |
| 113 | +#endif |
| 114 | +} |
| 115 | + d->irq_line, d->is_bridge ? " [bridge]" : ""); |
| 116 | + } |
| 117 | +#else |
| 118 | + (void)bus; |
| 119 | +#endif |
| 120 | +} |
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