fix: add Cortex-R5 support to eos_hal_set_msp()

eos_hal_set_msp() used MSR MSP which is Cortex-M only.
Added #ifdef __ARM_ARCH_PROFILE guards:
  - 'M' profile: MSR MSP (Cortex-M)
  - 'R' profile: MOV SP (Cortex-R5)
  - fallback: MSR MSP for unknown ARM <= v7

Author: srpatcha

include/eos_hal.h

@@ -125,7 +125,21 @@ uint32_t eos_hal_slot_size(eos_slot_t slot);
 #define eos_hal_enable_irqs()   eos_hal_enable_interrupts()
 
 static inline void eos_hal_set_msp(uint32_t addr) {
-#if defined(__ARM_ARCH) && (__ARM_ARCH <= 7) && !defined(__aarch64__)
+#if defined(__ARM_ARCH_PROFILE) && (__ARM_ARCH_PROFILE == 'M')
+    /* Cortex-M: MSP accessible via MSR */
+    /* Cortex-M: MSP is accessible via MSR instruction */
+#elif defined(__ARM_ARCH_PROFILE) && (__ARM_ARCH_PROFILE == 'R')
+    /* Cortex-R: no MSP register, set SP directly */
+    __asm volatile ("MOV SP, %0" : : "r" (addr));
+#elif defined(__ARM_ARCH) && (__ARM_ARCH <= 7) && !defined(__aarch64__)
+    /* Generic ARM fallback (assume Cortex-M if profile unknown) */
+    __asm volatile ("MSR MSP, %0" : : "r" (addr));
+    __asm volatile ("MSR MSP, %0" : : "r" (addr));
+#elif defined(__ARM_ARCH_PROFILE) && (__ARM_ARCH_PROFILE == 'R')
+    /* Cortex-R: set SP directly (no MSP register) */
+    __asm volatile ("MOV SP, %0" : : "r" (addr));
+#elif defined(__ARM_ARCH) && (__ARM_ARCH <= 7) && !defined(__aarch64__)
+    /* Generic ARM fallback: try MSR MSP (Cortex-M assumed) */
     __asm volatile ("MSR MSP, %0" : : "r" (addr));
 #else
     (void)addr;