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ogamespecogamespec
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Merge pull request #1365 from ogamespec/master
PPU PAR Refactoring (HDL)
2 parents f7bf860 + 3a8007b commit 6a1e3b6

9 files changed

Lines changed: 102 additions & 72 deletions

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‎HDL/Design/ppu/ppu.pdf‎

5.77 KB
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‎HDL/Design/ppu/ppu_schematic.png‎

230 KB
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‎HDL/PPU/Readme.md‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,8 @@
22

33
PPU implementation on Verilog.
44

5-
Status: regs.v is done, the rest of the stubs + TOP for now.
5+
Status: WIP
66

77
The PPU revision is selected by the macro: `RP2C02` or `RP2C07`. Other PPU revisions (RGB, clones) will be added over time.
88

9-
![ppu_schematic](/HDL/Design/ppu/ppu_schematic.png)
9+
![ppu_schematic](/HDL/Design/ppu/ppu_schematic.png)

‎HDL/PPU/pamux.v‎

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,20 @@
1+
module PAMUX (
2+
PCLK,
3+
n_H2_D, BLNK, F_AT, DB_PAR,
4+
FAT_in, PAR_in, PAD_in, CPU_DB, n_PA );
5+
6+
input PCLK;
7+
8+
input n_H2_D;
9+
input BLNK;
10+
input F_AT;
11+
input DB_PAR;
12+
13+
input [13:0] FAT_in;
14+
input [13:0] PAR_in;
15+
input [13:0] PAD_in;
16+
inout [7:0] CPU_DB;
17+
18+
output [13:0] n_PA;
19+
20+
endmodule // PAMUX

‎HDL/PPU/par.v‎

Lines changed: 16 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -1,37 +1,23 @@
1-
21
module PAR(
3-
n_PCLK, PCLK,
4-
BLNK, DB_PAR, F_AT, SC_CNT, RESCL, E_EV, TSTEP, F_TB, H0_DD, n_H2_D, I_1_32, W6_2_Ena,
5-
PAD_in, CPU_DB, TH, TV, NTH, NTV, FV,
6-
n_FVO, THO, TVO, n_PA );
2+
n_PCLK,
3+
H0_DD, n_FNT, BGSEL, OBSEL, O8_16, PAR_O, n_SH2, n_H1D, OB, PD, OV, n_FVO,
4+
PAddr_out);
75

86
input n_PCLK;
9-
input PCLK;
107

11-
input BLNK;
12-
input DB_PAR;
13-
input F_AT;
14-
input SC_CNT;
15-
input RESCL;
16-
input E_EV;
17-
input TSTEP;
18-
input F_TB;
198
input H0_DD;
20-
input n_H2_D;
21-
input I_1_32;
22-
input W6_2_Ena;
23-
24-
input [13:0] PAD_in;
25-
inout [7:0] CPU_DB;
26-
input [4:0] TH;
27-
input [4:0] TV;
28-
input NTH;
29-
input NTV;
30-
input [2:0] FV;
9+
input n_FNT;
10+
input BGSEL;
11+
input OBSEL;
12+
input O8_16;
13+
input PAR_O;
14+
input n_SH2;
15+
input n_H1D;
16+
input [7:0] OB;
17+
input [7:0] PD;
18+
input [3:0] OV;
19+
input [2:0] n_FVO;
3120

32-
output [2:0] n_FVO;
33-
output [4:0] THO;
34-
output [4:0] TVO;
35-
output [13:0] n_PA;
21+
output [13:0] PAddr_out;
3622

37-
endmodule // PAR
23+
endmodule // PAR

‎HDL/PPU/patgen.v‎

Lines changed: 0 additions & 24 deletions
This file was deleted.

‎HDL/PPU/ppu_top.v‎

Lines changed: 22 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -132,7 +132,9 @@ module PPU(RnW, D, RS, n_DBE, EXT, CLK, n_INT, ALE, AD, A, n_RD, n_WR, n_RES, VO
132132
wire [4:0] TVO;
133133
wire W6_2_Ena;
134134
wire [3:0] BGC; // Background color
135-
wire [13:0] PAD;
135+
wire [13:0] PAD_adr;
136+
wire [13:0] FAT_adr;
137+
wire [13:0] PAR_adr;
136138

137139
wire [7:0] CPU_DB; // Internal CPU data bus DB
138140
wire [7:0] PD; // Read-only PPU Data bus
@@ -379,7 +381,7 @@ module PPU(RnW, D, RS, n_DBE, EXT, CLK, n_INT, ALE, AD, A, n_RD, n_WR, n_RES, VO
379381
.n_ZPRIO(n_ZPRIO),
380382
.n_SH2(n_SH2) );
381383

382-
PataddrGen patgen(
384+
PAR par (
383385
.n_PCLK(n_PCLK),
384386
.H0_DD(H0_DD),
385387
.n_FNT(n_FNT),
@@ -393,25 +395,20 @@ module PPU(RnW, D, RS, n_DBE, EXT, CLK, n_INT, ALE, AD, A, n_RD, n_WR, n_RES, VO
393395
.PD(PD),
394396
.OV(OV[3:0]),
395397
.n_FVO(n_FVO),
396-
.PAddr_out(PAD) );
398+
.PAddr_out(PAD_adr) );
397399

398-
PAR par(
400+
TileCnt tilecnt (
399401
.n_PCLK(n_PCLK),
400402
.PCLK(PCLK),
401-
.BLNK(BLNK),
402-
.DB_PAR(DB_PAR),
403-
.F_AT(F_AT),
403+
.W6_2_Ena(W6_2_Ena),
404404
.SC_CNT(SC_CNT),
405405
.RESCL(RESCL),
406406
.E_EV(E_EV),
407407
.TSTEP(TSTEP),
408408
.F_TB(F_TB),
409409
.H0_DD(H0_DD),
410-
.n_H2_D(nH2_D),
411-
.I_1_32(I_1_32),
412-
.W6_2_Ena(W6_2_Ena),
413-
.PAD_in(PAD),
414-
.CPU_DB(CPU_DB),
410+
.BLNK(BLNK),
411+
.I_1_32(I_1_32),
415412
.TH(TH),
416413
.TV(TV),
417414
.NTH(NTH),
@@ -420,6 +417,19 @@ module PPU(RnW, D, RS, n_DBE, EXT, CLK, n_INT, ALE, AD, A, n_RD, n_WR, n_RES, VO
420417
.n_FVO(n_FVO),
421418
.THO(THO),
422419
.TVO(TVO),
420+
.FAT(FAT_adr),
421+
.PAR(PAR_adr) );
422+
423+
PAMUX pamux (
424+
.PCLK(PCLK),
425+
.n_H2_D(nH2_D),
426+
.BLNK(BLNK),
427+
.F_AT(F_AT),
428+
.DB_PAR(DB_PAR),
429+
.FAT_in(FAT_adr),
430+
.PAR_in(PAR_adr),
431+
.PAD_in(PAD_adr),
432+
.CPU_DB(CPU_DB),
423433
.n_PA(n_PA_out) );
424434

425435
ScrollRegs sccx(

‎HDL/PPU/regs.v‎

Lines changed: 9 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -100,8 +100,8 @@ module SCCXFirstSecond(RC, n_DBE, n_R2, n_W56, Frst, Scnd);
100100
wire W56;
101101
wire R2;
102102

103-
assign R2 = n_R2 ~| n_DBE;
104-
assign W56 = n_W56 ~| n_DBE;
103+
nor (R2, n_R2, n_DBE);
104+
nor (W56, n_W56, n_DBE);
105105

106106
sdffr2e FF_1 (.d(q2), .en(~W56), .res1(RC), .res2(R2), .phi_keep(W56), .q(q1), .nq(nq1) );
107107
sdffr2e FF_2 (.d(nq1), .en(W56), .res1(RC), .res2(R2), .phi_keep(~W56), .q(q2), .nq(nq2) );
@@ -169,7 +169,12 @@ module RWDecoder(RnW, n_DBE, n_RD, n_WR);
169169
output n_RD;
170170
output n_WR;
171171

172-
assign n_RD = ~( ~RnW ~| n_DBE );
173-
assign n_WR = ~( RnW ~| n_DBE );
172+
wire RD;
173+
wire WR;
174+
175+
nor (RD, ~RnW, n_DBE);
176+
nor (WR, RnW, n_DBE);
177+
not (n_RD, RD);
178+
not (n_WR, WR);
174179

175180
endmodule // RWDecoder

‎HDL/PPU/tilecnt.v‎

Lines changed: 33 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,33 @@
1+
module TileCnt (
2+
n_PCLK, PCLK,
3+
W6_2_Ena, SC_CNT, RESCL, E_EV, TSTEP, F_TB, H0_DD, BLNK, I_1_32,
4+
TH, TV, NTH, NTV, FV,
5+
n_FVO, THO, TVO, FAT, PAR );
6+
7+
input n_PCLK;
8+
input PCLK;
9+
10+
input W6_2_Ena;
11+
input SC_CNT;
12+
input RESCL;
13+
input E_EV;
14+
input TSTEP;
15+
input F_TB;
16+
input H0_DD;
17+
input BLNK;
18+
input I_1_32;
19+
20+
input [4:0] TH;
21+
input [4:0] TV;
22+
input NTH;
23+
input NTV;
24+
input [2:0] FV;
25+
26+
output [2:0] n_FVO;
27+
output [4:0] THO;
28+
output [4:0] TVO;
29+
30+
output [13:0] FAT;
31+
output [13:0] PAR;
32+
33+
endmodule // TileCnt

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