clk.md

Main Clock

To the right of the crosshair is one thick wire, which is the mclk signal distribution (we think so).

At the top and bottom are two special blocks, designed to distribute the amplified CLK across the entire surface of the chip.

Top mclk super buffer:

Poly	M1	M2

Bottom mclk super buffer (symmetrical to the upper one):

Poly	M1	M2
TBD

The outputs from the two super buffers are short-circuited and feed the main mclk rail.

In large scale chips, the CLK layout is usually called the Clock Tree: multiple clusters of DFF and other always (@CLK) sensitive blocks are symmetrically connected to a common CLK wire to minimize the Jitter effect.