Building on the DV1 framework and running in parallel with RTL2 and SW2, this task develops layered testbenches targeting the core datapath and packet processing components.
Verification focuses on modules introduced in RTL1 and extended in RTL2, including switching primitives, packet parsing, and metadata handling. Cocotb-based testbenches are structured to provide stimulus generation, protocol-aware checking, and functional coverage of packet flows through the processing pipeline.
Test scenarios explicitly cover heterogeneous operating conditions, such as interactions between modules with different data widths and clock domains. The verification environment reuses HAL-aligned access patterns defined in SW1 and exercised in SW2, ensuring consistency between software-visible behavior and RTL implementation.
By the end of DV2, individual modules and pipeline stages are thoroughly validated in isolation, with high confidence in correctness across a wide range of configurations.
Building on the DV1 framework and running in parallel with RTL2 and SW2, this task develops layered testbenches targeting the core datapath and packet processing components.
Verification focuses on modules introduced in RTL1 and extended in RTL2, including switching primitives, packet parsing, and metadata handling. Cocotb-based testbenches are structured to provide stimulus generation, protocol-aware checking, and functional coverage of packet flows through the processing pipeline.
Test scenarios explicitly cover heterogeneous operating conditions, such as interactions between modules with different data widths and clock domains. The verification environment reuses HAL-aligned access patterns defined in SW1 and exercised in SW2, ensuring consistency between software-visible behavior and RTL implementation.
By the end of DV2, individual modules and pipeline stages are thoroughly validated in isolation, with high confidence in correctness across a wide range of configurations.