Extending DV2 and aligned with RTL3 and SW3, this task introduces hardware/software co-verification to validate system-level behavior involving control-plane and datapath interaction.
This includes coupling the RTL simulation environment with instruction set simulators (ISS) for RISC-V platforms, enabling execution of real software (HAL and runtime API) against the simulated hardware. Register access, DMA configuration, and forwarding behavior are validated end-to-end using realistic software-driven scenarios.
The co-simulation setup leverages the same abstractions defined in SW1-SW3 and the infrastructure from DV1, ensuring continuity across the stack. Particular focus is placed on verifying correct operation under heterogeneous conditions, including synchronization across clock domains and interaction with DMA engines bridging different bus characteristics.
By the end of DV3, the combined hardware-software system is validated in simulation, demonstrating that software can reliably configure and control the NoC fabric.
Extending DV2 and aligned with RTL3 and SW3, this task introduces hardware/software co-verification to validate system-level behavior involving control-plane and datapath interaction.
This includes coupling the RTL simulation environment with instruction set simulators (ISS) for RISC-V platforms, enabling execution of real software (HAL and runtime API) against the simulated hardware. Register access, DMA configuration, and forwarding behavior are validated end-to-end using realistic software-driven scenarios.
The co-simulation setup leverages the same abstractions defined in SW1-SW3 and the infrastructure from DV1, ensuring continuity across the stack. Particular focus is placed on verifying correct operation under heterogeneous conditions, including synchronization across clock domains and interaction with DMA engines bridging different bus characteristics.
By the end of DV3, the combined hardware-software system is validated in simulation, demonstrating that software can reliably configure and control the NoC fabric.