Running in parallel with RTL4 and SW4, this task delivers a minimal but fully functional FPGA-based System-on-Chip integrating the openENOC fabric with a RISC-V processor cores.
The design reuses the complete NoC fabric assembled in RTL4 and is controlled through the HAL and runtime API developed in SW4. Integration focuses on a compact configuration suitable for low-cost FPGA platforms, including a single or small number of endpoints connected via the NoC.
The demo validates end-to-end functionality of the system, including packet movement between processing elements, basic forwarding behavior, and software-driven configuration of the fabric. Particular emphasis is placed on demonstrating correct operation across heterogeneous datapath conditions, such as differing bus widths and clock domains, as established throughout earlier work packages.
Deliverables include synthesizable designs, build scripts, and documentation enabling reproducible deployment on supported FPGA boards. By the end of DEM1, a working reference SoC is available, showcasing the viability of openENOC in a real hardware environment.
Running in parallel with RTL4 and SW4, this task delivers a minimal but fully functional FPGA-based System-on-Chip integrating the openENOC fabric with a RISC-V processor cores.
The design reuses the complete NoC fabric assembled in RTL4 and is controlled through the HAL and runtime API developed in SW4. Integration focuses on a compact configuration suitable for low-cost FPGA platforms, including a single or small number of endpoints connected via the NoC.
The demo validates end-to-end functionality of the system, including packet movement between processing elements, basic forwarding behavior, and software-driven configuration of the fabric. Particular emphasis is placed on demonstrating correct operation across heterogeneous datapath conditions, such as differing bus widths and clock domains, as established throughout earlier work packages.
Deliverables include synthesizable designs, build scripts, and documentation enabling reproducible deployment on supported FPGA boards. By the end of DEM1, a working reference SoC is available, showcasing the viability of openENOC in a real hardware environment.