Starting after DEM1 and continuing through the remainder of the project, this task expands the initial prototype into a more capable and representative demonstration platform.
The system is extended with multiple heterogeneous endpoints, such as additional processing elements, hardware accelerators, and memory interfaces, all interconnected through the openENOC fabric. External Ethernet connectivity is introduced, enabling interaction between the on-chip network and off-chip systems, effectively bridging NoC and standard networking environments.
This stage leverages the full software stack, including the runtime API and reference applications, to demonstrate realistic use cases such as data streaming, offload to accelerators, and multi-node communication patterns. The platform is also aligned with the verification infrastructure from WP3, enabling continuous validation on real hardware.
Deliverables include a complete FPGA reference design, integration guides, and demonstrator applications suitable for both evaluation and educational use. By the end of DEM2, the platform serves as a comprehensive showcase of openENOC capabilities, illustrating how a scalable, Ethernet-based NoC can be deployed in practical MPSoC systems and extended beyond the chip boundary.
Starting after DEM1 and continuing through the remainder of the project, this task expands the initial prototype into a more capable and representative demonstration platform.
The system is extended with multiple heterogeneous endpoints, such as additional processing elements, hardware accelerators, and memory interfaces, all interconnected through the openENOC fabric. External Ethernet connectivity is introduced, enabling interaction between the on-chip network and off-chip systems, effectively bridging NoC and standard networking environments.
This stage leverages the full software stack, including the runtime API and reference applications, to demonstrate realistic use cases such as data streaming, offload to accelerators, and multi-node communication patterns. The platform is also aligned with the verification infrastructure from WP3, enabling continuous validation on real hardware.
Deliverables include a complete FPGA reference design, integration guides, and demonstrator applications suitable for both evaluation and educational use. By the end of DEM2, the platform serves as a comprehensive showcase of openENOC capabilities, illustrating how a scalable, Ethernet-based NoC can be deployed in practical MPSoC systems and extended beyond the chip boundary.