Starting in parallel with RTL4, SW4, DV4, and DEM1, and continuing until the completion of the core development cycle, this task focuses on usability and onboarding.
It delivers step-by-step tutorials and developer guides that demonstrate how to work with the project across its full stack. This includes setting up the simulation environment (DV1-DV3), running verification workflows, interacting with the HAL and runtime API, and deploying designs on FPGA platforms as introduced in DEM1.
The guides are designed to bridge the gap between documentation and practice, using concrete examples and reference applications (SW4) to illustrate common workflows such as packet switching, DMA-based data movement, and integration of custom endpoints.
By the end of DOC3, new users can reproducibly simulate, build, and deploy the openENOC system, lowering the barrier to adoption and contribution.
Starting in parallel with RTL4, SW4, DV4, and DEM1, and continuing until the completion of the core development cycle, this task focuses on usability and onboarding.
It delivers step-by-step tutorials and developer guides that demonstrate how to work with the project across its full stack. This includes setting up the simulation environment (DV1-DV3), running verification workflows, interacting with the HAL and runtime API, and deploying designs on FPGA platforms as introduced in DEM1.
The guides are designed to bridge the gap between documentation and practice, using concrete examples and reference applications (SW4) to illustrate common workflows such as packet switching, DMA-based data movement, and integration of custom endpoints.
By the end of DOC3, new users can reproducibly simulate, build, and deploy the openENOC system, lowering the barrier to adoption and contribution.