Starting in the middle phase of RTL4, SW4, and DV4, this task integrates the openENOC RTL design into a fully open-source synthesis flow. The primary goal is to establish a functional and reproducible hardware compilation pipeline using FOSS tools such as Yosys and target FPGA technology mappings (e.g. openXC7).
The integration focuses on ensuring that the modular NoC architecture developed in RTL1-RTL4 can be correctly synthesized without reliance on proprietary tooling. This includes resolving mapping constraints for heterogeneous datapaths, validating synthesis compatibility of CDC structures, and ensuring that parameterized configurations (e.g. bus widths and port counts) are correctly handled by the synthesis flow.
PNR1 is closely aligned with ongoing verification (DV4) and FPGA prototyping (DEM1), enabling early validation of synthesis results against simulation and initial hardware builds. The outcome of this task is a working end-to-end open synthesis flow capable of producing synthesizable netlists for the openENOC system using only open-source tools.
Starting in the middle phase of RTL4, SW4, and DV4, this task integrates the openENOC RTL design into a fully open-source synthesis flow. The primary goal is to establish a functional and reproducible hardware compilation pipeline using FOSS tools such as Yosys and target FPGA technology mappings (e.g. openXC7).
The integration focuses on ensuring that the modular NoC architecture developed in RTL1-RTL4 can be correctly synthesized without reliance on proprietary tooling. This includes resolving mapping constraints for heterogeneous datapaths, validating synthesis compatibility of CDC structures, and ensuring that parameterized configurations (e.g. bus widths and port counts) are correctly handled by the synthesis flow.
PNR1 is closely aligned with ongoing verification (DV4) and FPGA prototyping (DEM1), enabling early validation of synthesis results against simulation and initial hardware builds. The outcome of this task is a working end-to-end open synthesis flow capable of producing synthesizable netlists for the openENOC system using only open-source tools.