Starting after the establishment of PNR1 and continuing until the end of the project, this task delivers a fully automated place-and-route and bitstream generation infrastructure.
Building on Yosys and openXC7/nextpnr, this stage introduces CI-integrated workflows for generating FPGA bitstreams in a reproducible and deterministic manner. The flow is tightly coupled with the verification infrastructure (DV4) and hardware demonstrations (DEM2), ensuring that every verified configuration can be directly mapped to a buildable hardware image.
Automation includes parameterized builds for different FPGA targets, integration of constraint management for heterogeneous NoC configurations, and regression-based validation of generated bitstreams against simulation results. The system is designed to support continuous integration, allowing every change in RTL, software, or verification infrastructure to be propagated through synthesis and implementation pipelines.
The outcome of PNR2 is a robust, fully open-source hardware build system that enables continuous, reproducible generation of FPGA images for the openENOC platform, closing the loop between design, verification, and deployment.
Starting after the establishment of PNR1 and continuing until the end of the project, this task delivers a fully automated place-and-route and bitstream generation infrastructure.
Building on Yosys and openXC7/nextpnr, this stage introduces CI-integrated workflows for generating FPGA bitstreams in a reproducible and deterministic manner. The flow is tightly coupled with the verification infrastructure (DV4) and hardware demonstrations (DEM2), ensuring that every verified configuration can be directly mapped to a buildable hardware image.
Automation includes parameterized builds for different FPGA targets, integration of constraint management for heterogeneous NoC configurations, and regression-based validation of generated bitstreams against simulation results. The system is designed to support continuous integration, allowing every change in RTL, software, or verification infrastructure to be propagated through synthesis and implementation pipelines.
The outcome of PNR2 is a robust, fully open-source hardware build system that enables continuous, reproducible generation of FPGA images for the openENOC platform, closing the loop between design, verification, and deployment.