Merge pull request #400 from enjoy-digital/fix-a7-ddr3-read-alignment

phy: Align Artix-7 DDR3 reads without altering CL

Author: enjoy-digital

litedram/phy/s7ddrphy.py

@@ -70,6 +70,13 @@ def __init__(self, pads, with_odelay,
         rdphase         = get_sys_phase(nphases, cl_sys_latency,   cl + cmd_latency)
         wrphase         = get_sys_phase(nphases, cwl_sys_latency, cwl + cmd_latency)
 
+        # Artix-7 requires read data one memory-clock phase into the ISERDESE2 word for reliable
+        # read leveling. This was previously achieved by programming CL + 1 in the DDR3 MR0. Keep
+        # the configured CL unchanged and express the compensation in the PHY schedule instead.
+        if (memtype == "DDR3") and (not with_odelay):
+            phase_cycles, rdphase = divmod(rdphase + 1, nphases)
+            cl_sys_latency -= phase_cycles
+
         # Registers --------------------------------------------------------------------------------
         self._rst             = CSRStorage()
 
@@ -121,12 +128,6 @@ def cdc(i):
         wdly_dq_bitslip_rst  = cdc(self._wdly_dq_bitslip_rst.wr_stb)
         wdly_dq_bitslip  = cdc(self._wdly_dq_bitslip.wr_stb)
 
-        # PHY settings -----------------------------------------------------------------------------
-        if (memtype == "DDR3") and (not with_odelay):
-            # DDR3 Write leveling is not possible on Artix7 due to the lack of ODELAYE2, adding +1
-            # to cl in MR register increases sys_clk_freq range.
-            cl += 1
-
         # Some calibrations like write_leveling or latency calibration are not supported
         # for DDR2 chip.
         write_calibrations = (with_odelay and (memtype not in ["DDR2"]))

test/test_s7ddrphy.py

@@ -0,0 +1,106 @@
+#
+# This file is part of LiteDRAM.
+#
+# Copyright (c) 2026 Florent Kermarrec <florent@enjoy-digital.fr>
+# SPDX-License-Identifier: BSD-2-Clause
+
+import unittest
+from types import SimpleNamespace
+
+from migen import *
+
+from litedram.common import get_default_cl
+from litedram.init import get_ddr3_phy_init_sequence
+from litedram.phy.s7ddrphy import A7DDRPHY, K7DDRPHY
+
+
+class TestS7DDRPHYSettings(unittest.TestCase):
+    sys_clk_freqs       = [50e6, 100e6, 125e6, 150e6, 175e6, 225e6]
+    ddr3_cls            = range(5, 15)
+    read_pipeline_cycles = 6
+
+    @staticmethod
+    def get_pads():
+        return Record([
+            ("a",       15),
+            ("ba",       3),
+            ("ras_n",    1),
+            ("cas_n",    1),
+            ("we_n",     1),
+            ("clk_p",    1),
+            ("clk_n",    1),
+            ("dq",       8),
+            ("dm",       1),
+            ("dqs_p",    1),
+            ("dqs_n",    1),
+        ])
+
+    @staticmethod
+    def get_rdphase(phy):
+        return phy.settings.rdphase.reset.value
+
+    @staticmethod
+    def get_mr0_cl(phy):
+        init_sequence, _ = get_ddr3_phy_init_sequence(
+            phy_settings    = phy.settings,
+            timing_settings = SimpleNamespace(tWTR=2),
+        )
+        mr0 = next(address for comment, address, _, _, _ in init_sequence
+            if comment.startswith("Load Mode Register 0"))
+        mr0_to_cl = {
+            0b0010 :  5,
+            0b0100 :  6,
+            0b0110 :  7,
+            0b1000 :  8,
+            0b1010 :  9,
+            0b1100 : 10,
+            0b1110 : 11,
+            0b0001 : 12,
+            0b0011 : 13,
+            0b0101 : 14,
+        }
+        mr0_cl = ((mr0 >> 2) & 0b1) | (((mr0 >> 4) & 0b111) << 1)
+        return mr0_to_cl[mr0_cl]
+
+    def test_a7_default_cl_is_preserved(self):
+        for sys_clk_freq in self.sys_clk_freqs:
+            with self.subTest(sys_clk_freq=sys_clk_freq):
+                phy         = A7DDRPHY(self.get_pads(), sys_clk_freq=sys_clk_freq)
+                tck         = 1/(4*sys_clk_freq)
+                expected_cl = get_default_cl("DDR3", tck)
+
+                self.assertEqual(phy.settings.cl, expected_cl)
+                self.assertEqual(self.get_mr0_cl(phy), expected_cl)
+
+    def test_a7_read_alignment(self):
+        for cl in self.ddr3_cls:
+            for cmd_latency in range(3):
+                with self.subTest(cl=cl, cmd_latency=cmd_latency):
+                    phy = A7DDRPHY(self.get_pads(),
+                        sys_clk_freq = 100e6,
+                        cl           = cl,
+                        cmd_latency  = cmd_latency,
+                    )
+                    rdphase          = self.get_rdphase(phy)
+                    read_sys_latency = phy.settings.read_latency - self.read_pipeline_cycles
+
+                    self.assertEqual(phy.settings.cl, cl)
+                    self.assertEqual(self.get_mr0_cl(phy), cl)
+                    self.assertEqual(
+                        rdphase + cl + cmd_latency,
+                        read_sys_latency*phy.settings.nphases + 1,
+                    )
+
+    def test_k7_read_alignment_is_unchanged(self):
+        for cl in self.ddr3_cls:
+            with self.subTest(cl=cl):
+                phy              = K7DDRPHY(self.get_pads(), sys_clk_freq=100e6, cl=cl)
+                rdphase          = self.get_rdphase(phy)
+                read_sys_latency = phy.settings.read_latency - self.read_pipeline_cycles
+
+                self.assertEqual(phy.settings.cl, cl)
+                self.assertEqual(self.get_mr0_cl(phy), cl)
+                self.assertEqual(
+                    rdphase + cl,
+                    read_sys_latency*phy.settings.nphases,
+                )