3 output tests now pass

Author: erangell

.DS_Store

@@ -55,6 +55,8 @@ P,PA7,1,PA6,0,PA5,1,PA4,0,PA3,1,PA2,0,PA1,1,PA0,0
 *Set CA0 to signal that data is ready
 P,CA0,1
 D,500
+P,CA1,0
+D,500
 
 *Set RW to Read mode.
 P,RW,1
@@ -83,6 +85,8 @@ P,PA7,0,PA6,1,PA5,0,PA4,1,PA3,0,PA2,1,PA1,0,PA0,1
 *Set CA0 to signal that data is ready
 P,CA0,1
 D,500
+P,CA1,0
+D,500
 
 *Pulse clock to latch the data
 P,CLK,1

SDCard/.DS_Store

@@ -36,17 +36,17 @@ P,CLK,1
 D,500
 P,CLK,0
 D,500
-* write 10101010 to ORA register 2
-P,A3,0,A2,0,A1,1,A0,0
+* write 10101010 to ORA register 1
+P,A3,0,A2,0,A1,0,A0,1
 P,D7,1,D6,0,D5,1,D4,0,D3,1,D2,0,D1,1,D0,0
 * expect port pins to be set 
 P,CLK,1
 D,500
 P,CLK,0
 D,500
 E,PA7,1,PA6,0,PA5,1,PA4,0,PA3,1,PA2,0,PA1,1,PA0,0
-* write 01010101 to ORA register 2
-P,A3,0,A2,0,A1,1,A0,0
+* write 01010101 to ORA register 1
+P,A3,0,A2,0,A1,0,A0,1
 P,D7,0,D6,1,D5,0,D4,1,D3,0,D2,1,D1,0,D0,1
 * expect port pins to be set 
 P,CLK,1

SDCard/T6522/T020R01I.csv

@@ -28,31 +28,31 @@ P,CLK,1
 D,500
 P,CLK,0
 
-*Set Data Direction Register A to store data in chip
-* Write $FF to DDRA Register 3 
-P,A3,0,A2,0,A1,1,A0,1
+*Set Data Direction Register B to store data in chip
+* Write $FF to DDRA Register 2 
+P,A3,0,A2,0,A1,1,A0,0
 P,D0,1,D1,1,D2,1,D3,1,D4,1,D5,1,D6,1,D7,1
 P,CLK,1
 D,500
 P,CLK,0
 D,500
-* write 10101010 to ORA register 1
-P,A3,0,A2,0,A1,0,A0,1
+* write 10101010 to ORB register 0
+P,A3,0,A2,0,A1,0,A0,0
 P,D7,1,D6,0,D5,1,D4,0,D3,1,D2,0,D1,1,D0,0
 * expect port pins to be set 
 P,CLK,1
 D,500
 P,CLK,0
 D,500
-E,PA7,1,PA6,0,PA5,1,PA4,0,PA3,1,PA2,0,PA1,1,PA0,0
-* write 01010101 to ORA register 1
-P,A3,0,A2,0,A1,0,A0,1
+E,PB7,1,PB6,0,PB5,1,PB4,0,PB3,1,PB2,0,PB1,1,PB0,0
+* write 01010101 to ORB register 0
+P,A3,0,A2,0,A1,0,A0,0
 P,D7,0,D6,1,D5,0,D4,1,D3,0,D2,1,D1,0,D0,1
 * expect port pins to be set 
 P,CLK,1
 D,500
 P,CLK,0
 D,500
-E,PA7,0,PA6,1,PA5,0,PA4,1,PA3,0,PA2,1,PA1,0,PA0,1
+E,PB7,0,PB6,1,PB5,0,PB4,1,PB3,0,PB2,1,PB1,0,PB0,1
 *Set RW to Read mode.
 P,RW,1