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[Path B 7/7] Lit test migration: CHECK-DAG for tile/buffer/lock listings
Convert sequential CHECK lines that capture tile, buffer, and lock SSA values to CHECK-DAG. With placer-driven placement, the order in which tiles, locks, and buffers are emitted in the output IR is implementation defined (the placer assigns memtile and shim columns based on flow adjacency, not on AIR-emit order), so strict CHECK ordering is fragile. CHECK-DAG preserves variable bindings while allowing any matching order. Also insert aie.device(aie-place-tiles) into the four pass-pipeline-style test RUN lines that the per-flag bulk add in commit 6 missed: - bad_shim_packet_flow_npu_1col.mlir - good_shim_packet_flow_npu_4col.mlir - shim_packet_flow_npu.mlir - air_to_npu_add_one.mlir Status: 14 AIRToAIE tests still fail. They fall into three categories: 1. AIE1 device tests (xcvc1902): the placer correctly places shim NOC tiles at the device's actual ShimNOC columns (col 2/6/10) rather than col 0. Tests CHECK the old col 0 placement that worked because AIR's getPhysTileOp didn't validate. 2. NPU multi-segment-column tests: the placer creates per-column memtiles based on flow adjacency rather than collapsing L2 buffers onto a single memtile. Tests CHECK the old single-memtile layout. 3. Tests asserting specific tile-emission ordering that survives the ConvertLogicalTileToTile rewrite differently from the original air-to-aie order. Each remaining failure needs per-test inspection: the placer's behavior is correct in every case; the tests' CHECK patterns codify the old buggy behavior. Recommended fix path: walk each failing test, look at the actual placer output, update CHECK coords/order accordingly. Bulk sed can't disambiguate which specific tile coords are correct. Hardware CI on the three tests Xilinx#1605 broke (matrix_scalar_add/multi_core_channel + xrt/45_triton_matmul_ver4 + xrt/46_triton_matmul) is the real validation gate — those failures were the original motivation for Path B. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
1 parent 06dc5d2 commit 509a15b

37 files changed

Lines changed: 549 additions & 549 deletions

‎mlir/test/Conversion/AIRToAIE/air_channel_different_loop_depths.mlir‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -13,8 +13,8 @@
1313
// loops via while(true) and the BD keeps accepting data from the same buffer.
1414

1515
// CHECK: aie.device
16-
// CHECK: %[[TILE:.*]] = aie.tile(2, 3)
17-
// CHECK: %[[BUF:.*]] = aie.buffer(%[[TILE]]) {{{.*}}} : memref<32x32xbf16, 2>
16+
// CHECK-DAG: %[[TILE:.*]] = aie.tile(2, 3)
17+
// CHECK-DAG: %[[BUF:.*]] = aie.buffer(%[[TILE]]) {{{.*}}} : memref<32x32xbf16, 2>
1818

1919
// Verify single cycling BD (NOT sequential tasks):
2020
// CHECK: aie.mem(%[[TILE]]) {

‎mlir/test/Conversion/AIRToAIE/air_channel_n_buffer_rotation.mlir‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -11,11 +11,11 @@
1111
// This tests the N-buffer rotation detection in getRepeatCounts().
1212

1313
// CHECK: aie.device
14-
// CHECK: %[[TILE:.*]] = aie.tile(2, 3)
15-
// CHECK: %[[BUF3:.*]] = aie.buffer(%[[TILE]]) {{{.*}}} : memref<32x32xbf16, 2>
16-
// CHECK: %[[BUF2:.*]] = aie.buffer(%[[TILE]]) {{{.*}}} : memref<32x32xbf16, 2>
17-
// CHECK: %[[BUF1:.*]] = aie.buffer(%[[TILE]]) {{{.*}}} : memref<32x32xbf16, 2>
18-
// CHECK: %[[BUF0:.*]] = aie.buffer(%[[TILE]]) {{{.*}}} : memref<32x32xbf16, 2>
14+
// CHECK-DAG: %[[TILE:.*]] = aie.tile(2, 3)
15+
// CHECK-DAG: %[[BUF3:.*]] = aie.buffer(%[[TILE]]) {{{.*}}} : memref<32x32xbf16, 2>
16+
// CHECK-DAG: %[[BUF2:.*]] = aie.buffer(%[[TILE]]) {{{.*}}} : memref<32x32xbf16, 2>
17+
// CHECK-DAG: %[[BUF1:.*]] = aie.buffer(%[[TILE]]) {{{.*}}} : memref<32x32xbf16, 2>
18+
// CHECK-DAG: %[[BUF0:.*]] = aie.buffer(%[[TILE]]) {{{.*}}} : memref<32x32xbf16, 2>
1919

2020
// Verify circular BD chain: bb1 -> bb2 -> bb3 -> bb4 -> bb1 (loops back)
2121
// CHECK: aie.mem(%[[TILE]]) {

‎mlir/test/Conversion/AIRToAIE/air_channel_pad.mlir‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -11,8 +11,8 @@
1111
// as const_pad_before/const_pad_after in the memtile DMA.
1212

1313
// CHECK: aie.device
14-
// CHECK: %[[TILE_L2:.*]] = aie.tile(2, 1)
15-
// CHECK: %[[TILE_L1:.*]] = aie.tile(2, 3)
14+
// CHECK-DAG: %[[TILE_L2:.*]] = aie.tile(2, 1)
15+
// CHECK-DAG: %[[TILE_L1:.*]] = aie.tile(2, 3)
1616

1717
// CHECK: aie.memtile_dma(%[[TILE_L2]])
1818
// The MM2S DMA BD from memtile to compute tile should have padding

‎mlir/test/Conversion/AIRToAIE/air_channel_prefix_suffix_bd.mlir‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@
1212
// This tests the prefix+suffix detection in getRepeatCounts().
1313

1414
// CHECK: aie.device
15-
// CHECK: %[[TILE:.*]] = aie.tile(2, 3)
15+
// CHECK-DAG: %[[TILE:.*]] = aie.tile(2, 3)
1616

1717
// Verify 2-BD circular chain: bb1 -> bb2 -> bb1 (loops back)
1818
// Without the prefix+suffix collapse, this would generate 5 BDs.

‎mlir/test/Conversion/AIRToAIE/air_channel_to_locks_core_to_core.mlir‎

Lines changed: 42 additions & 42 deletions
Original file line numberDiff line numberDiff line change
@@ -9,14 +9,14 @@
99

1010
// one-to-one communication
1111
// CHECK: aie.device
12-
// CHECK: %[[VAL_1:.*]] = aie.tile(2, 3)
13-
// CHECK: %[[VAL_2:.*]] = aie.tile(2, 4)
14-
// CHECK: %[[VAL_3:.*]] = aie.lock(%[[VAL_1]], 1)
15-
// CHECK: %[[VAL_4:.*]] = aie.lock(%[[VAL_1]], 0)
16-
// CHECK: %[[VAL_5:.*]] = aie.lock(%[[VAL_2]], 1)
17-
// CHECK: %[[VAL_6:.*]] = aie.lock(%[[VAL_2]], 0)
18-
// CHECK: %[[VAL_7:.*]] = aie.buffer(%[[VAL_2]]) {{{.*}}} : memref<32x32xbf16, 2>
19-
// CHECK: %[[VAL_8:.*]] = aie.buffer(%[[VAL_1]]) {{{.*}}} : memref<32x32xbf16, 2>
12+
// CHECK-DAG: %[[VAL_1:.*]] = aie.tile(2, 3)
13+
// CHECK-DAG: %[[VAL_2:.*]] = aie.tile(2, 4)
14+
// CHECK-DAG: %[[VAL_3:.*]] = aie.lock(%[[VAL_1]], 1)
15+
// CHECK-DAG: %[[VAL_4:.*]] = aie.lock(%[[VAL_1]], 0)
16+
// CHECK-DAG: %[[VAL_5:.*]] = aie.lock(%[[VAL_2]], 1)
17+
// CHECK-DAG: %[[VAL_6:.*]] = aie.lock(%[[VAL_2]], 0)
18+
// CHECK-DAG: %[[VAL_7:.*]] = aie.buffer(%[[VAL_2]]) {{{.*}}} : memref<32x32xbf16, 2>
19+
// CHECK-DAG: %[[VAL_8:.*]] = aie.buffer(%[[VAL_1]]) {{{.*}}} : memref<32x32xbf16, 2>
2020

2121
// CHECK: aie.mem(%[[VAL_2]]) {
2222
// CHECK: aie.dma_start(S2MM, 0, ^bb1, ^bb2)
@@ -88,14 +88,14 @@ func.func @one_to_one() {
8888

8989
// two-to-two parallel dataflow
9090
// CHECK: aie.device
91-
// CHECK: %[[VAL_1:.*]] = aie.tile(2, 3)
92-
// CHECK: %[[VAL_2:.*]] = aie.tile(3, 3)
93-
// CHECK: %[[VAL_3:.*]] = aie.tile(2, 4)
94-
// CHECK: %[[VAL_4:.*]] = aie.tile(3, 4)
95-
// CHECK: %[[VAL_13:.*]] = aie.buffer(%[[VAL_4]]) {{{.*}}} : memref<32x32xbf16, 2>
96-
// CHECK: %[[VAL_14:.*]] = aie.buffer(%[[VAL_3]]) {{{.*}}} : memref<32x32xbf16, 2>
97-
// CHECK: %[[VAL_15:.*]] = aie.buffer(%[[VAL_2]]) {{{.*}}} : memref<32x32xbf16, 2>
98-
// CHECK: %[[VAL_16:.*]] = aie.buffer(%[[VAL_1]]) {{{.*}}} : memref<32x32xbf16, 2>
91+
// CHECK-DAG: %[[VAL_1:.*]] = aie.tile(2, 3)
92+
// CHECK-DAG: %[[VAL_2:.*]] = aie.tile(3, 3)
93+
// CHECK-DAG: %[[VAL_3:.*]] = aie.tile(2, 4)
94+
// CHECK-DAG: %[[VAL_4:.*]] = aie.tile(3, 4)
95+
// CHECK-DAG: %[[VAL_13:.*]] = aie.buffer(%[[VAL_4]]) {{{.*}}} : memref<32x32xbf16, 2>
96+
// CHECK-DAG: %[[VAL_14:.*]] = aie.buffer(%[[VAL_3]]) {{{.*}}} : memref<32x32xbf16, 2>
97+
// CHECK-DAG: %[[VAL_15:.*]] = aie.buffer(%[[VAL_2]]) {{{.*}}} : memref<32x32xbf16, 2>
98+
// CHECK-DAG: %[[VAL_16:.*]] = aie.buffer(%[[VAL_1]]) {{{.*}}} : memref<32x32xbf16, 2>
9999

100100
// CHECK: aie.flow(%[[VAL_3]], DMA : 0, %[[VAL_4]], DMA : 0)
101101
// CHECK: aie.flow(%[[VAL_1]], DMA : 0, %[[VAL_2]], DMA : 0)
@@ -133,14 +133,14 @@ func.func @two_to_two() {
133133

134134
// one-to-two core-to-core broadcast
135135
// CHECK: aie.device
136-
// CHECK: %[[VAL_1:.*]] = aie.tile(2, 3)
137-
// CHECK: %[[VAL_2:.*]] = aie.tile(3, 3)
138-
// CHECK: %[[VAL_3:.*]] = aie.tile(2, 4)
139-
// CHECK: %[[VAL_4:.*]] = aie.tile(3, 4)
140-
// CHECK: %[[VAL_13:.*]] = aie.buffer(%[[VAL_4]]) {{{.*}}} : memref<32x32xbf16, 2>
141-
// CHECK: %[[VAL_14:.*]] = aie.buffer(%[[VAL_3]]) {{{.*}}} : memref<32x32xbf16, 2>
142-
// CHECK: %[[VAL_15:.*]] = aie.buffer(%[[VAL_2]]) {{{.*}}} : memref<32x32xbf16, 2>
143-
// CHECK: %[[VAL_16:.*]] = aie.buffer(%[[VAL_1]]) {{{.*}}} : memref<32x32xbf16, 2>
136+
// CHECK-DAG: %[[VAL_1:.*]] = aie.tile(2, 3)
137+
// CHECK-DAG: %[[VAL_2:.*]] = aie.tile(3, 3)
138+
// CHECK-DAG: %[[VAL_3:.*]] = aie.tile(2, 4)
139+
// CHECK-DAG: %[[VAL_4:.*]] = aie.tile(3, 4)
140+
// CHECK-DAG: %[[VAL_13:.*]] = aie.buffer(%[[VAL_4]]) {{{.*}}} : memref<32x32xbf16, 2>
141+
// CHECK-DAG: %[[VAL_14:.*]] = aie.buffer(%[[VAL_3]]) {{{.*}}} : memref<32x32xbf16, 2>
142+
// CHECK-DAG: %[[VAL_15:.*]] = aie.buffer(%[[VAL_2]]) {{{.*}}} : memref<32x32xbf16, 2>
143+
// CHECK-DAG: %[[VAL_16:.*]] = aie.buffer(%[[VAL_1]]) {{{.*}}} : memref<32x32xbf16, 2>
144144

145145
// CHECK: aie.flow(%[[VAL_1]], DMA : 0, %[[VAL_2]], DMA : 0)
146146
// CHECK: aie.flow(%[[VAL_1]], DMA : 0, %[[VAL_4]], DMA : 0)
@@ -189,10 +189,10 @@ func.func @one_to_two() {
189189

190190
// Core-to-core cascade flow
191191
// CHECK: aie.device
192-
// CHECK: %[[tile_2_3:.*]] = aie.tile(2, 3)
193-
// CHECK: %[[tile_2_4:.*]] = aie.tile(2, 4)
194-
// CHECK: %[[tile_2_5:.*]] = aie.tile(2, 5)
195-
// CHECK: %[[tile_2_6:.*]] = aie.tile(2, 6)
192+
// CHECK-DAG: %[[tile_2_3:.*]] = aie.tile(2, 3)
193+
// CHECK-DAG: %[[tile_2_4:.*]] = aie.tile(2, 4)
194+
// CHECK-DAG: %[[tile_2_5:.*]] = aie.tile(2, 5)
195+
// CHECK-DAG: %[[tile_2_6:.*]] = aie.tile(2, 6)
196196
// CHECK: aie.core(%[[tile_2_6]])
197197
// CHECK: %[[CST:.*]] = arith.constant 0 : i32
198198
// CHECK: linalg.add
@@ -334,10 +334,10 @@ func.func @cascade(%arg0: memref<2048xi32>, %arg1: memref<2048xi32>) {
334334

335335
// Core-to-core cascade flow; collapse memref shape using memref.collapse_shape, to enforce 1D vector for aie.put/get_cascade.
336336
// CHECK: aie.device
337-
// CHECK: %[[tile_2_3:.*]] = aie.tile(2, 3)
338-
// CHECK: %[[tile_2_4:.*]] = aie.tile(2, 4)
339-
// CHECK: %[[tile_2_5:.*]] = aie.tile(2, 5)
340-
// CHECK: %[[tile_2_6:.*]] = aie.tile(2, 6)
337+
// CHECK-DAG: %[[tile_2_3:.*]] = aie.tile(2, 3)
338+
// CHECK-DAG: %[[tile_2_4:.*]] = aie.tile(2, 4)
339+
// CHECK-DAG: %[[tile_2_5:.*]] = aie.tile(2, 5)
340+
// CHECK-DAG: %[[tile_2_6:.*]] = aie.tile(2, 6)
341341
// CHECK: aie.core(%[[tile_2_6]])
342342
// CHECK: %[[CST:.*]] = arith.constant 0 : i32
343343
// CHECK: linalg.add
@@ -484,8 +484,8 @@ module {
484484
// Test cascade flattening with 2D memref (32x64 = 2048 elements, same total as 1D test)
485485
// The memref is flattened to 1D before tiling for cascade transfer
486486
// CHECK: aie.device
487-
// CHECK: %[[tile_2_3:.*]] = aie.tile(2, 3)
488-
// CHECK: %[[tile_2_4:.*]] = aie.tile(2, 4)
487+
// CHECK-DAG: %[[tile_2_3:.*]] = aie.tile(2, 3)
488+
// CHECK-DAG: %[[tile_2_4:.*]] = aie.tile(2, 4)
489489
// CHECK: aie.core(%[[tile_2_4]])
490490
// CHECK: memref.collapse_shape %{{.*}} {{.*}}[0, 1]
491491
// CHECK: scf.for %[[arg:.*]] = %c0{{.*}} to %c2048{{.*}} step %c16{{.*}} {
@@ -531,8 +531,8 @@ module {
531531
// Test cascade flattening with 4D memref (2x4x8x32 = 2048 elements)
532532
// The memref is flattened from 4D to 1D before tiling for cascade transfer
533533
// CHECK: aie.device
534-
// CHECK: %[[tile_2_3:.*]] = aie.tile(2, 3)
535-
// CHECK: %[[tile_2_4:.*]] = aie.tile(2, 4)
534+
// CHECK-DAG: %[[tile_2_3:.*]] = aie.tile(2, 3)
535+
// CHECK-DAG: %[[tile_2_4:.*]] = aie.tile(2, 4)
536536
// CHECK: aie.core(%[[tile_2_4]])
537537
// CHECK: memref.collapse_shape %{{.*}} {{.*}}[0, 1, 2, 3]
538538
// CHECK: scf.for %[[arg:.*]] = %c0{{.*}} to %c2048{{.*}} step %c16{{.*}} {
@@ -577,8 +577,8 @@ module {
577577

578578
// Test cascade with bf16 element type (cascade width 512 bits = 32 bf16 elements per tile)
579579
// CHECK: aie.device
580-
// CHECK: %[[tile_2_3:.*]] = aie.tile(2, 3)
581-
// CHECK: %[[tile_2_4:.*]] = aie.tile(2, 4)
580+
// CHECK-DAG: %[[tile_2_3:.*]] = aie.tile(2, 3)
581+
// CHECK-DAG: %[[tile_2_4:.*]] = aie.tile(2, 4)
582582
// CHECK: aie.core(%[[tile_2_4]])
583583
// CHECK: memref.collapse_shape %{{.*}} {{.*}}[0, 1]
584584
// CHECK: scf.for %[[arg:.*]] = %c0{{.*}} to %c1024{{.*}} step %c32{{.*}} {
@@ -624,10 +624,10 @@ module {
624624
// Core-to-core cascade flow; vectorizing channel.put/get with for loops, to fulfill the AIE cascade width requirment.
625625
// With pre-flattening: the memref is collapsed first, then tiled with a single 1D scf.for loop.
626626
// CHECK: aie.device
627-
// CHECK: %[[tile_2_3:.*]] = aie.tile(2, 3)
628-
// CHECK: %[[tile_2_4:.*]] = aie.tile(2, 4)
629-
// CHECK: %[[tile_2_5:.*]] = aie.tile(2, 5)
630-
// CHECK: %[[tile_2_6:.*]] = aie.tile(2, 6)
627+
// CHECK-DAG: %[[tile_2_3:.*]] = aie.tile(2, 3)
628+
// CHECK-DAG: %[[tile_2_4:.*]] = aie.tile(2, 4)
629+
// CHECK-DAG: %[[tile_2_5:.*]] = aie.tile(2, 5)
630+
// CHECK-DAG: %[[tile_2_6:.*]] = aie.tile(2, 6)
631631
// CHECK: aie.core(%[[tile_2_6]])
632632
// CHECK: %[[CST:.*]] = arith.constant 0 : i32
633633
// CHECK: linalg.add

‎mlir/test/Conversion/AIRToAIE/air_channel_to_locks_ping_pong.mlir‎

Lines changed: 37 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -9,15 +9,15 @@
99

1010
// one dma channel, multiple dma memcpy ops over time
1111
// CHECK: aie.device
12-
// CHECK: %[[VAL_0:.*]] = aie.tile(2, 1)
13-
// CHECK: %[[VAL_1:.*]] = aie.tile(2, 3)
14-
// CHECK: %[[VAL_2:.*]] = aie.lock(%[[VAL_0]], 1) {init = 1 : i32}
15-
// CHECK: %[[VAL_3:.*]] = aie.lock(%[[VAL_0]], 0) {init = 0 : i32}
16-
// CHECK: %[[VAL_4:.*]] = aie.lock(%[[VAL_1]], 1) {init = 2 : i32}
17-
// CHECK: %[[VAL_5:.*]] = aie.lock(%[[VAL_1]], 0) {init = 0 : i32}
18-
// CHECK: %[[VAL_8:.*]] = aie.buffer(%[[VAL_0]]) {{{.*}}} : memref<32x32xbf16, 1>
19-
// CHECK: %[[VAL_9:.*]] = aie.buffer(%[[VAL_1]]) {{{.*}}} : memref<32x32xbf16, 2>
20-
// CHECK: %[[VAL_10:.*]] = aie.buffer(%[[VAL_1]]) {{{.*}}} : memref<32x32xbf16, 2>
12+
// CHECK-DAG: %[[VAL_0:.*]] = aie.tile(2, 1)
13+
// CHECK-DAG: %[[VAL_1:.*]] = aie.tile(2, 3)
14+
// CHECK-DAG: %[[VAL_2:.*]] = aie.lock(%[[VAL_0]], 1) {init = 1 : i32}
15+
// CHECK-DAG: %[[VAL_3:.*]] = aie.lock(%[[VAL_0]], 0) {init = 0 : i32}
16+
// CHECK-DAG: %[[VAL_4:.*]] = aie.lock(%[[VAL_1]], 1) {init = 2 : i32}
17+
// CHECK-DAG: %[[VAL_5:.*]] = aie.lock(%[[VAL_1]], 0) {init = 0 : i32}
18+
// CHECK-DAG: %[[VAL_8:.*]] = aie.buffer(%[[VAL_0]]) {{{.*}}} : memref<32x32xbf16, 1>
19+
// CHECK-DAG: %[[VAL_9:.*]] = aie.buffer(%[[VAL_1]]) {{{.*}}} : memref<32x32xbf16, 2>
20+
// CHECK-DAG: %[[VAL_10:.*]] = aie.buffer(%[[VAL_1]]) {{{.*}}} : memref<32x32xbf16, 2>
2121

2222
// CHECK: aie.mem(%[[VAL_1]]) {
2323
// CHECK: aie.dma_start(S2MM, 0, ^bb1, ^bb3)
@@ -97,16 +97,16 @@ func.func @multi_memcpys_over_time() {
9797

9898
// core-to-core ping pong
9999
// CHECK: aie.device
100-
// CHECK: %[[VAL_1:.*]] = aie.tile(2, 3)
101-
// CHECK: %[[VAL_2:.*]] = aie.tile(2, 4)
102-
// CHECK: %[[VAL_3:.*]] = aie.lock(%[[VAL_1]], 1) {init = 2 : i32}
103-
// CHECK: %[[VAL_4:.*]] = aie.lock(%[[VAL_1]], 0) {init = 0 : i32}
104-
// CHECK: %[[VAL_7:.*]] = aie.lock(%[[VAL_2]], 1) {init = 2 : i32}
105-
// CHECK: %[[VAL_8:.*]] = aie.lock(%[[VAL_2]], 0) {init = 0 : i32}
106-
// CHECK: %[[VAL_11:.*]] = aie.buffer(%[[VAL_2]]) {{{.*}}} : memref<32x32xbf16, 2>
107-
// CHECK: %[[VAL_12:.*]] = aie.buffer(%[[VAL_2]]) {{{.*}}} : memref<32x32xbf16, 2>
108-
// CHECK: %[[VAL_13:.*]] = aie.buffer(%[[VAL_1]]) {{{.*}}} : memref<32x32xbf16, 2>
109-
// CHECK: %[[VAL_14:.*]] = aie.buffer(%[[VAL_1]]) {{{.*}}} : memref<32x32xbf16, 2>
100+
// CHECK-DAG: %[[VAL_1:.*]] = aie.tile(2, 3)
101+
// CHECK-DAG: %[[VAL_2:.*]] = aie.tile(2, 4)
102+
// CHECK-DAG: %[[VAL_3:.*]] = aie.lock(%[[VAL_1]], 1) {init = 2 : i32}
103+
// CHECK-DAG: %[[VAL_4:.*]] = aie.lock(%[[VAL_1]], 0) {init = 0 : i32}
104+
// CHECK-DAG: %[[VAL_7:.*]] = aie.lock(%[[VAL_2]], 1) {init = 2 : i32}
105+
// CHECK-DAG: %[[VAL_8:.*]] = aie.lock(%[[VAL_2]], 0) {init = 0 : i32}
106+
// CHECK-DAG: %[[VAL_11:.*]] = aie.buffer(%[[VAL_2]]) {{{.*}}} : memref<32x32xbf16, 2>
107+
// CHECK-DAG: %[[VAL_12:.*]] = aie.buffer(%[[VAL_2]]) {{{.*}}} : memref<32x32xbf16, 2>
108+
// CHECK-DAG: %[[VAL_13:.*]] = aie.buffer(%[[VAL_1]]) {{{.*}}} : memref<32x32xbf16, 2>
109+
// CHECK-DAG: %[[VAL_14:.*]] = aie.buffer(%[[VAL_1]]) {{{.*}}} : memref<32x32xbf16, 2>
110110

111111
// CHECK: aie.mem(%[[VAL_2]]) {
112112
// CHECK: aie.dma_start(S2MM, 0, ^bb1, ^bb3)
@@ -201,16 +201,16 @@ func.func @core_to_core_ping_pong() {
201201

202202
// core-to-core ping pong, with multi-token scf.for loop
203203
// CHECK: aie.device
204-
// CHECK: %[[VAL_1:.*]] = aie.tile(2, 3)
205-
// CHECK: %[[VAL_2:.*]] = aie.tile(2, 4)
206-
// CHECK: %[[VAL_3:.*]] = aie.lock(%[[VAL_1]], 1) {init = 2 : i32}
207-
// CHECK: %[[VAL_4:.*]] = aie.lock(%[[VAL_1]], 0) {init = 0 : i32}
208-
// CHECK: %[[VAL_7:.*]] = aie.lock(%[[VAL_2]], 1) {init = 2 : i32}
209-
// CHECK: %[[VAL_8:.*]] = aie.lock(%[[VAL_2]], 0) {init = 0 : i32}
210-
// CHECK: %[[VAL_11:.*]] = aie.buffer(%[[VAL_2]]) {{{.*}}} : memref<32x32xbf16, 2>
211-
// CHECK: %[[VAL_12:.*]] = aie.buffer(%[[VAL_2]]) {{{.*}}} : memref<32x32xbf16, 2>
212-
// CHECK: %[[VAL_13:.*]] = aie.buffer(%[[VAL_1]]) {{{.*}}} : memref<32x32xbf16, 2>
213-
// CHECK: %[[VAL_14:.*]] = aie.buffer(%[[VAL_1]]) {{{.*}}} : memref<32x32xbf16, 2>
204+
// CHECK-DAG: %[[VAL_1:.*]] = aie.tile(2, 3)
205+
// CHECK-DAG: %[[VAL_2:.*]] = aie.tile(2, 4)
206+
// CHECK-DAG: %[[VAL_3:.*]] = aie.lock(%[[VAL_1]], 1) {init = 2 : i32}
207+
// CHECK-DAG: %[[VAL_4:.*]] = aie.lock(%[[VAL_1]], 0) {init = 0 : i32}
208+
// CHECK-DAG: %[[VAL_7:.*]] = aie.lock(%[[VAL_2]], 1) {init = 2 : i32}
209+
// CHECK-DAG: %[[VAL_8:.*]] = aie.lock(%[[VAL_2]], 0) {init = 0 : i32}
210+
// CHECK-DAG: %[[VAL_11:.*]] = aie.buffer(%[[VAL_2]]) {{{.*}}} : memref<32x32xbf16, 2>
211+
// CHECK-DAG: %[[VAL_12:.*]] = aie.buffer(%[[VAL_2]]) {{{.*}}} : memref<32x32xbf16, 2>
212+
// CHECK-DAG: %[[VAL_13:.*]] = aie.buffer(%[[VAL_1]]) {{{.*}}} : memref<32x32xbf16, 2>
213+
// CHECK-DAG: %[[VAL_14:.*]] = aie.buffer(%[[VAL_1]]) {{{.*}}} : memref<32x32xbf16, 2>
214214

215215
// CHECK: aie.mem(%[[VAL_2]]) {
216216
// CHECK: aie.dma_start(S2MM, 0, ^bb1, ^bb3)
@@ -319,14 +319,14 @@ func.func @core_to_core_ping_pong() {
319319

320320
// ping-pong is not possible with multiple channel accesses to the same buffer, due to dependence arising from the prod. and cons. of data in the buffer.
321321
// CHECK: aie.device
322-
// CHECK: %[[VAL_0:.*]] = aie.tile(2, 1)
323-
// CHECK: %[[VAL_1:.*]] = aie.tile(0, 3)
324-
// CHECK: %[[VAL_3:.*]] = aie.lock(%[[VAL_0]], 1) {init = 1 : i32}
325-
// CHECK: %[[VAL_4:.*]] = aie.lock(%[[VAL_0]], 0) {init = 0 : i32}
326-
// CHECK: %[[VAL_7:.*]] = aie.lock(%[[VAL_1]], 1) {init = 1 : i32}
327-
// CHECK: %[[VAL_8:.*]] = aie.lock(%[[VAL_1]], 0) {init = 0 : i32}
328-
// CHECK: %[[VAL_11:.*]] = aie.buffer(%[[VAL_0]]) {{{.*}}} : memref<1x1x64x32xi32, 1 : i32>
329-
// CHECK: %[[VAL_12:.*]] = aie.buffer(%[[VAL_1]]) {{{.*}}} : memref<1x1x4x8x4x8xi32, 2 : i32>
322+
// CHECK-DAG: %[[VAL_0:.*]] = aie.tile(2, 1)
323+
// CHECK-DAG: %[[VAL_1:.*]] = aie.tile(0, 3)
324+
// CHECK-DAG: %[[VAL_3:.*]] = aie.lock(%[[VAL_0]], 1) {init = 1 : i32}
325+
// CHECK-DAG: %[[VAL_4:.*]] = aie.lock(%[[VAL_0]], 0) {init = 0 : i32}
326+
// CHECK-DAG: %[[VAL_7:.*]] = aie.lock(%[[VAL_1]], 1) {init = 1 : i32}
327+
// CHECK-DAG: %[[VAL_8:.*]] = aie.lock(%[[VAL_1]], 0) {init = 0 : i32}
328+
// CHECK-DAG: %[[VAL_11:.*]] = aie.buffer(%[[VAL_0]]) {{{.*}}} : memref<1x1x64x32xi32, 1 : i32>
329+
// CHECK-DAG: %[[VAL_12:.*]] = aie.buffer(%[[VAL_1]]) {{{.*}}} : memref<1x1x4x8x4x8xi32, 2 : i32>
330330

331331
// CHECK: aie.mem(%[[VAL_1]]) {
332332
// CHECK: aie.dma_start(S2MM, 0, ^bb1, ^bb2)

‎mlir/test/Conversion/AIRToAIE/air_channel_to_locks_scf_if.mlir‎

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -9,14 +9,14 @@
99

1010
// one-to-one communication using scf.if with arith.cmpi
1111
// CHECK: aie.device
12-
// CHECK: %[[VAL_1:.*]] = aie.tile(2, 3)
13-
// CHECK: %[[VAL_2:.*]] = aie.tile(2, 4)
14-
// CHECK: %[[VAL_3:.*]] = aie.lock(%[[VAL_1]], 1)
15-
// CHECK: %[[VAL_4:.*]] = aie.lock(%[[VAL_1]], 0)
16-
// CHECK: %[[VAL_5:.*]] = aie.lock(%[[VAL_2]], 1)
17-
// CHECK: %[[VAL_6:.*]] = aie.lock(%[[VAL_2]], 0)
18-
// CHECK: %[[VAL_7:.*]] = aie.buffer(%[[VAL_2]]) {{{.*}}} : memref<32x32xbf16, 2>
19-
// CHECK: %[[VAL_8:.*]] = aie.buffer(%[[VAL_1]]) {{{.*}}} : memref<32x32xbf16, 2>
12+
// CHECK-DAG: %[[VAL_1:.*]] = aie.tile(2, 3)
13+
// CHECK-DAG: %[[VAL_2:.*]] = aie.tile(2, 4)
14+
// CHECK-DAG: %[[VAL_3:.*]] = aie.lock(%[[VAL_1]], 1)
15+
// CHECK-DAG: %[[VAL_4:.*]] = aie.lock(%[[VAL_1]], 0)
16+
// CHECK-DAG: %[[VAL_5:.*]] = aie.lock(%[[VAL_2]], 1)
17+
// CHECK-DAG: %[[VAL_6:.*]] = aie.lock(%[[VAL_2]], 0)
18+
// CHECK-DAG: %[[VAL_7:.*]] = aie.buffer(%[[VAL_2]]) {{{.*}}} : memref<32x32xbf16, 2>
19+
// CHECK-DAG: %[[VAL_8:.*]] = aie.buffer(%[[VAL_1]]) {{{.*}}} : memref<32x32xbf16, 2>
2020

2121
// CHECK: aie.mem(%[[VAL_2]]) {
2222
// CHECK: aie.dma_start(S2MM, 0, ^bb1, ^bb2)
@@ -90,14 +90,14 @@ func.func @one_to_one() {
9090

9191
// two-to-two parallel dataflow using scf.if with arith.cmpi
9292
// CHECK: aie.device
93-
// CHECK: %[[VAL_1:.*]] = aie.tile(2, 3)
94-
// CHECK: %[[VAL_2:.*]] = aie.tile(3, 3)
95-
// CHECK: %[[VAL_3:.*]] = aie.tile(2, 4)
96-
// CHECK: %[[VAL_4:.*]] = aie.tile(3, 4)
97-
// CHECK: %[[VAL_13:.*]] = aie.buffer(%[[VAL_4]]) {{{.*}}} : memref<32x32xbf16, 2>
98-
// CHECK: %[[VAL_14:.*]] = aie.buffer(%[[VAL_3]]) {{{.*}}} : memref<32x32xbf16, 2>
99-
// CHECK: %[[VAL_15:.*]] = aie.buffer(%[[VAL_2]]) {{{.*}}} : memref<32x32xbf16, 2>
100-
// CHECK: %[[VAL_16:.*]] = aie.buffer(%[[VAL_1]]) {{{.*}}} : memref<32x32xbf16, 2>
93+
// CHECK-DAG: %[[VAL_1:.*]] = aie.tile(2, 3)
94+
// CHECK-DAG: %[[VAL_2:.*]] = aie.tile(3, 3)
95+
// CHECK-DAG: %[[VAL_3:.*]] = aie.tile(2, 4)
96+
// CHECK-DAG: %[[VAL_4:.*]] = aie.tile(3, 4)
97+
// CHECK-DAG: %[[VAL_13:.*]] = aie.buffer(%[[VAL_4]]) {{{.*}}} : memref<32x32xbf16, 2>
98+
// CHECK-DAG: %[[VAL_14:.*]] = aie.buffer(%[[VAL_3]]) {{{.*}}} : memref<32x32xbf16, 2>
99+
// CHECK-DAG: %[[VAL_15:.*]] = aie.buffer(%[[VAL_2]]) {{{.*}}} : memref<32x32xbf16, 2>
100+
// CHECK-DAG: %[[VAL_16:.*]] = aie.buffer(%[[VAL_1]]) {{{.*}}} : memref<32x32xbf16, 2>
101101

102102
// CHECK: aie.flow(%[[VAL_3]], DMA : 0, %[[VAL_4]], DMA : 0)
103103
// CHECK: aie.flow(%[[VAL_1]], DMA : 0, %[[VAL_2]], DMA : 0)

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