Useful helpers for Bluespec developers.
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This project provides helper scripts that can be used to create Bluespec projects. The generated Makefile supports
- Compile and simulate using Bluesim
- Compile and simulate using
bscsupported Verilog simulators - Build IP-XACT Packets for use in Xilinx Vivado
- Python 3
- Bluespec Compiler
bsc
To get a local copy up and running follow these simple steps.
Have the bluespec compiler and Python 3 installed.
- Clone the repo
git clone https://github.com/esa-tu-darmstadt/BSVTools.git- Create a new directory for the Bluespec project
- Run the following command to create all necessary files for the Bluespec project. The
--test_diris for big projects where it is better to separate testbench from source code. Optionally specify interfaces which should be added to the Bluespec module with--interfaces <interface>(e.g., for a TaPaSCo PE with memory access use--interfaces tapasco axi-master).
path/to/BSVTools/bsvNew.py PROJECT_NAME [--test_dir]The script creates a number of basic Bluespec modules that can be extended as desired.
BSVTools stores device specific information in the file .bsv_tools. By default this file is excluded from Git using .gitignore. A new .bsv_tools file can be created using:
path/to/BSVTools/bsvAdd.pySimulate using Bluesim
makeSimulate using Verilog (Modelsim/Questasim by default)
make SIM_TYPE=VERILOGBuild IP-XACT packet (Needs Vivado in path):
make SIM_TYPE=VERILOG ipRun a custom Vivado Tcl flow on the generated Verilog (Needs Vivado in path), for example:
make SIM_TYPE=VERILOG vivado_tcl PART=xcku3p-ffvb676-2-e SCRIPT=$(pwd)/synth.tclThe vivado_tcl target creates a Vivado project in build/PROJECT_NAME, copies the generated Verilog sources into
build/PROJECT_NAME/src, and sources the Tcl file given by SCRIPT. The sourced script can use the variables
project_dir, project_name, src_path, and script_path.
For example, a small synthesis script could look like this:
read_xdc [file dirname $script_path]/constr.xdc
synth_design -top mkTop -mode out_of_context
report_timing_summary -file $project_dir/${project_name}_timing.rpt
report_utilization -file $project_dir/${project_name}_util.rpt
write_checkpoint -force $project_dir/${project_name}_syn.dcpFor more examples, please refer to the Documentation
See the open issues for a list of proposed features (and known issues).
Contributions are what make the open source community such an amazing place to be learn, inspire, and create. Any contributions you make are greatly appreciated.
- Fork the Project
- Create your Feature Branch (
git checkout -b feature/AmazingFeature) - Commit your Changes (
git commit -m 'Add some AmazingFeature') - Push to the Branch (
git push origin feature/AmazingFeature) - Open a Pull Request
Distributed under the MIT License. See LICENSE for more information.
Embedded Systems and Applications Group - https://www.esa.informatik.tu-darmstadt.de
Project Link: https://github.com/esa-tu-darmstadt/BSVTools