diff --git a/documentation/tapasco-NVMulator.md b/documentation/tapasco-NVMulator.md new file mode 100644 index 00000000..032a5117 --- /dev/null +++ b/documentation/tapasco-NVMulator.md @@ -0,0 +1,51 @@ +NVMulator (Non-Volatile Memory Emulator) +=================== +An open-source easy-to-use hardware emulation module that can be seamlessly inserted between the PE of the FPGA processing elements on the FPGA and a conventional DRAM-based memory system. This feature has been proposed in [[Tamimi2023]](#paper) into TaPaSCo. + +Table of Contents +----------------- + 1. [Usage](#usage) + 2. [Compatibility](#compatibility) + +Usage +----- +To use the NVMulator, please follow the steps outlined below: + +### Composing a hardware design + +``` +tapasco compose [arraysum x 1] @ 100MHz -p AU280 --features 'NVMulator {enabled: true}' +``` + + +### API example +To set the desired latency, please use ```nvMulator(READ_DELAY, WRITE_DELAY, NVM_MODE)``` function call in the API of the TaPaSCo as follow: + +``` +#define READ_DELAY 100 // in clock cycles +#define WRITE_DELAY 200 // in clock cycles +#define NVM_MODE 1 // enable NVM emulation mode + +int main() { + tapasco::Tapasco tapasco; + + tapasco.nvMulator(READ_DELAY, WRITE_DELAY, NVM_MODE); + + auto job = tapasco.launch(PE_ID, reg1, reg2, ...); + job(); + + return 0; +} +``` + + +Compatibility +------------- + +NVMulator only supports the Alveo U280 platform that exploits DDR memory. It is not compatible +with PE-local memories and HBM. Compatibility with other TaPaSCo features is not guaranteed. + +References +---------- +[Tamimi2023] Tamimi, S., Bernhardt, B., Florian, S., Petrov, I., and Koch, A. (2023). NVMulator: A Configurable Open-Source Non-Volatile Memory Emulator for FPGAs. In *Applied Reconfigurable Computing. Architectures, Tools, and Applications (ARC)*. + diff --git a/runtime/libtapasco/src/device.rs b/runtime/libtapasco/src/device.rs index faee2ce6..93874315 100644 --- a/runtime/libtapasco/src/device.rs +++ b/runtime/libtapasco/src/device.rs @@ -348,8 +348,21 @@ impl Device { let zynqmp_vfio_mode = true; let mut is_pcie = false; let mut svm_in_use = false; + let mut nv_in_use = false; + let mut nv_offset = 0; if name == "pcie" { - + + // check whether NVMulator is in use + for comp in &s.platform { + if comp.name == "PLATFORM_COMPONENT_NVMULATOR" { + nv_in_use = true; + nv_offset = comp.offset; + if nv_offset == 0 { + trace!("ERROR: NVMulator offset is zero!"); + } + trace!("Found the NVMulator module in {}", nv_offset); + } + } // check whether SVM is in use for comp in &s.platform { if comp.name == "PLATFORM_COMPONENT_MMU" { @@ -406,6 +419,7 @@ impl Device { settings .get::("dma.write_buffers") .context(ConfigSnafu)?, + nv_offset as usize, ) .context(DMASnafu)?, ), diff --git a/runtime/libtapasco/src/dma.rs b/runtime/libtapasco/src/dma.rs index 9a109888..fc66cefa 100644 --- a/runtime/libtapasco/src/dma.rs +++ b/runtime/libtapasco/src/dma.rs @@ -84,6 +84,7 @@ type Result = std::result::Result; pub trait DMAControl: Debug { fn copy_to(&self, data: &[u8], ptr: DeviceAddress) -> Result<()>; fn copy_from(&self, ptr: DeviceAddress, data: &mut [u8]) -> Result<()>; + fn nvMulator(&self, read_delay: u64, write_delay: u64, mode: u64) -> Result<()>; } #[derive(Debug, Getters)] @@ -144,6 +145,11 @@ impl DMAControl for DriverDMA { }; Ok(()) } + + fn nvMulator(&self, read_delay: u64, write_delay: u64, mode: u64) -> Result<()> { + trace!("configuring NVMulator"); + Ok(()) + } } #[derive(Debug, Getters)] @@ -186,6 +192,11 @@ impl DMAControl for VfioDMA { // nothing to copy, 'data' is same buffer that PE operated on Ok(()) } + + fn nvMulator(&self, read_delay: u64, write_delay: u64, mode: u64) -> Result<()> { + trace!("configuring NVMulator"); + Ok(()) + } } /// Use the CPU to transfer data @@ -263,6 +274,11 @@ impl DMAControl for DirectDMA { Ok(()) } + + fn nvMulator(&self, read_delay: u64, write_delay: u64, mode: u64) -> Result<()> { + trace!("configuring NVMulator"); + Ok(()) + } } /// DMA implementation for SVM support @@ -316,4 +332,9 @@ impl DMAControl for SVMDMA { trace!("Migration to host memory complete."); Ok(()) } + + fn nvMulator(&self, read_delay: u64, write_delay: u64, mode: u64) -> Result<()> { + trace!("configuring NVMulator"); + Ok(()) + } } diff --git a/runtime/libtapasco/src/dma_user_space.rs b/runtime/libtapasco/src/dma_user_space.rs index cca451aa..023de7fd 100644 --- a/runtime/libtapasco/src/dma_user_space.rs +++ b/runtime/libtapasco/src/dma_user_space.rs @@ -87,6 +87,7 @@ pub struct UserSpaceDMA { write_int_cntr: AtomicU64, read_cntr: AtomicU64, read_int_cntr: AtomicU64, + emulator_offset:usize, } impl UserSpaceDMA { @@ -100,6 +101,7 @@ impl UserSpaceDMA { read_num_buf: usize, write_buf_size: usize, write_num_buf: usize, + emulator_offset: usize, ) -> Result { trace!( "Using setting: Read {} x {}B, Write {} x {}B", @@ -181,6 +183,7 @@ impl UserSpaceDMA { write_int_cntr: AtomicU64::new(0), read_int_cntr: AtomicU64::new(0), read_cntr: AtomicU64::new(0), + emulator_offset: emulator_offset, }) } @@ -298,6 +301,32 @@ impl UserSpaceDMA { used_buffers.retain(|(x, _y, _z, _a)| *x >= read_int_cntr_used); Ok(()) } + + fn configure_nvMulator( + &self, + dma_engine_memory: &MutexGuard>, + read_delay: u64, + write_delay: u64, + mode: u64, + ) { + let mut offset = (self.emulator_offset as usize + 0x30) as isize; + unsafe { + let ptr = dma_engine_memory.as_ptr().offset(offset); + write_volatile(ptr as *mut u64, read_delay); + }; + + offset = (self.emulator_offset as usize + 0x40) as isize; + unsafe { + let ptr = dma_engine_memory.as_ptr().offset(offset); + write_volatile(ptr as *mut u64, write_delay); + }; + + offset = (self.emulator_offset as usize + 0x20) as isize; + unsafe { + let ptr = dma_engine_memory.as_ptr().offset(offset); + write_volatile(ptr as *mut u64, mode); + }; + } } impl DMAControl for UserSpaceDMA { @@ -437,4 +466,21 @@ impl DMAControl for UserSpaceDMA { Ok(()) } + + fn nvMulator(&self, read_delay: u64, write_delay: u64, mode: u64) -> Result<()> { + trace!("configuring NVNulator with (read: {}, write: {}) in mode {}", + read_delay, + write_delay, + mode); + + let dma_engine_memory = self.memory.lock()?; + self.configure_nvMulator( + &dma_engine_memory, + read_delay, + write_delay, + mode, + ); + + Ok(()) + } } diff --git a/runtime/libtapasco/src/ffi.rs b/runtime/libtapasco/src/ffi.rs index 3eb80891..9e676215 100644 --- a/runtime/libtapasco/src/ffi.rs +++ b/runtime/libtapasco/src/ffi.rs @@ -800,6 +800,22 @@ pub unsafe extern "C" fn tapasco_memory_copy_from( } } +/// # Safety +/// TODO +#[no_mangle] +pub unsafe extern "C" fn tapasco_nvMulator( + mem: *mut TapascoOffchipMemory, + read_delay: usize, + write_delay: usize, + mode: usize, +) -> isize { + + let tl = &mut *mem; + tl.dma().nvMulator(read_delay.try_into().unwrap(), write_delay.try_into().unwrap(), mode.try_into().unwrap()).context(DMASnafu); + + return 10; +} + /// # Safety /// TODO #[no_mangle] diff --git a/runtime/libtapasco/src/tapasco.hpp b/runtime/libtapasco/src/tapasco.hpp index 989ecbf4..10e93593 100644 --- a/runtime/libtapasco/src/tapasco.hpp +++ b/runtime/libtapasco/src/tapasco.hpp @@ -332,6 +332,15 @@ class TapascoMemory { return this->copy_from(src, dst, len); } + int nvMulator(uint64_t read_delay, uint64_t write_delay, uint64_t mode) { + std::ostringstream stringStream; + if (tapasco_nvMulator(mem, read_delay, write_delay, mode) == -1) { + handle_error(); + return -1; + } + return 0; + } + private: TapascoOffchipMemory *mem; }; @@ -593,6 +602,17 @@ struct Tapasco { return this->default_memory_internal.copy_from(src, dst, len); } +/** + * Configuring NVMulator. + * @param read_delay delay for read channel (in clock cycles) + * @param write_delay delay for write channel (in clock cycles) + * @param mode enable NVM emulation mode + * @return TAPASCO_SUCCESS if copy was successful, an error code otherwise + **/ + int nvMulator(size_t read_delay, size_t write_delay, size_t mode) { + return this->default_memory_internal.nvMulator(read_delay, write_delay, mode); + } + /** * Returns the number of PEs of kernel k_id in the currently loaded *bitstream. diff --git a/toolflow/vivado/common/ip/NVEmulator/component.xml b/toolflow/vivado/common/ip/NVEmulator/component.xml new file mode 100644 index 00000000..74b9f4b4 --- /dev/null +++ b/toolflow/vivado/common/ip/NVEmulator/component.xml @@ -0,0 +1,2718 @@ + + + esa.informatik.tu-darmstadt.de + user + NVEmulator + 1.0 + + + M_AXI_MIG + + + + + + + + + AWID + + + M_AXI_MIG_awid + + + + + AWADDR + + + M_AXI_MIG_awaddr + + + + + AWLEN + + + M_AXI_MIG_awlen + + + + + AWSIZE + + + M_AXI_MIG_awsize + + + + + AWBURST + + + M_AXI_MIG_awburst + + + + + AWLOCK + + + M_AXI_MIG_awlock + + + + + AWCACHE + + + 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+ + + + M_AXI_MIG_wlast + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXI_MIG_bvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + M_AXI_MIG_bready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + M_AXI_MIG_bresp + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + M_AXI_MIG_bid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + interrupt + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + + choice_list_99a1d2b9 + LEVEL_HIGH + LEVEL_LOW + EDGE_RISING + EDGE_FALLING + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/BRAM2.v + verilogSource + + + src/SizedFIFO.v + verilogSource + + + src/mkNVEmulator.v + verilogSource + CHECKSUM_0a55dba3 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/BRAM2.v + verilogSource + + + src/SizedFIFO.v + verilogSource + + + src/mkNVEmulator.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/NVEmulator_v1_0.tcl + tclSource + CHECKSUM_f92e9879 + XGUI_VERSION_2 + + + + NVEmulator + + + Component_Name + mkNVEmulator_v1_0 + + + + + + zynq + virtex7 + kintex7 + artix7 + zynquplus + qvirtex7 + kintex7l + qkintex7 + qkintex7l + artix7l + aartix7 + qartix7 + qzynq + azynq + spartan7 + virtexu + virtexuplus + virtexuplusHBM + kintexuplus + kintexu + + + /UserIP + + NVEmulator + package_project + 1 + 2022-11-29T18:24:45Z + + + + + + 2020.1 + + + + + + + + + diff --git a/toolflow/vivado/common/ip/NVEmulator/src/BRAM2.v b/toolflow/vivado/common/ip/NVEmulator/src/BRAM2.v new file mode 100644 index 00000000..98d73891 --- /dev/null +++ b/toolflow/vivado/common/ip/NVEmulator/src/BRAM2.v @@ -0,0 +1,95 @@ + +`ifdef BSV_ASSIGNMENT_DELAY +`else + `define BSV_ASSIGNMENT_DELAY +`endif + +// Dual-Ported BRAM (WRITE FIRST) +module BRAM2(CLKA, + ENA, + WEA, + ADDRA, + DIA, + DOA, + CLKB, + ENB, + WEB, + ADDRB, + DIB, + DOB + ); + + parameter PIPELINED = 0; + parameter ADDR_WIDTH = 1; + parameter DATA_WIDTH = 1; + parameter MEMSIZE = 1; + + input CLKA; + input ENA; + input WEA; + input [ADDR_WIDTH-1:0] ADDRA; + input [DATA_WIDTH-1:0] DIA; + output [DATA_WIDTH-1:0] DOA; + + input CLKB; + input ENB; + input WEB; + input [ADDR_WIDTH-1:0] ADDRB; + input [DATA_WIDTH-1:0] DIB; + output [DATA_WIDTH-1:0] DOB; + + (* RAM_STYLE = "BLOCK" *) + reg [DATA_WIDTH-1:0] RAM[0:MEMSIZE-1] /* synthesis syn_ramstyle="no_rw_check" */ ; + reg [DATA_WIDTH-1:0] DOA_R; + reg [DATA_WIDTH-1:0] DOB_R; + reg [DATA_WIDTH-1:0] DOA_R2; + reg [DATA_WIDTH-1:0] DOB_R2; + +`ifdef BSV_NO_INITIAL_BLOCKS +`else + // synopsys translate_off + integer i; + initial + begin : init_block + for (i = 0; i < MEMSIZE; i = i + 1) begin + RAM[i] = { ((DATA_WIDTH+1)/2) { 2'b10 } }; + end + DOA_R = { ((DATA_WIDTH+1)/2) { 2'b10 } }; + DOB_R = { ((DATA_WIDTH+1)/2) { 2'b10 } }; + DOA_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } }; + DOB_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } }; + end + // synopsys translate_on +`endif // !`ifdef BSV_NO_INITIAL_BLOCKS + + always @(posedge CLKA) begin + if (ENA) begin + if (WEA) begin + RAM[ADDRA] <= `BSV_ASSIGNMENT_DELAY DIA; + DOA_R <= `BSV_ASSIGNMENT_DELAY DIA; + end + else begin + DOA_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDRA]; + end + end + DOA_R2 <= `BSV_ASSIGNMENT_DELAY DOA_R; + end + + always @(posedge CLKB) begin + if (ENB) begin + if (WEB) begin + RAM[ADDRB] <= `BSV_ASSIGNMENT_DELAY DIB; + DOB_R <= `BSV_ASSIGNMENT_DELAY DIB; + end + else begin + DOB_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDRB]; + end + end + DOB_R2 <= `BSV_ASSIGNMENT_DELAY DOB_R; + end + + // Output drivers + assign DOA = (PIPELINED) ? DOA_R2 : DOA_R; + assign DOB = (PIPELINED) ? DOB_R2 : DOB_R; + +endmodule // BRAM2 diff --git a/toolflow/vivado/common/ip/NVEmulator/src/SizedFIFO.v b/toolflow/vivado/common/ip/NVEmulator/src/SizedFIFO.v new file mode 100644 index 00000000..a2a89444 --- /dev/null +++ b/toolflow/vivado/common/ip/NVEmulator/src/SizedFIFO.v @@ -0,0 +1,259 @@ + +`ifdef BSV_ASSIGNMENT_DELAY +`else + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge +`endif + +`ifdef BSV_ASYNC_RESET + `define BSV_ARESET_EDGE_META or `BSV_RESET_EDGE RST +`else + `define BSV_ARESET_EDGE_META +`endif + +`ifdef BSV_RESET_FIFO_HEAD + `define BSV_ARESET_EDGE_HEAD `BSV_ARESET_EDGE_META +`else + `define BSV_ARESET_EDGE_HEAD +`endif + +`ifdef BSV_RESET_FIFO_ARRAY + `define BSV_ARESET_EDGE_ARRAY `BSV_ARESET_EDGE_META +`else + `define BSV_ARESET_EDGE_ARRAY +`endif + + +// Sized fifo. Model has output register which improves timing +module SizedFIFO(CLK, RST, D_IN, ENQ, FULL_N, D_OUT, DEQ, EMPTY_N, CLR); + parameter p1width = 1; // data width + parameter p2depth = 3; + parameter p3cntr_width = 1; // log(p2depth-1) + // The -1 is allowed since this model has a fast output register + parameter guarded = 1'b1; + localparam p2depth2 = (p2depth >= 2) ? (p2depth -2) : 0 ; + + input CLK; + input RST; + input CLR; + input [p1width - 1 : 0] D_IN; + input ENQ; + input DEQ; + + output FULL_N; + output EMPTY_N; + output [p1width - 1 : 0] D_OUT; + + reg not_ring_full; + reg ring_empty; + + reg [p3cntr_width-1 : 0] head; + wire [p3cntr_width-1 : 0] next_head; + + reg [p3cntr_width-1 : 0] tail; + wire [p3cntr_width-1 : 0] next_tail; + + // if the depth is too small, don't create an ill-sized array; + // instead, make a 1-sized array and let the initial block report an error + (* RAM_STYLE = "DISTRIBUTED" *) + reg [p1width - 1 : 0] arr[0: p2depth2]; + + reg [p1width - 1 : 0] D_OUT; + reg hasodata; + + wire [p3cntr_width-1:0] depthLess2 = p2depth2[p3cntr_width-1:0] ; + + wire [p3cntr_width-1 : 0] incr_tail; + wire [p3cntr_width-1 : 0] incr_head; + + assign incr_tail = tail + 1'b1 ; + assign incr_head = head + 1'b1 ; + + assign next_head = (head == depthLess2 ) ? {p3cntr_width{1'b0}} : incr_head ; + assign next_tail = (tail == depthLess2 ) ? {p3cntr_width{1'b0}} : incr_tail ; + + assign EMPTY_N = hasodata; + assign FULL_N = not_ring_full; + +`ifdef BSV_NO_INITIAL_BLOCKS +`else // not BSV_NO_INITIAL_BLOCKS + // synopsys translate_off + initial + begin : initial_block + integer i; + D_OUT = {((p1width + 1)/2){2'b10}} ; + + ring_empty = 1'b1; + not_ring_full = 1'b1; + hasodata = 1'b0; + head = {p3cntr_width {1'b0}} ; + tail = {p3cntr_width {1'b0}} ; + + for (i = 0; i <= p2depth2; i = i + 1) + begin + arr[i] = D_OUT ; + end + end + // synopsys translate_on +`endif // BSV_NO_INITIAL_BLOCKS + + + always @(posedge CLK `BSV_ARESET_EDGE_META) + begin + if (RST == `BSV_RESET_VALUE) + begin + head <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ; + tail <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ; + ring_empty <= `BSV_ASSIGNMENT_DELAY 1'b1; + not_ring_full <= `BSV_ASSIGNMENT_DELAY 1'b1; + hasodata <= `BSV_ASSIGNMENT_DELAY 1'b0; + end // if (RST == `BSV_RESET_VALUE) + else + begin + + casez ({CLR, DEQ, ENQ, hasodata, ring_empty}) + // Clear operation + 5'b1????: begin + head <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ; + tail <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ; + ring_empty <= `BSV_ASSIGNMENT_DELAY 1'b1; + not_ring_full <= `BSV_ASSIGNMENT_DELAY 1'b1; + hasodata <= `BSV_ASSIGNMENT_DELAY 1'b0; + end + // ----------------------- + // DEQ && ENQ case -- change head and tail if added to ring + 5'b011?0: begin + tail <= `BSV_ASSIGNMENT_DELAY next_tail; + head <= `BSV_ASSIGNMENT_DELAY next_head; + end + // ----------------------- + // DEQ only and NO data is in ring + 5'b010?1: begin + hasodata <= `BSV_ASSIGNMENT_DELAY 1'b0; + end + // DEQ only and data is in ring (move the head pointer) + 5'b010?0: begin + head <= `BSV_ASSIGNMENT_DELAY next_head; + not_ring_full <= `BSV_ASSIGNMENT_DELAY 1'b1; + ring_empty <= `BSV_ASSIGNMENT_DELAY next_head == tail ; + end + // ----------------------- + // ENQ only when empty + 5'b0010?: begin + hasodata <= `BSV_ASSIGNMENT_DELAY 1'b1; + end + // ENQ only when not empty + 5'b0011?: begin + if ( not_ring_full ) // Drop this test to save redundant test + // but be warnned that with test fifo overflow causes loss of new data + // while without test fifo drops all but head entry! (pointer overflow) + begin + tail <= `BSV_ASSIGNMENT_DELAY next_tail; + ring_empty <= `BSV_ASSIGNMENT_DELAY 1'b0; + not_ring_full <= `BSV_ASSIGNMENT_DELAY ! (next_tail == head) ; + end + end + endcase + end // else: !if(RST == `BSV_RESET_VALUE) + end // always @ (posedge CLK) + + // Update the fast data out register + always @(posedge CLK `BSV_ARESET_EDGE_HEAD) + begin +`ifdef BSV_RESET_FIFO_HEAD + if (RST == `BSV_RESET_VALUE) + begin + D_OUT <= `BSV_ASSIGNMENT_DELAY {p1width {1'b0}} ; + end // if (RST == `BSV_RESET_VALUE) + else +`endif + begin + casez ({CLR, DEQ, ENQ, hasodata, ring_empty}) + // DEQ && ENQ cases + 5'b011?0: begin D_OUT <= `BSV_ASSIGNMENT_DELAY arr[head]; end + 5'b011?1: begin D_OUT <= `BSV_ASSIGNMENT_DELAY D_IN; end + // DEQ only and data is in ring + 5'b010?0: begin D_OUT <= `BSV_ASSIGNMENT_DELAY arr[head]; end + // ENQ only when empty + 5'b0010?: begin D_OUT <= `BSV_ASSIGNMENT_DELAY D_IN; end + endcase + end // else: !if(RST == `BSV_RESET_VALUE) + end // always @ (posedge CLK) + + // Update the memory array reset is OFF + always @(posedge CLK `BSV_ARESET_EDGE_ARRAY) + begin: array +`ifdef BSV_RESET_FIFO_ARRAY + if (RST == `BSV_RESET_VALUE) + begin: rst_array + integer i; + for (i = 0; i <= p2depth2 && p2depth > 2; i = i + 1) + begin + arr[i] <= `BSV_ASSIGNMENT_DELAY {p1width {1'b0}} ; + end + end // if (RST == `BSV_RESET_VALUE) + else +`endif + begin + if (!CLR && ENQ && ((DEQ && !ring_empty) || (!DEQ && hasodata && not_ring_full))) + begin + arr[tail] <= `BSV_ASSIGNMENT_DELAY D_IN; + end + end // else: !if(RST == `BSV_RESET_VALUE) + end // always @ (posedge CLK) + + // synopsys translate_off + always@(posedge CLK) + begin: error_checks + reg deqerror, enqerror ; + + deqerror = 0; + enqerror = 0; + if (RST == ! `BSV_RESET_VALUE) + begin + if ( ! EMPTY_N && DEQ ) + begin + deqerror = 1 ; + $display( "Warning: SizedFIFO: %m -- Dequeuing from empty fifo" ) ; + end + if ( ! FULL_N && ENQ && (!DEQ || guarded) ) + begin + enqerror = 1 ; + $display( "Warning: SizedFIFO: %m -- Enqueuing to a full fifo" ) ; + end + end + end // block: error_checks + // synopsys translate_on + + // synopsys translate_off + // Some assertions about parameter values + initial + begin : parameter_assertions + integer ok ; + ok = 1 ; + + if ( p2depth <= 1) + begin + ok = 0; + $display ( "Warning SizedFIFO: %m -- depth parameter increased from %0d to 2", p2depth); + end + + if ( p3cntr_width <= 0 ) + begin + ok = 0; + $display ( "ERROR SizedFIFO: %m -- width parameter must be greater than 0" ) ; + end + + if ( ok == 0 ) $finish ; + + end // initial begin + // synopsys translate_on + +endmodule diff --git a/toolflow/vivado/common/ip/NVEmulator/src/mkNVEmulator.v b/toolflow/vivado/common/ip/NVEmulator/src/mkNVEmulator.v new file mode 100644 index 00000000..e17131a8 --- /dev/null +++ b/toolflow/vivado/common/ip/NVEmulator/src/mkNVEmulator.v @@ -0,0 +1,2828 @@ +// +// Generated by Bluespec Compiler, version 2022.01 (build 066c7a8) +// +// On Tue Nov 29 19:24:20 CET 2022 +// +// +// Ports: +// Name I/O size props +// S_AXI_arready O 1 +// S_AXI_rvalid O 1 +// S_AXI_rdata O 64 +// S_AXI_rresp O 2 +// S_AXI_awready O 1 +// S_AXI_wready O 1 +// S_AXI_bvalid O 1 +// S_AXI_bresp O 2 +// S_AXI_NV_arready O 1 +// S_AXI_NV_rvalid O 1 +// S_AXI_NV_rid O 1 +// S_AXI_NV_rdata O 512 +// S_AXI_NV_rresp O 2 +// S_AXI_NV_rlast O 1 +// S_AXI_NV_awready O 1 +// S_AXI_NV_wready O 1 +// S_AXI_NV_bvalid O 1 +// S_AXI_NV_bresp O 2 +// S_AXI_NV_bid O 1 +// M_AXI_MIG_arvalid O 1 +// M_AXI_MIG_arid O 1 +// M_AXI_MIG_araddr O 34 +// M_AXI_MIG_arlen O 8 +// M_AXI_MIG_arsize O 3 +// M_AXI_MIG_arburst O 2 +// M_AXI_MIG_arlock O 1 +// M_AXI_MIG_arcache O 4 +// M_AXI_MIG_arprot O 3 +// M_AXI_MIG_arqos O 4 +// M_AXI_MIG_arregion O 4 +// M_AXI_MIG_rready O 1 +// M_AXI_MIG_awvalid O 1 +// M_AXI_MIG_awid O 1 +// M_AXI_MIG_awaddr O 34 +// M_AXI_MIG_awlen O 8 +// M_AXI_MIG_awsize O 3 +// M_AXI_MIG_awburst O 2 +// M_AXI_MIG_awlock O 1 +// M_AXI_MIG_awcache O 4 +// M_AXI_MIG_awprot O 3 +// M_AXI_MIG_awqos O 4 +// M_AXI_MIG_awregion O 4 +// M_AXI_MIG_wvalid O 1 +// M_AXI_MIG_wdata O 512 +// M_AXI_MIG_wstrb O 64 +// M_AXI_MIG_wlast O 1 +// M_AXI_MIG_bready O 1 +// interrupt O 1 reg +// CLK I 1 clock +// RST_N I 1 reset +// S_AXI_arvalid I 1 +// S_AXI_araddr I 12 +// S_AXI_arprot I 3 +// S_AXI_rready I 1 +// S_AXI_awvalid I 1 +// S_AXI_awaddr I 12 +// S_AXI_awprot I 3 +// S_AXI_wvalid I 1 +// S_AXI_wdata I 64 +// S_AXI_wstrb I 8 +// S_AXI_bready I 1 +// S_AXI_NV_arvalid I 1 +// S_AXI_NV_arid I 1 reg +// S_AXI_NV_araddr I 64 reg +// S_AXI_NV_arlen I 8 reg +// S_AXI_NV_arsize I 3 reg +// S_AXI_NV_arburst I 2 reg +// S_AXI_NV_arlock I 1 reg +// S_AXI_NV_arcache I 4 reg +// S_AXI_NV_arprot I 3 reg +// S_AXI_NV_arqos I 4 reg +// S_AXI_NV_arregion I 4 reg +// S_AXI_NV_rready I 1 +// S_AXI_NV_awvalid I 1 +// S_AXI_NV_awid I 1 reg +// S_AXI_NV_awaddr I 64 reg +// S_AXI_NV_awlen I 8 reg +// S_AXI_NV_awsize I 3 reg +// S_AXI_NV_awburst I 2 reg +// S_AXI_NV_awlock I 1 reg +// S_AXI_NV_awcache I 4 reg +// S_AXI_NV_awprot I 3 reg +// S_AXI_NV_awqos I 4 reg +// S_AXI_NV_awregion I 4 reg +// S_AXI_NV_wvalid I 1 +// S_AXI_NV_wdata I 512 reg +// S_AXI_NV_wstrb I 64 reg +// S_AXI_NV_wlast I 1 reg +// S_AXI_NV_bready I 1 +// M_AXI_MIG_arready I 1 +// M_AXI_MIG_rvalid I 1 +// M_AXI_MIG_rid I 1 reg +// M_AXI_MIG_rdata I 512 reg +// M_AXI_MIG_rresp I 2 reg +// M_AXI_MIG_rlast I 1 reg +// M_AXI_MIG_awready I 1 +// M_AXI_MIG_wready I 1 +// M_AXI_MIG_bvalid I 1 +// M_AXI_MIG_bresp I 2 reg +// M_AXI_MIG_bid I 1 reg +// +// Combinational paths from inputs to outputs: +// S_AXI_rready -> S_AXI_arready +// +// + +`ifdef BSV_ASSIGNMENT_DELAY +`else + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge +`endif + +module mkNVEmulator(CLK, + RST_N, + + S_AXI_arready, + + S_AXI_arvalid, + + S_AXI_araddr, + + S_AXI_arprot, + + S_AXI_rvalid, + + S_AXI_rready, + + S_AXI_rdata, + + S_AXI_rresp, + + S_AXI_awready, + + S_AXI_awvalid, + + S_AXI_awaddr, + + S_AXI_awprot, + + S_AXI_wready, + + S_AXI_wvalid, + + S_AXI_wdata, + + S_AXI_wstrb, + + S_AXI_bvalid, + + S_AXI_bready, + + S_AXI_bresp, + + S_AXI_NV_arvalid, + + S_AXI_NV_arready, + + S_AXI_NV_arid, + S_AXI_NV_araddr, + S_AXI_NV_arlen, + S_AXI_NV_arsize, + S_AXI_NV_arburst, + S_AXI_NV_arlock, + S_AXI_NV_arcache, + S_AXI_NV_arprot, + S_AXI_NV_arqos, + S_AXI_NV_arregion, + + S_AXI_NV_rready, + + S_AXI_NV_rvalid, + + S_AXI_NV_rid, + + S_AXI_NV_rdata, + + S_AXI_NV_rresp, + + S_AXI_NV_rlast, + + S_AXI_NV_awready, + + S_AXI_NV_awvalid, + + S_AXI_NV_awid, + S_AXI_NV_awaddr, + S_AXI_NV_awlen, + S_AXI_NV_awsize, + S_AXI_NV_awburst, + S_AXI_NV_awlock, + S_AXI_NV_awcache, + S_AXI_NV_awprot, + S_AXI_NV_awqos, + S_AXI_NV_awregion, + + S_AXI_NV_wready, + + S_AXI_NV_wvalid, + + S_AXI_NV_wdata, + S_AXI_NV_wstrb, + S_AXI_NV_wlast, + + S_AXI_NV_bready, + + S_AXI_NV_bvalid, + + S_AXI_NV_bresp, + + S_AXI_NV_bid, + + M_AXI_MIG_arvalid, + + M_AXI_MIG_arready, + + M_AXI_MIG_arid, + + M_AXI_MIG_araddr, + + M_AXI_MIG_arlen, + + M_AXI_MIG_arsize, + + M_AXI_MIG_arburst, + + M_AXI_MIG_arlock, + + M_AXI_MIG_arcache, + + M_AXI_MIG_arprot, + + M_AXI_MIG_arqos, + + M_AXI_MIG_arregion, + + M_AXI_MIG_rready, + + M_AXI_MIG_rvalid, + + M_AXI_MIG_rid, + M_AXI_MIG_rdata, + M_AXI_MIG_rresp, + M_AXI_MIG_rlast, + + M_AXI_MIG_awready, + + M_AXI_MIG_awvalid, + + M_AXI_MIG_awid, + + M_AXI_MIG_awaddr, + + M_AXI_MIG_awlen, + + M_AXI_MIG_awsize, + + M_AXI_MIG_awburst, + + M_AXI_MIG_awlock, + + M_AXI_MIG_awcache, + + M_AXI_MIG_awprot, + + M_AXI_MIG_awqos, + + M_AXI_MIG_awregion, + + M_AXI_MIG_wready, + + M_AXI_MIG_wvalid, + + M_AXI_MIG_wdata, + + M_AXI_MIG_wstrb, + + M_AXI_MIG_wlast, + + M_AXI_MIG_bvalid, + + M_AXI_MIG_bready, + + M_AXI_MIG_bresp, + M_AXI_MIG_bid, + + interrupt); + input CLK; + input RST_N; + + // value method s_rd_arready + output S_AXI_arready; + + // action method s_rd_parvalid + input S_AXI_arvalid; + + // action method s_rd_paraddr + input [11 : 0] S_AXI_araddr; + + // action method s_rd_parprot + input [2 : 0] S_AXI_arprot; + + // value method s_rd_rvalid + output S_AXI_rvalid; + + // action method s_rd_prready + input S_AXI_rready; + + // value method s_rd_rdata + output [63 : 0] S_AXI_rdata; + + // value method s_rd_rresp + output [1 : 0] S_AXI_rresp; + + // value method s_wr_awready + output S_AXI_awready; + + // action method s_wr_pawvalid + input S_AXI_awvalid; + + // action method s_wr_pawaddr + input [11 : 0] S_AXI_awaddr; + + // action method s_wr_pawprot + input [2 : 0] S_AXI_awprot; + + // value method s_wr_wready + output S_AXI_wready; + + // action method s_wr_pwvalid + input S_AXI_wvalid; + + // action method s_wr_pwdata + input [63 : 0] S_AXI_wdata; + + // action method s_wr_pwstrb + input [7 : 0] S_AXI_wstrb; + + // value method s_wr_bvalid + output S_AXI_bvalid; + + // action method s_wr_pbready + input S_AXI_bready; + + // value method s_wr_bresp + output [1 : 0] S_AXI_bresp; + + // action method in_read_parvalid + input S_AXI_NV_arvalid; + + // value method in_read_arready + output S_AXI_NV_arready; + + // action method in_read_parchannel + input S_AXI_NV_arid; + input [63 : 0] S_AXI_NV_araddr; + input [7 : 0] S_AXI_NV_arlen; + input [2 : 0] S_AXI_NV_arsize; + input [1 : 0] S_AXI_NV_arburst; + input S_AXI_NV_arlock; + input [3 : 0] S_AXI_NV_arcache; + input [2 : 0] S_AXI_NV_arprot; + input [3 : 0] S_AXI_NV_arqos; + input [3 : 0] S_AXI_NV_arregion; + + // action method in_read_prready + input S_AXI_NV_rready; + + // value method in_read_rvalid + output S_AXI_NV_rvalid; + + // value method in_read_rid + output S_AXI_NV_rid; + + // value method in_read_rdata + output [511 : 0] S_AXI_NV_rdata; + + // value method in_read_rresp + output [1 : 0] S_AXI_NV_rresp; + + // value method in_read_rlast + output S_AXI_NV_rlast; + + // value method in_read_ruser + + // value method in_write_awready + output S_AXI_NV_awready; + + // action method in_write_pawvalid + input S_AXI_NV_awvalid; + + // action method in_write_pawchannel + input S_AXI_NV_awid; + input [63 : 0] S_AXI_NV_awaddr; + input [7 : 0] S_AXI_NV_awlen; + input [2 : 0] S_AXI_NV_awsize; + input [1 : 0] S_AXI_NV_awburst; + input S_AXI_NV_awlock; + input [3 : 0] S_AXI_NV_awcache; + input [2 : 0] S_AXI_NV_awprot; + input [3 : 0] S_AXI_NV_awqos; + input [3 : 0] S_AXI_NV_awregion; + + // value method in_write_wready + output S_AXI_NV_wready; + + // action method in_write_pwvalid + input S_AXI_NV_wvalid; + + // action method in_write_pwchannel + input [511 : 0] S_AXI_NV_wdata; + input [63 : 0] S_AXI_NV_wstrb; + input S_AXI_NV_wlast; + + // action method in_write_pbready + input S_AXI_NV_bready; + + // value method in_write_bvalid + output S_AXI_NV_bvalid; + + // value method in_write_bresp + output [1 : 0] S_AXI_NV_bresp; + + // value method in_write_bid + output S_AXI_NV_bid; + + // value method in_write_buser + + // value method out_read_arvalid + output M_AXI_MIG_arvalid; + + // action method out_read_parready + input M_AXI_MIG_arready; + + // value method out_read_arid + output M_AXI_MIG_arid; + + // value method out_read_araddr + output [33 : 0] M_AXI_MIG_araddr; + + // value method out_read_arlen + output [7 : 0] M_AXI_MIG_arlen; + + // value method out_read_arsize + output [2 : 0] M_AXI_MIG_arsize; + + // value method out_read_arburst + output [1 : 0] M_AXI_MIG_arburst; + + // value method out_read_arlock + output M_AXI_MIG_arlock; + + // value method out_read_arcache + output [3 : 0] M_AXI_MIG_arcache; + + // value method out_read_arprot + output [2 : 0] M_AXI_MIG_arprot; + + // value method out_read_arqos + output [3 : 0] M_AXI_MIG_arqos; + + // value method out_read_arregion + output [3 : 0] M_AXI_MIG_arregion; + + // value method out_read_aruser + + // value method out_read_rready + output M_AXI_MIG_rready; + + // action method out_read_prvalid + input M_AXI_MIG_rvalid; + + // action method out_read_prchannel + input M_AXI_MIG_rid; + input [511 : 0] M_AXI_MIG_rdata; + input [1 : 0] M_AXI_MIG_rresp; + input M_AXI_MIG_rlast; + + // action method out_write_pawready + input M_AXI_MIG_awready; + + // value method out_write_awvalid + output M_AXI_MIG_awvalid; + + // value method out_write_awid + output M_AXI_MIG_awid; + + // value method out_write_awaddr + output [33 : 0] M_AXI_MIG_awaddr; + + // value method out_write_awlen + output [7 : 0] M_AXI_MIG_awlen; + + // value method out_write_awsize + output [2 : 0] M_AXI_MIG_awsize; + + // value method out_write_awburst + output [1 : 0] M_AXI_MIG_awburst; + + // value method out_write_awlock + output M_AXI_MIG_awlock; + + // value method out_write_awcache + output [3 : 0] M_AXI_MIG_awcache; + + // value method out_write_awprot + output [2 : 0] M_AXI_MIG_awprot; + + // value method out_write_awqos + output [3 : 0] M_AXI_MIG_awqos; + + // value method out_write_awregion + output [3 : 0] M_AXI_MIG_awregion; + + // value method out_write_awuser + + // action method out_write_pwready + input M_AXI_MIG_wready; + + // value method out_write_wvalid + output M_AXI_MIG_wvalid; + + // value method out_write_wdata + output [511 : 0] M_AXI_MIG_wdata; + + // value method out_write_wstrb + output [63 : 0] M_AXI_MIG_wstrb; + + // value method out_write_wlast + output M_AXI_MIG_wlast; + + // value method out_write_wuser + + // action method out_write_pbvalid + input M_AXI_MIG_bvalid; + + // value method out_write_bready + output M_AXI_MIG_bready; + + // action method out_write_bin + input [1 : 0] M_AXI_MIG_bresp; + input M_AXI_MIG_bid; + + // value method interrupt + output interrupt; + + // signals for module outputs + wire [511 : 0] M_AXI_MIG_wdata, S_AXI_NV_rdata; + wire [63 : 0] M_AXI_MIG_wstrb, S_AXI_rdata; + wire [33 : 0] M_AXI_MIG_araddr, M_AXI_MIG_awaddr; + wire [7 : 0] M_AXI_MIG_arlen, M_AXI_MIG_awlen; + wire [3 : 0] M_AXI_MIG_arcache, + M_AXI_MIG_arqos, + M_AXI_MIG_arregion, + M_AXI_MIG_awcache, + M_AXI_MIG_awqos, + M_AXI_MIG_awregion; + wire [2 : 0] M_AXI_MIG_arprot, + M_AXI_MIG_arsize, + M_AXI_MIG_awprot, + M_AXI_MIG_awsize; + wire [1 : 0] M_AXI_MIG_arburst, + M_AXI_MIG_awburst, + S_AXI_NV_bresp, + S_AXI_NV_rresp, + S_AXI_bresp, + S_AXI_rresp; + wire M_AXI_MIG_arid, + M_AXI_MIG_arlock, + M_AXI_MIG_arvalid, + M_AXI_MIG_awid, + M_AXI_MIG_awlock, + M_AXI_MIG_awvalid, + M_AXI_MIG_bready, + M_AXI_MIG_rready, + M_AXI_MIG_wlast, + M_AXI_MIG_wvalid, + S_AXI_NV_arready, + S_AXI_NV_awready, + S_AXI_NV_bid, + S_AXI_NV_bvalid, + S_AXI_NV_rid, + S_AXI_NV_rlast, + S_AXI_NV_rvalid, + S_AXI_NV_wready, + S_AXI_arready, + S_AXI_awready, + S_AXI_bvalid, + S_AXI_rvalid, + S_AXI_wready, + interrupt; + + // inlined wires + reg [66 : 0] s_config_readSlave_out_rv$port1__write_1; + wire [579 : 0] fifo_Read_Rs_data_wDataIn$wget, + fifo_Read_Rs_data_wDataOut$wget; + wire [576 : 0] nv_write_arinpkg_data$wget; + wire [515 : 0] mig_read_rinpkg$wget; + wire [93 : 0] nv_read_arinpkg$wget, nv_write_arinpkg_addr$wget; + wire [87 : 0] s_config_writeSlave_in_rv$port1__read, + s_config_writeSlave_in_rv$port1__write_1, + s_config_writeSlave_in_rv$port2__read; + wire [72 : 0] s_config_writeSlave_dataIn_rv$port0__write_1, + s_config_writeSlave_dataIn_rv$port1__read, + s_config_writeSlave_dataIn_rv$port2__read; + wire [66 : 0] s_config_readSlave_out_rv$port1__read, + s_config_readSlave_out_rv$port2__read; + wire [15 : 0] s_config_readSlave_in_rv$port1__read, + s_config_readSlave_in_rv$port1__write_1, + s_config_readSlave_in_rv$port2__read, + s_config_writeSlave_addrIn_rv$port0__write_1, + s_config_writeSlave_addrIn_rv$port1__read, + s_config_writeSlave_addrIn_rv$port2__read; + wire [2 : 0] mig_write_rinpkg$wget, + s_config_writeSlave_out_rv$port1__read, + s_config_writeSlave_out_rv$port2__read; + wire s_config_readIsHandled$whas, + s_config_readSlave_in_rv$EN_port0__write, + s_config_readSlave_in_rv$EN_port1__write, + s_config_readSlave_out_rv$EN_port0__write, + s_config_readSlave_out_rv$EN_port1__write, + s_config_writeIsHandled$whas, + s_config_writeSlave_addrIn_rv$EN_port0__write, + s_config_writeSlave_addrIn_rv$EN_port1__write, + s_config_writeSlave_dataIn_rv$EN_port0__write, + s_config_writeSlave_dataIn_rv$EN_port1__write, + s_config_writeSlave_in_rv$EN_port0__write, + s_config_writeSlave_in_rv$EN_port1__write, + s_config_writeSlave_out_rv$EN_port0__write, + s_config_writeSlave_out_rv$EN_port1__write; + + // register cycleCount + reg [63 : 0] cycleCount; + wire [63 : 0] cycleCount$D_IN; + wire cycleCount$EN; + + // register cycleCount_Overflow + reg [63 : 0] cycleCount_Overflow; + wire [63 : 0] cycleCount_Overflow$D_IN; + wire cycleCount_Overflow$EN; + + // register error + reg error; + wire error$D_IN, error$EN; + + // register fifo_Read_Rs_data_rCache + reg [589 : 0] fifo_Read_Rs_data_rCache; + wire [589 : 0] fifo_Read_Rs_data_rCache$D_IN; + wire fifo_Read_Rs_data_rCache$EN; + + // register fifo_Read_Rs_data_rRdPtr + reg [8 : 0] fifo_Read_Rs_data_rRdPtr; + wire [8 : 0] fifo_Read_Rs_data_rRdPtr$D_IN; + wire fifo_Read_Rs_data_rRdPtr$EN; + + // register fifo_Read_Rs_data_rWrPtr + reg [8 : 0] fifo_Read_Rs_data_rWrPtr; + wire [8 : 0] fifo_Read_Rs_data_rWrPtr$D_IN; + wire fifo_Read_Rs_data_rWrPtr$EN; + + // register idle + reg idle; + wire idle$D_IN, idle$EN; + + // register interruptR + reg interruptR; + wire interruptR$D_IN, interruptR$EN; + + // register isReadWaiting + reg isReadWaiting; + wire isReadWaiting$D_IN, isReadWaiting$EN; + + // register isWriteWaiting + reg isWriteWaiting; + wire isWriteWaiting$D_IN, isWriteWaiting$EN; + + // register mig_read_isRst_isInReset + reg mig_read_isRst_isInReset; + wire mig_read_isRst_isInReset$D_IN, mig_read_isRst_isInReset$EN; + + // register mig_write_isRst_isInReset + reg mig_write_isRst_isInReset; + wire mig_write_isRst_isInReset$D_IN, mig_write_isRst_isInReset$EN; + + // register nv_read_isRst_isInReset + reg nv_read_isRst_isInReset; + wire nv_read_isRst_isInReset$D_IN, nv_read_isRst_isInReset$EN; + + // register nv_write_isRst_isInReset + reg nv_write_isRst_isInReset; + wire nv_write_isRst_isInReset$D_IN, nv_write_isRst_isInReset$EN; + + // register operation + reg operation; + wire operation$D_IN, operation$EN; + + // register rand_rd_r + reg [31 : 0] rand_rd_r; + wire [31 : 0] rand_rd_r$D_IN; + wire rand_rd_r$EN; + + // register rand_wr_r + reg [31 : 0] rand_wr_r; + wire [31 : 0] rand_wr_r$D_IN; + wire rand_wr_r$EN; + + // register readNumberOfCycleToWait + reg [63 : 0] readNumberOfCycleToWait; + wire [63 : 0] readNumberOfCycleToWait$D_IN; + wire readNumberOfCycleToWait$EN; + + // register read_data + reg [515 : 0] read_data; + wire [515 : 0] read_data$D_IN; + wire read_data$EN; + + // register read_delay + reg [63 : 0] read_delay; + wire [63 : 0] read_delay$D_IN; + wire read_delay$EN; + + // register s_config_readBusy + reg s_config_readBusy; + wire s_config_readBusy$D_IN, s_config_readBusy$EN; + + // register s_config_readSlave_in_rv + reg [15 : 0] s_config_readSlave_in_rv; + wire [15 : 0] s_config_readSlave_in_rv$D_IN; + wire s_config_readSlave_in_rv$EN; + + // register s_config_readSlave_isRst_isInReset + reg s_config_readSlave_isRst_isInReset; + wire s_config_readSlave_isRst_isInReset$D_IN, + s_config_readSlave_isRst_isInReset$EN; + + // register s_config_readSlave_out_rv + reg [66 : 0] s_config_readSlave_out_rv; + wire [66 : 0] s_config_readSlave_out_rv$D_IN; + wire s_config_readSlave_out_rv$EN; + + // register s_config_writeBusy + reg s_config_writeBusy; + wire s_config_writeBusy$D_IN, s_config_writeBusy$EN; + + // register s_config_writeSlave_addrIn_rv + reg [15 : 0] s_config_writeSlave_addrIn_rv; + wire [15 : 0] s_config_writeSlave_addrIn_rv$D_IN; + wire s_config_writeSlave_addrIn_rv$EN; + + // register s_config_writeSlave_dataIn_rv + reg [72 : 0] s_config_writeSlave_dataIn_rv; + wire [72 : 0] s_config_writeSlave_dataIn_rv$D_IN; + wire s_config_writeSlave_dataIn_rv$EN; + + // register s_config_writeSlave_in_rv + reg [87 : 0] s_config_writeSlave_in_rv; + wire [87 : 0] s_config_writeSlave_in_rv$D_IN; + wire s_config_writeSlave_in_rv$EN; + + // register s_config_writeSlave_isRst_isInReset + reg s_config_writeSlave_isRst_isInReset; + wire s_config_writeSlave_isRst_isInReset$D_IN, + s_config_writeSlave_isRst_isInReset$EN; + + // register s_config_writeSlave_out_rv + reg [2 : 0] s_config_writeSlave_out_rv; + wire [2 : 0] s_config_writeSlave_out_rv$D_IN; + wire s_config_writeSlave_out_rv$EN; + + // register start + reg start; + wire start$D_IN, start$EN; + + // register status + reg [63 : 0] status; + wire [63 : 0] status$D_IN; + wire status$EN; + + // register writeNumberOfCycleToWait + reg [11 : 0] writeNumberOfCycleToWait; + wire [11 : 0] writeNumberOfCycleToWait$D_IN; + wire writeNumberOfCycleToWait$EN; + + // register write_delay + reg [63 : 0] write_delay; + wire [63 : 0] write_delay$D_IN; + wire write_delay$EN; + + // ports of submodule fifo_Read_Rq + wire [63 : 0] fifo_Read_Rq$D_IN, fifo_Read_Rq$D_OUT; + wire fifo_Read_Rq$CLR, + fifo_Read_Rq$DEQ, + fifo_Read_Rq$EMPTY_N, + fifo_Read_Rq$ENQ, + fifo_Read_Rq$FULL_N; + + // ports of submodule fifo_Read_Rq_delay_mig + wire [383 : 0] fifo_Read_Rq_delay_mig$D_IN, fifo_Read_Rq_delay_mig$D_OUT; + wire fifo_Read_Rq_delay_mig$CLR, + fifo_Read_Rq_delay_mig$DEQ, + fifo_Read_Rq_delay_mig$EMPTY_N, + fifo_Read_Rq_delay_mig$ENQ, + fifo_Read_Rq_delay_mig$FULL_N; + + // ports of submodule fifo_Read_Rq_delay_nv + wire [383 : 0] fifo_Read_Rq_delay_nv$D_IN; + wire fifo_Read_Rq_delay_nv$CLR, + fifo_Read_Rq_delay_nv$DEQ, + fifo_Read_Rq_delay_nv$ENQ; + + // ports of submodule fifo_Read_Rs_data_memory + wire [579 : 0] fifo_Read_Rs_data_memory$DIA, + fifo_Read_Rs_data_memory$DIB, + fifo_Read_Rs_data_memory$DOB; + wire [7 : 0] fifo_Read_Rs_data_memory$ADDRA, fifo_Read_Rs_data_memory$ADDRB; + wire fifo_Read_Rs_data_memory$ENA, + fifo_Read_Rs_data_memory$ENB, + fifo_Read_Rs_data_memory$WEA, + fifo_Read_Rs_data_memory$WEB; + + // ports of submodule fifo_Write_Rq_Addr + wire [63 : 0] fifo_Write_Rq_Addr$D_IN, fifo_Write_Rq_Addr$D_OUT; + wire fifo_Write_Rq_Addr$CLR, + fifo_Write_Rq_Addr$DEQ, + fifo_Write_Rq_Addr$EMPTY_N, + fifo_Write_Rq_Addr$ENQ, + fifo_Write_Rq_Addr$FULL_N; + + // ports of submodule fifo_Write_Rq_Data + wire [576 : 0] fifo_Write_Rq_Data$D_IN; + wire fifo_Write_Rq_Data$CLR, fifo_Write_Rq_Data$DEQ, fifo_Write_Rq_Data$ENQ; + + // ports of submodule fifo_Write_Rq_delay_mig + wire [383 : 0] fifo_Write_Rq_delay_mig$D_IN, fifo_Write_Rq_delay_mig$D_OUT; + wire fifo_Write_Rq_delay_mig$CLR, + fifo_Write_Rq_delay_mig$DEQ, + fifo_Write_Rq_delay_mig$EMPTY_N, + fifo_Write_Rq_delay_mig$ENQ, + fifo_Write_Rq_delay_mig$FULL_N; + + // ports of submodule fifo_Write_Rq_delay_nv + wire [383 : 0] fifo_Write_Rq_delay_nv$D_IN, fifo_Write_Rq_delay_nv$D_OUT; + wire fifo_Write_Rq_delay_nv$CLR, + fifo_Write_Rq_delay_nv$DEQ, + fifo_Write_Rq_delay_nv$EMPTY_N, + fifo_Write_Rq_delay_nv$ENQ, + fifo_Write_Rq_delay_nv$FULL_N; + + // ports of submodule fifo_Write_Rs + wire [2 : 0] fifo_Write_Rs$D_IN, fifo_Write_Rs$D_OUT; + wire fifo_Write_Rs$CLR, + fifo_Write_Rs$DEQ, + fifo_Write_Rs$EMPTY_N, + fifo_Write_Rs$ENQ, + fifo_Write_Rs$FULL_N; + + // ports of submodule mig_read_in + wire [63 : 0] mig_read_in$D_IN, mig_read_in$D_OUT; + wire mig_read_in$CLR, + mig_read_in$DEQ, + mig_read_in$EMPTY_N, + mig_read_in$ENQ, + mig_read_in$FULL_N; + + // ports of submodule mig_read_out + wire [515 : 0] mig_read_out$D_IN; + wire mig_read_out$CLR, mig_read_out$DEQ, mig_read_out$ENQ; + + // ports of submodule mig_read_out_1 + wire [515 : 0] mig_read_out_1$D_IN, mig_read_out_1$D_OUT; + wire mig_read_out_1$CLR, + mig_read_out_1$DEQ, + mig_read_out_1$EMPTY_N, + mig_read_out_1$ENQ, + mig_read_out_1$FULL_N; + + // ports of submodule mig_write_in_addr + wire [63 : 0] mig_write_in_addr$D_IN, mig_write_in_addr$D_OUT; + wire mig_write_in_addr$CLR, + mig_write_in_addr$DEQ, + mig_write_in_addr$EMPTY_N, + mig_write_in_addr$ENQ, + mig_write_in_addr$FULL_N; + + // ports of submodule mig_write_in_data + wire [576 : 0] mig_write_in_data$D_IN, mig_write_in_data$D_OUT; + wire mig_write_in_data$CLR, + mig_write_in_data$DEQ, + mig_write_in_data$EMPTY_N, + mig_write_in_data$ENQ, + mig_write_in_data$FULL_N; + + // ports of submodule mig_write_out + wire [2 : 0] mig_write_out$D_IN, mig_write_out$D_OUT; + wire mig_write_out$CLR, + mig_write_out$DEQ, + mig_write_out$EMPTY_N, + mig_write_out$ENQ, + mig_write_out$FULL_N; + + // ports of submodule nv_read_in + wire [93 : 0] nv_read_in$D_IN, nv_read_in$D_OUT; + wire nv_read_in$CLR, + nv_read_in$DEQ, + nv_read_in$EMPTY_N, + nv_read_in$ENQ, + nv_read_in$FULL_N; + + // ports of submodule nv_read_out + wire [515 : 0] nv_read_out$D_IN, nv_read_out$D_OUT; + wire nv_read_out$CLR, + nv_read_out$DEQ, + nv_read_out$EMPTY_N, + nv_read_out$ENQ, + nv_read_out$FULL_N; + + // ports of submodule nv_write_in_addr + wire [93 : 0] nv_write_in_addr$D_IN, nv_write_in_addr$D_OUT; + wire nv_write_in_addr$CLR, + nv_write_in_addr$DEQ, + nv_write_in_addr$EMPTY_N, + nv_write_in_addr$ENQ, + nv_write_in_addr$FULL_N; + + // ports of submodule nv_write_in_data + wire [576 : 0] nv_write_in_data$D_IN, nv_write_in_data$D_OUT; + wire nv_write_in_data$CLR, + nv_write_in_data$DEQ, + nv_write_in_data$EMPTY_N, + nv_write_in_data$ENQ, + nv_write_in_data$FULL_N; + + // ports of submodule nv_write_out + wire [2 : 0] nv_write_out$D_IN, nv_write_out$D_OUT; + wire nv_write_out$CLR, + nv_write_out$DEQ, + nv_write_out$EMPTY_N, + nv_write_out$ENQ, + nv_write_out$FULL_N; + + // rule scheduling signals + wire WILL_FIRE_RL_migRecieveReadResponse_nvSendReadResponse, + WILL_FIRE_RL_nvSendReadResponseResponse, + WILL_FIRE_RL_nvSendReadResponseWaitingLoop, + WILL_FIRE_RL_nvSendWriteResponseLast, + WILL_FIRE_RL_s_config_1_axiWriteFallback, + WILL_FIRE_RL_s_config_1_axiWriteSpecial, + WILL_FIRE_RL_s_config_1_axiWriteSpecialIsHandled, + WILL_FIRE_RL_s_config_1_axiWriteSpecialIsHandled_1, + WILL_FIRE_RL_s_config_1_axiWriteSpecialIsHandled_2, + WILL_FIRE_RL_s_config_1_axiWriteSpecialIsHandled_3, + WILL_FIRE_RL_s_config_1_axiWriteSpecialIsHandled_4, + WILL_FIRE_RL_s_config_1_axiWriteSpecial_1, + WILL_FIRE_RL_s_config_1_axiWriteSpecial_2, + WILL_FIRE_RL_s_config_1_axiWriteSpecial_3, + WILL_FIRE_RL_s_config_1_axiWriteSpecial_4, + WILL_FIRE_RL_s_config_axiReadFallback, + WILL_FIRE_RL_s_config_axiReadSpecial, + WILL_FIRE_RL_s_config_axiReadSpecialIsHandled, + WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_1, + WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_2, + WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_3, + WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_4, + WILL_FIRE_RL_s_config_axiReadSpecial_1, + WILL_FIRE_RL_s_config_axiReadSpecial_2, + WILL_FIRE_RL_s_config_axiReadSpecial_3, + WILL_FIRE_RL_s_config_axiReadSpecial_4, + WILL_FIRE_RL_writeDelayCalibrator2; + + // inputs to muxes for submodule ports + wire [66 : 0] MUX_s_config_readSlave_out_rv$port1__write_1__VAL_1, + MUX_s_config_readSlave_out_rv$port1__write_1__VAL_2, + MUX_s_config_readSlave_out_rv$port1__write_1__VAL_3, + MUX_s_config_readSlave_out_rv$port1__write_1__VAL_4, + MUX_s_config_readSlave_out_rv$port1__write_1__VAL_5; + wire [63 : 0] MUX_readNumberOfCycleToWait$write_1__VAL_2, + MUX_read_delay$write_1__VAL_2, + MUX_write_delay$write_1__VAL_2; + wire [11 : 0] MUX_writeNumberOfCycleToWait$write_1__VAL_1, + MUX_writeNumberOfCycleToWait$write_1__VAL_2; + wire MUX_isReadWaiting$write_1__SEL_1, + MUX_isWriteWaiting$write_1__SEL_1, + MUX_isWriteWaiting$write_1__SEL_2, + MUX_read_delay$write_1__SEL_1; + + // remaining internal signals + wire [579 : 0] fifo_Read_Rs_data_wDataIn_whas__46_AND_fifo_Re_ETC___d359; + wire [511 : 0] x__read_read_response_data__h23540; + wire [127 : 0] IF_fifo_Read_Rq_delay_mig_first__70_BITS_63_TO_ETC___d483, + IF_fifo_Write_Rq_delay_nv_first__25_BITS_63_TO_ETC___d435, + _0_CONCAT_cycleCount_93_33_PLUS_184467440737095_ETC___d434, + _0_CONCAT_fifo_Read_Rq_delay_mig_first__70_BITS_ETC___d480, + _0_CONCAT_fifo_Read_Rq_delay_mig_first__70_BITS_ETC__q1, + _0_CONCAT_fifo_Write_Rq_delay_nv_first__25_BITS_ETC___d430, + _0_CONCAT_fifo_Write_Rq_delay_nv_first__25_BITS_ETC__q3; + wire [63 : 0] IF_mig_read_out_1_first__68_BIT_0_69_THEN_IF_0_ETC___d488, + v__h5354, + v__h5718; + wire [8 : 0] x__h23641, x__h24038; + wire [7 : 0] IF_s_config_writeSlave_in_rv_BIT_3_THEN_s_conf_ETC__q2, + IF_s_config_writeSlave_in_rv_BIT_3_THEN_s_conf_ETC__q4; + wire x__read_read_response_id__h23539; + + // value method s_rd_arready + assign S_AXI_arready = + !s_config_readSlave_isRst_isInReset && + !s_config_readSlave_in_rv$port1__read[15] ; + + // value method s_rd_rvalid + assign S_AXI_rvalid = + !s_config_readSlave_isRst_isInReset && + s_config_readSlave_out_rv[66] ; + + // value method s_rd_rdata + assign S_AXI_rdata = + s_config_readSlave_out_rv[66] ? + s_config_readSlave_out_rv[65:2] : + 64'd0 ; + + // value method s_rd_rresp + assign S_AXI_rresp = + s_config_readSlave_out_rv[66] ? + s_config_readSlave_out_rv[1:0] : + 2'd0 ; + + // value method s_wr_awready + assign S_AXI_awready = + !s_config_writeSlave_isRst_isInReset && + !s_config_writeSlave_addrIn_rv[15] ; + + // value method s_wr_wready + assign S_AXI_wready = + !s_config_writeSlave_isRst_isInReset && + !s_config_writeSlave_dataIn_rv[72] ; + + // value method s_wr_bvalid + assign S_AXI_bvalid = + !s_config_writeSlave_isRst_isInReset && + s_config_writeSlave_out_rv[2] ; + + // value method s_wr_bresp + assign S_AXI_bresp = + s_config_writeSlave_out_rv[2] ? + s_config_writeSlave_out_rv[1:0] : + 2'd0 ; + + // value method in_read_arready + assign S_AXI_NV_arready = !nv_read_isRst_isInReset && nv_read_in$FULL_N ; + + // value method in_read_rvalid + assign S_AXI_NV_rvalid = !nv_read_isRst_isInReset && nv_read_out$EMPTY_N ; + + // value method in_read_rid + assign S_AXI_NV_rid = nv_read_out$EMPTY_N && nv_read_out$D_OUT[515] ; + + // value method in_read_rdata + assign S_AXI_NV_rdata = + nv_read_out$EMPTY_N ? nv_read_out$D_OUT[514:3] : 512'd0 ; + + // value method in_read_rresp + assign S_AXI_NV_rresp = + nv_read_out$EMPTY_N ? nv_read_out$D_OUT[2:1] : 2'd0 ; + + // value method in_read_rlast + assign S_AXI_NV_rlast = nv_read_out$EMPTY_N && nv_read_out$D_OUT[0] ; + + // value method in_write_awready + assign S_AXI_NV_awready = + !nv_write_isRst_isInReset && nv_write_in_addr$FULL_N ; + + // value method in_write_wready + assign S_AXI_NV_wready = + !nv_write_isRst_isInReset && nv_write_in_data$FULL_N ; + + // value method in_write_bvalid + assign S_AXI_NV_bvalid = !nv_write_isRst_isInReset && nv_write_out$EMPTY_N ; + + // value method in_write_bresp + assign S_AXI_NV_bresp = + nv_write_out$EMPTY_N ? nv_write_out$D_OUT[1:0] : 2'd0 ; + + // value method in_write_bid + assign S_AXI_NV_bid = nv_write_out$EMPTY_N && nv_write_out$D_OUT[2] ; + + // value method out_read_arvalid + assign M_AXI_MIG_arvalid = + !mig_read_isRst_isInReset && mig_read_in$EMPTY_N ; + + // value method out_read_arid + assign M_AXI_MIG_arid = mig_read_in$EMPTY_N && mig_read_in$D_OUT[63] ; + + // value method out_read_araddr + assign M_AXI_MIG_araddr = + mig_read_in$EMPTY_N ? mig_read_in$D_OUT[62:29] : 34'd0 ; + + // value method out_read_arlen + assign M_AXI_MIG_arlen = + mig_read_in$EMPTY_N ? mig_read_in$D_OUT[28:21] : 8'd0 ; + + // value method out_read_arsize + assign M_AXI_MIG_arsize = + mig_read_in$EMPTY_N ? mig_read_in$D_OUT[20:18] : 3'd0 ; + + // value method out_read_arburst + assign M_AXI_MIG_arburst = + mig_read_in$EMPTY_N ? mig_read_in$D_OUT[17:16] : 2'd0 ; + + // value method out_read_arlock + assign M_AXI_MIG_arlock = mig_read_in$EMPTY_N && mig_read_in$D_OUT[15] ; + + // value method out_read_arcache + assign M_AXI_MIG_arcache = + mig_read_in$EMPTY_N ? mig_read_in$D_OUT[14:11] : 4'd0 ; + + // value method out_read_arprot + assign M_AXI_MIG_arprot = + mig_read_in$EMPTY_N ? mig_read_in$D_OUT[10:8] : 3'd0 ; + + // value method out_read_arqos + assign M_AXI_MIG_arqos = + mig_read_in$EMPTY_N ? mig_read_in$D_OUT[7:4] : 4'd0 ; + + // value method out_read_arregion + assign M_AXI_MIG_arregion = + mig_read_in$EMPTY_N ? mig_read_in$D_OUT[3:0] : 4'd0 ; + + // value method out_read_rready + assign M_AXI_MIG_rready = + !mig_read_isRst_isInReset && mig_read_out_1$FULL_N ; + + // value method out_write_awvalid + assign M_AXI_MIG_awvalid = + !mig_write_isRst_isInReset && mig_write_in_addr$EMPTY_N ; + + // value method out_write_awid + assign M_AXI_MIG_awid = + mig_write_in_addr$EMPTY_N && mig_write_in_addr$D_OUT[63] ; + + // value method out_write_awaddr + assign M_AXI_MIG_awaddr = + mig_write_in_addr$EMPTY_N ? + mig_write_in_addr$D_OUT[62:29] : + 34'd0 ; + + // value method out_write_awlen + assign M_AXI_MIG_awlen = + mig_write_in_addr$EMPTY_N ? + mig_write_in_addr$D_OUT[28:21] : + 8'd0 ; + + // value method out_write_awsize + assign M_AXI_MIG_awsize = + mig_write_in_addr$EMPTY_N ? + mig_write_in_addr$D_OUT[20:18] : + 3'd0 ; + + // value method out_write_awburst + assign M_AXI_MIG_awburst = + mig_write_in_addr$EMPTY_N ? + mig_write_in_addr$D_OUT[17:16] : + 2'd0 ; + + // value method out_write_awlock + assign M_AXI_MIG_awlock = + mig_write_in_addr$EMPTY_N && mig_write_in_addr$D_OUT[15] ; + + // value method out_write_awcache + assign M_AXI_MIG_awcache = + mig_write_in_addr$EMPTY_N ? + mig_write_in_addr$D_OUT[14:11] : + 4'd0 ; + + // value method out_write_awprot + assign M_AXI_MIG_awprot = + mig_write_in_addr$EMPTY_N ? + mig_write_in_addr$D_OUT[10:8] : + 3'd0 ; + + // value method out_write_awqos + assign M_AXI_MIG_awqos = + mig_write_in_addr$EMPTY_N ? mig_write_in_addr$D_OUT[7:4] : 4'd0 ; + + // value method out_write_awregion + assign M_AXI_MIG_awregion = + mig_write_in_addr$EMPTY_N ? mig_write_in_addr$D_OUT[3:0] : 4'd0 ; + + // value method out_write_wvalid + assign M_AXI_MIG_wvalid = + !mig_write_isRst_isInReset && mig_write_in_data$EMPTY_N ; + + // value method out_write_wdata + assign M_AXI_MIG_wdata = + mig_write_in_data$EMPTY_N ? + mig_write_in_data$D_OUT[576:65] : + 512'd0 ; + + // value method out_write_wstrb + assign M_AXI_MIG_wstrb = + mig_write_in_data$EMPTY_N ? + mig_write_in_data$D_OUT[64:1] : + 64'd0 ; + + // value method out_write_wlast + assign M_AXI_MIG_wlast = + mig_write_in_data$EMPTY_N && mig_write_in_data$D_OUT[0] ; + + // value method out_write_bready + assign M_AXI_MIG_bready = + !mig_write_isRst_isInReset && mig_write_out$FULL_N ; + + // value method interrupt + assign interrupt = interruptR ; + + // submodule fifo_Read_Rq + SizedFIFO #(.p1width(32'd64), + .p2depth(32'd10), + .p3cntr_width(32'd4), + .guarded(1'd1)) fifo_Read_Rq(.RST(RST_N), + .CLK(CLK), + .D_IN(fifo_Read_Rq$D_IN), + .ENQ(fifo_Read_Rq$ENQ), + .DEQ(fifo_Read_Rq$DEQ), + .CLR(fifo_Read_Rq$CLR), + .D_OUT(fifo_Read_Rq$D_OUT), + .FULL_N(fifo_Read_Rq$FULL_N), + .EMPTY_N(fifo_Read_Rq$EMPTY_N)); + + // submodule fifo_Read_Rq_delay_mig + SizedFIFO #(.p1width(32'd384), + .p2depth(32'd10), + .p3cntr_width(32'd4), + .guarded(1'd1)) fifo_Read_Rq_delay_mig(.RST(RST_N), + .CLK(CLK), + .D_IN(fifo_Read_Rq_delay_mig$D_IN), + .ENQ(fifo_Read_Rq_delay_mig$ENQ), + .DEQ(fifo_Read_Rq_delay_mig$DEQ), + .CLR(fifo_Read_Rq_delay_mig$CLR), + .D_OUT(fifo_Read_Rq_delay_mig$D_OUT), + .FULL_N(fifo_Read_Rq_delay_mig$FULL_N), + .EMPTY_N(fifo_Read_Rq_delay_mig$EMPTY_N)); + + // submodule fifo_Read_Rq_delay_nv + SizedFIFO #(.p1width(32'd384), + .p2depth(32'd10), + .p3cntr_width(32'd4), + .guarded(1'd1)) fifo_Read_Rq_delay_nv(.RST(RST_N), + .CLK(CLK), + .D_IN(fifo_Read_Rq_delay_nv$D_IN), + .ENQ(fifo_Read_Rq_delay_nv$ENQ), + .DEQ(fifo_Read_Rq_delay_nv$DEQ), + .CLR(fifo_Read_Rq_delay_nv$CLR), + .D_OUT(), + .FULL_N(), + .EMPTY_N()); + + // submodule fifo_Read_Rs_data_memory + BRAM2 #(.PIPELINED(1'd0), + .ADDR_WIDTH(32'd8), + .DATA_WIDTH(32'd580), + .MEMSIZE(9'd256)) fifo_Read_Rs_data_memory(.CLKA(CLK), + .CLKB(CLK), + .ADDRA(fifo_Read_Rs_data_memory$ADDRA), + .ADDRB(fifo_Read_Rs_data_memory$ADDRB), + .DIA(fifo_Read_Rs_data_memory$DIA), + .DIB(fifo_Read_Rs_data_memory$DIB), + .WEA(fifo_Read_Rs_data_memory$WEA), + .WEB(fifo_Read_Rs_data_memory$WEB), + .ENA(fifo_Read_Rs_data_memory$ENA), + .ENB(fifo_Read_Rs_data_memory$ENB), + .DOA(), + .DOB(fifo_Read_Rs_data_memory$DOB)); + + // submodule fifo_Write_Rq_Addr + SizedFIFO #(.p1width(32'd64), + .p2depth(32'd10), + .p3cntr_width(32'd4), + .guarded(1'd1)) fifo_Write_Rq_Addr(.RST(RST_N), + .CLK(CLK), + .D_IN(fifo_Write_Rq_Addr$D_IN), + .ENQ(fifo_Write_Rq_Addr$ENQ), + .DEQ(fifo_Write_Rq_Addr$DEQ), + .CLR(fifo_Write_Rq_Addr$CLR), + .D_OUT(fifo_Write_Rq_Addr$D_OUT), + .FULL_N(fifo_Write_Rq_Addr$FULL_N), + .EMPTY_N(fifo_Write_Rq_Addr$EMPTY_N)); + + // submodule fifo_Write_Rq_Data + SizedFIFO #(.p1width(32'd577), + .p2depth(32'd10), + .p3cntr_width(32'd4), + .guarded(1'd1)) fifo_Write_Rq_Data(.RST(RST_N), + .CLK(CLK), + .D_IN(fifo_Write_Rq_Data$D_IN), + .ENQ(fifo_Write_Rq_Data$ENQ), + .DEQ(fifo_Write_Rq_Data$DEQ), + .CLR(fifo_Write_Rq_Data$CLR), + .D_OUT(), + .FULL_N(), + .EMPTY_N()); + + // submodule fifo_Write_Rq_delay_mig + SizedFIFO #(.p1width(32'd384), + .p2depth(32'd10), + .p3cntr_width(32'd4), + .guarded(1'd1)) fifo_Write_Rq_delay_mig(.RST(RST_N), + .CLK(CLK), + .D_IN(fifo_Write_Rq_delay_mig$D_IN), + .ENQ(fifo_Write_Rq_delay_mig$ENQ), + .DEQ(fifo_Write_Rq_delay_mig$DEQ), + .CLR(fifo_Write_Rq_delay_mig$CLR), + .D_OUT(fifo_Write_Rq_delay_mig$D_OUT), + .FULL_N(fifo_Write_Rq_delay_mig$FULL_N), + .EMPTY_N(fifo_Write_Rq_delay_mig$EMPTY_N)); + + // submodule fifo_Write_Rq_delay_nv + SizedFIFO #(.p1width(32'd384), + .p2depth(32'd10), + .p3cntr_width(32'd4), + .guarded(1'd1)) fifo_Write_Rq_delay_nv(.RST(RST_N), + .CLK(CLK), + .D_IN(fifo_Write_Rq_delay_nv$D_IN), + .ENQ(fifo_Write_Rq_delay_nv$ENQ), + .DEQ(fifo_Write_Rq_delay_nv$DEQ), + .CLR(fifo_Write_Rq_delay_nv$CLR), + .D_OUT(fifo_Write_Rq_delay_nv$D_OUT), + .FULL_N(fifo_Write_Rq_delay_nv$FULL_N), + .EMPTY_N(fifo_Write_Rq_delay_nv$EMPTY_N)); + + // submodule fifo_Write_Rs + SizedFIFO #(.p1width(32'd3), + .p2depth(32'd10), + .p3cntr_width(32'd4), + .guarded(1'd1)) fifo_Write_Rs(.RST(RST_N), + .CLK(CLK), + .D_IN(fifo_Write_Rs$D_IN), + .ENQ(fifo_Write_Rs$ENQ), + .DEQ(fifo_Write_Rs$DEQ), + .CLR(fifo_Write_Rs$CLR), + .D_OUT(fifo_Write_Rs$D_OUT), + .FULL_N(fifo_Write_Rs$FULL_N), + .EMPTY_N(fifo_Write_Rs$EMPTY_N)); + + // submodule mig_read_in + SizedFIFO #(.p1width(32'd64), + .p2depth(32'd10), + .p3cntr_width(32'd4), + .guarded(1'd1)) mig_read_in(.RST(RST_N), + .CLK(CLK), + .D_IN(mig_read_in$D_IN), + .ENQ(mig_read_in$ENQ), + .DEQ(mig_read_in$DEQ), + .CLR(mig_read_in$CLR), + .D_OUT(mig_read_in$D_OUT), + .FULL_N(mig_read_in$FULL_N), + .EMPTY_N(mig_read_in$EMPTY_N)); + + // submodule mig_read_out + SizedFIFO #(.p1width(32'd516), + .p2depth(32'd10), + .p3cntr_width(32'd4), + .guarded(1'd1)) mig_read_out(.RST(RST_N), + .CLK(CLK), + .D_IN(mig_read_out$D_IN), + .ENQ(mig_read_out$ENQ), + .DEQ(mig_read_out$DEQ), + .CLR(mig_read_out$CLR), + .D_OUT(), + .FULL_N(), + .EMPTY_N()); + + // submodule mig_read_out_1 + SizedFIFO #(.p1width(32'd516), + .p2depth(32'd10), + .p3cntr_width(32'd4), + .guarded(1'd1)) mig_read_out_1(.RST(RST_N), + .CLK(CLK), + .D_IN(mig_read_out_1$D_IN), + .ENQ(mig_read_out_1$ENQ), + .DEQ(mig_read_out_1$DEQ), + .CLR(mig_read_out_1$CLR), + .D_OUT(mig_read_out_1$D_OUT), + .FULL_N(mig_read_out_1$FULL_N), + .EMPTY_N(mig_read_out_1$EMPTY_N)); + + // submodule mig_write_in_addr + SizedFIFO #(.p1width(32'd64), + .p2depth(32'd10), + .p3cntr_width(32'd4), + .guarded(1'd1)) mig_write_in_addr(.RST(RST_N), + .CLK(CLK), + .D_IN(mig_write_in_addr$D_IN), + .ENQ(mig_write_in_addr$ENQ), + .DEQ(mig_write_in_addr$DEQ), + .CLR(mig_write_in_addr$CLR), + .D_OUT(mig_write_in_addr$D_OUT), + .FULL_N(mig_write_in_addr$FULL_N), + .EMPTY_N(mig_write_in_addr$EMPTY_N)); + + // submodule mig_write_in_data + SizedFIFO #(.p1width(32'd577), + .p2depth(32'd10), + .p3cntr_width(32'd4), + .guarded(1'd1)) mig_write_in_data(.RST(RST_N), + .CLK(CLK), + .D_IN(mig_write_in_data$D_IN), + .ENQ(mig_write_in_data$ENQ), + .DEQ(mig_write_in_data$DEQ), + .CLR(mig_write_in_data$CLR), + .D_OUT(mig_write_in_data$D_OUT), + .FULL_N(mig_write_in_data$FULL_N), + .EMPTY_N(mig_write_in_data$EMPTY_N)); + + // submodule mig_write_out + SizedFIFO #(.p1width(32'd3), + .p2depth(32'd10), + .p3cntr_width(32'd4), + .guarded(1'd1)) mig_write_out(.RST(RST_N), + .CLK(CLK), + .D_IN(mig_write_out$D_IN), + .ENQ(mig_write_out$ENQ), + .DEQ(mig_write_out$DEQ), + .CLR(mig_write_out$CLR), + .D_OUT(mig_write_out$D_OUT), + .FULL_N(mig_write_out$FULL_N), + .EMPTY_N(mig_write_out$EMPTY_N)); + + // submodule nv_read_in + SizedFIFO #(.p1width(32'd94), + .p2depth(32'd10), + .p3cntr_width(32'd4), + .guarded(1'd1)) nv_read_in(.RST(RST_N), + .CLK(CLK), + .D_IN(nv_read_in$D_IN), + .ENQ(nv_read_in$ENQ), + .DEQ(nv_read_in$DEQ), + .CLR(nv_read_in$CLR), + .D_OUT(nv_read_in$D_OUT), + .FULL_N(nv_read_in$FULL_N), + .EMPTY_N(nv_read_in$EMPTY_N)); + + // submodule nv_read_out + SizedFIFO #(.p1width(32'd516), + .p2depth(32'd10), + .p3cntr_width(32'd4), + .guarded(1'd1)) nv_read_out(.RST(RST_N), + .CLK(CLK), + .D_IN(nv_read_out$D_IN), + .ENQ(nv_read_out$ENQ), + .DEQ(nv_read_out$DEQ), + .CLR(nv_read_out$CLR), + .D_OUT(nv_read_out$D_OUT), + .FULL_N(nv_read_out$FULL_N), + .EMPTY_N(nv_read_out$EMPTY_N)); + + // submodule nv_write_in_addr + SizedFIFO #(.p1width(32'd94), + .p2depth(32'd10), + .p3cntr_width(32'd4), + .guarded(1'd1)) nv_write_in_addr(.RST(RST_N), + .CLK(CLK), + .D_IN(nv_write_in_addr$D_IN), + .ENQ(nv_write_in_addr$ENQ), + .DEQ(nv_write_in_addr$DEQ), + .CLR(nv_write_in_addr$CLR), + .D_OUT(nv_write_in_addr$D_OUT), + .FULL_N(nv_write_in_addr$FULL_N), + .EMPTY_N(nv_write_in_addr$EMPTY_N)); + + // submodule nv_write_in_data + SizedFIFO #(.p1width(32'd577), + .p2depth(32'd10), + .p3cntr_width(32'd4), + .guarded(1'd1)) nv_write_in_data(.RST(RST_N), + .CLK(CLK), + .D_IN(nv_write_in_data$D_IN), + .ENQ(nv_write_in_data$ENQ), + .DEQ(nv_write_in_data$DEQ), + .CLR(nv_write_in_data$CLR), + .D_OUT(nv_write_in_data$D_OUT), + .FULL_N(nv_write_in_data$FULL_N), + .EMPTY_N(nv_write_in_data$EMPTY_N)); + + // submodule nv_write_out + SizedFIFO #(.p1width(32'd3), + .p2depth(32'd10), + .p3cntr_width(32'd4), + .guarded(1'd1)) nv_write_out(.RST(RST_N), + .CLK(CLK), + .D_IN(nv_write_out$D_IN), + .ENQ(nv_write_out$ENQ), + .DEQ(nv_write_out$DEQ), + .CLR(nv_write_out$CLR), + .D_OUT(nv_write_out$D_OUT), + .FULL_N(nv_write_out$FULL_N), + .EMPTY_N(nv_write_out$EMPTY_N)); + + // rule RL_writeDelayCalibrator2 + assign WILL_FIRE_RL_writeDelayCalibrator2 = + fifo_Write_Rq_delay_nv$EMPTY_N && !isWriteWaiting ; + + // rule RL_s_config_axiReadSpecialIsHandled + assign WILL_FIRE_RL_s_config_axiReadSpecialIsHandled = + s_config_readSlave_in_rv[15] && + s_config_readSlave_in_rv[9:6] == 4'd0 ; + + // rule RL_s_config_axiReadSpecialIsHandled_1 + assign WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_1 = + s_config_readSlave_in_rv[15] && + s_config_readSlave_in_rv[9:6] == 4'd2 ; + + // rule RL_s_config_axiReadSpecialIsHandled_2 + assign WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_2 = + s_config_readSlave_in_rv[15] && + s_config_readSlave_in_rv[9:6] == 4'd4 ; + + // rule RL_s_config_axiReadSpecialIsHandled_3 + assign WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_3 = + s_config_readSlave_in_rv[15] && + s_config_readSlave_in_rv[9:6] == 4'd6 ; + + // rule RL_s_config_axiReadSpecialIsHandled_4 + assign WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_4 = + s_config_readSlave_in_rv[15] && + s_config_readSlave_in_rv[9:6] == 4'd8 ; + + // rule RL_s_config_axiReadSpecial + assign WILL_FIRE_RL_s_config_axiReadSpecial = + s_config_readSlave_in_rv[15] && + !s_config_readSlave_out_rv$port1__read[66] && + s_config_readSlave_in_rv[9:6] == 4'd0 && + !s_config_readBusy ; + + // rule RL_s_config_axiReadSpecial_1 + assign WILL_FIRE_RL_s_config_axiReadSpecial_1 = + s_config_readSlave_in_rv[15] && + !s_config_readSlave_out_rv$port1__read[66] && + s_config_readSlave_in_rv[9:6] == 4'd2 && + !s_config_readBusy ; + + // rule RL_s_config_axiReadSpecial_2 + assign WILL_FIRE_RL_s_config_axiReadSpecial_2 = + s_config_readSlave_in_rv[15] && + !s_config_readSlave_out_rv$port1__read[66] && + s_config_readSlave_in_rv[9:6] == 4'd4 && + !s_config_readBusy ; + + // rule RL_s_config_axiReadSpecial_3 + assign WILL_FIRE_RL_s_config_axiReadSpecial_3 = + s_config_readSlave_in_rv[15] && + !s_config_readSlave_out_rv$port1__read[66] && + s_config_readSlave_in_rv[9:6] == 4'd6 && + !s_config_readBusy ; + + // rule RL_s_config_axiReadSpecial_4 + assign WILL_FIRE_RL_s_config_axiReadSpecial_4 = + s_config_readSlave_in_rv[15] && + !s_config_readSlave_out_rv$port1__read[66] && + s_config_readSlave_in_rv[9:6] == 4'd8 && + !s_config_readBusy ; + + // rule RL_s_config_axiReadFallback + assign WILL_FIRE_RL_s_config_axiReadFallback = + s_config_readSlave_in_rv[15] && + !s_config_readSlave_out_rv$port1__read[66] && + !s_config_readIsHandled$whas ; + + // rule RL_s_config_1_axiWriteSpecialIsHandled + assign WILL_FIRE_RL_s_config_1_axiWriteSpecialIsHandled = + s_config_writeSlave_in_rv[87] && + s_config_writeSlave_in_rv[81:78] == 4'd0 ; + + // rule RL_s_config_1_axiWriteSpecial + assign WILL_FIRE_RL_s_config_1_axiWriteSpecial = + s_config_writeSlave_in_rv[87] && + !s_config_writeSlave_out_rv$port1__read[2] && + s_config_writeSlave_in_rv[81:78] == 4'd0 && + !s_config_writeBusy && + !start ; + + // rule RL_s_config_1_axiWriteSpecialIsHandled_1 + assign WILL_FIRE_RL_s_config_1_axiWriteSpecialIsHandled_1 = + s_config_writeSlave_in_rv[87] && + s_config_writeSlave_in_rv[81:78] == 4'd2 ; + + // rule RL_s_config_1_axiWriteSpecial_1 + assign WILL_FIRE_RL_s_config_1_axiWriteSpecial_1 = + s_config_writeSlave_in_rv[87] && + !s_config_writeSlave_out_rv$port1__read[2] && + s_config_writeSlave_in_rv[81:78] == 4'd2 && + !s_config_writeBusy ; + + // rule RL_s_config_1_axiWriteSpecialIsHandled_2 + assign WILL_FIRE_RL_s_config_1_axiWriteSpecialIsHandled_2 = + s_config_writeSlave_in_rv[87] && + s_config_writeSlave_in_rv[81:78] == 4'd4 ; + + // rule RL_s_config_1_axiWriteSpecialIsHandled_3 + assign WILL_FIRE_RL_s_config_1_axiWriteSpecialIsHandled_3 = + s_config_writeSlave_in_rv[87] && + s_config_writeSlave_in_rv[81:78] == 4'd6 ; + + // rule RL_s_config_1_axiWriteSpecialIsHandled_4 + assign WILL_FIRE_RL_s_config_1_axiWriteSpecialIsHandled_4 = + s_config_writeSlave_in_rv[87] && + s_config_writeSlave_in_rv[81:78] == 4'd8 ; + + // rule RL_s_config_1_axiWriteSpecial_4 + assign WILL_FIRE_RL_s_config_1_axiWriteSpecial_4 = + s_config_writeSlave_in_rv[87] && + !s_config_writeSlave_out_rv$port1__read[2] && + s_config_writeSlave_in_rv[81:78] == 4'd8 && + !s_config_writeBusy ; + + // rule RL_s_config_1_axiWriteFallback + assign WILL_FIRE_RL_s_config_1_axiWriteFallback = + s_config_writeSlave_in_rv[87] && + !s_config_writeSlave_out_rv$port1__read[2] && + !s_config_writeIsHandled$whas && + !WILL_FIRE_RL_s_config_1_axiWriteSpecial_4 && + !WILL_FIRE_RL_s_config_1_axiWriteSpecial_3 && + !WILL_FIRE_RL_s_config_1_axiWriteSpecial_2 && + !WILL_FIRE_RL_s_config_1_axiWriteSpecial_1 && + !WILL_FIRE_RL_s_config_1_axiWriteSpecial ; + + // rule RL_migRecieveReadResponse_nvSendReadResponse + assign WILL_FIRE_RL_migRecieveReadResponse_nvSendReadResponse = + fifo_Read_Rs_data_rRdPtr + 9'd128 != fifo_Read_Rs_data_rWrPtr && + mig_read_out_1$EMPTY_N && + fifo_Read_Rq_delay_mig$EMPTY_N ; + + // rule RL_s_config_1_axiWriteSpecial_3 + assign WILL_FIRE_RL_s_config_1_axiWriteSpecial_3 = + s_config_writeSlave_in_rv[87] && + !s_config_writeSlave_out_rv$port1__read[2] && + s_config_writeSlave_in_rv[81:78] == 4'd6 && + !s_config_writeBusy ; + + // rule RL_s_config_1_axiWriteSpecial_2 + assign WILL_FIRE_RL_s_config_1_axiWriteSpecial_2 = + s_config_writeSlave_in_rv[87] && + !s_config_writeSlave_out_rv$port1__read[2] && + s_config_writeSlave_in_rv[81:78] == 4'd4 && + !s_config_writeBusy ; + + // rule RL_nvSendReadResponseWaitingLoop + assign WILL_FIRE_RL_nvSendReadResponseWaitingLoop = + nv_read_out$FULL_N && readNumberOfCycleToWait != 64'd0 && + isReadWaiting ; + + // rule RL_nvSendWriteResponseLast + assign WILL_FIRE_RL_nvSendWriteResponseLast = + fifo_Write_Rs$EMPTY_N && nv_write_out$FULL_N && isWriteWaiting ; + + // rule RL_nvSendReadResponseResponse + assign WILL_FIRE_RL_nvSendReadResponseResponse = + fifo_Read_Rs_data_rRdPtr != fifo_Read_Rs_data_rWrPtr && + !isReadWaiting ; + + // inputs to muxes for submodule ports + assign MUX_isReadWaiting$write_1__SEL_1 = + WILL_FIRE_RL_nvSendReadResponseWaitingLoop && + readNumberOfCycleToWait == 64'd1 ; + assign MUX_isWriteWaiting$write_1__SEL_1 = + WILL_FIRE_RL_writeDelayCalibrator2 && + writeNumberOfCycleToWait == 12'd0 ; + assign MUX_isWriteWaiting$write_1__SEL_2 = + WILL_FIRE_RL_nvSendWriteResponseLast && + writeNumberOfCycleToWait == 12'd1 ; + assign MUX_read_delay$write_1__SEL_1 = start && !operation ; + assign MUX_readNumberOfCycleToWait$write_1__VAL_2 = + readNumberOfCycleToWait - 64'd1 ; + assign MUX_read_delay$write_1__VAL_2 = + { s_config_writeSlave_in_rv[10] ? + s_config_writeSlave_in_rv[74:67] : + read_delay[63:56], + s_config_writeSlave_in_rv[9] ? + s_config_writeSlave_in_rv[66:59] : + read_delay[55:48], + s_config_writeSlave_in_rv[8] ? + s_config_writeSlave_in_rv[58:51] : + read_delay[47:40], + s_config_writeSlave_in_rv[7] ? + s_config_writeSlave_in_rv[50:43] : + read_delay[39:32], + s_config_writeSlave_in_rv[6] ? + s_config_writeSlave_in_rv[42:35] : + read_delay[31:24], + s_config_writeSlave_in_rv[5] ? + s_config_writeSlave_in_rv[34:27] : + read_delay[23:16], + s_config_writeSlave_in_rv[4] ? + s_config_writeSlave_in_rv[26:19] : + read_delay[15:8], + s_config_writeSlave_in_rv[3] ? + s_config_writeSlave_in_rv[18:11] : + read_delay[7:0] } ; + assign MUX_s_config_readSlave_out_rv$port1__write_1__VAL_1 = + { 1'd1, v__h5354, 2'd0 } ; + assign MUX_s_config_readSlave_out_rv$port1__write_1__VAL_2 = + { 1'd1, status, 2'd0 } ; + assign MUX_s_config_readSlave_out_rv$port1__write_1__VAL_3 = + { 1'd1, v__h5718, 2'd0 } ; + assign MUX_s_config_readSlave_out_rv$port1__write_1__VAL_4 = + { 1'd1, read_delay, 2'd0 } ; + assign MUX_s_config_readSlave_out_rv$port1__write_1__VAL_5 = + { 1'd1, write_delay, 2'd0 } ; + assign MUX_writeNumberOfCycleToWait$write_1__VAL_1 = + (_0_CONCAT_fifo_Write_Rq_delay_nv_first__25_BITS_ETC___d430 <= + IF_fifo_Write_Rq_delay_nv_first__25_BITS_63_TO_ETC___d435) ? + 12'd1 : + _0_CONCAT_fifo_Write_Rq_delay_nv_first__25_BITS_ETC__q3[11:0] ; + assign MUX_writeNumberOfCycleToWait$write_1__VAL_2 = + writeNumberOfCycleToWait - 12'd1 ; + assign MUX_write_delay$write_1__VAL_2 = + { s_config_writeSlave_in_rv[10] ? + s_config_writeSlave_in_rv[74:67] : + write_delay[63:56], + s_config_writeSlave_in_rv[9] ? + s_config_writeSlave_in_rv[66:59] : + write_delay[55:48], + s_config_writeSlave_in_rv[8] ? + s_config_writeSlave_in_rv[58:51] : + write_delay[47:40], + s_config_writeSlave_in_rv[7] ? + s_config_writeSlave_in_rv[50:43] : + write_delay[39:32], + s_config_writeSlave_in_rv[6] ? + s_config_writeSlave_in_rv[42:35] : + write_delay[31:24], + s_config_writeSlave_in_rv[5] ? + s_config_writeSlave_in_rv[34:27] : + write_delay[23:16], + s_config_writeSlave_in_rv[4] ? + s_config_writeSlave_in_rv[26:19] : + write_delay[15:8], + s_config_writeSlave_in_rv[3] ? + s_config_writeSlave_in_rv[18:11] : + write_delay[7:0] } ; + + // inlined wires + assign s_config_readIsHandled$whas = + WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_4 || + WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_3 || + WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_2 || + WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_1 || + WILL_FIRE_RL_s_config_axiReadSpecialIsHandled ; + assign s_config_writeIsHandled$whas = + WILL_FIRE_RL_s_config_1_axiWriteSpecialIsHandled_4 || + WILL_FIRE_RL_s_config_1_axiWriteSpecialIsHandled_3 || + WILL_FIRE_RL_s_config_1_axiWriteSpecialIsHandled_2 || + WILL_FIRE_RL_s_config_1_axiWriteSpecialIsHandled_1 || + WILL_FIRE_RL_s_config_1_axiWriteSpecialIsHandled ; + assign fifo_Read_Rs_data_wDataIn$wget = + { mig_read_out_1$D_OUT, + IF_mig_read_out_1_first__68_BIT_0_69_THEN_IF_0_ETC___d488 } ; + assign fifo_Read_Rs_data_wDataOut$wget = + (fifo_Read_Rs_data_rCache[589] && + fifo_Read_Rs_data_rCache[588:580] == fifo_Read_Rs_data_rRdPtr) ? + fifo_Read_Rs_data_rCache[579:0] : + fifo_Read_Rs_data_memory$DOB ; + assign mig_read_rinpkg$wget = + { M_AXI_MIG_rid, + M_AXI_MIG_rdata, + M_AXI_MIG_rresp, + M_AXI_MIG_rlast } ; + assign mig_write_rinpkg$wget = { M_AXI_MIG_bid, M_AXI_MIG_bresp } ; + assign nv_read_arinpkg$wget = + { S_AXI_NV_arid, + S_AXI_NV_araddr, + S_AXI_NV_arlen, + S_AXI_NV_arsize, + S_AXI_NV_arburst, + S_AXI_NV_arlock, + S_AXI_NV_arcache, + S_AXI_NV_arprot, + S_AXI_NV_arqos, + S_AXI_NV_arregion } ; + assign nv_write_arinpkg_addr$wget = + { S_AXI_NV_awid, + S_AXI_NV_awaddr, + S_AXI_NV_awlen, + S_AXI_NV_awsize, + S_AXI_NV_awburst, + S_AXI_NV_awlock, + S_AXI_NV_awcache, + S_AXI_NV_awprot, + S_AXI_NV_awqos, + S_AXI_NV_awregion } ; + assign nv_write_arinpkg_data$wget = + { S_AXI_NV_wdata, S_AXI_NV_wstrb, S_AXI_NV_wlast } ; + assign s_config_readSlave_in_rv$EN_port0__write = + WILL_FIRE_RL_s_config_axiReadFallback || + WILL_FIRE_RL_s_config_axiReadSpecial_4 || + WILL_FIRE_RL_s_config_axiReadSpecial_3 || + WILL_FIRE_RL_s_config_axiReadSpecial_2 || + WILL_FIRE_RL_s_config_axiReadSpecial_1 || + WILL_FIRE_RL_s_config_axiReadSpecial ; + assign s_config_readSlave_in_rv$port1__read = + s_config_readSlave_in_rv$EN_port0__write ? + 16'd10922 : + s_config_readSlave_in_rv ; + assign s_config_readSlave_in_rv$EN_port1__write = + !s_config_readSlave_in_rv$port1__read[15] && + !s_config_readSlave_isRst_isInReset && + S_AXI_arvalid ; + assign s_config_readSlave_in_rv$port1__write_1 = + { 1'd1, S_AXI_araddr, S_AXI_arprot } ; + assign s_config_readSlave_in_rv$port2__read = + s_config_readSlave_in_rv$EN_port1__write ? + s_config_readSlave_in_rv$port1__write_1 : + s_config_readSlave_in_rv$port1__read ; + assign s_config_readSlave_out_rv$EN_port0__write = + s_config_readSlave_out_rv[66] && + !s_config_readSlave_isRst_isInReset && + S_AXI_rready ; + assign s_config_readSlave_out_rv$port1__read = + s_config_readSlave_out_rv$EN_port0__write ? + 67'h2AAAAAAAAAAAAAAAA : + s_config_readSlave_out_rv ; + assign s_config_readSlave_out_rv$EN_port1__write = + WILL_FIRE_RL_s_config_axiReadSpecial || + WILL_FIRE_RL_s_config_axiReadSpecial_1 || + WILL_FIRE_RL_s_config_axiReadSpecial_2 || + WILL_FIRE_RL_s_config_axiReadSpecial_3 || + WILL_FIRE_RL_s_config_axiReadSpecial_4 || + WILL_FIRE_RL_s_config_axiReadFallback ; + always@(WILL_FIRE_RL_s_config_axiReadSpecial or + MUX_s_config_readSlave_out_rv$port1__write_1__VAL_1 or + WILL_FIRE_RL_s_config_axiReadSpecial_1 or + MUX_s_config_readSlave_out_rv$port1__write_1__VAL_2 or + WILL_FIRE_RL_s_config_axiReadSpecial_2 or + MUX_s_config_readSlave_out_rv$port1__write_1__VAL_3 or + WILL_FIRE_RL_s_config_axiReadSpecial_3 or + MUX_s_config_readSlave_out_rv$port1__write_1__VAL_4 or + WILL_FIRE_RL_s_config_axiReadSpecial_4 or + MUX_s_config_readSlave_out_rv$port1__write_1__VAL_5 or + WILL_FIRE_RL_s_config_axiReadFallback) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_s_config_axiReadSpecial: + s_config_readSlave_out_rv$port1__write_1 = + MUX_s_config_readSlave_out_rv$port1__write_1__VAL_1; + WILL_FIRE_RL_s_config_axiReadSpecial_1: + s_config_readSlave_out_rv$port1__write_1 = + MUX_s_config_readSlave_out_rv$port1__write_1__VAL_2; + WILL_FIRE_RL_s_config_axiReadSpecial_2: + s_config_readSlave_out_rv$port1__write_1 = + MUX_s_config_readSlave_out_rv$port1__write_1__VAL_3; + WILL_FIRE_RL_s_config_axiReadSpecial_3: + s_config_readSlave_out_rv$port1__write_1 = + MUX_s_config_readSlave_out_rv$port1__write_1__VAL_4; + WILL_FIRE_RL_s_config_axiReadSpecial_4: + s_config_readSlave_out_rv$port1__write_1 = + MUX_s_config_readSlave_out_rv$port1__write_1__VAL_5; + WILL_FIRE_RL_s_config_axiReadFallback: + s_config_readSlave_out_rv$port1__write_1 = 67'h40000000000000000; + default: s_config_readSlave_out_rv$port1__write_1 = + 67'h2AAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign s_config_readSlave_out_rv$port2__read = + s_config_readSlave_out_rv$EN_port1__write ? + s_config_readSlave_out_rv$port1__write_1 : + s_config_readSlave_out_rv$port1__read ; + assign s_config_writeSlave_in_rv$EN_port0__write = + WILL_FIRE_RL_s_config_1_axiWriteSpecial_4 || + WILL_FIRE_RL_s_config_1_axiWriteSpecial_3 || + WILL_FIRE_RL_s_config_1_axiWriteSpecial_2 || + WILL_FIRE_RL_s_config_1_axiWriteSpecial_1 || + WILL_FIRE_RL_s_config_1_axiWriteFallback || + WILL_FIRE_RL_s_config_1_axiWriteSpecial ; + assign s_config_writeSlave_in_rv$port1__read = + s_config_writeSlave_in_rv$EN_port0__write ? + 88'h2AAAAAAAAAAAAAAAAAAAAA : + s_config_writeSlave_in_rv ; + assign s_config_writeSlave_in_rv$EN_port1__write = + s_config_writeSlave_addrIn_rv$port1__read[15] && + s_config_writeSlave_dataIn_rv$port1__read[72] && + !s_config_writeSlave_in_rv$port1__read[87] ; + assign s_config_writeSlave_in_rv$port1__write_1 = + { 1'd1, + s_config_writeSlave_addrIn_rv$port1__read[14:3], + s_config_writeSlave_dataIn_rv$port1__read[71:0], + s_config_writeSlave_addrIn_rv$port1__read[2:0] } ; + assign s_config_writeSlave_in_rv$port2__read = + s_config_writeSlave_in_rv$EN_port1__write ? + s_config_writeSlave_in_rv$port1__write_1 : + s_config_writeSlave_in_rv$port1__read ; + assign s_config_writeSlave_out_rv$EN_port0__write = + s_config_writeSlave_out_rv[2] && + !s_config_writeSlave_isRst_isInReset && + S_AXI_bready ; + assign s_config_writeSlave_out_rv$port1__read = + s_config_writeSlave_out_rv$EN_port0__write ? + 3'd2 : + s_config_writeSlave_out_rv ; + assign s_config_writeSlave_out_rv$EN_port1__write = + WILL_FIRE_RL_s_config_1_axiWriteSpecial_4 || + WILL_FIRE_RL_s_config_1_axiWriteSpecial_3 || + WILL_FIRE_RL_s_config_1_axiWriteSpecial_2 || + WILL_FIRE_RL_s_config_1_axiWriteSpecial_1 || + WILL_FIRE_RL_s_config_1_axiWriteFallback || + WILL_FIRE_RL_s_config_1_axiWriteSpecial ; + assign s_config_writeSlave_out_rv$port2__read = + s_config_writeSlave_out_rv$EN_port1__write ? + 3'd4 : + s_config_writeSlave_out_rv$port1__read ; + assign s_config_writeSlave_addrIn_rv$EN_port0__write = + !s_config_writeSlave_addrIn_rv[15] && + !s_config_writeSlave_isRst_isInReset && + S_AXI_awvalid ; + assign s_config_writeSlave_addrIn_rv$port0__write_1 = + { 1'd1, S_AXI_awaddr, S_AXI_awprot } ; + assign s_config_writeSlave_addrIn_rv$port1__read = + s_config_writeSlave_addrIn_rv$EN_port0__write ? + s_config_writeSlave_addrIn_rv$port0__write_1 : + s_config_writeSlave_addrIn_rv ; + assign s_config_writeSlave_addrIn_rv$EN_port1__write = + s_config_writeSlave_addrIn_rv$port1__read[15] && + s_config_writeSlave_dataIn_rv$port1__read[72] && + !s_config_writeSlave_in_rv$port1__read[87] ; + assign s_config_writeSlave_addrIn_rv$port2__read = + s_config_writeSlave_addrIn_rv$EN_port1__write ? + 16'd10922 : + s_config_writeSlave_addrIn_rv$port1__read ; + assign s_config_writeSlave_dataIn_rv$EN_port0__write = + !s_config_writeSlave_dataIn_rv[72] && + !s_config_writeSlave_isRst_isInReset && + S_AXI_wvalid ; + assign s_config_writeSlave_dataIn_rv$port0__write_1 = + { 1'd1, S_AXI_wdata, S_AXI_wstrb } ; + assign s_config_writeSlave_dataIn_rv$port1__read = + s_config_writeSlave_dataIn_rv$EN_port0__write ? + s_config_writeSlave_dataIn_rv$port0__write_1 : + s_config_writeSlave_dataIn_rv ; + assign s_config_writeSlave_dataIn_rv$EN_port1__write = + s_config_writeSlave_addrIn_rv$port1__read[15] && + s_config_writeSlave_dataIn_rv$port1__read[72] && + !s_config_writeSlave_in_rv$port1__read[87] ; + assign s_config_writeSlave_dataIn_rv$port2__read = + s_config_writeSlave_dataIn_rv$EN_port1__write ? + 73'h0AAAAAAAAAAAAAAAAAA : + s_config_writeSlave_dataIn_rv$port1__read ; + + // register cycleCount + assign cycleCount$D_IN = cycleCount + 64'd1 ; + assign cycleCount$EN = 1'd1 ; + + // register cycleCount_Overflow + assign cycleCount_Overflow$D_IN = cycleCount_Overflow + 64'd1 ; + assign cycleCount_Overflow$EN = cycleCount == 64'hFFFFFFFFFFFFFFFF ; + + // register error + assign error$D_IN = 1'b0 ; + assign error$EN = 1'b0 ; + + // register fifo_Read_Rs_data_rCache + assign fifo_Read_Rs_data_rCache$D_IN = + { 1'd1, + fifo_Read_Rs_data_rWrPtr, + fifo_Read_Rs_data_wDataIn_whas__46_AND_fifo_Re_ETC___d359 } ; + assign fifo_Read_Rs_data_rCache$EN = + WILL_FIRE_RL_migRecieveReadResponse_nvSendReadResponse ; + + // register fifo_Read_Rs_data_rRdPtr + assign fifo_Read_Rs_data_rRdPtr$D_IN = x__h24038 ; + assign fifo_Read_Rs_data_rRdPtr$EN = + WILL_FIRE_RL_nvSendReadResponseResponse ; + + // register fifo_Read_Rs_data_rWrPtr + assign fifo_Read_Rs_data_rWrPtr$D_IN = x__h23641 ; + assign fifo_Read_Rs_data_rWrPtr$EN = + WILL_FIRE_RL_migRecieveReadResponse_nvSendReadResponse ; + + // register idle + assign idle$D_IN = 1'b0 ; + assign idle$EN = 1'b0 ; + + // register interruptR + assign interruptR$D_IN = 1'b0 ; + assign interruptR$EN = 1'd1 ; + + // register isReadWaiting + assign isReadWaiting$D_IN = !MUX_isReadWaiting$write_1__SEL_1 ; + assign isReadWaiting$EN = + WILL_FIRE_RL_nvSendReadResponseWaitingLoop && + readNumberOfCycleToWait == 64'd1 || + WILL_FIRE_RL_nvSendReadResponseResponse ; + + // register isWriteWaiting + assign isWriteWaiting$D_IN = MUX_isWriteWaiting$write_1__SEL_1 ; + assign isWriteWaiting$EN = + WILL_FIRE_RL_writeDelayCalibrator2 && + writeNumberOfCycleToWait == 12'd0 || + WILL_FIRE_RL_nvSendWriteResponseLast && + writeNumberOfCycleToWait == 12'd1 ; + + // register mig_read_isRst_isInReset + assign mig_read_isRst_isInReset$D_IN = 1'd0 ; + assign mig_read_isRst_isInReset$EN = mig_read_isRst_isInReset ; + + // register mig_write_isRst_isInReset + assign mig_write_isRst_isInReset$D_IN = 1'd0 ; + assign mig_write_isRst_isInReset$EN = mig_write_isRst_isInReset ; + + // register nv_read_isRst_isInReset + assign nv_read_isRst_isInReset$D_IN = 1'd0 ; + assign nv_read_isRst_isInReset$EN = nv_read_isRst_isInReset ; + + // register nv_write_isRst_isInReset + assign nv_write_isRst_isInReset$D_IN = 1'd0 ; + assign nv_write_isRst_isInReset$EN = nv_write_isRst_isInReset ; + + // register operation + assign operation$D_IN = + IF_s_config_writeSlave_in_rv_BIT_3_THEN_s_conf_ETC__q4[0] ; + assign operation$EN = WILL_FIRE_RL_s_config_1_axiWriteSpecial_2 ; + + // register rand_rd_r + assign rand_rd_r$D_IN = 32'h0 ; + assign rand_rd_r$EN = 1'b0 ; + + // register rand_wr_r + assign rand_wr_r$D_IN = 32'h0 ; + assign rand_wr_r$EN = 1'b0 ; + + // register readNumberOfCycleToWait + assign readNumberOfCycleToWait$D_IN = + WILL_FIRE_RL_nvSendReadResponseResponse ? + fifo_Read_Rs_data_wDataOut$wget[63:0] : + MUX_readNumberOfCycleToWait$write_1__VAL_2 ; + assign readNumberOfCycleToWait$EN = + WILL_FIRE_RL_nvSendReadResponseResponse || + WILL_FIRE_RL_nvSendReadResponseWaitingLoop ; + + // register read_data + assign read_data$D_IN = fifo_Read_Rs_data_wDataOut$wget[579:64] ; + assign read_data$EN = WILL_FIRE_RL_nvSendReadResponseResponse ; + + // register read_delay + assign read_delay$D_IN = + MUX_read_delay$write_1__SEL_1 ? + 64'd0 : + MUX_read_delay$write_1__VAL_2 ; + assign read_delay$EN = + start && !operation || + WILL_FIRE_RL_s_config_1_axiWriteSpecial_3 ; + + // register s_config_readBusy + assign s_config_readBusy$D_IN = 1'b0 ; + assign s_config_readBusy$EN = 1'b0 ; + + // register s_config_readSlave_in_rv + assign s_config_readSlave_in_rv$D_IN = + s_config_readSlave_in_rv$port2__read ; + assign s_config_readSlave_in_rv$EN = 1'b1 ; + + // register s_config_readSlave_isRst_isInReset + assign s_config_readSlave_isRst_isInReset$D_IN = 1'd0 ; + assign s_config_readSlave_isRst_isInReset$EN = + s_config_readSlave_isRst_isInReset ; + + // register s_config_readSlave_out_rv + assign s_config_readSlave_out_rv$D_IN = + s_config_readSlave_out_rv$port2__read ; + assign s_config_readSlave_out_rv$EN = 1'b1 ; + + // register s_config_writeBusy + assign s_config_writeBusy$D_IN = 1'b0 ; + assign s_config_writeBusy$EN = 1'b0 ; + + // register s_config_writeSlave_addrIn_rv + assign s_config_writeSlave_addrIn_rv$D_IN = + s_config_writeSlave_addrIn_rv$port2__read ; + assign s_config_writeSlave_addrIn_rv$EN = 1'b1 ; + + // register s_config_writeSlave_dataIn_rv + assign s_config_writeSlave_dataIn_rv$D_IN = + s_config_writeSlave_dataIn_rv$port2__read ; + assign s_config_writeSlave_dataIn_rv$EN = 1'b1 ; + + // register s_config_writeSlave_in_rv + assign s_config_writeSlave_in_rv$D_IN = + s_config_writeSlave_in_rv$port2__read ; + assign s_config_writeSlave_in_rv$EN = 1'b1 ; + + // register s_config_writeSlave_isRst_isInReset + assign s_config_writeSlave_isRst_isInReset$D_IN = 1'd0 ; + assign s_config_writeSlave_isRst_isInReset$EN = + s_config_writeSlave_isRst_isInReset ; + + // register s_config_writeSlave_out_rv + assign s_config_writeSlave_out_rv$D_IN = + s_config_writeSlave_out_rv$port2__read ; + assign s_config_writeSlave_out_rv$EN = 1'b1 ; + + // register start + assign start$D_IN = + WILL_FIRE_RL_s_config_1_axiWriteSpecial && + IF_s_config_writeSlave_in_rv_BIT_3_THEN_s_conf_ETC__q2[0] ; + assign start$EN = WILL_FIRE_RL_s_config_1_axiWriteSpecial || start ; + + // register status + assign status$D_IN = + { s_config_writeSlave_in_rv[10] ? + s_config_writeSlave_in_rv[74:67] : + status[63:56], + s_config_writeSlave_in_rv[9] ? + s_config_writeSlave_in_rv[66:59] : + status[55:48], + s_config_writeSlave_in_rv[8] ? + s_config_writeSlave_in_rv[58:51] : + status[47:40], + s_config_writeSlave_in_rv[7] ? + s_config_writeSlave_in_rv[50:43] : + status[39:32], + s_config_writeSlave_in_rv[6] ? + s_config_writeSlave_in_rv[42:35] : + status[31:24], + s_config_writeSlave_in_rv[5] ? + s_config_writeSlave_in_rv[34:27] : + status[23:16], + s_config_writeSlave_in_rv[4] ? + s_config_writeSlave_in_rv[26:19] : + status[15:8], + s_config_writeSlave_in_rv[3] ? + s_config_writeSlave_in_rv[18:11] : + status[7:0] } ; + assign status$EN = WILL_FIRE_RL_s_config_1_axiWriteSpecial_1 ; + + // register writeNumberOfCycleToWait + assign writeNumberOfCycleToWait$D_IN = + MUX_isWriteWaiting$write_1__SEL_1 ? + MUX_writeNumberOfCycleToWait$write_1__VAL_1 : + MUX_writeNumberOfCycleToWait$write_1__VAL_2 ; + assign writeNumberOfCycleToWait$EN = + WILL_FIRE_RL_writeDelayCalibrator2 && + writeNumberOfCycleToWait == 12'd0 || + WILL_FIRE_RL_nvSendWriteResponseLast ; + + // register write_delay + assign write_delay$D_IN = + MUX_read_delay$write_1__SEL_1 ? + 64'd0 : + MUX_write_delay$write_1__VAL_2 ; + assign write_delay$EN = + start && !operation || + WILL_FIRE_RL_s_config_1_axiWriteSpecial_4 ; + + // submodule fifo_Read_Rq + assign fifo_Read_Rq$D_IN = + { nv_read_in$D_OUT[93], nv_read_in$D_OUT[62:0] } ; + assign fifo_Read_Rq$ENQ = nv_read_in$EMPTY_N && fifo_Read_Rq$FULL_N ; + assign fifo_Read_Rq$DEQ = + fifo_Read_Rq$EMPTY_N && mig_read_in$FULL_N && + fifo_Read_Rq_delay_mig$FULL_N ; + assign fifo_Read_Rq$CLR = 1'b0 ; + + // submodule fifo_Read_Rq_delay_mig + assign fifo_Read_Rq_delay_mig$D_IN = + { fifo_Read_Rq$D_OUT, cycleCount, 192'd0, cycleCount_Overflow } ; + assign fifo_Read_Rq_delay_mig$ENQ = + fifo_Read_Rq$EMPTY_N && mig_read_in$FULL_N && + fifo_Read_Rq_delay_mig$FULL_N ; + assign fifo_Read_Rq_delay_mig$DEQ = + WILL_FIRE_RL_migRecieveReadResponse_nvSendReadResponse && + mig_read_out_1$D_OUT[0] ; + assign fifo_Read_Rq_delay_mig$CLR = 1'b0 ; + + // submodule fifo_Read_Rq_delay_nv + assign fifo_Read_Rq_delay_nv$D_IN = 384'h0 ; + assign fifo_Read_Rq_delay_nv$ENQ = 1'b0 ; + assign fifo_Read_Rq_delay_nv$DEQ = 1'b0 ; + assign fifo_Read_Rq_delay_nv$CLR = 1'b0 ; + + // submodule fifo_Read_Rs_data_memory + assign fifo_Read_Rs_data_memory$ADDRA = fifo_Read_Rs_data_rWrPtr[7:0] ; + assign fifo_Read_Rs_data_memory$ADDRB = + WILL_FIRE_RL_nvSendReadResponseResponse ? + x__h24038[7:0] : + fifo_Read_Rs_data_rRdPtr[7:0] ; + assign fifo_Read_Rs_data_memory$DIA = + fifo_Read_Rs_data_wDataIn_whas__46_AND_fifo_Re_ETC___d359 ; + assign fifo_Read_Rs_data_memory$DIB = + 580'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + assign fifo_Read_Rs_data_memory$WEA = + WILL_FIRE_RL_migRecieveReadResponse_nvSendReadResponse ; + assign fifo_Read_Rs_data_memory$WEB = 1'd0 ; + assign fifo_Read_Rs_data_memory$ENA = 1'b1 ; + assign fifo_Read_Rs_data_memory$ENB = 1'b1 ; + + // submodule fifo_Write_Rq_Addr + assign fifo_Write_Rq_Addr$D_IN = + { nv_write_in_addr$D_OUT[93], nv_write_in_addr$D_OUT[62:0] } ; + assign fifo_Write_Rq_Addr$ENQ = + nv_write_in_addr$EMPTY_N && fifo_Write_Rq_Addr$FULL_N ; + assign fifo_Write_Rq_Addr$DEQ = + fifo_Write_Rq_Addr$EMPTY_N && mig_write_in_addr$FULL_N && + fifo_Write_Rq_delay_mig$FULL_N ; + assign fifo_Write_Rq_Addr$CLR = 1'b0 ; + + // submodule fifo_Write_Rq_Data + assign fifo_Write_Rq_Data$D_IN = 577'h0 ; + assign fifo_Write_Rq_Data$ENQ = 1'b0 ; + assign fifo_Write_Rq_Data$DEQ = 1'b0 ; + assign fifo_Write_Rq_Data$CLR = 1'b0 ; + + // submodule fifo_Write_Rq_delay_mig + assign fifo_Write_Rq_delay_mig$D_IN = + { fifo_Write_Rq_Addr$D_OUT, + cycleCount, + 192'd0, + cycleCount_Overflow } ; + assign fifo_Write_Rq_delay_mig$ENQ = + fifo_Write_Rq_Addr$EMPTY_N && mig_write_in_addr$FULL_N && + fifo_Write_Rq_delay_mig$FULL_N ; + assign fifo_Write_Rq_delay_mig$DEQ = + fifo_Write_Rq_delay_mig$EMPTY_N && + fifo_Write_Rq_delay_nv$FULL_N ; + assign fifo_Write_Rq_delay_mig$CLR = 1'b0 ; + + // submodule fifo_Write_Rq_delay_nv + assign fifo_Write_Rq_delay_nv$D_IN = + { fifo_Write_Rq_delay_mig$D_OUT[383:192], + 51'd0, + { 5'd0, fifo_Write_Rq_delay_mig$D_OUT[348:341] + 8'd1 } + + { 1'd0, write_delay[11:0] }, + fifo_Write_Rq_delay_mig$D_OUT[127:0] } ; + assign fifo_Write_Rq_delay_nv$ENQ = + fifo_Write_Rq_delay_mig$EMPTY_N && + fifo_Write_Rq_delay_nv$FULL_N ; + assign fifo_Write_Rq_delay_nv$DEQ = MUX_isWriteWaiting$write_1__SEL_1 ; + assign fifo_Write_Rq_delay_nv$CLR = 1'b0 ; + + // submodule fifo_Write_Rs + assign fifo_Write_Rs$D_IN = mig_write_out$D_OUT ; + assign fifo_Write_Rs$ENQ = mig_write_out$EMPTY_N && fifo_Write_Rs$FULL_N ; + assign fifo_Write_Rs$DEQ = MUX_isWriteWaiting$write_1__SEL_2 ; + assign fifo_Write_Rs$CLR = 1'b0 ; + + // submodule mig_read_in + assign mig_read_in$D_IN = fifo_Read_Rq$D_OUT ; + assign mig_read_in$ENQ = + fifo_Read_Rq$EMPTY_N && mig_read_in$FULL_N && + fifo_Read_Rq_delay_mig$FULL_N ; + assign mig_read_in$DEQ = + mig_read_in$EMPTY_N && !mig_read_isRst_isInReset && + M_AXI_MIG_arready ; + assign mig_read_in$CLR = 1'b0 ; + + // submodule mig_read_out + assign mig_read_out$D_IN = 516'h0 ; + assign mig_read_out$ENQ = 1'b0 ; + assign mig_read_out$DEQ = 1'b0 ; + assign mig_read_out$CLR = 1'b0 ; + + // submodule mig_read_out_1 + assign mig_read_out_1$D_IN = mig_read_rinpkg$wget ; + assign mig_read_out_1$ENQ = + mig_read_out_1$FULL_N && !mig_read_isRst_isInReset && + M_AXI_MIG_rvalid ; + assign mig_read_out_1$DEQ = + WILL_FIRE_RL_migRecieveReadResponse_nvSendReadResponse ; + assign mig_read_out_1$CLR = 1'b0 ; + + // submodule mig_write_in_addr + assign mig_write_in_addr$D_IN = fifo_Write_Rq_Addr$D_OUT ; + assign mig_write_in_addr$ENQ = + fifo_Write_Rq_Addr$EMPTY_N && mig_write_in_addr$FULL_N && + fifo_Write_Rq_delay_mig$FULL_N ; + assign mig_write_in_addr$DEQ = + mig_write_in_addr$EMPTY_N && !mig_write_isRst_isInReset && + M_AXI_MIG_awready ; + assign mig_write_in_addr$CLR = 1'b0 ; + + // submodule mig_write_in_data + assign mig_write_in_data$D_IN = nv_write_in_data$D_OUT ; + assign mig_write_in_data$ENQ = + nv_write_in_data$EMPTY_N && mig_write_in_data$FULL_N ; + assign mig_write_in_data$DEQ = + mig_write_in_data$EMPTY_N && !mig_write_isRst_isInReset && + M_AXI_MIG_wready ; + assign mig_write_in_data$CLR = 1'b0 ; + + // submodule mig_write_out + assign mig_write_out$D_IN = mig_write_rinpkg$wget ; + assign mig_write_out$ENQ = + mig_write_out$FULL_N && !mig_write_isRst_isInReset && + M_AXI_MIG_bvalid ; + assign mig_write_out$DEQ = mig_write_out$EMPTY_N && fifo_Write_Rs$FULL_N ; + assign mig_write_out$CLR = 1'b0 ; + + // submodule nv_read_in + assign nv_read_in$D_IN = nv_read_arinpkg$wget ; + assign nv_read_in$ENQ = + nv_read_in$FULL_N && !nv_read_isRst_isInReset && + S_AXI_NV_arvalid ; + assign nv_read_in$DEQ = nv_read_in$EMPTY_N && fifo_Read_Rq$FULL_N ; + assign nv_read_in$CLR = 1'b0 ; + + // submodule nv_read_out + assign nv_read_out$D_IN = read_data ; + assign nv_read_out$ENQ = MUX_isReadWaiting$write_1__SEL_1 ; + assign nv_read_out$DEQ = + nv_read_out$EMPTY_N && !nv_read_isRst_isInReset && + S_AXI_NV_rready ; + assign nv_read_out$CLR = 1'b0 ; + + // submodule nv_write_in_addr + assign nv_write_in_addr$D_IN = nv_write_arinpkg_addr$wget ; + assign nv_write_in_addr$ENQ = + nv_write_in_addr$FULL_N && !nv_write_isRst_isInReset && + S_AXI_NV_awvalid ; + assign nv_write_in_addr$DEQ = + nv_write_in_addr$EMPTY_N && fifo_Write_Rq_Addr$FULL_N ; + assign nv_write_in_addr$CLR = 1'b0 ; + + // submodule nv_write_in_data + assign nv_write_in_data$D_IN = nv_write_arinpkg_data$wget ; + assign nv_write_in_data$ENQ = + nv_write_in_data$FULL_N && !nv_write_isRst_isInReset && + S_AXI_NV_wvalid ; + assign nv_write_in_data$DEQ = + nv_write_in_data$EMPTY_N && mig_write_in_data$FULL_N ; + assign nv_write_in_data$CLR = 1'b0 ; + + // submodule nv_write_out + assign nv_write_out$D_IN = fifo_Write_Rs$D_OUT ; + assign nv_write_out$ENQ = MUX_isWriteWaiting$write_1__SEL_2 ; + assign nv_write_out$DEQ = + nv_write_out$EMPTY_N && !nv_write_isRst_isInReset && + S_AXI_NV_bready ; + assign nv_write_out$CLR = 1'b0 ; + + // remaining internal signals + assign IF_fifo_Read_Rq_delay_mig_first__70_BITS_63_TO_ETC___d483 = + (fifo_Read_Rq_delay_mig$D_OUT[63:0] == cycleCount_Overflow) ? + { 64'd0, cycleCount } : + _0_CONCAT_cycleCount_93_33_PLUS_184467440737095_ETC___d434 ; + assign IF_fifo_Write_Rq_delay_nv_first__25_BITS_63_TO_ETC___d435 = + (fifo_Write_Rq_delay_nv$D_OUT[63:0] == cycleCount_Overflow) ? + { 64'd0, cycleCount } : + _0_CONCAT_cycleCount_93_33_PLUS_184467440737095_ETC___d434 ; + assign IF_mig_read_out_1_first__68_BIT_0_69_THEN_IF_0_ETC___d488 = + mig_read_out_1$D_OUT[0] ? + ((_0_CONCAT_fifo_Read_Rq_delay_mig_first__70_BITS_ETC___d480 <= + IF_fifo_Read_Rq_delay_mig_first__70_BITS_63_TO_ETC___d483) ? + 64'd1 : + _0_CONCAT_fifo_Read_Rq_delay_mig_first__70_BITS_ETC__q1[63:0]) : + 64'd1 ; + assign IF_s_config_writeSlave_in_rv_BIT_3_THEN_s_conf_ETC__q2 = + s_config_writeSlave_in_rv[3] ? + s_config_writeSlave_in_rv[18:11] : + { 7'd0, start } ; + assign IF_s_config_writeSlave_in_rv_BIT_3_THEN_s_conf_ETC__q4 = + s_config_writeSlave_in_rv[3] ? + s_config_writeSlave_in_rv[18:11] : + { 7'd0, operation } ; + assign _0_CONCAT_cycleCount_93_33_PLUS_184467440737095_ETC___d434 = + { 64'd0, cycleCount } + 128'h0000000000000000FFFFFFFFFFFFFFFF ; + assign _0_CONCAT_fifo_Read_Rq_delay_mig_first__70_BITS_ETC___d480 = + { 64'd0, fifo_Read_Rq_delay_mig$D_OUT[319:256] } + + { 115'd0, + { 5'd0, fifo_Read_Rq_delay_mig$D_OUT[348:341] + 8'd1 } + + { 1'd0, read_delay[11:0] } } ; + assign _0_CONCAT_fifo_Read_Rq_delay_mig_first__70_BITS_ETC__q1 = + _0_CONCAT_fifo_Read_Rq_delay_mig_first__70_BITS_ETC___d480 - + IF_fifo_Read_Rq_delay_mig_first__70_BITS_63_TO_ETC___d483 ; + assign _0_CONCAT_fifo_Write_Rq_delay_nv_first__25_BITS_ETC___d430 = + { 64'd0, fifo_Write_Rq_delay_nv$D_OUT[319:256] } + + { 64'd0, fifo_Write_Rq_delay_nv$D_OUT[191:128] } ; + assign _0_CONCAT_fifo_Write_Rq_delay_nv_first__25_BITS_ETC__q3 = + _0_CONCAT_fifo_Write_Rq_delay_nv_first__25_BITS_ETC___d430 - + IF_fifo_Write_Rq_delay_nv_first__25_BITS_63_TO_ETC___d435 ; + assign fifo_Read_Rs_data_wDataIn_whas__46_AND_fifo_Re_ETC___d359 = + { x__read_read_response_id__h23539, + x__read_read_response_data__h23540, + WILL_FIRE_RL_migRecieveReadResponse_nvSendReadResponse ? + fifo_Read_Rs_data_wDataIn$wget[66:65] : + 2'd0, + WILL_FIRE_RL_migRecieveReadResponse_nvSendReadResponse && + fifo_Read_Rs_data_wDataIn$wget[64], + WILL_FIRE_RL_migRecieveReadResponse_nvSendReadResponse ? + fifo_Read_Rs_data_wDataIn$wget[63:0] : + 64'd0 } ; + assign v__h5354 = { 63'd0, start } ; + assign v__h5718 = { 63'd0, operation } ; + assign x__h23641 = fifo_Read_Rs_data_rWrPtr + 9'd1 ; + assign x__h24038 = fifo_Read_Rs_data_rRdPtr + 9'd1 ; + assign x__read_read_response_data__h23540 = + WILL_FIRE_RL_migRecieveReadResponse_nvSendReadResponse ? + fifo_Read_Rs_data_wDataIn$wget[578:67] : + 512'd0 ; + assign x__read_read_response_id__h23539 = + WILL_FIRE_RL_migRecieveReadResponse_nvSendReadResponse && + fifo_Read_Rs_data_wDataIn$wget[579] ; + + // handling of inlined registers + + always@(posedge CLK) + begin + if (RST_N == `BSV_RESET_VALUE) + begin + cycleCount <= `BSV_ASSIGNMENT_DELAY 64'd0; + cycleCount_Overflow <= `BSV_ASSIGNMENT_DELAY 64'd0; + error <= `BSV_ASSIGNMENT_DELAY 1'd0; + fifo_Read_Rs_data_rCache <= `BSV_ASSIGNMENT_DELAY + 590'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + fifo_Read_Rs_data_rRdPtr <= `BSV_ASSIGNMENT_DELAY 9'd0; + fifo_Read_Rs_data_rWrPtr <= `BSV_ASSIGNMENT_DELAY 9'd0; + idle <= `BSV_ASSIGNMENT_DELAY 1'd1; + interruptR <= `BSV_ASSIGNMENT_DELAY 1'd0; + isReadWaiting <= `BSV_ASSIGNMENT_DELAY 1'd0; + isWriteWaiting <= `BSV_ASSIGNMENT_DELAY 1'd0; + rand_rd_r <= `BSV_ASSIGNMENT_DELAY 32'd1; + rand_wr_r <= `BSV_ASSIGNMENT_DELAY 32'd1; + readNumberOfCycleToWait <= `BSV_ASSIGNMENT_DELAY 64'd0; + read_delay <= `BSV_ASSIGNMENT_DELAY 64'd0; + s_config_readBusy <= `BSV_ASSIGNMENT_DELAY 1'd0; + s_config_readSlave_in_rv <= `BSV_ASSIGNMENT_DELAY 16'd10922; + s_config_readSlave_out_rv <= `BSV_ASSIGNMENT_DELAY + 67'h2AAAAAAAAAAAAAAAA; + s_config_writeBusy <= `BSV_ASSIGNMENT_DELAY 1'd0; + s_config_writeSlave_addrIn_rv <= `BSV_ASSIGNMENT_DELAY 16'd10922; + s_config_writeSlave_dataIn_rv <= `BSV_ASSIGNMENT_DELAY + 73'h0AAAAAAAAAAAAAAAAAA; + s_config_writeSlave_in_rv <= `BSV_ASSIGNMENT_DELAY + 88'h2AAAAAAAAAAAAAAAAAAAAA; + s_config_writeSlave_out_rv <= `BSV_ASSIGNMENT_DELAY 3'd2; + start <= `BSV_ASSIGNMENT_DELAY 1'd0; + status <= `BSV_ASSIGNMENT_DELAY 64'd0; + writeNumberOfCycleToWait <= `BSV_ASSIGNMENT_DELAY 12'd0; + write_delay <= `BSV_ASSIGNMENT_DELAY 64'd0; + end + else + begin + if (cycleCount$EN) + cycleCount <= `BSV_ASSIGNMENT_DELAY cycleCount$D_IN; + if (cycleCount_Overflow$EN) + cycleCount_Overflow <= `BSV_ASSIGNMENT_DELAY + cycleCount_Overflow$D_IN; + if (error$EN) error <= `BSV_ASSIGNMENT_DELAY error$D_IN; + if (fifo_Read_Rs_data_rCache$EN) + fifo_Read_Rs_data_rCache <= `BSV_ASSIGNMENT_DELAY + fifo_Read_Rs_data_rCache$D_IN; + if (fifo_Read_Rs_data_rRdPtr$EN) + fifo_Read_Rs_data_rRdPtr <= `BSV_ASSIGNMENT_DELAY + fifo_Read_Rs_data_rRdPtr$D_IN; + if (fifo_Read_Rs_data_rWrPtr$EN) + fifo_Read_Rs_data_rWrPtr <= `BSV_ASSIGNMENT_DELAY + fifo_Read_Rs_data_rWrPtr$D_IN; + if (idle$EN) idle <= `BSV_ASSIGNMENT_DELAY idle$D_IN; + if (interruptR$EN) + interruptR <= `BSV_ASSIGNMENT_DELAY interruptR$D_IN; + if (isReadWaiting$EN) + isReadWaiting <= `BSV_ASSIGNMENT_DELAY isReadWaiting$D_IN; + if (isWriteWaiting$EN) + isWriteWaiting <= `BSV_ASSIGNMENT_DELAY isWriteWaiting$D_IN; + if (rand_rd_r$EN) rand_rd_r <= `BSV_ASSIGNMENT_DELAY rand_rd_r$D_IN; + if (rand_wr_r$EN) rand_wr_r <= `BSV_ASSIGNMENT_DELAY rand_wr_r$D_IN; + if (readNumberOfCycleToWait$EN) + readNumberOfCycleToWait <= `BSV_ASSIGNMENT_DELAY + readNumberOfCycleToWait$D_IN; + if (read_delay$EN) + read_delay <= `BSV_ASSIGNMENT_DELAY read_delay$D_IN; + if (s_config_readBusy$EN) + s_config_readBusy <= `BSV_ASSIGNMENT_DELAY s_config_readBusy$D_IN; + if (s_config_readSlave_in_rv$EN) + s_config_readSlave_in_rv <= `BSV_ASSIGNMENT_DELAY + s_config_readSlave_in_rv$D_IN; + if (s_config_readSlave_out_rv$EN) + s_config_readSlave_out_rv <= `BSV_ASSIGNMENT_DELAY + s_config_readSlave_out_rv$D_IN; + if (s_config_writeBusy$EN) + s_config_writeBusy <= `BSV_ASSIGNMENT_DELAY s_config_writeBusy$D_IN; + if (s_config_writeSlave_addrIn_rv$EN) + s_config_writeSlave_addrIn_rv <= `BSV_ASSIGNMENT_DELAY + s_config_writeSlave_addrIn_rv$D_IN; + if (s_config_writeSlave_dataIn_rv$EN) + s_config_writeSlave_dataIn_rv <= `BSV_ASSIGNMENT_DELAY + s_config_writeSlave_dataIn_rv$D_IN; + if (s_config_writeSlave_in_rv$EN) + s_config_writeSlave_in_rv <= `BSV_ASSIGNMENT_DELAY + s_config_writeSlave_in_rv$D_IN; + if (s_config_writeSlave_out_rv$EN) + s_config_writeSlave_out_rv <= `BSV_ASSIGNMENT_DELAY + s_config_writeSlave_out_rv$D_IN; + if (start$EN) start <= `BSV_ASSIGNMENT_DELAY start$D_IN; + if (status$EN) status <= `BSV_ASSIGNMENT_DELAY status$D_IN; + if (writeNumberOfCycleToWait$EN) + writeNumberOfCycleToWait <= `BSV_ASSIGNMENT_DELAY + writeNumberOfCycleToWait$D_IN; + if (write_delay$EN) + write_delay <= `BSV_ASSIGNMENT_DELAY write_delay$D_IN; + end + if (operation$EN) operation <= `BSV_ASSIGNMENT_DELAY operation$D_IN; + if (read_data$EN) read_data <= `BSV_ASSIGNMENT_DELAY read_data$D_IN; + end + + always@(posedge CLK or `BSV_RESET_EDGE RST_N) + if (RST_N == `BSV_RESET_VALUE) + begin + mig_read_isRst_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; + mig_write_isRst_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; + nv_read_isRst_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; + nv_write_isRst_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; + s_config_readSlave_isRst_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; + s_config_writeSlave_isRst_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; + end + else + begin + if (mig_read_isRst_isInReset$EN) + mig_read_isRst_isInReset <= `BSV_ASSIGNMENT_DELAY + mig_read_isRst_isInReset$D_IN; + if (mig_write_isRst_isInReset$EN) + mig_write_isRst_isInReset <= `BSV_ASSIGNMENT_DELAY + mig_write_isRst_isInReset$D_IN; + if (nv_read_isRst_isInReset$EN) + nv_read_isRst_isInReset <= `BSV_ASSIGNMENT_DELAY + nv_read_isRst_isInReset$D_IN; + if (nv_write_isRst_isInReset$EN) + nv_write_isRst_isInReset <= `BSV_ASSIGNMENT_DELAY + nv_write_isRst_isInReset$D_IN; + if (s_config_readSlave_isRst_isInReset$EN) + s_config_readSlave_isRst_isInReset <= `BSV_ASSIGNMENT_DELAY + s_config_readSlave_isRst_isInReset$D_IN; + if (s_config_writeSlave_isRst_isInReset$EN) + s_config_writeSlave_isRst_isInReset <= `BSV_ASSIGNMENT_DELAY + s_config_writeSlave_isRst_isInReset$D_IN; + end + + // synopsys translate_off + `ifdef BSV_NO_INITIAL_BLOCKS + `else // not BSV_NO_INITIAL_BLOCKS + initial + begin + cycleCount = 64'hAAAAAAAAAAAAAAAA; + cycleCount_Overflow = 64'hAAAAAAAAAAAAAAAA; + error = 1'h0; + fifo_Read_Rs_data_rCache = + 590'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + fifo_Read_Rs_data_rRdPtr = 9'h0AA; + fifo_Read_Rs_data_rWrPtr = 9'h0AA; + idle = 1'h0; + interruptR = 1'h0; + isReadWaiting = 1'h0; + isWriteWaiting = 1'h0; + mig_read_isRst_isInReset = 1'h0; + mig_write_isRst_isInReset = 1'h0; + nv_read_isRst_isInReset = 1'h0; + nv_write_isRst_isInReset = 1'h0; + operation = 1'h0; + rand_rd_r = 32'hAAAAAAAA; + rand_wr_r = 32'hAAAAAAAA; + readNumberOfCycleToWait = 64'hAAAAAAAAAAAAAAAA; + read_data = + 516'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + read_delay = 64'hAAAAAAAAAAAAAAAA; + s_config_readBusy = 1'h0; + s_config_readSlave_in_rv = 16'hAAAA; + s_config_readSlave_isRst_isInReset = 1'h0; + s_config_readSlave_out_rv = 67'h2AAAAAAAAAAAAAAAA; + s_config_writeBusy = 1'h0; + s_config_writeSlave_addrIn_rv = 16'hAAAA; + s_config_writeSlave_dataIn_rv = 73'h0AAAAAAAAAAAAAAAAAA; + s_config_writeSlave_in_rv = 88'hAAAAAAAAAAAAAAAAAAAAAA; + s_config_writeSlave_isRst_isInReset = 1'h0; + s_config_writeSlave_out_rv = 3'h2; + start = 1'h0; + status = 64'hAAAAAAAAAAAAAAAA; + writeNumberOfCycleToWait = 12'hAAA; + write_delay = 64'hAAAAAAAAAAAAAAAA; + end + `endif // BSV_NO_INITIAL_BLOCKS + // synopsys translate_on + + // handling of system tasks + + // synopsys translate_off + always@(negedge CLK) + begin + #0; + if (RST_N != `BSV_RESET_VALUE) + if ((WILL_FIRE_RL_s_config_axiReadSpecial_1 || + WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_1) && + (WILL_FIRE_RL_s_config_axiReadSpecial_2 || + WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_2 || + WILL_FIRE_RL_s_config_axiReadSpecial_3 || + WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_3 || + WILL_FIRE_RL_s_config_axiReadSpecial_4 || + WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_4)) + + if (RST_N != `BSV_RESET_VALUE) + if ((WILL_FIRE_RL_s_config_axiReadSpecial_2 || + WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_2) && + (WILL_FIRE_RL_s_config_axiReadSpecial_3 || + WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_3 || + WILL_FIRE_RL_s_config_axiReadSpecial_4 || + WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_4)) + + if (RST_N != `BSV_RESET_VALUE) + if ((WILL_FIRE_RL_s_config_axiReadSpecial_3 || + WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_3) && + (WILL_FIRE_RL_s_config_axiReadSpecial_4 || + WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_4)) + + if (RST_N != `BSV_RESET_VALUE) + if ((WILL_FIRE_RL_s_config_axiReadSpecial || + WILL_FIRE_RL_s_config_axiReadSpecialIsHandled) && + (WILL_FIRE_RL_s_config_axiReadSpecial_1 || + WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_1 || + WILL_FIRE_RL_s_config_axiReadSpecial_2 || + WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_2 || + WILL_FIRE_RL_s_config_axiReadSpecial_3 || + WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_3 || + WILL_FIRE_RL_s_config_axiReadSpecial_4 || + WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_4)) + + if (RST_N != `BSV_RESET_VALUE) + if ((WILL_FIRE_RL_s_config_axiReadSpecial || + WILL_FIRE_RL_s_config_axiReadSpecialIsHandled || + WILL_FIRE_RL_s_config_axiReadSpecial_1 || + WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_1 || + WILL_FIRE_RL_s_config_axiReadSpecial_2 || + WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_2 || + WILL_FIRE_RL_s_config_axiReadSpecial_3 || + WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_3 || + WILL_FIRE_RL_s_config_axiReadSpecial_4 || + WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_4) && + WILL_FIRE_RL_s_config_axiReadFallback) + + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecialIsHandled_1 && + WILL_FIRE_RL_s_config_1_axiWriteSpecialIsHandled) + + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecialIsHandled_1 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial) + + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_1 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial) + + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_1 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial && + s_config_writeSlave_in_rv[81:78] == 4'd2 && + s_config_writeSlave_in_rv[87] && + !s_config_writeBusy) + + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecialIsHandled_2 && + WILL_FIRE_RL_s_config_1_axiWriteSpecialIsHandled_1) + + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecialIsHandled_2 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial_1) + + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecialIsHandled_2 && + WILL_FIRE_RL_s_config_1_axiWriteSpecialIsHandled) + + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecialIsHandled_2 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial) + + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecialIsHandled_3 && + WILL_FIRE_RL_s_config_1_axiWriteSpecialIsHandled_2) + + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecialIsHandled_3 && + WILL_FIRE_RL_s_config_1_axiWriteSpecialIsHandled_1) + + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecialIsHandled_3 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial_1) + + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecialIsHandled_3 && + WILL_FIRE_RL_s_config_1_axiWriteSpecialIsHandled) + + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecialIsHandled_3 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial) + + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecialIsHandled_4 && + WILL_FIRE_RL_s_config_1_axiWriteSpecialIsHandled_3) + + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecialIsHandled_4 && + WILL_FIRE_RL_s_config_1_axiWriteSpecialIsHandled_2) + + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecialIsHandled_4 && + WILL_FIRE_RL_s_config_1_axiWriteSpecialIsHandled_1) + + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecialIsHandled_4 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial_1) + + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecialIsHandled_4 && + WILL_FIRE_RL_s_config_1_axiWriteSpecialIsHandled) + + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecialIsHandled_4 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial) + + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_4 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial_1) + + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_4 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial_1 && + s_config_writeSlave_in_rv[81:78] == 4'd8 && + s_config_writeSlave_in_rv[87] && + !s_config_writeBusy) + + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_4 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial) + + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_4 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial && + s_config_writeSlave_in_rv[81:78] == 4'd8 && + s_config_writeSlave_in_rv[87] && + !s_config_writeBusy) + + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_3 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial_4) + + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_3 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial_4 && + s_config_writeSlave_in_rv[81:78] == 4'd6 && + s_config_writeSlave_in_rv[87] && + !s_config_writeBusy) + + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_3 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial_1) + + + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_3 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial_1 && + s_config_writeSlave_in_rv[81:78] == 4'd6 && + s_config_writeSlave_in_rv[87] && + !s_config_writeBusy) + + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_3 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial) + + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_3 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial && + s_config_writeSlave_in_rv[81:78] == 4'd6 && + s_config_writeSlave_in_rv[87] && + !s_config_writeBusy) + + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_2 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial_4) + + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_2 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial_4 && + s_config_writeSlave_in_rv[81:78] == 4'd4 && + s_config_writeSlave_in_rv[87] && + !s_config_writeBusy) + + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_2 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial_3) + + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_2 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial_3 && + s_config_writeSlave_in_rv[81:78] == 4'd4 && + s_config_writeSlave_in_rv[87] && + !s_config_writeBusy) + + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_2 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial_1) + + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_2 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial_1 && + s_config_writeSlave_in_rv[81:78] == 4'd4 && + s_config_writeSlave_in_rv[87] && + !s_config_writeBusy) + + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_2 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial) + + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_s_config_1_axiWriteSpecial_2 && + WILL_FIRE_RL_s_config_1_axiWriteSpecial && + s_config_writeSlave_in_rv[81:78] == 4'd4 && + s_config_writeSlave_in_rv[87] && + !s_config_writeBusy) + + end + // synopsys translate_on +endmodule // mkNVEmulator + diff --git a/toolflow/vivado/common/ip/NVEmulator/xgui/NVEmulator_v1_0.tcl b/toolflow/vivado/common/ip/NVEmulator/xgui/NVEmulator_v1_0.tcl new file mode 100644 index 00000000..0db18e9a --- /dev/null +++ b/toolflow/vivado/common/ip/NVEmulator/xgui/NVEmulator_v1_0.tcl @@ -0,0 +1,10 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + ipgui::add_page $IPINST -name "Page 0" + + +} + + diff --git a/toolflow/vivado/common/ip/NVEmulator/xgui/mkNVEmulator_v1_0.tcl b/toolflow/vivado/common/ip/NVEmulator/xgui/mkNVEmulator_v1_0.tcl new file mode 100644 index 00000000..0db18e9a --- /dev/null +++ b/toolflow/vivado/common/ip/NVEmulator/xgui/mkNVEmulator_v1_0.tcl @@ -0,0 +1,10 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + ipgui::add_page $IPINST -name "Page 0" + + +} + + diff --git a/toolflow/vivado/platform/AU280/plugins/NVMulator.tcl b/toolflow/vivado/platform/AU280/plugins/NVMulator.tcl new file mode 100644 index 00000000..dd3be557 --- /dev/null +++ b/toolflow/vivado/platform/AU280/plugins/NVMulator.tcl @@ -0,0 +1,26 @@ +# Copyright (c) 2014-2023 Embedded Systems and Applications, TU Darmstadt. +# +# This file is part of TaPaSCo +# (see https://github.com/esa-tu-darmstadt/tapasco). +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU Lesser General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public License +# along with this program. If not, see . +# + +namespace eval nvmulator { + + proc is_nvmulator_supported {} { + return true + } + +} diff --git a/toolflow/vivado/platform/common/plugins/NVMulator.tcl b/toolflow/vivado/platform/common/plugins/NVMulator.tcl new file mode 100644 index 00000000..090f27fd --- /dev/null +++ b/toolflow/vivado/platform/common/plugins/NVMulator.tcl @@ -0,0 +1,79 @@ +# Copyright (c) 2014-2023 Embedded Systems and Applications, TU Darmstadt. +# +# This file is part of TaPaSCo +# (see https://github.com/esa-tu-darmstadt/tapasco). +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU Lesser General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public License +# along with this program. If not, see . +# +namespace eval nvmulator { + + proc is_nvmulator_supported {} { + return false + } + + proc add_nvmulator {} { + if {[tapasco::is_feature_enabled "NVMulator"]} { + if {![is_nvmulator_supported]} { + puts "ERROR: NVMulator is not supported by specified platform" + exit 1 + } + + set oldCurInst [current_bd_instance .] + + current_bd_instance "/memory" + set memory_p_aresetn [tapasco::subsystem::get_port "mem" "rst" "peripheral" "resetn"] + set memory_clk [tapasco::subsystem::get_port "mem" "clk"] + set design_clk [tapasco::subsystem::get_port "design" "clk"] + + set nvmulator [create_bd_cell -type ip -vlnv esa.informatik.tu-darmstadt.de:user:NVEmulator:1.0 NVMulator] + connect_bd_net [get_bd_pins $memory_clk] [get_bd_pins $nvmulator/CLK] + connect_bd_net [get_bd_pins $memory_p_aresetn] [get_bd_pins $nvmulator/RST_N] + + delete_bd_objs [get_bd_intf_nets /memory/mig_ic_M00_AXI] + connect_bd_intf_net [get_bd_intf_pins $nvmulator/M_AXI_MIG] [get_bd_intf_pins /memory/mig/C0_DDR4_S_AXI] + connect_bd_intf_net [get_bd_intf_pins /memory/mig_ic/M00_AXI] [get_bd_intf_pins $nvmulator/S_AXI_NV] + + set nvmulator_ic [create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 nvmulator_ic] + set_property -dict [list CONFIG.NUM_CLKS {2} CONFIG.NUM_MI {1} CONFIG.NUM_SI {1}] [get_bd_cells $nvmulator_ic] + connect_bd_net [get_bd_pins $nvmulator_ic/aclk] [get_bd_pins $memory_clk] + connect_bd_net [get_bd_pins $nvmulator_ic/aclk1] [get_bd_pins $design_clk] + connect_bd_net [get_bd_pins $memory_p_aresetn] [get_bd_pins $nvmulator_ic/aresetn] + + set s_nvm [create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 "S_NVM"] + connect_bd_intf_net [get_bd_intf_pins /memory/S_NVM] [get_bd_intf_pins $nvmulator_ic/S00_AXI] + connect_bd_intf_net [get_bd_intf_pins $nvmulator_ic/M00_AXI] [get_bd_intf_pins $nvmulator/S_AXI] + + current_bd_instance "/host" + set m_nvm [create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 "M_NVM"] + set num_host_out_old [get_property CONFIG.NUM_MI [get_bd_cells /host/out_ic]] + set num_host_out [expr "$num_host_out_old + 1"] + set_property -dict [list CONFIG.NUM_MI $num_host_out] [get_bd_cells /host/out_ic] + connect_bd_intf_net [get_bd_intf_pins /host/out_ic/[format "M%02d_AXI" $num_host_out_old]] $m_nvm + + connect_bd_intf_net [get_bd_intf_pins /host/M_NVM] [get_bd_intf_pins /memory/S_NVM] + + current_bd_instance $oldCurInst + } + return {} + } + + proc addressmap {{args {}}} { + if {[tapasco::is_feature_enabled "NVMulator"]} { + set args [lappend args "M_NVM" [list 0x50000 0x10000 0 "PLATFORM_COMPONENT_NVMULATOR"]] + } + return $args + } +} +tapasco::register_plugin "platform::nvmulator::add_nvmulator" "pre-wiring" +tapasco::register_plugin "platform::nvmulator::addressmap" "post-address-map"