Add RTT, PAGE_BUFFER

Author: bugadani

Cargo.toml

@@ -6,12 +6,10 @@ edition = "2018"
 
 [dependencies]
 panic-never = "0.1.0"
-ufmt = { version = "0.1.0", optional = true }
+ufmt = "0.1.0"
 cfg-if = "1.0"
 
 [features]
-log = ["ufmt"]
-
 # targets
 esp32 = []
 esp32s2 = []

ld/esp32.x

@@ -1,7 +1,7 @@
 MEMORY {
-    /* Middle of SRAM0 */
-    IRAM : ORIGIN = 0x40090000, LENGTH = 0x10000
-    RWDATA : ORIGIN = 0x3FFC0000, LENGTH = 0x20000
+    /* SRAM1 */
+    IRAM : ORIGIN = 0x400A0000, LENGTH = 0x8000
+    RWDATA : ORIGIN = 0x3FFE0000, LENGTH = 0x18000
 }
 
 INCLUDE "loader.x"

ld/esp32s2.x

@@ -1,7 +1,8 @@
 MEMORY {
     /* SRAM1 + 0x4000 cache + 0x400 vectors */
-    IRAM : ORIGIN = 0x4002C400, LENGTH = 0x10000
-    RWDATA : ORIGIN = 0x3FFBE000, LENGTH = 0x21000
+    IRAM : ORIGIN = 0x40028000 + 0x4000 + 0x400, LENGTH = 0x10000
+    /* SRAM1 over the data bus, after IRAM */
+    RWDATA : ORIGIN = 0x3FFB8000 + 0x4000 + 0x400 + 0x10000, LENGTH = 0x20000
 }
 
 INCLUDE "loader.x"

ld/esp32s3.x

@@ -1,7 +1,8 @@
 MEMORY {
-    /* SRAM2 + 0x8400 */
-    IRAM : ORIGIN = 0x40380400, LENGTH = 0x10000
-    RWDATA : ORIGIN = 0x3FCB0000, LENGTH = 0x20000
+    /* Use SRAM1 (+0x8400) which is accessible via both instruction and data busses */
+    IRAM : ORIGIN = 0x40380400, LENGTH = 0x40388000 - 0x40380400
+    /* SRAM1 over the data bus, after IRAM */
+    RWDATA : ORIGIN = 0x3FC98000, LENGTH = 0x20000
 }
 
 INCLUDE "loader.x"

src/chip/esp32.rs

@@ -94,3 +94,27 @@ pub fn major_chip_version() -> u8 {
 pub fn minor_chip_version() -> u8 {
     read_field::<0, 184, 2>()
 }
+
+/// Ensures that data (e.g. constants) are accessed through the data bus.
+pub unsafe fn read_via_data_bus(s: &u8) -> u8 {
+    // SRAM1
+    const DBUS_START: usize = 0x3FFE_0000;
+    const DBUS_END: usize = 0x4000_0000;
+
+    let addr = s as *const u8 as usize;
+    if addr >= DBUS_START && addr < DBUS_END {
+        *s
+    } else {
+        let byte_in_word = addr & 0x3;
+        let addr = addr - byte_in_word;
+
+        let word: u32;
+        core::arch::asm!(
+            "l32i {0}, {1}, 0",
+            out(reg) word,
+            in(reg) addr,
+        );
+
+        (word >> (byte_in_word * 8)) as u8
+    }
+}

src/chip/esp32c2.rs

@@ -93,3 +93,8 @@ pub fn major_chip_version() -> u8 {
 pub fn minor_chip_version() -> u8 {
     read_field::<2, 48, 4>()
 }
+
+/// Ensures that data (e.g. constants) are accessed through the data bus.
+pub unsafe fn read_via_data_bus(s: &u8) -> u8 {
+    unsafe { core::ptr::read(s as *const u8) }
+}

src/chip/esp32c3.rs

@@ -103,3 +103,8 @@ pub fn minor_chip_version() -> u8 {
 
     hi << 3 | lo
 }
+
+/// Ensures that data (e.g. constants) are accessed through the data bus.
+pub unsafe fn read_via_data_bus(s: &u8) -> u8 {
+    unsafe { core::ptr::read(s as *const u8) }
+}

src/chip/esp32c5.rs

@@ -62,3 +62,8 @@ pub fn major_chip_version() -> u8 {
 pub fn minor_chip_version() -> u8 {
     read_field::<1, 64, 4>()
 }
+
+/// Ensures that data (e.g. constants) are accessed through the data bus.
+pub unsafe fn read_via_data_bus(s: &u8) -> u8 {
+    unsafe { core::ptr::read(s as *const u8) }
+}

src/chip/esp32c6.rs

@@ -72,3 +72,8 @@ pub fn major_chip_version() -> u8 {
 pub fn minor_chip_version() -> u8 {
     read_field::<1, 114, 4>()
 }
+
+/// Ensures that data (e.g. constants) are accessed through the data bus.
+pub unsafe fn read_via_data_bus(s: &u8) -> u8 {
+    unsafe { core::ptr::read(s as *const u8) }
+}

src/chip/esp32c61.rs

@@ -62,3 +62,8 @@ pub fn major_chip_version() -> u8 {
 pub fn minor_chip_version() -> u8 {
     read_field::<1, 64, 4>()
 }
+
+/// Ensures that data (e.g. constants) are accessed through the data bus.
+pub unsafe fn read_via_data_bus(s: &u8) -> u8 {
+    unsafe { core::ptr::read(s as *const u8) }
+}