@@ -301,68 +301,15 @@ esp_err_t es8311_pa_power(bool enable)
301301 return ret ;
302302}
303303
304- esp_err_t es8311_codec_init ( audio_hal_codec_config_t * codec_cfg )
304+ esp_err_t es8311_config_sample ( int sample_rate )
305305{
306- uint8_t datmp , regv ;
307- int coeff ;
308306 esp_err_t ret = ESP_OK ;
309- i2c_init (); // ESP32 in master mode
310-
311- /* Enhance ES8311 I2C noise immunity */
312- ret |= es8311_write_reg (ES8311_GPIO_REG44 , 0x08 );
313- /* Due to occasional failures during the first I2C write with the ES8311 chip, a second write is performed to ensure reliability */
314- ret |= es8311_write_reg (ES8311_GPIO_REG44 , 0x08 );
315-
316- ret |= es8311_write_reg (ES8311_CLK_MANAGER_REG01 , 0x30 );
317- ret |= es8311_write_reg (ES8311_CLK_MANAGER_REG02 , 0x00 );
318- ret |= es8311_write_reg (ES8311_CLK_MANAGER_REG03 , 0x10 );
319- ret |= es8311_write_reg (ES8311_ADC_REG16 , 0x24 );
320- ret |= es8311_write_reg (ES8311_CLK_MANAGER_REG04 , 0x10 );
321- ret |= es8311_write_reg (ES8311_CLK_MANAGER_REG05 , 0x00 );
322- ret |= es8311_write_reg (ES8311_SYSTEM_REG0B , 0x00 );
323- ret |= es8311_write_reg (ES8311_SYSTEM_REG0C , 0x00 );
324- ret |= es8311_write_reg (ES8311_SYSTEM_REG10 , 0x1F );
325- ret |= es8311_write_reg (ES8311_SYSTEM_REG11 , 0x7F );
326- ret |= es8311_write_reg (ES8311_RESET_REG00 , 0x80 );
327- /* Set Codec into Master or Slave mode */
328- regv = es8311_read_reg (ES8311_RESET_REG00 );
329- /* Set master/slave audio interface */
330- audio_hal_codec_i2s_iface_t * i2s_cfg = & (codec_cfg -> i2s_iface );
331- switch (i2s_cfg -> mode ) {
332- case AUDIO_HAL_MODE_MASTER : /* MASTER MODE */
333- ESP_LOGI (TAG , "ES8311 in Master mode" );
334- regv |= 0x40 ;
335- break ;
336- case AUDIO_HAL_MODE_SLAVE : /* SLAVE MODE */
337- ESP_LOGI (TAG , "ES8311 in Slave mode" );
338- regv &= 0xBF ;
339- break ;
340- default :
341- regv &= 0xBF ;
342- }
343- ret |= es8311_write_reg (ES8311_RESET_REG00 , regv );
344- ret |= es8311_write_reg (ES8311_CLK_MANAGER_REG01 , 0x3F );
345- /* Select clock source for internal mclk */
346- switch (get_es8311_mclk_src ()) {
347- case FROM_MCLK_PIN :
348- regv = es8311_read_reg (ES8311_CLK_MANAGER_REG01 );
349- regv &= 0x7F ;
350- ret |= es8311_write_reg (ES8311_CLK_MANAGER_REG01 , regv );
351- break ;
352- case FROM_SCLK_PIN :
353- regv = es8311_read_reg (ES8311_CLK_MANAGER_REG01 );
354- regv |= 0x80 ;
355- ret |= es8311_write_reg (ES8311_CLK_MANAGER_REG01 , regv );
356- break ;
357- default :
358- regv = es8311_read_reg (ES8311_CLK_MANAGER_REG01 );
359- regv &= 0x7F ;
360- ret |= es8311_write_reg (ES8311_CLK_MANAGER_REG01 , regv );
361- break ;
362- }
307+ uint8_t datmp , regv ;
363308 int sample_fre = 0 ;
364309 int mclk_fre = 0 ;
365- switch (i2s_cfg -> samples ) {
310+ int coeff ;
311+
312+ switch (sample_rate ) {
366313 case AUDIO_HAL_08K_SAMPLES :
367314 sample_fre = 8000 ;
368315 break ;
@@ -391,6 +338,7 @@ esp_err_t es8311_codec_init(audio_hal_codec_config_t *codec_cfg)
391338 ESP_LOGE (TAG , "Unable to configure sample rate %dHz" , sample_fre );
392339 break ;
393340 }
341+
394342 mclk_fre = sample_fre * MCLK_DIV_FRE ;
395343 coeff = get_coeff (mclk_fre , sample_fre );
396344 if (coeff < 0 ) {
@@ -421,7 +369,13 @@ esp_err_t es8311_codec_init(audio_hal_codec_config_t *codec_cfg)
421369
422370 if (get_es8311_mclk_src () == FROM_SCLK_PIN ) {
423371 datmp = 3 ; /* DIG_MCLK = LRCK * 256 = BCLK * 8 */
372+ if (sample_fre == 8000 ) {
373+ /* When the sample rate is 8kHz, BCLK requires at least 512K (slot bit needs to be configured to 32bit).
374+ DIG_MCLK = LRCK * 256 = BCLK * 4 */
375+ datmp = 2 ;
376+ }
424377 }
378+
425379 regv |= (datmp ) << 3 ;
426380 ret |= es8311_write_reg (ES8311_CLK_MANAGER_REG02 , regv );
427381
@@ -456,6 +410,70 @@ esp_err_t es8311_codec_init(audio_hal_codec_config_t *codec_cfg)
456410 ret |= es8311_write_reg (ES8311_CLK_MANAGER_REG06 , regv );
457411 }
458412
413+ return ESP_OK ;
414+ }
415+
416+ esp_err_t es8311_codec_init (audio_hal_codec_config_t * codec_cfg )
417+ {
418+ uint8_t regv ;
419+ esp_err_t ret = ESP_OK ;
420+ i2c_init (); // ESP32 in master mode
421+
422+ /* Enhance ES8311 I2C noise immunity */
423+ ret |= es8311_write_reg (ES8311_GPIO_REG44 , 0x08 );
424+ /* Due to occasional failures during the first I2C write with the ES8311 chip, a second write is performed to ensure reliability */
425+ ret |= es8311_write_reg (ES8311_GPIO_REG44 , 0x08 );
426+
427+ ret |= es8311_write_reg (ES8311_CLK_MANAGER_REG01 , 0x30 );
428+ ret |= es8311_write_reg (ES8311_CLK_MANAGER_REG02 , 0x00 );
429+ ret |= es8311_write_reg (ES8311_CLK_MANAGER_REG03 , 0x10 );
430+ ret |= es8311_write_reg (ES8311_ADC_REG16 , 0x24 );
431+ ret |= es8311_write_reg (ES8311_CLK_MANAGER_REG04 , 0x10 );
432+ ret |= es8311_write_reg (ES8311_CLK_MANAGER_REG05 , 0x00 );
433+ ret |= es8311_write_reg (ES8311_SYSTEM_REG0B , 0x00 );
434+ ret |= es8311_write_reg (ES8311_SYSTEM_REG0C , 0x00 );
435+ ret |= es8311_write_reg (ES8311_SYSTEM_REG10 , 0x1F );
436+ ret |= es8311_write_reg (ES8311_SYSTEM_REG11 , 0x7F );
437+ ret |= es8311_write_reg (ES8311_RESET_REG00 , 0x80 );
438+ /* Set Codec into Master or Slave mode */
439+ regv = es8311_read_reg (ES8311_RESET_REG00 );
440+ /* Set master/slave audio interface */
441+ audio_hal_codec_i2s_iface_t * i2s_cfg = & (codec_cfg -> i2s_iface );
442+ switch (i2s_cfg -> mode ) {
443+ case AUDIO_HAL_MODE_MASTER : /* MASTER MODE */
444+ ESP_LOGI (TAG , "ES8311 in Master mode" );
445+ regv |= 0x40 ;
446+ break ;
447+ case AUDIO_HAL_MODE_SLAVE : /* SLAVE MODE */
448+ ESP_LOGI (TAG , "ES8311 in Slave mode" );
449+ regv &= 0xBF ;
450+ break ;
451+ default :
452+ regv &= 0xBF ;
453+ }
454+ ret |= es8311_write_reg (ES8311_RESET_REG00 , regv );
455+ ret |= es8311_write_reg (ES8311_CLK_MANAGER_REG01 , 0x3F );
456+ /* Select clock source for internal mclk */
457+ switch (get_es8311_mclk_src ()) {
458+ case FROM_MCLK_PIN :
459+ regv = es8311_read_reg (ES8311_CLK_MANAGER_REG01 );
460+ regv &= 0x7F ;
461+ ret |= es8311_write_reg (ES8311_CLK_MANAGER_REG01 , regv );
462+ break ;
463+ case FROM_SCLK_PIN :
464+ regv = es8311_read_reg (ES8311_CLK_MANAGER_REG01 );
465+ regv |= 0x80 ;
466+ ret |= es8311_write_reg (ES8311_CLK_MANAGER_REG01 , regv );
467+ break ;
468+ default :
469+ regv = es8311_read_reg (ES8311_CLK_MANAGER_REG01 );
470+ regv &= 0x7F ;
471+ ret |= es8311_write_reg (ES8311_CLK_MANAGER_REG01 , regv );
472+ break ;
473+ }
474+
475+ es8311_config_sample (i2s_cfg -> samples );
476+
459477 /* mclk inverted or not */
460478 if (INVERT_MCLK ) {
461479 regv = es8311_read_reg (ES8311_CLK_MANAGER_REG01 );
@@ -577,7 +595,9 @@ esp_err_t es8311_set_bits_per_sample(audio_hal_iface_bits_t bits)
577595esp_err_t es8311_codec_config_i2s (audio_hal_codec_mode_t mode , audio_hal_codec_i2s_iface_t * iface )
578596{
579597 int ret = ESP_OK ;
598+ ESP_LOGI (TAG , "CFG I2S: mode = %d, bits = %d, fmt = %d, samples = %d" , mode , iface -> bits , iface -> fmt , iface -> samples );
580599 ret |= es8311_set_bits_per_sample (iface -> bits );
600+ ret |= es8311_config_sample (iface -> samples );
581601 ret |= es8311_config_fmt (iface -> fmt );
582602 return ret ;
583603}
@@ -750,6 +770,6 @@ void es8311_read_all()
750770{
751771 for (int i = 0 ; i < 0x4A ; i ++ ) {
752772 uint8_t reg = es8311_read_reg (i );
753- ESP_LOGI (TAG , "REG:%02x, %02x" , reg , i );
773+ ESP_LOGI (TAG , "REG:%02x, %02x" , i , reg );
754774 }
755775}
0 commit comments