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Merge branch 'bugfix/potential_wifi_not_work_issue_esp32c2' into 'master'
fix: Fixed a potential issue that wifi may not work (for ESP32-C2 on ESP-IDF v5.0) See merge request application/esp-at!1487
2 parents 83455e2 + c8765c6 commit da4fb41

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‎module_config/module_esp32c2-2mb/patch/bbpll_calibration.patch‎

Lines changed: 88 additions & 0 deletions
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@@ -0,0 +1,88 @@
1+
diff --git a/components/esp_hw_support/port/esp32c2/rtc_clk.c b/components/esp_hw_support/port/esp32c2/rtc_clk.c
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index a0d88be36f..3b293e2fc4 100644
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--- a/components/esp_hw_support/port/esp32c2/rtc_clk.c
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+++ b/components/esp_hw_support/port/esp32c2/rtc_clk.c
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@@ -128,6 +128,7 @@ static void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq)
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clk_ll_bbpll_set_config(pll_freq, xtal_freq);
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/* WAIT CALIBRATION DONE */
8+
while(!regi2c_ctrl_ll_bbpll_calibration_is_done());
9+
+ esp_rom_delay_us(10);
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/* BBPLL CALIBRATION STOP */
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regi2c_ctrl_ll_bbpll_calibration_stop();
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@@ -350,6 +351,22 @@ bool rtc_dig_8m_enabled(void)
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return clk_ll_rc_fast_digi_is_enabled();
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}
16+
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+// Workaround for bootloader not calibration well issue.
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+// Placed in IRAM because disabling BBPLL may influence the cache
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+void rtc_clk_recalib_bbpll(void)
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+{
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+ rtc_cpu_freq_config_t old_config;
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+ rtc_clk_cpu_freq_get_config(&old_config);
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+
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+ rtc_clk_cpu_freq_set_xtal();
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+
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+ rtc_clk_bbpll_disable();
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+ rtc_clk_bbpll_enable();
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+ rtc_clk_bbpll_configure(rtc_clk_xtal_freq_get(), 480);
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+
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+ rtc_clk_cpu_freq_set_config(&old_config);
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+}
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+
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/* Name used in libphy.a:phy_chip_v7.o
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* TODO: update the library to use rtc_clk_xtal_freq_get
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*/
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diff --git a/components/esp_system/Kconfig b/components/esp_system/Kconfig
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index 0abd2abd9d..872434a480 100644
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--- a/components/esp_system/Kconfig
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+++ b/components/esp_system/Kconfig
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@@ -543,6 +543,15 @@ menu "ESP System Settings"
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(2). For special workflow, the chip needs do more things instead of restarting directly. This part
42+
needs to be done in callback function of interrupt.
43+
44+
+ config ESP_SYSTEM_BBPLL_RECALIB
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+ bool "Re-calibration BBPLL at startup"
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+ depends on IDF_TARGET_ESP32C2 || IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32C6 || IDF_TARGET_ESP32H2
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+ default y
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+ help
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+ This configuration helps to address an BBPLL inaccurate issue when boot from certain bootloader version,
50+
+ which may increase about the boot-up time by about 200 us. Disable this when your bootloader is built with
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+ ESP-IDF version v5.2 and above.
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+
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endmenu # ESP System Settings
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menu "IPC (Inter-Processor Call)"
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diff --git a/components/esp_system/port/cpu_start.c b/components/esp_system/port/cpu_start.c
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index b6e6b4a2f4..c64361193b 100644
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--- a/components/esp_system/port/cpu_start.c
59+
+++ b/components/esp_system/port/cpu_start.c
60+
@@ -419,6 +419,12 @@ void IRAM_ATTR call_start_cpu0(void)
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* In this stage, we re-configure the Flash (and MSPI) to required configuration
62+
*/
63+
spi_flash_init_chip_state();
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+
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+ // In earlier version of ESP-IDF, the PLL provided by bootloader is not stable enough.
66+
+ // Do calibration again here so that we can use better clock for the timing tuning.
67+
+#if CONFIG_ESP_SYSTEM_BBPLL_RECALIB
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+ rtc_clk_recalib_bbpll();
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+#endif
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#if CONFIG_IDF_TARGET_ESP32S3
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//On other chips, this feature is not provided by HW, or hasn't been tested yet.
72+
spi_timing_flash_tuning();
73+
diff --git a/components/soc/esp32c2/include/soc/rtc.h b/components/soc/esp32c2/include/soc/rtc.h
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index 131eecadaf..14ce306996 100644
75+
--- a/components/soc/esp32c2/include/soc/rtc.h
76+
+++ b/components/soc/esp32c2/include/soc/rtc.h
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@@ -502,6 +502,11 @@ void rtc_dig_clk8m_disable(void);
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*/
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bool rtc_dig_8m_enabled(void);
80+
81+
+/**
82+
+ * @brief Workaround for C2, S3, C6, H2. Trigger the calibration of PLL. Should be called when the bootloader doesn't provide a good enough PLL accuracy.
83+
+*/
84+
+void rtc_clk_recalib_bbpll(void);
85+
+
86+
/**
87+
* @brief Calculate the real clock value after the clock calibration
88+
*

‎module_config/module_esp32c2-2mb/patch/patch_list.ini‎

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Original file line numberDiff line numberDiff line change
@@ -7,3 +7,7 @@
77
[mbedtls_dynamic_buffer.patch]
88
path = esp-idf
99
note = "Fixed a potential ssl crash if uses mbedtls dynamic buffer feature and has ssl renegotiation"
10+
11+
[bbpll_calibration.patch]
12+
path = esp-idf
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note = "Fixed a potential issue that wifi may not work (for ESP32-C2 on ESP-IDF v5.0)"

‎module_config/module_esp32c2_default/patch/bbpll_calibration.patch‎

Lines changed: 88 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,88 @@
1+
diff --git a/components/esp_hw_support/port/esp32c2/rtc_clk.c b/components/esp_hw_support/port/esp32c2/rtc_clk.c
2+
index a0d88be36f..3b293e2fc4 100644
3+
--- a/components/esp_hw_support/port/esp32c2/rtc_clk.c
4+
+++ b/components/esp_hw_support/port/esp32c2/rtc_clk.c
5+
@@ -128,6 +128,7 @@ static void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq)
6+
clk_ll_bbpll_set_config(pll_freq, xtal_freq);
7+
/* WAIT CALIBRATION DONE */
8+
while(!regi2c_ctrl_ll_bbpll_calibration_is_done());
9+
+ esp_rom_delay_us(10);
10+
/* BBPLL CALIBRATION STOP */
11+
regi2c_ctrl_ll_bbpll_calibration_stop();
12+
13+
@@ -350,6 +351,22 @@ bool rtc_dig_8m_enabled(void)
14+
return clk_ll_rc_fast_digi_is_enabled();
15+
}
16+
17+
+// Workaround for bootloader not calibration well issue.
18+
+// Placed in IRAM because disabling BBPLL may influence the cache
19+
+void rtc_clk_recalib_bbpll(void)
20+
+{
21+
+ rtc_cpu_freq_config_t old_config;
22+
+ rtc_clk_cpu_freq_get_config(&old_config);
23+
+
24+
+ rtc_clk_cpu_freq_set_xtal();
25+
+
26+
+ rtc_clk_bbpll_disable();
27+
+ rtc_clk_bbpll_enable();
28+
+ rtc_clk_bbpll_configure(rtc_clk_xtal_freq_get(), 480);
29+
+
30+
+ rtc_clk_cpu_freq_set_config(&old_config);
31+
+}
32+
+
33+
/* Name used in libphy.a:phy_chip_v7.o
34+
* TODO: update the library to use rtc_clk_xtal_freq_get
35+
*/
36+
diff --git a/components/esp_system/Kconfig b/components/esp_system/Kconfig
37+
index 0abd2abd9d..872434a480 100644
38+
--- a/components/esp_system/Kconfig
39+
+++ b/components/esp_system/Kconfig
40+
@@ -543,6 +543,15 @@ menu "ESP System Settings"
41+
(2). For special workflow, the chip needs do more things instead of restarting directly. This part
42+
needs to be done in callback function of interrupt.
43+
44+
+ config ESP_SYSTEM_BBPLL_RECALIB
45+
+ bool "Re-calibration BBPLL at startup"
46+
+ depends on IDF_TARGET_ESP32C2 || IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32C6 || IDF_TARGET_ESP32H2
47+
+ default y
48+
+ help
49+
+ This configuration helps to address an BBPLL inaccurate issue when boot from certain bootloader version,
50+
+ which may increase about the boot-up time by about 200 us. Disable this when your bootloader is built with
51+
+ ESP-IDF version v5.2 and above.
52+
+
53+
endmenu # ESP System Settings
54+
55+
menu "IPC (Inter-Processor Call)"
56+
diff --git a/components/esp_system/port/cpu_start.c b/components/esp_system/port/cpu_start.c
57+
index b6e6b4a2f4..c64361193b 100644
58+
--- a/components/esp_system/port/cpu_start.c
59+
+++ b/components/esp_system/port/cpu_start.c
60+
@@ -419,6 +419,12 @@ void IRAM_ATTR call_start_cpu0(void)
61+
* In this stage, we re-configure the Flash (and MSPI) to required configuration
62+
*/
63+
spi_flash_init_chip_state();
64+
+
65+
+ // In earlier version of ESP-IDF, the PLL provided by bootloader is not stable enough.
66+
+ // Do calibration again here so that we can use better clock for the timing tuning.
67+
+#if CONFIG_ESP_SYSTEM_BBPLL_RECALIB
68+
+ rtc_clk_recalib_bbpll();
69+
+#endif
70+
#if CONFIG_IDF_TARGET_ESP32S3
71+
//On other chips, this feature is not provided by HW, or hasn't been tested yet.
72+
spi_timing_flash_tuning();
73+
diff --git a/components/soc/esp32c2/include/soc/rtc.h b/components/soc/esp32c2/include/soc/rtc.h
74+
index 131eecadaf..14ce306996 100644
75+
--- a/components/soc/esp32c2/include/soc/rtc.h
76+
+++ b/components/soc/esp32c2/include/soc/rtc.h
77+
@@ -502,6 +502,11 @@ void rtc_dig_clk8m_disable(void);
78+
*/
79+
bool rtc_dig_8m_enabled(void);
80+
81+
+/**
82+
+ * @brief Workaround for C2, S3, C6, H2. Trigger the calibration of PLL. Should be called when the bootloader doesn't provide a good enough PLL accuracy.
83+
+*/
84+
+void rtc_clk_recalib_bbpll(void);
85+
+
86+
/**
87+
* @brief Calculate the real clock value after the clock calibration
88+
*

‎module_config/module_esp32c2_default/patch/patch_list.ini‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -7,3 +7,7 @@
77
[mbedtls_dynamic_buffer.patch]
88
path = esp-idf
99
note = "Fixed a potential ssl crash if uses mbedtls dynamic buffer feature and has ssl renegotiation"
10+
11+
[bbpll_calibration.patch]
12+
path = esp-idf
13+
note = "Fixed a potential issue that wifi may not work (for ESP32-C2 on ESP-IDF v5.0)"

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