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Dzarda7Dzarda7
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feat: Add initial chip structure
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22 files changed

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22 files changed

+1348
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lines changed

‎CMakeLists.txt‎

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@@ -62,7 +62,8 @@ add_subdirectory(${CMAKE_SOURCE_DIR}/src)
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set(ESP_TARGET ${TARGET_CHIP} CACHE INTERNAL "Pass TARGET_CHIP as ESP_TARGET")
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add_subdirectory(${CMAKE_SOURCE_DIR}/esp-stub-lib)
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target_link_libraries(${TARGET_NAME} PRIVATE esp-stub-lib)
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add_subdirectory(${CMAKE_SOURCE_DIR}/soc)
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target_link_libraries(${TARGET_NAME} PRIVATE esp-stub-lib soc)
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add_custom_command(TARGET ${TARGET_NAME} POST_BUILD
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COMMAND ${CMAKE_SOURCE_DIR}/tools/elf2json.py ${CMAKE_BINARY_DIR}/${TARGET_NAME}${CMAKE_EXECUTABLE_SUFFIX_C} ${CMAKE_BINARY_DIR}/${TARGET_CHIP}.json

‎soc/CMakeLists.txt‎

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cmake_minimum_required(VERSION 3.28)
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add_library(soc STATIC)
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target_sources(soc PRIVATE
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common/soc.c
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common/uart_common.c
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common/watchdog_common.c
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)
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if(TARGET_CHIP STREQUAL "esp32")
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target_sources(soc PRIVATE targets/esp32.c)
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elseif(TARGET_CHIP STREQUAL "esp32s2")
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target_sources(soc PRIVATE targets/esp32s2.c)
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elseif(TARGET_CHIP STREQUAL "esp32s3")
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target_sources(soc PRIVATE targets/esp32s3.c)
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elseif(TARGET_CHIP STREQUAL "esp32c2")
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target_sources(soc PRIVATE targets/esp32c2.c)
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elseif(TARGET_CHIP STREQUAL "esp32c3")
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target_sources(soc PRIVATE targets/esp32c3.c)
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elseif(TARGET_CHIP STREQUAL "esp32c5")
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target_sources(soc PRIVATE targets/esp32c5.c)
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elseif(TARGET_CHIP STREQUAL "esp32c6")
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target_sources(soc PRIVATE targets/esp32c6.c)
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elseif(TARGET_CHIP STREQUAL "esp32c61")
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target_sources(soc PRIVATE targets/esp32c61.c)
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elseif(TARGET_CHIP STREQUAL "esp32h2")
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target_sources(soc PRIVATE targets/esp32h2.c)
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elseif(TARGET_CHIP STREQUAL "esp32p4")
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target_sources(soc PRIVATE targets/esp32p4.c)
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elseif(TARGET_CHIP STREQUAL "esp8266")
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target_sources(soc PRIVATE targets/esp8266.c)
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else()
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message(FATAL_ERROR "Unsupported TARGET_CHIP: ${TARGET_CHIP}")
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endif()
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# Include directories
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target_include_directories(soc PUBLIC
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${CMAKE_CURRENT_SOURCE_DIR}/include
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)

‎soc/common/soc.c‎

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/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0 OR MIT
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*/
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#include <stddef.h>
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#include "soc.h"
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/*
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* Single SoC info structure - chip-specific file provides this
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* Chip selected at compile time
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*/
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extern const soc_info_t soc_info;
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const soc_info_t* soc_get_info(void)
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{
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return &soc_info;
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}

‎soc/common/uart_common.c‎

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/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0 OR MIT
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*/
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#include "soc.h"
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void uart_init(void)
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{
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// Common UART initialization logic, especially interrupt handling
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}

‎soc/common/watchdog_common.c‎

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/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0 OR MIT
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*/
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#include "soc.h"
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void disable_watchdogs(void)
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{
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const rtc_t *rtc = soc_get_peripherals()->rtc;
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if (rtc->wdt_disable) {
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rtc->wdt_disable();
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}
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}
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void enable_watchdogs(void)
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{
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const rtc_t *rtc = soc_get_peripherals()->rtc;
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if (rtc->wdt_enable) {
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rtc->wdt_enable();
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}
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}

‎soc/include/peripherals/rtc.h‎

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/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0 OR MIT
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*/
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#pragma once
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* RTC/Power Management peripheral structure */
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typedef struct {
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/* Register offsets */
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uint32_t option1_reg;
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uint32_t wdtconfig0_reg;
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uint32_t wdtwprotect_reg;
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uint32_t swd_conf_reg;
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uint32_t swd_wprotect_reg;
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uint32_t cpu_per_conf_reg;
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uint32_t sysclk_conf_reg;
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/* Chip-specific values */
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uint32_t swd_wkey;
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uint32_t wdt_wkey;
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uint32_t swd_auto_feed_en_bit;
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uint32_t force_download_boot_bit;
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uint32_t cpuperiod_sel_mask;
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uint32_t cpuperiod_sel_shift;
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uint32_t cpuperiod_max;
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uint32_t soc_clk_sel_mask;
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uint32_t soc_clk_sel_shift;
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uint32_t soc_clk_max;
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/* Function pointers for RTC-specific operations */
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void (*wdt_disable)(void);
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void (*wdt_enable)(void);
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} rtc_t;
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#ifdef __cplusplus
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}
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#endif

‎soc/include/peripherals/system.h‎

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/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0 OR MIT
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*/
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#pragma once
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#include <stdint.h>
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#include <stdbool.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* SYSTEM registers structure (older chips - more registers) */
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typedef struct {
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uint32_t base_reg;
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uint32_t cpu_per_conf_reg;
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uint32_t sysclk_conf_reg;
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uint32_t cpuperiod_sel_mask;
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uint32_t cpuperiod_sel_shift;
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uint32_t cpuperiod_max;
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uint32_t soc_clk_sel_mask;
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uint32_t soc_clk_sel_shift;
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uint32_t soc_clk_max;
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} system_registers_t;
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/* PCR registers structure (newer chips - fewer registers) */
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typedef struct {
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uint32_t base_reg;
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uint32_t sysclk_conf_reg;
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uint32_t soc_clk_sel_mask;
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uint32_t soc_clk_sel_shift;
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uint32_t soc_clk_max;
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} pcr_registers_t;
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/* Combined system control peripheral registers structure */
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typedef struct {
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const system_registers_t *system; /* For older chips, NULL for newer chips */
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const pcr_registers_t *pcr; /* For newer chips, NULL for older chips */
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/* Function pointers for system-specific operations */
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void (*set_cpu_freq_max)(void);
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void (*restore_cpu_freq)(void);
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void (*configure_clocks)(void);
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} system_t;
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#ifdef __cplusplus
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}
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#endif

‎soc/include/peripherals/uart.h‎

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/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0 OR MIT
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*/
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#pragma once
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* UART peripheral structure */
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typedef struct {
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uint32_t fifo_reg;
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uint32_t int_st_reg;
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uint32_t int_ena_reg;
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uint32_t int_clr_reg;
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uint32_t clkdiv_reg;
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uint32_t status_reg;
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uint32_t clkdiv_mask;
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uint32_t clkdiv_frag_s;
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uint32_t clkdiv_frag_v;
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uint32_t rxfifo_cnt_mask;
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uint32_t uart_inum;
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uint32_t uart_usb_otg_num;
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uint32_t uart_usb_jtag_serial_num;
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} uart_t;
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#ifdef __cplusplus
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}
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#endif

‎soc/include/peripherals/usb.h‎

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/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0 OR MIT
5+
*/
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#pragma once
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* USB peripheral structure */
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typedef struct {
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uint32_t usb_intr_map_reg; /* USB JTAG Serial interrupt mapping */
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uint32_t usb_otg_intr_map_reg; /* USB OTG interrupt mapping */
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uint32_t hp_sys_usbotg20_ctrl_reg; /* USB OTG control register */
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uint32_t usb_inum; /* USB interrupt number */
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uint32_t clic_ext_intr_num_offset; /* RISC-V CLIC interrupt offset */
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} usb_t;
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#ifdef __cplusplus
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}
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#endif

‎soc/include/soc.h‎

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/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0 OR MIT
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*/
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#pragma once
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#include "peripherals/uart.h"
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#include "peripherals/usb.h"
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#include "peripherals/rtc.h"
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#include "peripherals/system.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Essential SoC Capabilities for flasher stub */
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typedef struct {
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bool is_riscv; /* RISC-V architecture (affects interrupt handling) */
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bool use_max_cpu_freq; /* Can safely use maximum CPU frequency */
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bool config_efuse_spi; /* Can configure SPI flash through efuse */
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} soc_capabilities_t;
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/* Essential peripherals for flasher stub */
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typedef struct {
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const uart_t *uart; /* UART communication with host */
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const usb_t *usb; /* USB communication (JTAG Serial / OTG) */
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const rtc_t *rtc; /* Watchdog and power management */
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const system_t *system; /* Clock and system control */
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} soc_peripherals_t;
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/* Main SoC structure */
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typedef struct {
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const soc_capabilities_t *capabilities;
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const soc_peripherals_t *peripherals;
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uint8_t security_info_bytes;
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uint32_t rom_spiflash_legacy_addr;
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} soc_info_t;
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const soc_info_t* soc_get_info(void);
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/* Convenience accessors */
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static inline const soc_capabilities_t* soc_get_capabilities(void)
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{
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return soc_get_info()->capabilities;
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}
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static inline const soc_peripherals_t* soc_get_peripherals(void)
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{
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return soc_get_info()->peripherals;
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}
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#ifdef __cplusplus
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}
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#endif

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