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Dzarda7Dzarda7
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feat: Add initial chip structure
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18 files changed

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18 files changed

+807
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lines changed

‎CMakeLists.txt‎

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@@ -62,7 +62,8 @@ add_subdirectory(${CMAKE_SOURCE_DIR}/src)
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set(ESP_TARGET ${TARGET_CHIP} CACHE INTERNAL "Pass TARGET_CHIP as ESP_TARGET")
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add_subdirectory(${CMAKE_SOURCE_DIR}/esp-stub-lib)
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target_link_libraries(${TARGET_NAME} PRIVATE esp-stub-lib)
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add_subdirectory(${CMAKE_SOURCE_DIR}/soc)
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target_link_libraries(${TARGET_NAME} PRIVATE esp-stub-lib soc)
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add_custom_command(TARGET ${TARGET_NAME} POST_BUILD
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COMMAND ${CMAKE_SOURCE_DIR}/tools/elf2json.py ${CMAKE_BINARY_DIR}/${TARGET_NAME}${CMAKE_EXECUTABLE_SUFFIX_C} ${CMAKE_BINARY_DIR}/${TARGET_CHIP}.json

‎soc/CMakeLists.txt‎

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cmake_minimum_required(VERSION 3.28)
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add_library(soc STATIC)
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target_sources(soc PRIVATE
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common/soc.c
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common/watchdog_common.c
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)
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target_sources(soc PRIVATE targets/${TARGET_CHIP}.c)
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# Include directories
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target_include_directories(soc PUBLIC
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${CMAKE_CURRENT_SOURCE_DIR}/include
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)

‎soc/common/soc.c‎

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/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0 OR MIT
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*/
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#include <stddef.h>
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#include "soc.h"
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/*
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* Single SoC info structure - chip-specific file provides this
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* Chip selected at compile time
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*/
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extern const struct soc_info g_soc_info;
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const struct soc_info* soc_get_info(void)
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{
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return &g_soc_info;
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}

‎soc/common/watchdog_common.c‎

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/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0 OR MIT
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*/
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#include "soc.h"
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void disable_watchdogs(void)
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{
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const struct watchdog *watchdog = soc_get_peripherals()->watchdog;
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if (watchdog->wdt_disable) {
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watchdog->wdt_disable();
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}
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}
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void enable_watchdogs(void)
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{
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const struct watchdog *watchdog = soc_get_peripherals()->watchdog;
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if (watchdog->wdt_enable) {
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watchdog->wdt_enable();
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}
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}

‎soc/include/peripherals/usb_otg.h‎

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/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0 OR MIT
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*/
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#pragma once
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* USB OTG peripheral structure */
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struct usb_otg {
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uint32_t usb_otg_intr_map_reg; /* USB OTG interrupt mapping */
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uint32_t hp_sys_usbotg20_ctrl_reg; /* USB OTG control register */
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uint32_t usb_inum; /* USB interrupt number */
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uint32_t clic_ext_intr_num_offset; /* RISC-V CLIC interrupt offset */
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};
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#ifdef __cplusplus
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}
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#endif

‎soc/include/peripherals/watchdog.h‎

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/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0 OR MIT
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*/
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#pragma once
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Watchdog peripheral structure */
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struct watchdog {
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/* Register offsets */
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uint32_t option1_reg;
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uint32_t wdtconfig0_reg;
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uint32_t wdtwprotect_reg;
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uint32_t swd_conf_reg;
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uint32_t swd_wprotect_reg;
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uint32_t cpu_per_conf_reg;
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uint32_t sysclk_conf_reg;
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/* Chip-specific values */
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uint32_t swd_wkey;
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uint32_t wdt_wkey;
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uint32_t swd_auto_feed_en_bit;
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uint32_t force_download_boot_bit;
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uint32_t cpuperiod_sel_mask;
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uint32_t cpuperiod_sel_shift;
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uint32_t cpuperiod_max;
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uint32_t soc_clk_sel_mask;
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uint32_t soc_clk_sel_shift;
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uint32_t soc_clk_max;
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/* Function pointers for RTC-specific operations */
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void (*wdt_disable)(void);
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void (*wdt_enable)(void);
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};
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#ifdef __cplusplus
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}
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#endif

‎soc/include/soc.h‎

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/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0 OR MIT
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*/
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#pragma once
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#include <stdbool.h>
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#include <stdint.h>
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#include "peripherals/usb_otg.h"
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#include "peripherals/watchdog.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Essential SoC Capabilities for flasher stub */
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struct soc_capabilities {
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bool is_riscv; /* RISC-V architecture (affects interrupt handling) */
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};
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/* Essential peripherals for flasher stub */
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struct soc_peripherals {
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const struct usb_otg *usb_otg; /* USB-OTG communication */
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const struct watchdog *watchdog; /* Watchdog and power management */
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};
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/* Main SoC structure */
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struct soc_info {
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const struct soc_capabilities *capabilities;
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const struct soc_peripherals *peripherals;
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uint8_t security_info_bytes;
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};
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const struct soc_info* soc_get_info(void);
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/* Convenience accessors */
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static inline const struct soc_capabilities* soc_get_capabilities(void)
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{
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return soc_get_info()->capabilities;
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}
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static inline const struct soc_peripherals* soc_get_peripherals(void)
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{
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return soc_get_info()->peripherals;
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}
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#ifdef __cplusplus
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}
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#endif

‎soc/targets/esp32.c‎

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/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0 OR MIT
5+
*/
6+
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#include <stddef.h>
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#include "soc.h"
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/* ESP32 capabilities */
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static const struct soc_capabilities esp32_capabilities = {
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.is_riscv = false,
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};
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/* ESP32 USB-OTG peripheral */
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static const struct usb_otg esp32_usb_otg = {
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.usb_otg_intr_map_reg = 0,
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.hp_sys_usbotg20_ctrl_reg = 0,
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.usb_inum = 0,
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.clic_ext_intr_num_offset = 0,
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};
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/* ESP32 Watchdog peripheral */
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static const struct watchdog esp32_watchdog = {
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.option1_reg = 0,
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.wdtconfig0_reg = 0,
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.wdtwprotect_reg = 0,
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.swd_conf_reg = 0,
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.swd_wprotect_reg = 0,
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.cpu_per_conf_reg = 0,
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.sysclk_conf_reg = 0,
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.swd_wkey = 0,
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.wdt_wkey = 0,
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.swd_auto_feed_en_bit = 0,
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.force_download_boot_bit = 0,
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.cpuperiod_sel_mask = 0,
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.cpuperiod_sel_shift = 0,
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.cpuperiod_max = 0,
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.soc_clk_sel_mask = 0,
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.soc_clk_sel_shift = 0,
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.soc_clk_max = 0,
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.wdt_disable = NULL,
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.wdt_enable = NULL,
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};
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/* ESP32 peripherals structure */
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static const struct soc_peripherals esp32_peripherals = {
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.usb_otg = &esp32_usb_otg,
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.watchdog = &esp32_watchdog,
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};
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/* ESP32 SoC info */
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const struct soc_info g_soc_info = {
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.capabilities = &esp32_capabilities,
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.peripherals = &esp32_peripherals,
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.security_info_bytes = 0,
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};

‎soc/targets/esp32c2.c‎

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/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0 OR MIT
5+
*/
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#include <stddef.h>
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#include "soc.h"
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/* ESP32C2 capabilities */
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static const struct soc_capabilities esp32c2_capabilities = {
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.is_riscv = true,
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};
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/* ESP32C2 USB-OTG peripheral */
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static const struct usb_otg esp32c2_usb_otg = {
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.usb_otg_intr_map_reg = 0,
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.hp_sys_usbotg20_ctrl_reg = 0,
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.usb_inum = 0,
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.clic_ext_intr_num_offset = 0,
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};
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/* ESP32C2 Watchdog peripheral */
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static const struct watchdog esp32c2_watchdog = {
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.option1_reg = 0,
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.wdtconfig0_reg = 0,
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.wdtwprotect_reg = 0,
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.swd_conf_reg = 0,
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.swd_wprotect_reg = 0,
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.cpu_per_conf_reg = 0,
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.sysclk_conf_reg = 0,
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.swd_wkey = 0,
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.wdt_wkey = 0,
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.swd_auto_feed_en_bit = 0,
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.force_download_boot_bit = 0,
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.cpuperiod_sel_mask = 0,
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.cpuperiod_sel_shift = 0,
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.cpuperiod_max = 0,
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.soc_clk_sel_mask = 0,
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.soc_clk_sel_shift = 0,
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.soc_clk_max = 0,
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.wdt_disable = NULL,
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.wdt_enable = NULL,
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};
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/* ESP32C2 peripherals structure */
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static const struct soc_peripherals esp32c2_peripherals = {
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.usb_otg = &esp32c2_usb_otg,
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.watchdog = &esp32c2_watchdog,
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};
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/* ESP32C2 SoC info */
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const struct soc_info g_soc_info = {
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.capabilities = &esp32c2_capabilities,
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.peripherals = &esp32c2_peripherals,
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.security_info_bytes = 0,
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};

‎soc/targets/esp32c3.c‎

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/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0 OR MIT
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*/
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#include <stddef.h>
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#include "soc.h"
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/* ESP32C3 capabilities */
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static const struct soc_capabilities esp32c3_capabilities = {
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.is_riscv = true,
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};
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/* ESP32C3 USB-OTG peripheral */
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static const struct usb_otg esp32c3_usb_otg = {
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.usb_otg_intr_map_reg = 0,
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.hp_sys_usbotg20_ctrl_reg = 0,
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.usb_inum = 0,
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.clic_ext_intr_num_offset = 0,
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};
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/* ESP32C3 Watchdog peripheral */
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static const struct watchdog esp32c3_watchdog = {
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.option1_reg = 0,
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.wdtconfig0_reg = 0,
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.wdtwprotect_reg = 0,
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.swd_conf_reg = 0,
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.swd_wprotect_reg = 0,
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.cpu_per_conf_reg = 0,
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.sysclk_conf_reg = 0,
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.swd_wkey = 0,
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.wdt_wkey = 0,
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.swd_auto_feed_en_bit = 0,
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.force_download_boot_bit = 0,
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.cpuperiod_sel_mask = 0,
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.cpuperiod_sel_shift = 0,
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.cpuperiod_max = 0,
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.soc_clk_sel_mask = 0,
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.soc_clk_sel_shift = 0,
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.soc_clk_max = 0,
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.wdt_disable = NULL,
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.wdt_enable = NULL,
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};
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/* ESP32C3 peripherals structure */
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static const struct soc_peripherals esp32c3_peripherals = {
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.usb_otg = &esp32c3_usb_otg,
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.watchdog = &esp32c3_watchdog,
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};
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/* ESP32C3 SoC info */
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const struct soc_info g_soc_info = {
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.capabilities = &esp32c3_capabilities,
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.peripherals = &esp32c3_peripherals,
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.security_info_bytes = 0,
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};

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