ESP32S31 rgb_panel 运行错误 (IDFGH-17836)

[hyzgit]

Answers checklist.

• I have read the documentation ESP-IDF Programming Guide and the issue is not addressed there.
• I have updated my IDF branch (master or release) to the latest version and checked that the issue is present there.
• I have searched the issue tracker for a similar issue and not found a similar issue.

IDF version.

master a602e67

Espressif SoC revision.

ESP32-S31

Operating System used.

Windows

How did you build your project?

Command line with Make

If you are using Windows, please specify command line type.

None

Development Kit.

ESP32-S31-Function-CoreBoard-1

Power Supply used.

USB

What is the expected behavior?

The system is operating normally without any abnormal errors. It will restart.

What is the actual behavior?

I (27) boot: ESP-IDF a602e67 2nd stage bootloader
I (27) boot: compile time Jun 19 2026 21:32:11
I (27) boot: Multicore bootloader
I (29) boot: chip revision: v0.0
I (29) boot: efuse block revision: v0.0
I (29) qio_mode: Enabling default flash chip QIO
I (29) boot.esp32s31: SPI Speed : 80MHz
I (30) boot.esp32s31: SPI Mode : QIO
I (30) boot.esp32s31: SPI Flash Size : 16MB
I (30) boot: Enabling RNG early entropy source...
I (31) boot: Partition Table:
I (31) boot: ## Label Usage Type ST Offset Length
I (31) boot: 0 nvs WiFi data 01 02 00009000 00006000
I (32) boot: 1 phy_init RF data 01 01 0000f000 00001000
I (32) boot: 2 factory factory app 00 00 00010000 00100000
I (34) boot: End of partition table
I (34) esp_image: segment 0: paddr=00010020 vaddr=50060020 size=0e224h ( 57892) map
I (43) esp_image: segment 1: paddr=0001e24c vaddr=2f000000 size=01dcch ( 7628) load
I (46) esp_image: segment 2: paddr=00020020 vaddr=50000020 size=5cee0h (380640) map
I (96) esp_image: segment 3: paddr=0007cf08 vaddr=2f001dcc size=0df80h ( 57216) load
I (106) esp_image: segment 4: paddr=0008ae90 vaddr=2f00fd80 size=03f78h ( 16248) load
I (114) boot: Loaded app from partition at offset 0x10000
I (114) boot: Disabling RNG early entropy source...
I (116) oct_psram: ECC is enabled
I (116) oct_psram: vendor id : 0x1a (UNKNOWN)
I (117) oct_psram: Latency : 0x01 (Fixed)
I (117) oct_psram: DriveStr. : 0x00 (25 Ohm)
I (117) oct_psram: dev id : 0x00 (generation 1)
I (118) oct_psram: density : 0x05 (128 Mbit)
I (118) oct_psram: good-die : 0x06 (Pass)
I (118) oct_psram: SRF : 0x02 (Slow Refresh)
I (119) oct_psram: BurstType : 0x00 ( Wrap)
I (119) oct_psram: BurstLen : 0x03 (2048 Byte)
I (119) oct_psram: BitMode : 0x00 (X8 Mode)
I (120) oct_psram: Readlatency : 0x04 (14 cycles@Fixed)
I (120) oct_psram: DriveStrength: 0x00 (1/1)
I (120) MSPI Timing: Enter psram timing tuning
I esp_psram: Found 16MB PSRAM device
I esp_psram: Speed: 200MHz
I (279) mmu_psram: .rodata xip on psram
I (300) mmu_psram: .text xip on psram
I (300) cpu_start: Multicore app
I (632) esp_psram: SPI SRAM memory test OK
I (640) cpu_start: Pro cpu start user code
I (640) cpu_start: cpu freq: 320000000 Hz
I (640) app_init: Application information:
I (641) app_init: Project name: rgb_panel
I (641) app_init: App version: 1
I (641) app_init: Compile time: Jun 19 2026 21:32:10
I (641) app_init: ELF file SHA256: dfc6415eb...
I (641) app_init: ESP-IDF: a602e67
I (642) efuse_init: Min chip rev: v0.0
I (642) efuse_init: Max chip rev: v0.99
I (642) efuse_init: Chip rev: v0.0
I (642) heap_init: Initializing. RAM available for dynamic allocation:
I (642) heap_init: At 2F025880 len 00055730 (341 KiB): RAM
I (643) heap_init: At 2F07AFB0 len 000041C0 (16 KiB): RAM
I (643) heap_init: At 2E000000 len 00007FE8 (31 KiB): RTCRAM
I (643) esp_psram: Adding pool of 13888K of PSRAM memory to heap allocator
I (644) esp_psram: Adding pool of 12K of PSRAM memory gap generated due to end address alignment of irom to the heap allocator
I (644) esp_psram: Adding pool of 7K of PSRAM memory gap generated due to end address alignment of drom to the heap allocator
I (645) spi_flash: detected chip: generic
I (645) spi_flash: flash io: qio
I (645) sleep_gpio: Configure to isolate all GPIO pins in sleep state
I (646) sleep_gpio: Enable automatic switching of GPIO sleep configuration
I (646) main_task: Started on CPU0
I (646) esp_psram: Reserving pool of 32K of internal memory for DMA/internal allocations
I (646) main_task: Calling app_main()
I (646) example: Turn off LCD backlight
I (646) example: Install RGB LCD panel driver
I (676) example: Initialize RGB LCD panel
IE psram_mspi: MSPI PSRAM error, intr_events: 0x98
E psram_mspi: psram read address invalid or misaligned

abort() was called at PC 0x50008dc1 on core 0
--- 0x50008dc1: mspi_psram_isr_handler_wrapper at C:/esp/master/esp-idf/components/esp_psram/system_layer/esp_psram_mspi.c:78
--- Stack dump detected
Core 0 register dump:
MEPC : 0x2f00b040 RA : 0x2f00aa6c SP : 0x2f0146e0 GP : 0x2f010588
--- 0x2f00b040: panic_abort at C:/esp/master/esp-idf/components/esp_system/panic.c:496
--- 0x2f00aa6c: esp_vApplicationTickHook at C:/esp/master/esp-idf/components/esp_system/freertos_hooks.c:31
TP : 0x2f029110 T0 : 0x37363534 T1 : 0x7271706f T2 : 0x33323130
S0/FP : 0x00000004 S1 : 0x2f014744 A0 : 0x2f01470c A1 : 0x2f014742
A2 : 0x00000000 A3 : 0x00000000 A4 : 0x00000001 A5 : 0x2f025000
A6 : 0x2f0146c9 A7 : 0x76757473 S2 : 0x00001881 S3 : 0x2f014f20
S4 : 0x00000000 S5 : 0x00000000 S6 : 0x00000007 S7 : 0x00000073
S8 : 0x0000000f S9 : 0x0000001f S10 : 0x00000000 S11 : 0xffffffff
T3 : 0x6e6d6c6b T4 : 0x6a696867 T5 : 0x66656463 T6 : 0x62613938
MSTATUS : 0x00001881 MTVEC : 0x2f000003 MCAUSE : 0x00000002 MTVAL : 0x00000000
--- 0x2f000003: _vector_table at ??:?
MHARTID : 0x00000000

--- To exit from IDF monitor please use "Ctrl+]". Alternatively, you can use Ctrl+T Ctrl+X to exit.

ELF file SHA256: dfc6415eb

Rebooting...
ESP-ROM:esp32s31-20251218
Build:Dec 18 2025
rst:0xc (SW_CPU_RESET),boot:0x58 (SPI_FAST_FLASH_BOOT)
Core0 Saved PC:0x2f00541e
--- 0x2f00541e: cpu_utility_ll_reset_cpu at C:/esp/master/esp-idf/components/hal/esp32s31/include/hal/cpu_utility_ll.h:24
--- (inlined by) esp_cpu_reset at C:/esp/master/esp-idf/components/esp_hw_support/cpu.c:49
Core1 Saved PC:0x2f005566
--- 0x2f005566: esp_cpu_wait_for_intr at C:/esp/master/esp-idf/components/esp_hw_support/cpu.c:57
SPI mode:DIO, clock div:1
load:0x2f0740c0,len:0x188c
load:0x2f06a2b0,len:0xd4c
--- 0x2f06a2b0: esp_bootloader_get_description at C:/esp/master/esp-idf/components/esp_bootloader_format/esp_bootloader_desc.c:40
load:0x2f06cfb0,len:0x347c
--- 0x2f06cfb0: is_xmc_chip_strict at C:/esp/master/esp-idf/components/bootloader_support/bootloader_flash/src/bootloader_flash.c:915
entry 0x2f06a2ba
--- 0x2f06a2ba: call_start_cpu0 at C:/esp/master/esp-idf/components/bootloader/subproject/main/bootloader_start.c:27
I (27) boot: ESP-IDF a602e67 2nd stage bootloader
I (27) boot: compile time Jun 19 2026 21:32:11
I (27) boot: Multicore bootloader
I (29) boot: chip revision: v0.0
I (29) boot: efuse block revision: v0.0
I (29) qio_mode: Enabling default flash chip QIO
I (29) boot.esp32s31: SPI Speed : 80MHz
I (30) boot.esp32s31: SPI Mode : QIO
I (30) boot.esp32s31: SPI Flash Size : 16MB
I (30) boot: Enabling RNG early entropy source...
I (31) boot: Partition Table:
I (31) boot: ## Label Usage Type ST Offset Length
I (31) boot: 0 nvs WiFi data 01 02 00009000 00006000
I (32) boot: 1 phy_init RF data 01 01 0000f000 00001000
I (33) boot: 2 factory factory app 00 00 00010000 00100000
I (34) boot: End of partition table
I (34) esp_image: segment 0: paddr=00010020 vaddr=50060020 size=0e224h ( 57892) map
I (44) esp_image: segment 1: paddr=0001e24c vaddr=2f000000 size=01dcch ( 7628) load
I (46) esp_image: segment 2: paddr=00020020 vaddr=50000020 size=5cee0h (380640) map
I (96) esp_image: segment 3: paddr=0007cf08 vaddr=2f001dcc size=0df80h ( 57216) load
I (106) esp_image: segment 4: paddr=0008ae90 vaddr=2f00fd80 size=03f78h ( 16248) load
I (114) boot: Loaded app from partition at offset 0x10000
I (114) boot: Disabling RNG early entropy source...
I (116) oct_psram: ECC is enabled
I (117) oct_psram: vendor id : 0x1a (UNKNOWN)
I (117) oct_psram: Latency : 0x01 (Fixed)
I (117) oct_psram: DriveStr. : 0x00 (25 Ohm)
I (118) oct_psram: dev id : 0x00 (generation 1)
I (118) oct_psram: density : 0x05 (128 Mbit)
I (118) oct_psram: good-die : 0x06 (Pass)
I (119) oct_psram: SRF : 0x02 (Slow Refresh)
I (119) oct_psram: BurstType : 0x00 ( Wrap)
I (119) oct_psram: BurstLen : 0x03 (2048 Byte)
I (120) oct_psram: BitMode : 0x00 (X8 Mode)
I (120) oct_psram: Readlatency : 0x04 (14 cycles@Fixed)
I (120) oct_psram: DriveStrength: 0x00 (1/1)
I (121) MSPI Timing: Enter psram timing tuning
I esp_psram: Found 16MB PSRAM device
I esp_psram: Speed: 200MHz
I (279) mmu_psram: .rodata xip on psram
I (300) mmu_psram: .text xip on psram
I (301) cpu_start: Multicore app
I (632) esp_psram: SPI SRAM memory test OK
I (640) cpu_start: Pro cpu start user code
I (640) cpu_start: cpu freq: 320000000 Hz
I (641) app_init: Application information:
I (641) app_init: Project name: rgb_panel
I (641) app_init: App version: 1
I (641) app_init: Compile time: Jun 19 2026 21:32:10
I (641) app_init: ELF file SHA256: dfc6415eb...
I (642) app_init: ESP-IDF: a602e67
I (642) efuse_init: Min chip rev: v0.0
I (642) efuse_init: Max chip rev: v0.99
I (642) efuse_init: Chip rev: v0.0
I (642) heap_init: Initializing. RAM available for dynamic allocation:
I (643) heap_init: At 2F025880 len 00055730 (341 KiB): RAM
I (643) heap_init: At 2F07AFB0 len 000041C0 (16 KiB): RAM
I (643) heap_init: At 2E000000 len 00007FE8 (31 KiB): RTCRAM
I (644) esp_psram: Adding pool of 13888K of PSRAM memory to heap allocator
I (644) esp_psram: Adding pool of 12K of PSRAM memory gap generated due to end address alignment of irom to the heap allocator
I (644) esp_psram: Adding pool of 7K of PSRAM memory gap generated due to end address alignment of drom to the heap allocator
I (645) spi_flash: detected chip: generic
I (645) spi_flash: flash io: qio
什么问题

Steps to reproduce.

1. Step
2. Step
3. Step
   ...

Debug Logs.

Diagnostic report archive.

No response

More Information.

No response

[Kainarx]

Hi, thank you for your report.
Did you run examples/peripherals/lcd/rgb_panel directly?
Have you made any modifications to the relevant code? If so, could you provide the code that reproduced the issue?

[hyzgit]

Hi, thank you for your report.嗨，感谢您的报告。 Did you run examples/peripherals/lcd/rgb_panel directly?你是直接运行了 examples/peripherals/lcd/rgb_panel 吗？ Have you made any modifications to the relevant code? If so, could you provide the code that reproduced the issue?您是否对相关代码进行了任何修改？如果进行了修改，请提供能够重现该问题的代码。

Yes, the GPIO definition for RGB24 was modified and the PSRAM was enabled.

this is sdkconfig file.

https://limewire.com/d/l8mRr#Iu81sybXiT

[hyzgit]

Hi, thank you for your report. Did you run examples/peripherals/lcd/rgb_panel directly? Have you made any modifications to the relevant code? If so, could you provide the code that reproduced the issue?

The project was also uploaded together in a package.

https://limewire.com/d/l8mRr#Iu81sybXiT

[Kainarx]

I took a look at your sdkconfig. You have used GPIOs reserved for SPI0/1. Regarding the selection of GPIOs, please refer to the S31 development documentation.

[hyzgit]

I took a look at your sdkconfig. You have used GPIOs reserved for SPI0/1. Regarding the selection of GPIOs, please refer to the S31 development documentation.

RGB LCD GPIO assignment

CONFIG_EXAMPLE_LCD_VSYNC_GPIO=58
CONFIG_EXAMPLE_LCD_HSYNC_GPIO=59
CONFIG_EXAMPLE_LCD_DE_GPIO=60
CONFIG_EXAMPLE_LCD_PCLK_GPIO=2
CONFIG_EXAMPLE_LCD_DATA0_GPIO=0
CONFIG_EXAMPLE_LCD_DATA1_GPIO=3
CONFIG_EXAMPLE_LCD_DATA2_GPIO=49
CONFIG_EXAMPLE_LCD_DATA3_GPIO=1
CONFIG_EXAMPLE_LCD_DATA4_GPIO=47
CONFIG_EXAMPLE_LCD_DATA5_GPIO=48
CONFIG_EXAMPLE_LCD_DATA6_GPIO=45
CONFIG_EXAMPLE_LCD_DATA7_GPIO=46
CONFIG_EXAMPLE_LCD_DATA8_GPIO=43
CONFIG_EXAMPLE_LCD_DATA9_GPIO=44
CONFIG_EXAMPLE_LCD_DATA10_GPIO=40
CONFIG_EXAMPLE_LCD_DATA11_GPIO=42
CONFIG_EXAMPLE_LCD_DATA12_GPIO=39
CONFIG_EXAMPLE_LCD_DATA13_GPIO=38
CONFIG_EXAMPLE_LCD_DATA14_GPIO=37
CONFIG_EXAMPLE_LCD_DATA15_GPIO=36
CONFIG_EXAMPLE_LCD_DATA16_GPIO=35
CONFIG_EXAMPLE_LCD_DATA17_GPIO=20
CONFIG_EXAMPLE_LCD_DATA18_GPIO=21
CONFIG_EXAMPLE_LCD_DATA19_GPIO=22
CONFIG_EXAMPLE_LCD_DATA20_GPIO=23
CONFIG_EXAMPLE_LCD_DATA21_GPIO=24
CONFIG_EXAMPLE_LCD_DATA22_GPIO=25
CONFIG_EXAMPLE_LCD_DATA23_GPIO=4

I am using the ESP32-S31-Function-Coreboard-1 development board, and all these GPIOs are connected via the J2 interface. I have checked and confirmed that none of them use the SPI0/1 interfaces.

1. SPI0/1 Flash Pin Allocation

Pin Name | GPIO | Flash Signal Pin | GPIO Matrix Capability | Direction | Functional Description

SPI0_CS | GPIO26 | FLASH_CS | Not Supported | Input/Output | SPI Chip Select signal (CS)
SPI0_Q | GPIO27 | FLASH_Q | Not Supported | Input/Output | SPI Data line 1 (MISO / D1)
SPI0_WP | GPIO28 | FLASH_WP | Not Supported | Input/Output | SPI Write Protect signal (WP / D2)
SPI0_HD | GPIO30 | FLASH_HOLD | Not Supported | Input/Output | SPI Hold signal (HOLD / D3)
SPI0_CLK | GPIO31 | CLK/FLASH_CLK | Not Supported | Output | SPI Serial Clock line (CLK)
SPI0_D | GPIO32 | FLASH_D | Not Supported | Input/Output | SPI Data line 0 (MOSI / D0)

[Kainarx]

OK, my mistake, I misread that. It’s strange—I don’t have any issues when I use your sdkconfig. Do you encounter problems when using the default sdkconfig and setting the UART as the console?

[hyzgit]

OK, my mistake, I misread that. It’s strange—I don’t have any issues when I use your sdkconfig. Do you encounter problems when using the default sdkconfig and setting the UART as the console?

I have also uploaded the project. Can it run normally when using my project?

[Kainarx]

0001-fix-rgb_lcd-fix-frame-buffer-alignment.patch
Can you try this patch？

[hyzgit]

0001-fix-rgb_lcd-fix-frame-buffer-alignment.patch Can you try this patch？

Thank you. I'll give it a try.