diff --git a/CMakeLists.txt b/CMakeLists.txt index 598f7ca..931605d 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -23,6 +23,7 @@ set(srcs src/security.c src/uart.c src/usb_serial_jtag.c + src/clock.c ) if(STUB_LOG_ENABLED IN_LIST STUB_COMPILE_DEFS) diff --git a/example/stub_main.c b/example/stub_main.c index 2be4ad7..455811d 100644 --- a/example/stub_main.c +++ b/example/stub_main.c @@ -9,6 +9,7 @@ #include #include +#include #include #include #include @@ -63,6 +64,11 @@ static void example_security(void) } } +static void __attribute__((unused)) test_clock_init(void) +{ + stub_lib_clock_init(); +} + static int __attribute__((unused)) handle_test_uart(void) { void *uart_rx_interrupt_handler = NULL; diff --git a/include/esp-stub-lib/clock.h b/include/esp-stub-lib/clock.h new file mode 100644 index 0000000..4fc9be0 --- /dev/null +++ b/include/esp-stub-lib/clock.h @@ -0,0 +1,22 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 OR MIT + */ + +#pragma once + +#include + +#ifdef __cplusplus +extern "C" { +#endif // __cplusplus + +/** + * @brief Initialize clock to higher CPU frequency if possible + */ +void stub_lib_clock_init(void); + +#ifdef __cplusplus +} +#endif // __cplusplus diff --git a/include/esp-stub-lib/soc_utils.h b/include/esp-stub-lib/soc_utils.h index 66a74ec..f43f42d 100644 --- a/include/esp-stub-lib/soc_utils.h +++ b/include/esp-stub-lib/soc_utils.h @@ -6,6 +6,8 @@ #pragma once +#include + #define ETS_UNCACHED_ADDR(addr) (addr) #define ETS_CACHED_ADDR(addr) (addr) @@ -28,11 +30,11 @@ } while(0) #define REG_CLR_BIT(_r, _b) do { \ - REG_WRITE(_r, REG_READ(_r) & (~(_b))); \ + REG_WRITE(_r, REG_READ(_r) & (~(volatile uint32_t)(_b))); \ } while(0) #define REG_SET_BITS(_r, _b, _m) do { \ - REG_WRITE(_r, (REG_READ(_r) & ~(_m)) | ((_b) & (_m))); \ + REG_WRITE(_r, (REG_READ(_r) & ~(volatile uint32_t)(_m)) | ((volatile uint32_t)(_b) & (volatile uint32_t)(_m))); \ } while(0) // Field manipulation macros @@ -41,7 +43,7 @@ }) #define REG_SET_FIELD(_r, _f, _v) do { \ - REG_WRITE(_r, (REG_READ(_r) & ~((_f##_V) << (_f##_S))) | (((_v) & (_f##_V)) << (_f##_S))); \ + REG_WRITE(_r, (REG_READ(_r) & ~((volatile uint32_t)((_f##_V) << (_f##_S)))) | (((volatile uint32_t)(_v) & (_f##_V)) << (_f##_S))); \ } while(0) // Value field manipulation macros @@ -49,9 +51,9 @@ #define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f)) >> (_f##_S)) -#define VALUE_SET_FIELD(_r, _f, _v) ((_r) = ((_r) & ~((_f) << (_f##_S))) | ((_v) << (_f##_S))) +#define VALUE_SET_FIELD(_r, _f, _v) ((_r) = ((_r) & ~((volatile uint32_t)((_f) << (_f##_S)))) | ((volatile uint32_t)(_v) << (_f##_S))) -#define VALUE_SET_FIELD2(_r, _f, _v) ((_r) = ((_r) & ~(_f)) | ((_v) << (_f##_S))) +#define VALUE_SET_FIELD2(_r, _f, _v) ((_r) = ((_r) & ~(volatile uint32_t)(_f)) | ((volatile uint32_t)(_v) << (_f##_S))) // Field to value conversion macros #define FIELD_TO_VALUE(_f, _v) (((_v) & (_f)) << _f##_S) @@ -64,7 +66,7 @@ #define WRITE_PERI_REG(addr, val) REG_WRITE(ETS_UNCACHED_ADDR(addr), (uint32_t)(val)) #define CLEAR_PERI_REG_MASK(reg, mask) do { \ - WRITE_PERI_REG(reg, READ_PERI_REG(reg) & (~(mask))); \ + WRITE_PERI_REG(reg, READ_PERI_REG(reg) & (~(volatile uint32_t)(mask))); \ } while(0) #define SET_PERI_REG_MASK(reg, mask) do { \ @@ -80,7 +82,7 @@ }) #define SET_PERI_REG_BITS(reg, bit_map, value, shift) do { \ - WRITE_PERI_REG(reg, (READ_PERI_REG(reg) & (~((bit_map) << (shift)))) | (((value) & (bit_map)) << (shift))); \ + WRITE_PERI_REG(reg, (READ_PERI_REG(reg) & (~((volatile uint32_t)(bit_map) << (shift)))) | (((volatile uint32_t)(value) & (volatile uint32_t)(bit_map)) << (shift))); \ } while(0) #define GET_PERI_REG_BITS2(reg, mask, shift) ({ \ diff --git a/src/clock.c b/src/clock.c new file mode 100644 index 0000000..4ba6f7c --- /dev/null +++ b/src/clock.c @@ -0,0 +1,12 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 OR MIT + */ + +#include + +void stub_lib_clock_init(void) +{ + stub_target_clock_init(); +} diff --git a/src/target/base/include/target/clock.h b/src/target/base/include/target/clock.h new file mode 100644 index 0000000..36c2d07 --- /dev/null +++ b/src/target/base/include/target/clock.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 OR MIT + */ + +#pragma once + +#include +#include + +/** + * @brief Initialize clock + */ +void stub_target_clock_init(void); + +/** + * @brief Get CPU frequency + * + * @return CPU frequency in Hz + */ +uint32_t stub_target_get_cpu_freq(void); + +/** + * @brief Get APB frequency + * + * @return APB frequency in Hz + */ +uint32_t stub_target_get_apb_freq(void); diff --git a/src/target/common/src/uart.c b/src/target/common/src/uart.c index 5611d4f..21955cd 100644 --- a/src/target/common/src/uart.c +++ b/src/target/common/src/uart.c @@ -7,14 +7,14 @@ #include #include #include +#include #include -extern void esp_rom_set_cpu_ticks_per_us(uint32_t ticks_per_us); -extern uint32_t esp_rom_get_cpu_freq(void); extern void esp_rom_uart_set_as_console(uint8_t uart_no); extern void esp_rom_uart_tx_wait_idle(uint8_t uart_num); extern void esp_rom_uart_div_modify(uint8_t uart_no, uint32_t divisor); extern void esp_rom_uart_flush_tx(uint8_t uart_no); +extern uint32_t esp_rom_get_xtal_freq(void); void __attribute__((weak)) stub_target_uart_wait_idle(uint8_t uart_num) { @@ -23,20 +23,23 @@ void __attribute__((weak)) stub_target_uart_wait_idle(uint8_t uart_num) void __attribute__((weak)) stub_target_uart_init(uint8_t uart_num) { - esp_rom_set_cpu_ticks_per_us(esp_rom_get_cpu_freq() / 1000000); stub_target_rom_uart_attach(NULL); - uint32_t clock = esp_rom_get_cpu_freq(); + uint32_t clock = esp_rom_get_xtal_freq(); stub_target_rom_uart_init(uart_num, clock); esp_rom_uart_set_as_console(uart_num); } void __attribute__((weak)) stub_target_uart_rominit_set_baudrate(uint8_t uart_num, uint32_t baudrate) { - uint32_t clock = esp_rom_get_cpu_freq() << 4; - uint32_t divisor = clock / baudrate; + extern void stub_lib_delay_us(uint32_t us); + + stub_lib_delay_us(5 * 1000); + + uint32_t clk_div = (esp_rom_get_xtal_freq() << 4) / baudrate; stub_target_uart_wait_idle(uart_num); - esp_rom_uart_div_modify(uart_num, divisor); - // TODO: Consider decimal part + esp_rom_uart_div_modify(uart_num, clk_div); + + stub_lib_delay_us(5 * 1000); } void __attribute__((weak)) stub_target_uart_tx_flush(uint8_t uart_no) diff --git a/src/target/esp32/CMakeLists.txt b/src/target/esp32/CMakeLists.txt index 9a1055a..3386c00 100644 --- a/src/target/esp32/CMakeLists.txt +++ b/src/target/esp32/CMakeLists.txt @@ -2,6 +2,7 @@ set(srcs src/trax.c src/uart.c src/security.c + src/clock.c ) add_library(${ESP_TARGET_LIB} STATIC ${srcs}) diff --git a/src/target/esp32/include/soc/rtc_cntl_reg.h b/src/target/esp32/include/soc/rtc_cntl_reg.h new file mode 100644 index 0000000..01d4bff --- /dev/null +++ b/src/target/esp32/include/soc/rtc_cntl_reg.h @@ -0,0 +1,2047 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 OR MIT + */ +#pragma once + +#include +#define RTC_CNTL_OPTIONS0_REG (DR_REG_RTCCNTL_BASE + 0x0) +/* RTC_CNTL_SW_SYS_RST : WO ;bitpos:[31] ;default: 1'd0 ; */ +/*description: SW system reset*/ +#define RTC_CNTL_SW_SYS_RST (BIT(31)) +#define RTC_CNTL_SW_SYS_RST_M (BIT(31)) +#define RTC_CNTL_SW_SYS_RST_V 0x1 +#define RTC_CNTL_SW_SYS_RST_S 31 +/* RTC_CNTL_DG_WRAP_FORCE_NORST : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: digital core force no reset in deep sleep*/ +#define RTC_CNTL_DG_WRAP_FORCE_NORST (BIT(30)) +#define RTC_CNTL_DG_WRAP_FORCE_NORST_M (BIT(30)) +#define RTC_CNTL_DG_WRAP_FORCE_NORST_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_NORST_S 30 +/* RTC_CNTL_DG_WRAP_FORCE_RST : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: digital wrap force reset in deep sleep*/ +#define RTC_CNTL_DG_WRAP_FORCE_RST (BIT(29)) +#define RTC_CNTL_DG_WRAP_FORCE_RST_M (BIT(29)) +#define RTC_CNTL_DG_WRAP_FORCE_RST_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_RST_S 29 +/* RTC_CNTL_ANALOG_FORCE_NOISO : R/W ;bitpos:[28] ;default: 1'd1 ; */ +/*description: */ +#define RTC_CNTL_ANALOG_FORCE_NOISO (BIT(28)) +#define RTC_CNTL_ANALOG_FORCE_NOISO_M (BIT(28)) +#define RTC_CNTL_ANALOG_FORCE_NOISO_V 0x1 +#define RTC_CNTL_ANALOG_FORCE_NOISO_S 28 +/* RTC_CNTL_PLL_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */ +/*description: */ +#define RTC_CNTL_PLL_FORCE_NOISO (BIT(27)) +#define RTC_CNTL_PLL_FORCE_NOISO_M (BIT(27)) +#define RTC_CNTL_PLL_FORCE_NOISO_V 0x1 +#define RTC_CNTL_PLL_FORCE_NOISO_S 27 +/* RTC_CNTL_XTL_FORCE_NOISO : R/W ;bitpos:[26] ;default: 1'd1 ; */ +/*description: */ +#define RTC_CNTL_XTL_FORCE_NOISO (BIT(26)) +#define RTC_CNTL_XTL_FORCE_NOISO_M (BIT(26)) +#define RTC_CNTL_XTL_FORCE_NOISO_V 0x1 +#define RTC_CNTL_XTL_FORCE_NOISO_S 26 +/* RTC_CNTL_ANALOG_FORCE_ISO : R/W ;bitpos:[25] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_ANALOG_FORCE_ISO (BIT(25)) +#define RTC_CNTL_ANALOG_FORCE_ISO_M (BIT(25)) +#define RTC_CNTL_ANALOG_FORCE_ISO_V 0x1 +#define RTC_CNTL_ANALOG_FORCE_ISO_S 25 +/* RTC_CNTL_PLL_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_PLL_FORCE_ISO (BIT(24)) +#define RTC_CNTL_PLL_FORCE_ISO_M (BIT(24)) +#define RTC_CNTL_PLL_FORCE_ISO_V 0x1 +#define RTC_CNTL_PLL_FORCE_ISO_S 24 +/* RTC_CNTL_XTL_FORCE_ISO : R/W ;bitpos:[23] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_XTL_FORCE_ISO (BIT(23)) +#define RTC_CNTL_XTL_FORCE_ISO_M (BIT(23)) +#define RTC_CNTL_XTL_FORCE_ISO_V 0x1 +#define RTC_CNTL_XTL_FORCE_ISO_S 23 +/* RTC_CNTL_BIAS_CORE_FORCE_PU : R/W ;bitpos:[22] ;default: 1'd1 ; */ +/*description: BIAS_CORE force power up*/ +#define RTC_CNTL_BIAS_CORE_FORCE_PU (BIT(22)) +#define RTC_CNTL_BIAS_CORE_FORCE_PU_M (BIT(22)) +#define RTC_CNTL_BIAS_CORE_FORCE_PU_V 0x1 +#define RTC_CNTL_BIAS_CORE_FORCE_PU_S 22 +/* RTC_CNTL_BIAS_CORE_FORCE_PD : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: BIAS_CORE force power down*/ +#define RTC_CNTL_BIAS_CORE_FORCE_PD (BIT(21)) +#define RTC_CNTL_BIAS_CORE_FORCE_PD_M (BIT(21)) +#define RTC_CNTL_BIAS_CORE_FORCE_PD_V 0x1 +#define RTC_CNTL_BIAS_CORE_FORCE_PD_S 21 +/* RTC_CNTL_BIAS_CORE_FOLW_8M : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: BIAS_CORE follow CK8M*/ +#define RTC_CNTL_BIAS_CORE_FOLW_8M (BIT(20)) +#define RTC_CNTL_BIAS_CORE_FOLW_8M_M (BIT(20)) +#define RTC_CNTL_BIAS_CORE_FOLW_8M_V 0x1 +#define RTC_CNTL_BIAS_CORE_FOLW_8M_S 20 +/* RTC_CNTL_BIAS_I2C_FORCE_PU : R/W ;bitpos:[19] ;default: 1'd1 ; */ +/*description: BIAS_I2C force power up*/ +#define RTC_CNTL_BIAS_I2C_FORCE_PU (BIT(19)) +#define RTC_CNTL_BIAS_I2C_FORCE_PU_M (BIT(19)) +#define RTC_CNTL_BIAS_I2C_FORCE_PU_V 0x1 +#define RTC_CNTL_BIAS_I2C_FORCE_PU_S 19 +/* RTC_CNTL_BIAS_I2C_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: BIAS_I2C force power down*/ +#define RTC_CNTL_BIAS_I2C_FORCE_PD (BIT(18)) +#define RTC_CNTL_BIAS_I2C_FORCE_PD_M (BIT(18)) +#define RTC_CNTL_BIAS_I2C_FORCE_PD_V 0x1 +#define RTC_CNTL_BIAS_I2C_FORCE_PD_S 18 +/* RTC_CNTL_BIAS_I2C_FOLW_8M : R/W ;bitpos:[17] ;default: 1'd0 ; */ +/*description: BIAS_I2C follow CK8M*/ +#define RTC_CNTL_BIAS_I2C_FOLW_8M (BIT(17)) +#define RTC_CNTL_BIAS_I2C_FOLW_8M_M (BIT(17)) +#define RTC_CNTL_BIAS_I2C_FOLW_8M_V 0x1 +#define RTC_CNTL_BIAS_I2C_FOLW_8M_S 17 +/* RTC_CNTL_BIAS_FORCE_NOSLEEP : R/W ;bitpos:[16] ;default: 1'd1 ; */ +/*description: BIAS_SLEEP force no sleep*/ +#define RTC_CNTL_BIAS_FORCE_NOSLEEP (BIT(16)) +#define RTC_CNTL_BIAS_FORCE_NOSLEEP_M (BIT(16)) +#define RTC_CNTL_BIAS_FORCE_NOSLEEP_V 0x1 +#define RTC_CNTL_BIAS_FORCE_NOSLEEP_S 16 +/* RTC_CNTL_BIAS_FORCE_SLEEP : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: BIAS_SLEEP force sleep*/ +#define RTC_CNTL_BIAS_FORCE_SLEEP (BIT(15)) +#define RTC_CNTL_BIAS_FORCE_SLEEP_M (BIT(15)) +#define RTC_CNTL_BIAS_FORCE_SLEEP_V 0x1 +#define RTC_CNTL_BIAS_FORCE_SLEEP_S 15 +/* RTC_CNTL_BIAS_SLEEP_FOLW_8M : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: BIAS_SLEEP follow CK8M*/ +#define RTC_CNTL_BIAS_SLEEP_FOLW_8M (BIT(14)) +#define RTC_CNTL_BIAS_SLEEP_FOLW_8M_M (BIT(14)) +#define RTC_CNTL_BIAS_SLEEP_FOLW_8M_V 0x1 +#define RTC_CNTL_BIAS_SLEEP_FOLW_8M_S 14 +/* RTC_CNTL_XTL_FORCE_PU : R/W ;bitpos:[13] ;default: 1'd1 ; */ +/*description: crystall force power up*/ +#define RTC_CNTL_XTL_FORCE_PU (BIT(13)) +#define RTC_CNTL_XTL_FORCE_PU_M (BIT(13)) +#define RTC_CNTL_XTL_FORCE_PU_V 0x1 +#define RTC_CNTL_XTL_FORCE_PU_S 13 +/* RTC_CNTL_XTL_FORCE_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: crystall force power down*/ +#define RTC_CNTL_XTL_FORCE_PD (BIT(12)) +#define RTC_CNTL_XTL_FORCE_PD_M (BIT(12)) +#define RTC_CNTL_XTL_FORCE_PD_V 0x1 +#define RTC_CNTL_XTL_FORCE_PD_S 12 +/* RTC_CNTL_BBPLL_FORCE_PU : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: BB_PLL force power up*/ +#define RTC_CNTL_BBPLL_FORCE_PU (BIT(11)) +#define RTC_CNTL_BBPLL_FORCE_PU_M (BIT(11)) +#define RTC_CNTL_BBPLL_FORCE_PU_V 0x1 +#define RTC_CNTL_BBPLL_FORCE_PU_S 11 +/* RTC_CNTL_BBPLL_FORCE_PD : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: BB_PLL force power down*/ +#define RTC_CNTL_BBPLL_FORCE_PD (BIT(10)) +#define RTC_CNTL_BBPLL_FORCE_PD_M (BIT(10)) +#define RTC_CNTL_BBPLL_FORCE_PD_V 0x1 +#define RTC_CNTL_BBPLL_FORCE_PD_S 10 +/* RTC_CNTL_BBPLL_I2C_FORCE_PU : R/W ;bitpos:[9] ;default: 1'd0 ; */ +/*description: BB_PLL_I2C force power up*/ +#define RTC_CNTL_BBPLL_I2C_FORCE_PU (BIT(9)) +#define RTC_CNTL_BBPLL_I2C_FORCE_PU_M (BIT(9)) +#define RTC_CNTL_BBPLL_I2C_FORCE_PU_V 0x1 +#define RTC_CNTL_BBPLL_I2C_FORCE_PU_S 9 +/* RTC_CNTL_BBPLL_I2C_FORCE_PD : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: BB_PLL _I2C force power down*/ +#define RTC_CNTL_BBPLL_I2C_FORCE_PD (BIT(8)) +#define RTC_CNTL_BBPLL_I2C_FORCE_PD_M (BIT(8)) +#define RTC_CNTL_BBPLL_I2C_FORCE_PD_V 0x1 +#define RTC_CNTL_BBPLL_I2C_FORCE_PD_S 8 +/* RTC_CNTL_BB_I2C_FORCE_PU : R/W ;bitpos:[7] ;default: 1'd0 ; */ +/*description: BB_I2C force power up*/ +#define RTC_CNTL_BB_I2C_FORCE_PU (BIT(7)) +#define RTC_CNTL_BB_I2C_FORCE_PU_M (BIT(7)) +#define RTC_CNTL_BB_I2C_FORCE_PU_V 0x1 +#define RTC_CNTL_BB_I2C_FORCE_PU_S 7 +/* RTC_CNTL_BB_I2C_FORCE_PD : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: BB_I2C force power down*/ +#define RTC_CNTL_BB_I2C_FORCE_PD (BIT(6)) +#define RTC_CNTL_BB_I2C_FORCE_PD_M (BIT(6)) +#define RTC_CNTL_BB_I2C_FORCE_PD_V 0x1 +#define RTC_CNTL_BB_I2C_FORCE_PD_S 6 +/* RTC_CNTL_SW_PROCPU_RST : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: PRO CPU SW reset*/ +#define RTC_CNTL_SW_PROCPU_RST (BIT(5)) +#define RTC_CNTL_SW_PROCPU_RST_M (BIT(5)) +#define RTC_CNTL_SW_PROCPU_RST_V 0x1 +#define RTC_CNTL_SW_PROCPU_RST_S 5 +/* RTC_CNTL_SW_APPCPU_RST : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: APP CPU SW reset*/ +#define RTC_CNTL_SW_APPCPU_RST (BIT(4)) +#define RTC_CNTL_SW_APPCPU_RST_M (BIT(4)) +#define RTC_CNTL_SW_APPCPU_RST_V 0x1 +#define RTC_CNTL_SW_APPCPU_RST_S 4 +/* RTC_CNTL_SW_STALL_PROCPU_C0 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */ +/*description: {reg_sw_stall_procpu_c1[5:0] reg_sw_stall_procpu_c0[1:0]} == + 0x86 will stall PRO CPU*/ +#define RTC_CNTL_SW_STALL_PROCPU_C0 0x00000003 +#define RTC_CNTL_SW_STALL_PROCPU_C0_M ((RTC_CNTL_SW_STALL_PROCPU_C0_V)<<(RTC_CNTL_SW_STALL_PROCPU_C0_S)) +#define RTC_CNTL_SW_STALL_PROCPU_C0_V 0x3 +#define RTC_CNTL_SW_STALL_PROCPU_C0_S 2 +/* RTC_CNTL_SW_STALL_APPCPU_C0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: {reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == + 0x86 will stall APP CPU*/ +#define RTC_CNTL_SW_STALL_APPCPU_C0 0x00000003 +#define RTC_CNTL_SW_STALL_APPCPU_C0_M ((RTC_CNTL_SW_STALL_APPCPU_C0_V)<<(RTC_CNTL_SW_STALL_APPCPU_C0_S)) +#define RTC_CNTL_SW_STALL_APPCPU_C0_V 0x3 +#define RTC_CNTL_SW_STALL_APPCPU_C0_S 0 + +#define RTC_CNTL_SLP_TIMER0_REG (DR_REG_RTCCNTL_BASE + 0x4) +/* RTC_CNTL_SLP_VAL_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: RTC sleep timer low 32 bits*/ +#define RTC_CNTL_SLP_VAL_LO 0xFFFFFFFF +#define RTC_CNTL_SLP_VAL_LO_M ((RTC_CNTL_SLP_VAL_LO_V)<<(RTC_CNTL_SLP_VAL_LO_S)) +#define RTC_CNTL_SLP_VAL_LO_V 0xFFFFFFFF +#define RTC_CNTL_SLP_VAL_LO_S 0 + +#define RTC_CNTL_SLP_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x8) +/* RTC_CNTL_MAIN_TIMER_ALARM_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */ +/*description: timer alarm enable bit*/ +#define RTC_CNTL_MAIN_TIMER_ALARM_EN (BIT(16)) +#define RTC_CNTL_MAIN_TIMER_ALARM_EN_M (BIT(16)) +#define RTC_CNTL_MAIN_TIMER_ALARM_EN_V 0x1 +#define RTC_CNTL_MAIN_TIMER_ALARM_EN_S 16 +/* RTC_CNTL_SLP_VAL_HI : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: RTC sleep timer high 16 bits*/ +#define RTC_CNTL_SLP_VAL_HI 0x0000FFFF +#define RTC_CNTL_SLP_VAL_HI_M ((RTC_CNTL_SLP_VAL_HI_V)<<(RTC_CNTL_SLP_VAL_HI_S)) +#define RTC_CNTL_SLP_VAL_HI_V 0xFFFF +#define RTC_CNTL_SLP_VAL_HI_S 0 + +#define RTC_CNTL_TIME_UPDATE_REG (DR_REG_RTCCNTL_BASE + 0xc) +/* RTC_CNTL_TIME_UPDATE : WO ;bitpos:[31] ;default: 1'h0 ; */ +/*description: Set 1: to update register with RTC timer*/ +#define RTC_CNTL_TIME_UPDATE (BIT(31)) +#define RTC_CNTL_TIME_UPDATE_M (BIT(31)) +#define RTC_CNTL_TIME_UPDATE_V 0x1 +#define RTC_CNTL_TIME_UPDATE_S 31 +/* RTC_CNTL_TIME_VALID : RO ;bitpos:[30] ;default: 1'b0 ; */ +/*description: To indicate the register is updated*/ +#define RTC_CNTL_TIME_VALID (BIT(30)) +#define RTC_CNTL_TIME_VALID_M (BIT(30)) +#define RTC_CNTL_TIME_VALID_V 0x1 +#define RTC_CNTL_TIME_VALID_S 30 + +#define RTC_CNTL_TIME0_REG (DR_REG_RTCCNTL_BASE + 0x10) +/* RTC_CNTL_TIME_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: RTC timer low 32 bits*/ +#define RTC_CNTL_TIME_LO 0xFFFFFFFF +#define RTC_CNTL_TIME_LO_M ((RTC_CNTL_TIME_LO_V)<<(RTC_CNTL_TIME_LO_S)) +#define RTC_CNTL_TIME_LO_V 0xFFFFFFFF +#define RTC_CNTL_TIME_LO_S 0 + +#define RTC_CNTL_TIME1_REG (DR_REG_RTCCNTL_BASE + 0x14) +/* RTC_CNTL_TIME_HI : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: RTC timer high 16 bits*/ +#define RTC_CNTL_TIME_HI 0x0000FFFF +#define RTC_CNTL_TIME_HI_M ((RTC_CNTL_TIME_HI_V)<<(RTC_CNTL_TIME_HI_S)) +#define RTC_CNTL_TIME_HI_V 0xFFFF +#define RTC_CNTL_TIME_HI_S 0 + +#define RTC_CNTL_STATE0_REG (DR_REG_RTCCNTL_BASE + 0x18) +/* RTC_CNTL_SLEEP_EN : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: sleep enable bit*/ +#define RTC_CNTL_SLEEP_EN (BIT(31)) +#define RTC_CNTL_SLEEP_EN_M (BIT(31)) +#define RTC_CNTL_SLEEP_EN_V 0x1 +#define RTC_CNTL_SLEEP_EN_S 31 +/* RTC_CNTL_SLP_REJECT : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: sleep reject bit*/ +#define RTC_CNTL_SLP_REJECT (BIT(30)) +#define RTC_CNTL_SLP_REJECT_M (BIT(30)) +#define RTC_CNTL_SLP_REJECT_V 0x1 +#define RTC_CNTL_SLP_REJECT_S 30 +/* RTC_CNTL_SLP_WAKEUP : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: sleep wakeup bit*/ +#define RTC_CNTL_SLP_WAKEUP (BIT(29)) +#define RTC_CNTL_SLP_WAKEUP_M (BIT(29)) +#define RTC_CNTL_SLP_WAKEUP_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_S 29 +/* RTC_CNTL_SDIO_ACTIVE_IND : RO ;bitpos:[28] ;default: 1'd0 ; */ +/*description: SDIO active indication*/ +#define RTC_CNTL_SDIO_ACTIVE_IND (BIT(28)) +#define RTC_CNTL_SDIO_ACTIVE_IND_M (BIT(28)) +#define RTC_CNTL_SDIO_ACTIVE_IND_V 0x1 +#define RTC_CNTL_SDIO_ACTIVE_IND_S 28 +/* RTC_CNTL_ULP_CP_SLP_TIMER_EN : R/W ;bitpos:[24] ;default: 1'd0 ; */ +/*description: ULP-coprocessor timer enable bit*/ +#define RTC_CNTL_ULP_CP_SLP_TIMER_EN (BIT(24)) +#define RTC_CNTL_ULP_CP_SLP_TIMER_EN_M (BIT(24)) +#define RTC_CNTL_ULP_CP_SLP_TIMER_EN_V 0x1 +#define RTC_CNTL_ULP_CP_SLP_TIMER_EN_S 24 +/* RTC_CNTL_TOUCH_SLP_TIMER_EN : R/W ;bitpos:[23] ;default: 1'd0 ; */ +/*description: touch timer enable bit*/ +#define RTC_CNTL_TOUCH_SLP_TIMER_EN (BIT(23)) +#define RTC_CNTL_TOUCH_SLP_TIMER_EN_M (BIT(23)) +#define RTC_CNTL_TOUCH_SLP_TIMER_EN_V 0x1 +#define RTC_CNTL_TOUCH_SLP_TIMER_EN_S 23 +/* RTC_CNTL_APB2RTC_BRIDGE_SEL : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: 1: APB to RTC using bridge 0: APB to RTC using sync*/ +#define RTC_CNTL_APB2RTC_BRIDGE_SEL (BIT(22)) +#define RTC_CNTL_APB2RTC_BRIDGE_SEL_M (BIT(22)) +#define RTC_CNTL_APB2RTC_BRIDGE_SEL_V 0x1 +#define RTC_CNTL_APB2RTC_BRIDGE_SEL_S 22 +/* RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN : R/W ;bitpos:[21] ;default: 1'd1 ; */ +/*description: ULP-coprocessor force wake up*/ +#define RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN (BIT(21)) +#define RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN_M (BIT(21)) +#define RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN_V 0x1 +#define RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN_S 21 +/* RTC_CNTL_TOUCH_WAKEUP_FORCE_EN : R/W ;bitpos:[20] ;default: 1'd1 ; */ +/*description: touch controller force wake up*/ +#define RTC_CNTL_TOUCH_WAKEUP_FORCE_EN (BIT(20)) +#define RTC_CNTL_TOUCH_WAKEUP_FORCE_EN_M (BIT(20)) +#define RTC_CNTL_TOUCH_WAKEUP_FORCE_EN_V 0x1 +#define RTC_CNTL_TOUCH_WAKEUP_FORCE_EN_S 20 + +#define RTC_CNTL_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x1c) +/* RTC_CNTL_PLL_BUF_WAIT : R/W ;bitpos:[31:24] ;default: 8'd40 ; */ +/*description: PLL wait cycles in slow_clk_rtc*/ +#define RTC_CNTL_PLL_BUF_WAIT 0x000000FF +#define RTC_CNTL_PLL_BUF_WAIT_M ((RTC_CNTL_PLL_BUF_WAIT_V)<<(RTC_CNTL_PLL_BUF_WAIT_S)) +#define RTC_CNTL_PLL_BUF_WAIT_V 0xFF +#define RTC_CNTL_PLL_BUF_WAIT_S 24 +#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 20 +/* RTC_CNTL_XTL_BUF_WAIT : R/W ;bitpos:[23:14] ;default: 10'd80 ; */ +/*description: XTAL wait cycles in slow_clk_rtc*/ +#define RTC_CNTL_XTL_BUF_WAIT 0x000003FF +#define RTC_CNTL_XTL_BUF_WAIT_M ((RTC_CNTL_XTL_BUF_WAIT_V)<<(RTC_CNTL_XTL_BUF_WAIT_S)) +#define RTC_CNTL_XTL_BUF_WAIT_V 0x3FF +#define RTC_CNTL_XTL_BUF_WAIT_S 14 +#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 20 +/* RTC_CNTL_CK8M_WAIT : R/W ;bitpos:[13:6] ;default: 8'h10 ; */ +/*description: CK8M wait cycles in slow_clk_rtc*/ +#define RTC_CNTL_CK8M_WAIT 0x000000FF +#define RTC_CNTL_CK8M_WAIT_M ((RTC_CNTL_CK8M_WAIT_V)<<(RTC_CNTL_CK8M_WAIT_S)) +#define RTC_CNTL_CK8M_WAIT_V 0xFF +#define RTC_CNTL_CK8M_WAIT_S 6 +/* RTC_CNTL_CPU_STALL_WAIT : R/W ;bitpos:[5:1] ;default: 5'd1 ; */ +/*description: CPU stall wait cycles in fast_clk_rtc*/ +#define RTC_CNTL_CPU_STALL_WAIT 0x0000001F +#define RTC_CNTL_CPU_STALL_WAIT_M ((RTC_CNTL_CPU_STALL_WAIT_V)<<(RTC_CNTL_CPU_STALL_WAIT_S)) +#define RTC_CNTL_CPU_STALL_WAIT_V 0x1F +#define RTC_CNTL_CPU_STALL_WAIT_S 1 +/* RTC_CNTL_CPU_STALL_EN : R/W ;bitpos:[0] ;default: 1'd1 ; */ +/*description: CPU stall enable bit*/ +#define RTC_CNTL_CPU_STALL_EN (BIT(0)) +#define RTC_CNTL_CPU_STALL_EN_M (BIT(0)) +#define RTC_CNTL_CPU_STALL_EN_V 0x1 +#define RTC_CNTL_CPU_STALL_EN_S 0 + +#define RTC_CNTL_TIMER2_REG (DR_REG_RTCCNTL_BASE + 0x20) +/* RTC_CNTL_MIN_TIME_CK8M_OFF : R/W ;bitpos:[31:24] ;default: 8'h1 ; */ +/*description: minimal cycles in slow_clk_rtc for CK8M in power down state*/ +#define RTC_CNTL_MIN_TIME_CK8M_OFF 0x000000FF +#define RTC_CNTL_MIN_TIME_CK8M_OFF_M ((RTC_CNTL_MIN_TIME_CK8M_OFF_V)<<(RTC_CNTL_MIN_TIME_CK8M_OFF_S)) +#define RTC_CNTL_MIN_TIME_CK8M_OFF_V 0xFF +#define RTC_CNTL_MIN_TIME_CK8M_OFF_S 24 +/* RTC_CNTL_ULPCP_TOUCH_START_WAIT : R/W ;bitpos:[23:15] ;default: 9'h10 ; */ +/*description: wait cycles in slow_clk_rtc before ULP-coprocessor / touch controller + start to work*/ +#define RTC_CNTL_ULPCP_TOUCH_START_WAIT 0x000001FF +#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_M ((RTC_CNTL_ULPCP_TOUCH_START_WAIT_V)<<(RTC_CNTL_ULPCP_TOUCH_START_WAIT_S)) +#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_V 0x1FF +#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_S 15 + +#define RTC_CNTL_TIMER3_REG (DR_REG_RTCCNTL_BASE + 0x24) +/* RTC_CNTL_ROM_RAM_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'd10 ; */ +/*description: */ +#define RTC_CNTL_ROM_RAM_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_ROM_RAM_POWERUP_TIMER_M ((RTC_CNTL_ROM_RAM_POWERUP_TIMER_V)<<(RTC_CNTL_ROM_RAM_POWERUP_TIMER_S)) +#define RTC_CNTL_ROM_RAM_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_ROM_RAM_POWERUP_TIMER_S 25 +/* RTC_CNTL_ROM_RAM_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h16 ; */ +/*description: */ +#define RTC_CNTL_ROM_RAM_WAIT_TIMER 0x000001FF +#define RTC_CNTL_ROM_RAM_WAIT_TIMER_M ((RTC_CNTL_ROM_RAM_WAIT_TIMER_V)<<(RTC_CNTL_ROM_RAM_WAIT_TIMER_S)) +#define RTC_CNTL_ROM_RAM_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_ROM_RAM_WAIT_TIMER_S 16 +/* RTC_CNTL_WIFI_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */ +/*description: */ +#define RTC_CNTL_WIFI_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_WIFI_POWERUP_TIMER_M ((RTC_CNTL_WIFI_POWERUP_TIMER_V)<<(RTC_CNTL_WIFI_POWERUP_TIMER_S)) +#define RTC_CNTL_WIFI_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_WIFI_POWERUP_TIMER_S 9 +/* RTC_CNTL_WIFI_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */ +/*description: */ +#define RTC_CNTL_WIFI_WAIT_TIMER 0x000001FF +#define RTC_CNTL_WIFI_WAIT_TIMER_M ((RTC_CNTL_WIFI_WAIT_TIMER_V)<<(RTC_CNTL_WIFI_WAIT_TIMER_S)) +#define RTC_CNTL_WIFI_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_WIFI_WAIT_TIMER_S 0 + +#define RTC_CNTL_TIMER4_REG (DR_REG_RTCCNTL_BASE + 0x28) +/* RTC_CNTL_DG_WRAP_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h8 ; */ +/*description: */ +#define RTC_CNTL_DG_WRAP_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_M ((RTC_CNTL_DG_WRAP_POWERUP_TIMER_V)<<(RTC_CNTL_DG_WRAP_POWERUP_TIMER_S)) +#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_S 25 +/* RTC_CNTL_DG_WRAP_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h20 ; */ +/*description: */ +#define RTC_CNTL_DG_WRAP_WAIT_TIMER 0x000001FF +#define RTC_CNTL_DG_WRAP_WAIT_TIMER_M ((RTC_CNTL_DG_WRAP_WAIT_TIMER_V)<<(RTC_CNTL_DG_WRAP_WAIT_TIMER_S)) +#define RTC_CNTL_DG_WRAP_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_DG_WRAP_WAIT_TIMER_S 16 +/* RTC_CNTL_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */ +/*description: */ +#define RTC_CNTL_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_POWERUP_TIMER_M ((RTC_CNTL_POWERUP_TIMER_V)<<(RTC_CNTL_POWERUP_TIMER_S)) +#define RTC_CNTL_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_POWERUP_TIMER_S 9 +/* RTC_CNTL_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */ +/*description: */ +#define RTC_CNTL_WAIT_TIMER 0x000001FF +#define RTC_CNTL_WAIT_TIMER_M ((RTC_CNTL_WAIT_TIMER_V)<<(RTC_CNTL_WAIT_TIMER_S)) +#define RTC_CNTL_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_WAIT_TIMER_S 0 + +#define RTC_CNTL_TIMER5_REG (DR_REG_RTCCNTL_BASE + 0x2c) +/* RTC_CNTL_RTCMEM_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h9 ; */ +/*description: */ +#define RTC_CNTL_RTCMEM_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_RTCMEM_POWERUP_TIMER_M ((RTC_CNTL_RTCMEM_POWERUP_TIMER_V)<<(RTC_CNTL_RTCMEM_POWERUP_TIMER_S)) +#define RTC_CNTL_RTCMEM_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_RTCMEM_POWERUP_TIMER_S 25 +/* RTC_CNTL_RTCMEM_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h14 ; */ +/*description: */ +#define RTC_CNTL_RTCMEM_WAIT_TIMER 0x000001FF +#define RTC_CNTL_RTCMEM_WAIT_TIMER_M ((RTC_CNTL_RTCMEM_WAIT_TIMER_V)<<(RTC_CNTL_RTCMEM_WAIT_TIMER_S)) +#define RTC_CNTL_RTCMEM_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_RTCMEM_WAIT_TIMER_S 16 +/* RTC_CNTL_MIN_SLP_VAL : R/W ;bitpos:[15:8] ;default: 8'h80 ; */ +/*description: minimal sleep cycles in slow_clk_rtc*/ +#define RTC_CNTL_MIN_SLP_VAL 0x000000FF +#define RTC_CNTL_MIN_SLP_VAL_M ((RTC_CNTL_MIN_SLP_VAL_V)<<(RTC_CNTL_MIN_SLP_VAL_S)) +#define RTC_CNTL_MIN_SLP_VAL_V 0xFF +#define RTC_CNTL_MIN_SLP_VAL_S 8 +/* RTC_CNTL_ULP_CP_SUBTIMER_PREDIV : R/W ;bitpos:[7:0] ;default: 8'd1 ; */ +/*description: */ +#define RTC_CNTL_ULP_CP_SUBTIMER_PREDIV 0x000000FF +#define RTC_CNTL_ULP_CP_SUBTIMER_PREDIV_M ((RTC_CNTL_ULP_CP_SUBTIMER_PREDIV_V)<<(RTC_CNTL_ULP_CP_SUBTIMER_PREDIV_S)) +#define RTC_CNTL_ULP_CP_SUBTIMER_PREDIV_V 0xFF +#define RTC_CNTL_ULP_CP_SUBTIMER_PREDIV_S 0 + +#define RTC_CNTL_ANA_CONF_REG (DR_REG_RTCCNTL_BASE + 0x30) +/* RTC_CNTL_PLL_I2C_PU : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: 1: PLL_I2C power up otherwise power down*/ +#define RTC_CNTL_PLL_I2C_PU (BIT(31)) +#define RTC_CNTL_PLL_I2C_PU_M (BIT(31)) +#define RTC_CNTL_PLL_I2C_PU_V 0x1 +#define RTC_CNTL_PLL_I2C_PU_S 31 +/* RTC_CNTL_CKGEN_I2C_PU : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: 1: CKGEN_I2C power up otherwise power down*/ +#define RTC_CNTL_CKGEN_I2C_PU (BIT(30)) +#define RTC_CNTL_CKGEN_I2C_PU_M (BIT(30)) +#define RTC_CNTL_CKGEN_I2C_PU_V 0x1 +#define RTC_CNTL_CKGEN_I2C_PU_S 30 +/* RTC_CNTL_RFRX_PBUS_PU : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: 1: RFRX_PBUS power up otherwise power down*/ +#define RTC_CNTL_RFRX_PBUS_PU (BIT(28)) +#define RTC_CNTL_RFRX_PBUS_PU_M (BIT(28)) +#define RTC_CNTL_RFRX_PBUS_PU_V 0x1 +#define RTC_CNTL_RFRX_PBUS_PU_S 28 +/* RTC_CNTL_TXRF_I2C_PU : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: 1: TXRF_I2C power up otherwise power down*/ +#define RTC_CNTL_TXRF_I2C_PU (BIT(27)) +#define RTC_CNTL_TXRF_I2C_PU_M (BIT(27)) +#define RTC_CNTL_TXRF_I2C_PU_V 0x1 +#define RTC_CNTL_TXRF_I2C_PU_S 27 +/* RTC_CNTL_PVTMON_PU : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: 1: PVTMON power up otherwise power down*/ +#define RTC_CNTL_PVTMON_PU (BIT(26)) +#define RTC_CNTL_PVTMON_PU_M (BIT(26)) +#define RTC_CNTL_PVTMON_PU_V 0x1 +#define RTC_CNTL_PVTMON_PU_S 26 +/* RTC_CNTL_BBPLL_CAL_SLP_START : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: start BBPLL calibration during sleep*/ +#define RTC_CNTL_BBPLL_CAL_SLP_START (BIT(25)) +#define RTC_CNTL_BBPLL_CAL_SLP_START_M (BIT(25)) +#define RTC_CNTL_BBPLL_CAL_SLP_START_V 0x1 +#define RTC_CNTL_BBPLL_CAL_SLP_START_S 25 +/* RTC_CNTL_PLLA_FORCE_PU : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: PLLA force power up*/ +#define RTC_CNTL_PLLA_FORCE_PU (BIT(24)) +#define RTC_CNTL_PLLA_FORCE_PU_M (BIT(24)) +#define RTC_CNTL_PLLA_FORCE_PU_V 0x1 +#define RTC_CNTL_PLLA_FORCE_PU_S 24 +/* RTC_CNTL_PLLA_FORCE_PD : R/W ;bitpos:[23] ;default: 1'b1 ; */ +/*description: PLLA force power down*/ +#define RTC_CNTL_PLLA_FORCE_PD (BIT(23)) +#define RTC_CNTL_PLLA_FORCE_PD_M (BIT(23)) +#define RTC_CNTL_PLLA_FORCE_PD_V 0x1 +#define RTC_CNTL_PLLA_FORCE_PD_S 23 + +#define RTC_CNTL_RESET_STATE_REG (DR_REG_RTCCNTL_BASE + 0x34) +/* RTC_CNTL_PROCPU_STAT_VECTOR_SEL : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: PRO CPU state vector sel*/ +#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL (BIT(13)) +#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_M (BIT(13)) +#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_V 0x1 +#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_S 13 +/* RTC_CNTL_APPCPU_STAT_VECTOR_SEL : R/W ;bitpos:[12] ;default: 1'b1 ; */ +/*description: APP CPU state vector sel*/ +#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL (BIT(12)) +#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_M (BIT(12)) +#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_V 0x1 +#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_S 12 +/* RTC_CNTL_RESET_CAUSE_APPCPU : RO ;bitpos:[11:6] ;default: 0 ; */ +/*description: reset cause of APP CPU*/ +#define RTC_CNTL_RESET_CAUSE_APPCPU 0x0000003F +#define RTC_CNTL_RESET_CAUSE_APPCPU_M ((RTC_CNTL_RESET_CAUSE_APPCPU_V)<<(RTC_CNTL_RESET_CAUSE_APPCPU_S)) +#define RTC_CNTL_RESET_CAUSE_APPCPU_V 0x3F +#define RTC_CNTL_RESET_CAUSE_APPCPU_S 6 +/* RTC_CNTL_RESET_CAUSE_PROCPU : RO ;bitpos:[5:0] ;default: 0 ; */ +/*description: reset cause of PRO CPU*/ +#define RTC_CNTL_RESET_CAUSE_PROCPU 0x0000003F +#define RTC_CNTL_RESET_CAUSE_PROCPU_M ((RTC_CNTL_RESET_CAUSE_PROCPU_V)<<(RTC_CNTL_RESET_CAUSE_PROCPU_S)) +#define RTC_CNTL_RESET_CAUSE_PROCPU_V 0x3F +#define RTC_CNTL_RESET_CAUSE_PROCPU_S 0 + +#define RTC_CNTL_WAKEUP_STATE_REG (DR_REG_RTCCNTL_BASE + 0x38) +/* RTC_CNTL_GPIO_WAKEUP_FILTER : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: enable filter for gpio wakeup event*/ +#define RTC_CNTL_GPIO_WAKEUP_FILTER (BIT(22)) +#define RTC_CNTL_GPIO_WAKEUP_FILTER_M (BIT(22)) +#define RTC_CNTL_GPIO_WAKEUP_FILTER_V 0x1 +#define RTC_CNTL_GPIO_WAKEUP_FILTER_S 22 +/* RTC_CNTL_WAKEUP_ENA : R/W ;bitpos:[21:11] ;default: 11'b1100 ; */ +/*description: wakeup enable bitmap*/ +#define RTC_CNTL_WAKEUP_ENA 0x000007FF +#define RTC_CNTL_WAKEUP_ENA_M ((RTC_CNTL_WAKEUP_ENA_V)<<(RTC_CNTL_WAKEUP_ENA_S)) +#define RTC_CNTL_WAKEUP_ENA_V 0x7FF +#define RTC_CNTL_WAKEUP_ENA_S 11 +/* RTC_CNTL_WAKEUP_CAUSE : RO ;bitpos:[10:0] ;default: 11'h0 ; */ +/*description: wakeup cause*/ +#define RTC_CNTL_WAKEUP_CAUSE 0x000007FF +#define RTC_CNTL_WAKEUP_CAUSE_M ((RTC_CNTL_WAKEUP_CAUSE_V)<<(RTC_CNTL_WAKEUP_CAUSE_S)) +#define RTC_CNTL_WAKEUP_CAUSE_V 0x7FF +#define RTC_CNTL_WAKEUP_CAUSE_S 0 + +#define RTC_CNTL_INT_ENA_REG (DR_REG_RTCCNTL_BASE + 0x3c) +/* RTC_CNTL_MAIN_TIMER_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: enable RTC main timer interrupt*/ +#define RTC_CNTL_MAIN_TIMER_INT_ENA (BIT(8)) +#define RTC_CNTL_MAIN_TIMER_INT_ENA_M (BIT(8)) +#define RTC_CNTL_MAIN_TIMER_INT_ENA_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_ENA_S 8 +/* RTC_CNTL_BROWN_OUT_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: enable brown out interrupt*/ +#define RTC_CNTL_BROWN_OUT_INT_ENA (BIT(7)) +#define RTC_CNTL_BROWN_OUT_INT_ENA_M (BIT(7)) +#define RTC_CNTL_BROWN_OUT_INT_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_ENA_S 7 +/* RTC_CNTL_TOUCH_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: enable touch interrupt*/ +#define RTC_CNTL_TOUCH_INT_ENA (BIT(6)) +#define RTC_CNTL_TOUCH_INT_ENA_M (BIT(6)) +#define RTC_CNTL_TOUCH_INT_ENA_V 0x1 +#define RTC_CNTL_TOUCH_INT_ENA_S 6 +/* RTC_CNTL_ULP_CP_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: enable ULP-coprocessor interrupt*/ +#define RTC_CNTL_ULP_CP_INT_ENA (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_ENA_M (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_ENA_V 0x1 +#define RTC_CNTL_ULP_CP_INT_ENA_S 5 +/* RTC_CNTL_TIME_VALID_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: enable RTC time valid interrupt*/ +#define RTC_CNTL_TIME_VALID_INT_ENA (BIT(4)) +#define RTC_CNTL_TIME_VALID_INT_ENA_M (BIT(4)) +#define RTC_CNTL_TIME_VALID_INT_ENA_V 0x1 +#define RTC_CNTL_TIME_VALID_INT_ENA_S 4 +/* RTC_CNTL_WDT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: enable RTC WDT interrupt*/ +#define RTC_CNTL_WDT_INT_ENA (BIT(3)) +#define RTC_CNTL_WDT_INT_ENA_M (BIT(3)) +#define RTC_CNTL_WDT_INT_ENA_V 0x1 +#define RTC_CNTL_WDT_INT_ENA_S 3 +/* RTC_CNTL_SDIO_IDLE_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: enable SDIO idle interrupt*/ +#define RTC_CNTL_SDIO_IDLE_INT_ENA (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_ENA_M (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_ENA_V 0x1 +#define RTC_CNTL_SDIO_IDLE_INT_ENA_S 2 +/* RTC_CNTL_SLP_REJECT_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: enable sleep reject interrupt*/ +#define RTC_CNTL_SLP_REJECT_INT_ENA (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ENA_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ENA_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_ENA_S 1 +/* RTC_CNTL_SLP_WAKEUP_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: enable sleep wakeup interrupt*/ +#define RTC_CNTL_SLP_WAKEUP_INT_ENA (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_S 0 + +#define RTC_CNTL_INT_RAW_REG (DR_REG_RTCCNTL_BASE + 0x40) +/* RTC_CNTL_MAIN_TIMER_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: RTC main timer interrupt raw*/ +#define RTC_CNTL_MAIN_TIMER_INT_RAW (BIT(8)) +#define RTC_CNTL_MAIN_TIMER_INT_RAW_M (BIT(8)) +#define RTC_CNTL_MAIN_TIMER_INT_RAW_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_RAW_S 8 +/* RTC_CNTL_BROWN_OUT_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: brown out interrupt raw*/ +#define RTC_CNTL_BROWN_OUT_INT_RAW (BIT(7)) +#define RTC_CNTL_BROWN_OUT_INT_RAW_M (BIT(7)) +#define RTC_CNTL_BROWN_OUT_INT_RAW_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_RAW_S 7 +/* RTC_CNTL_TOUCH_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: touch interrupt raw*/ +#define RTC_CNTL_TOUCH_INT_RAW (BIT(6)) +#define RTC_CNTL_TOUCH_INT_RAW_M (BIT(6)) +#define RTC_CNTL_TOUCH_INT_RAW_V 0x1 +#define RTC_CNTL_TOUCH_INT_RAW_S 6 +/* RTC_CNTL_ULP_CP_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: ULP-coprocessor interrupt raw*/ +#define RTC_CNTL_ULP_CP_INT_RAW (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_RAW_M (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_RAW_V 0x1 +#define RTC_CNTL_ULP_CP_INT_RAW_S 5 +/* RTC_CNTL_TIME_VALID_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: RTC time valid interrupt raw*/ +#define RTC_CNTL_TIME_VALID_INT_RAW (BIT(4)) +#define RTC_CNTL_TIME_VALID_INT_RAW_M (BIT(4)) +#define RTC_CNTL_TIME_VALID_INT_RAW_V 0x1 +#define RTC_CNTL_TIME_VALID_INT_RAW_S 4 +/* RTC_CNTL_WDT_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: RTC WDT interrupt raw*/ +#define RTC_CNTL_WDT_INT_RAW (BIT(3)) +#define RTC_CNTL_WDT_INT_RAW_M (BIT(3)) +#define RTC_CNTL_WDT_INT_RAW_V 0x1 +#define RTC_CNTL_WDT_INT_RAW_S 3 +/* RTC_CNTL_SDIO_IDLE_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: SDIO idle interrupt raw*/ +#define RTC_CNTL_SDIO_IDLE_INT_RAW (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_RAW_M (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_RAW_V 0x1 +#define RTC_CNTL_SDIO_IDLE_INT_RAW_S 2 +/* RTC_CNTL_SLP_REJECT_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: sleep reject interrupt raw*/ +#define RTC_CNTL_SLP_REJECT_INT_RAW (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_RAW_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_RAW_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_RAW_S 1 +/* RTC_CNTL_SLP_WAKEUP_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: sleep wakeup interrupt raw*/ +#define RTC_CNTL_SLP_WAKEUP_INT_RAW (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_RAW_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_RAW_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_RAW_S 0 + +#define RTC_CNTL_INT_ST_REG (DR_REG_RTCCNTL_BASE + 0x44) +/* RTC_CNTL_MAIN_TIMER_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: RTC main timer interrupt state*/ +#define RTC_CNTL_MAIN_TIMER_INT_ST (BIT(8)) +#define RTC_CNTL_MAIN_TIMER_INT_ST_M (BIT(8)) +#define RTC_CNTL_MAIN_TIMER_INT_ST_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_ST_S 8 +/* RTC_CNTL_BROWN_OUT_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: brown out interrupt state*/ +#define RTC_CNTL_BROWN_OUT_INT_ST (BIT(7)) +#define RTC_CNTL_BROWN_OUT_INT_ST_M (BIT(7)) +#define RTC_CNTL_BROWN_OUT_INT_ST_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_ST_S 7 +/* RTC_CNTL_TOUCH_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: touch interrupt state*/ +#define RTC_CNTL_TOUCH_INT_ST (BIT(6)) +#define RTC_CNTL_TOUCH_INT_ST_M (BIT(6)) +#define RTC_CNTL_TOUCH_INT_ST_V 0x1 +#define RTC_CNTL_TOUCH_INT_ST_S 6 +/* RTC_CNTL_SAR_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: ULP-coprocessor interrupt state*/ +#define RTC_CNTL_SAR_INT_ST (BIT(5)) +#define RTC_CNTL_SAR_INT_ST_M (BIT(5)) +#define RTC_CNTL_SAR_INT_ST_V 0x1 +#define RTC_CNTL_SAR_INT_ST_S 5 +/* RTC_CNTL_TIME_VALID_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: RTC time valid interrupt state*/ +#define RTC_CNTL_TIME_VALID_INT_ST (BIT(4)) +#define RTC_CNTL_TIME_VALID_INT_ST_M (BIT(4)) +#define RTC_CNTL_TIME_VALID_INT_ST_V 0x1 +#define RTC_CNTL_TIME_VALID_INT_ST_S 4 +/* RTC_CNTL_WDT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: RTC WDT interrupt state*/ +#define RTC_CNTL_WDT_INT_ST (BIT(3)) +#define RTC_CNTL_WDT_INT_ST_M (BIT(3)) +#define RTC_CNTL_WDT_INT_ST_V 0x1 +#define RTC_CNTL_WDT_INT_ST_S 3 +/* RTC_CNTL_SDIO_IDLE_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: SDIO idle interrupt state*/ +#define RTC_CNTL_SDIO_IDLE_INT_ST (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_ST_M (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_ST_V 0x1 +#define RTC_CNTL_SDIO_IDLE_INT_ST_S 2 +/* RTC_CNTL_SLP_REJECT_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: sleep reject interrupt state*/ +#define RTC_CNTL_SLP_REJECT_INT_ST (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ST_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ST_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_ST_S 1 +/* RTC_CNTL_SLP_WAKEUP_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: sleep wakeup interrupt state*/ +#define RTC_CNTL_SLP_WAKEUP_INT_ST (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ST_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ST_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_ST_S 0 + +#define RTC_CNTL_INT_CLR_REG (DR_REG_RTCCNTL_BASE + 0x48) +/* RTC_CNTL_MAIN_TIMER_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Clear RTC main timer interrupt state*/ +#define RTC_CNTL_MAIN_TIMER_INT_CLR (BIT(8)) +#define RTC_CNTL_MAIN_TIMER_INT_CLR_M (BIT(8)) +#define RTC_CNTL_MAIN_TIMER_INT_CLR_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_CLR_S 8 +/* RTC_CNTL_BROWN_OUT_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Clear brown out interrupt state*/ +#define RTC_CNTL_BROWN_OUT_INT_CLR (BIT(7)) +#define RTC_CNTL_BROWN_OUT_INT_CLR_M (BIT(7)) +#define RTC_CNTL_BROWN_OUT_INT_CLR_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_CLR_S 7 +/* RTC_CNTL_TOUCH_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Clear touch interrupt state*/ +#define RTC_CNTL_TOUCH_INT_CLR (BIT(6)) +#define RTC_CNTL_TOUCH_INT_CLR_M (BIT(6)) +#define RTC_CNTL_TOUCH_INT_CLR_V 0x1 +#define RTC_CNTL_TOUCH_INT_CLR_S 6 +/* RTC_CNTL_SAR_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Clear ULP-coprocessor interrupt state*/ +#define RTC_CNTL_SAR_INT_CLR (BIT(5)) +#define RTC_CNTL_SAR_INT_CLR_M (BIT(5)) +#define RTC_CNTL_SAR_INT_CLR_V 0x1 +#define RTC_CNTL_SAR_INT_CLR_S 5 +/* RTC_CNTL_TIME_VALID_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Clear RTC time valid interrupt state*/ +#define RTC_CNTL_TIME_VALID_INT_CLR (BIT(4)) +#define RTC_CNTL_TIME_VALID_INT_CLR_M (BIT(4)) +#define RTC_CNTL_TIME_VALID_INT_CLR_V 0x1 +#define RTC_CNTL_TIME_VALID_INT_CLR_S 4 +/* RTC_CNTL_WDT_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Clear RTC WDT interrupt state*/ +#define RTC_CNTL_WDT_INT_CLR (BIT(3)) +#define RTC_CNTL_WDT_INT_CLR_M (BIT(3)) +#define RTC_CNTL_WDT_INT_CLR_V 0x1 +#define RTC_CNTL_WDT_INT_CLR_S 3 +/* RTC_CNTL_SDIO_IDLE_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Clear SDIO idle interrupt state*/ +#define RTC_CNTL_SDIO_IDLE_INT_CLR (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_CLR_M (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_CLR_V 0x1 +#define RTC_CNTL_SDIO_IDLE_INT_CLR_S 2 +/* RTC_CNTL_SLP_REJECT_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Clear sleep reject interrupt state*/ +#define RTC_CNTL_SLP_REJECT_INT_CLR (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_CLR_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_CLR_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_CLR_S 1 +/* RTC_CNTL_SLP_WAKEUP_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Clear sleep wakeup interrupt state*/ +#define RTC_CNTL_SLP_WAKEUP_INT_CLR (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_CLR_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_CLR_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_CLR_S 0 + +#define RTC_CNTL_STORE0_REG (DR_REG_RTCCNTL_BASE + 0x4c) +/* RTC_CNTL_SCRATCH0 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: 32-bit general purpose retention register*/ +#define RTC_CNTL_SCRATCH0 0xFFFFFFFF +#define RTC_CNTL_SCRATCH0_M ((RTC_CNTL_SCRATCH0_V)<<(RTC_CNTL_SCRATCH0_S)) +#define RTC_CNTL_SCRATCH0_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH0_S 0 + +#define RTC_CNTL_STORE1_REG (DR_REG_RTCCNTL_BASE + 0x50) +/* RTC_CNTL_SCRATCH1 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: 32-bit general purpose retention register*/ +#define RTC_CNTL_SCRATCH1 0xFFFFFFFF +#define RTC_CNTL_SCRATCH1_M ((RTC_CNTL_SCRATCH1_V)<<(RTC_CNTL_SCRATCH1_S)) +#define RTC_CNTL_SCRATCH1_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH1_S 0 + +#define RTC_CNTL_STORE2_REG (DR_REG_RTCCNTL_BASE + 0x54) +/* RTC_CNTL_SCRATCH2 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: 32-bit general purpose retention register*/ +#define RTC_CNTL_SCRATCH2 0xFFFFFFFF +#define RTC_CNTL_SCRATCH2_M ((RTC_CNTL_SCRATCH2_V)<<(RTC_CNTL_SCRATCH2_S)) +#define RTC_CNTL_SCRATCH2_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH2_S 0 + +#define RTC_CNTL_STORE3_REG (DR_REG_RTCCNTL_BASE + 0x58) +/* RTC_CNTL_SCRATCH3 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: 32-bit general purpose retention register*/ +#define RTC_CNTL_SCRATCH3 0xFFFFFFFF +#define RTC_CNTL_SCRATCH3_M ((RTC_CNTL_SCRATCH3_V)<<(RTC_CNTL_SCRATCH3_S)) +#define RTC_CNTL_SCRATCH3_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH3_S 0 + +#define RTC_CNTL_EXT_XTL_CONF_REG (DR_REG_RTCCNTL_BASE + 0x5c) +/* RTC_CNTL_XTL_EXT_CTR_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: enable control XTAL by external pads*/ +#define RTC_CNTL_XTL_EXT_CTR_EN (BIT(31)) +#define RTC_CNTL_XTL_EXT_CTR_EN_M (BIT(31)) +#define RTC_CNTL_XTL_EXT_CTR_EN_V 0x1 +#define RTC_CNTL_XTL_EXT_CTR_EN_S 31 +/* RTC_CNTL_XTL_EXT_CTR_LV : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: 0: power down XTAL at high level 1: power down XTAL at low level*/ +#define RTC_CNTL_XTL_EXT_CTR_LV (BIT(30)) +#define RTC_CNTL_XTL_EXT_CTR_LV_M (BIT(30)) +#define RTC_CNTL_XTL_EXT_CTR_LV_V 0x1 +#define RTC_CNTL_XTL_EXT_CTR_LV_S 30 + +#define RTC_CNTL_EXT_WAKEUP_CONF_REG (DR_REG_RTCCNTL_BASE + 0x60) +/* RTC_CNTL_EXT_WAKEUP1_LV : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: 0: external wakeup at low level 1: external wakeup at high level*/ +#define RTC_CNTL_EXT_WAKEUP1_LV (BIT(31)) +#define RTC_CNTL_EXT_WAKEUP1_LV_M (BIT(31)) +#define RTC_CNTL_EXT_WAKEUP1_LV_V 0x1 +#define RTC_CNTL_EXT_WAKEUP1_LV_S 31 +/* RTC_CNTL_EXT_WAKEUP0_LV : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: 0: external wakeup at low level 1: external wakeup at high level*/ +#define RTC_CNTL_EXT_WAKEUP0_LV (BIT(30)) +#define RTC_CNTL_EXT_WAKEUP0_LV_M (BIT(30)) +#define RTC_CNTL_EXT_WAKEUP0_LV_V 0x1 +#define RTC_CNTL_EXT_WAKEUP0_LV_S 30 + +#define RTC_CNTL_SLP_REJECT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x64) +/* RTC_CNTL_REJECT_CAUSE : RO ;bitpos:[31:28] ;default: 4'b0 ; */ +/*description: sleep reject cause*/ +#define RTC_CNTL_REJECT_CAUSE 0x0000000F +#define RTC_CNTL_REJECT_CAUSE_M ((RTC_CNTL_REJECT_CAUSE_V)<<(RTC_CNTL_REJECT_CAUSE_S)) +#define RTC_CNTL_REJECT_CAUSE_V 0xF +#define RTC_CNTL_REJECT_CAUSE_S 28 +/* RTC_CNTL_DEEP_SLP_REJECT_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: enable reject for deep sleep*/ +#define RTC_CNTL_DEEP_SLP_REJECT_EN (BIT(27)) +#define RTC_CNTL_DEEP_SLP_REJECT_EN_M (BIT(27)) +#define RTC_CNTL_DEEP_SLP_REJECT_EN_V 0x1 +#define RTC_CNTL_DEEP_SLP_REJECT_EN_S 27 +/* RTC_CNTL_LIGHT_SLP_REJECT_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: enable reject for light sleep*/ +#define RTC_CNTL_LIGHT_SLP_REJECT_EN (BIT(26)) +#define RTC_CNTL_LIGHT_SLP_REJECT_EN_M (BIT(26)) +#define RTC_CNTL_LIGHT_SLP_REJECT_EN_V 0x1 +#define RTC_CNTL_LIGHT_SLP_REJECT_EN_S 26 +/* RTC_CNTL_SDIO_REJECT_EN : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: enable SDIO reject*/ +#define RTC_CNTL_SDIO_REJECT_EN (BIT(25)) +#define RTC_CNTL_SDIO_REJECT_EN_M (BIT(25)) +#define RTC_CNTL_SDIO_REJECT_EN_V 0x1 +#define RTC_CNTL_SDIO_REJECT_EN_S 25 +/* RTC_CNTL_GPIO_REJECT_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: enable GPIO reject*/ +#define RTC_CNTL_GPIO_REJECT_EN (BIT(24)) +#define RTC_CNTL_GPIO_REJECT_EN_M (BIT(24)) +#define RTC_CNTL_GPIO_REJECT_EN_V 0x1 +#define RTC_CNTL_GPIO_REJECT_EN_S 24 + +#define RTC_CNTL_CPU_PERIOD_CONF_REG (DR_REG_RTCCNTL_BASE + 0x68) +/* RTC_CNTL_CPUPERIOD_SEL : R/W ;bitpos:[31:30] ;default: 2'b00 ; */ +/*description: CPU period sel*/ +#define RTC_CNTL_CPUPERIOD_SEL 0x00000003 +#define RTC_CNTL_CPUPERIOD_SEL_M ((RTC_CNTL_CPUPERIOD_SEL_V)<<(RTC_CNTL_CPUPERIOD_SEL_S)) +#define RTC_CNTL_CPUPERIOD_SEL_V 0x3 +#define RTC_CNTL_CPUPERIOD_SEL_S 30 +/* RTC_CNTL_CPUSEL_CONF : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: CPU sel option*/ +#define RTC_CNTL_CPUSEL_CONF (BIT(29)) +#define RTC_CNTL_CPUSEL_CONF_M (BIT(29)) +#define RTC_CNTL_CPUSEL_CONF_V 0x1 +#define RTC_CNTL_CPUSEL_CONF_S 29 + +#define RTC_CNTL_SDIO_ACT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x6c) +/* RTC_CNTL_SDIO_ACT_DNUM : R/W ;bitpos:[31:22] ;default: 10'b0 ; */ +/*description: */ +#define RTC_CNTL_SDIO_ACT_DNUM 0x000003FF +#define RTC_CNTL_SDIO_ACT_DNUM_M ((RTC_CNTL_SDIO_ACT_DNUM_V)<<(RTC_CNTL_SDIO_ACT_DNUM_S)) +#define RTC_CNTL_SDIO_ACT_DNUM_V 0x3FF +#define RTC_CNTL_SDIO_ACT_DNUM_S 22 + +#define RTC_CNTL_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x70) +/* RTC_CNTL_ANA_CLK_RTC_SEL : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ +/*description: slow_clk_rtc sel. 0: SLOW_CK 1: CK_XTAL_32K 2: CK8M_D256_OUT*/ +#define RTC_CNTL_ANA_CLK_RTC_SEL 0x00000003 +#define RTC_CNTL_ANA_CLK_RTC_SEL_M ((RTC_CNTL_ANA_CLK_RTC_SEL_V)<<(RTC_CNTL_ANA_CLK_RTC_SEL_S)) +#define RTC_CNTL_ANA_CLK_RTC_SEL_V 0x3 +#define RTC_CNTL_ANA_CLK_RTC_SEL_S 30 +/* RTC_CNTL_FAST_CLK_RTC_SEL : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: fast_clk_rtc sel. 0: XTAL div 4 1: CK8M*/ +#define RTC_CNTL_FAST_CLK_RTC_SEL (BIT(29)) +#define RTC_CNTL_FAST_CLK_RTC_SEL_M (BIT(29)) +#define RTC_CNTL_FAST_CLK_RTC_SEL_V 0x1 +#define RTC_CNTL_FAST_CLK_RTC_SEL_S 29 +/* RTC_CNTL_SOC_CLK_SEL : R/W ;bitpos:[28:27] ;default: 2'd0 ; */ +/*description: SOC clock sel. 0: XTAL 1: PLL 2: CK8M 3: APLL*/ +#define RTC_CNTL_SOC_CLK_SEL 0x00000003 +#define RTC_CNTL_SOC_CLK_SEL_M ((RTC_CNTL_SOC_CLK_SEL_V)<<(RTC_CNTL_SOC_CLK_SEL_S)) +#define RTC_CNTL_SOC_CLK_SEL_V 0x3 +#define RTC_CNTL_SOC_CLK_SEL_S 27 +/* RTC_CNTL_CK8M_FORCE_PU : R/W ;bitpos:[26] ;default: 1'd0 ; */ +/*description: CK8M force power up*/ +#define RTC_CNTL_CK8M_FORCE_PU (BIT(26)) +#define RTC_CNTL_CK8M_FORCE_PU_M (BIT(26)) +#define RTC_CNTL_CK8M_FORCE_PU_V 0x1 +#define RTC_CNTL_CK8M_FORCE_PU_S 26 +/* RTC_CNTL_CK8M_FORCE_PD : R/W ;bitpos:[25] ;default: 1'd0 ; */ +/*description: CK8M force power down*/ +#define RTC_CNTL_CK8M_FORCE_PD (BIT(25)) +#define RTC_CNTL_CK8M_FORCE_PD_M (BIT(25)) +#define RTC_CNTL_CK8M_FORCE_PD_V 0x1 +#define RTC_CNTL_CK8M_FORCE_PD_S 25 +/* RTC_CNTL_CK8M_DFREQ : R/W ;bitpos:[24:17] ;default: 8'd0 ; */ +/*description: CK8M_DFREQ*/ +#define RTC_CNTL_CK8M_DFREQ 0x000000FF +#define RTC_CNTL_CK8M_DFREQ_M ((RTC_CNTL_CK8M_DFREQ_V)<<(RTC_CNTL_CK8M_DFREQ_S)) +#define RTC_CNTL_CK8M_DFREQ_V 0xFF +#define RTC_CNTL_CK8M_DFREQ_S 17 +#define RTC_CNTL_CK8M_DFREQ_DEFAULT 172 +/* RTC_CNTL_CK8M_FORCE_NOGATING : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: CK8M force no gating during sleep*/ +#define RTC_CNTL_CK8M_FORCE_NOGATING (BIT(16)) +#define RTC_CNTL_CK8M_FORCE_NOGATING_M (BIT(16)) +#define RTC_CNTL_CK8M_FORCE_NOGATING_V 0x1 +#define RTC_CNTL_CK8M_FORCE_NOGATING_S 16 +/* RTC_CNTL_XTAL_FORCE_NOGATING : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: XTAL force no gating during sleep*/ +#define RTC_CNTL_XTAL_FORCE_NOGATING (BIT(15)) +#define RTC_CNTL_XTAL_FORCE_NOGATING_M (BIT(15)) +#define RTC_CNTL_XTAL_FORCE_NOGATING_V 0x1 +#define RTC_CNTL_XTAL_FORCE_NOGATING_S 15 +/* RTC_CNTL_CK8M_DIV_SEL : R/W ;bitpos:[14:12] ;default: 3'd2 ; */ +/*description: divider = reg_ck8m_div_sel + 1*/ +#define RTC_CNTL_CK8M_DIV_SEL 0x00000007 +#define RTC_CNTL_CK8M_DIV_SEL_M ((RTC_CNTL_CK8M_DIV_SEL_V)<<(RTC_CNTL_CK8M_DIV_SEL_S)) +#define RTC_CNTL_CK8M_DIV_SEL_V 0x7 +#define RTC_CNTL_CK8M_DIV_SEL_S 12 +/* RTC_CNTL_CK8M_DFREQ_FORCE : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_CK8M_DFREQ_FORCE (BIT(11)) +#define RTC_CNTL_CK8M_DFREQ_FORCE_M (BIT(11)) +#define RTC_CNTL_CK8M_DFREQ_FORCE_V 0x1 +#define RTC_CNTL_CK8M_DFREQ_FORCE_S 11 +/* RTC_CNTL_DIG_CLK8M_EN : R/W ;bitpos:[10] ;default: 1'd0 ; */ +/*description: enable CK8M for digital core (no relationship with RTC core)*/ +#define RTC_CNTL_DIG_CLK8M_EN (BIT(10)) +#define RTC_CNTL_DIG_CLK8M_EN_M (BIT(10)) +#define RTC_CNTL_DIG_CLK8M_EN_V 0x1 +#define RTC_CNTL_DIG_CLK8M_EN_S 10 +/* RTC_CNTL_DIG_CLK8M_D256_EN : R/W ;bitpos:[9] ;default: 1'd1 ; */ +/*description: enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/ +#define RTC_CNTL_DIG_CLK8M_D256_EN (BIT(9)) +#define RTC_CNTL_DIG_CLK8M_D256_EN_M (BIT(9)) +#define RTC_CNTL_DIG_CLK8M_D256_EN_V 0x1 +#define RTC_CNTL_DIG_CLK8M_D256_EN_S 9 +/* RTC_CNTL_DIG_XTAL32K_EN : R/W ;bitpos:[8] ;default: 1'd0 ; */ +/*description: enable CK_XTAL_32K for digital core (no relationship with RTC core)*/ +#define RTC_CNTL_DIG_XTAL32K_EN (BIT(8)) +#define RTC_CNTL_DIG_XTAL32K_EN_M (BIT(8)) +#define RTC_CNTL_DIG_XTAL32K_EN_V 0x1 +#define RTC_CNTL_DIG_XTAL32K_EN_S 8 +/* RTC_CNTL_ENB_CK8M_DIV : R/W ;bitpos:[7] ;default: 1'd0 ; */ +/*description: 1: CK8M_D256_OUT is actually CK8M 0: CK8M_D256_OUT is CK8M divided by 256*/ +#define RTC_CNTL_ENB_CK8M_DIV (BIT(7)) +#define RTC_CNTL_ENB_CK8M_DIV_M (BIT(7)) +#define RTC_CNTL_ENB_CK8M_DIV_V 0x1 +#define RTC_CNTL_ENB_CK8M_DIV_S 7 +/* RTC_CNTL_ENB_CK8M : R/W ;bitpos:[6] ;default: 1'd0 ; */ +/*description: disable CK8M and CK8M_D256_OUT*/ +#define RTC_CNTL_ENB_CK8M (BIT(6)) +#define RTC_CNTL_ENB_CK8M_M (BIT(6)) +#define RTC_CNTL_ENB_CK8M_V 0x1 +#define RTC_CNTL_ENB_CK8M_S 6 +/* RTC_CNTL_CK8M_DIV : R/W ;bitpos:[5:4] ;default: 2'b01 ; */ +/*description: CK8M_D256_OUT divider. 00: div128 01: div256 10: div512 11: div1024.*/ +#define RTC_CNTL_CK8M_DIV 0x00000003 +#define RTC_CNTL_CK8M_DIV_M ((RTC_CNTL_CK8M_DIV_V)<<(RTC_CNTL_CK8M_DIV_S)) +#define RTC_CNTL_CK8M_DIV_V 0x3 +#define RTC_CNTL_CK8M_DIV_S 4 + +#define RTC_CNTL_SDIO_CONF_REG (DR_REG_RTCCNTL_BASE + 0x74) +/* RTC_CNTL_XPD_SDIO_REG : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: SW option for XPD_SDIO_REG. Only active when reg_sdio_force = 1*/ +#define RTC_CNTL_XPD_SDIO_REG (BIT(31)) +#define RTC_CNTL_XPD_SDIO_REG_M (BIT(31)) +#define RTC_CNTL_XPD_SDIO_REG_V 0x1 +#define RTC_CNTL_XPD_SDIO_REG_S 31 +/* RTC_CNTL_DREFH_SDIO : R/W ;bitpos:[30:29] ;default: 2'b00 ; */ +/*description: SW option for DREFH_SDIO. Only active when reg_sdio_force = 1*/ +#define RTC_CNTL_DREFH_SDIO 0x00000003 +#define RTC_CNTL_DREFH_SDIO_M ((RTC_CNTL_DREFH_SDIO_V)<<(RTC_CNTL_DREFH_SDIO_S)) +#define RTC_CNTL_DREFH_SDIO_V 0x3 +#define RTC_CNTL_DREFH_SDIO_S 29 +/* RTC_CNTL_DREFM_SDIO : R/W ;bitpos:[28:27] ;default: 2'b00 ; */ +/*description: SW option for DREFM_SDIO. Only active when reg_sdio_force = 1*/ +#define RTC_CNTL_DREFM_SDIO 0x00000003 +#define RTC_CNTL_DREFM_SDIO_M ((RTC_CNTL_DREFM_SDIO_V)<<(RTC_CNTL_DREFM_SDIO_S)) +#define RTC_CNTL_DREFM_SDIO_V 0x3 +#define RTC_CNTL_DREFM_SDIO_S 27 +/* RTC_CNTL_DREFL_SDIO : R/W ;bitpos:[26:25] ;default: 2'b01 ; */ +/*description: SW option for DREFL_SDIO. Only active when reg_sdio_force = 1*/ +#define RTC_CNTL_DREFL_SDIO 0x00000003 +#define RTC_CNTL_DREFL_SDIO_M ((RTC_CNTL_DREFL_SDIO_V)<<(RTC_CNTL_DREFL_SDIO_S)) +#define RTC_CNTL_DREFL_SDIO_V 0x3 +#define RTC_CNTL_DREFL_SDIO_S 25 +/* RTC_CNTL_REG1P8_READY : RO ;bitpos:[24] ;default: 1'd0 ; */ +/*description: read only register for REG1P8_READY*/ +#define RTC_CNTL_REG1P8_READY (BIT(24)) +#define RTC_CNTL_REG1P8_READY_M (BIT(24)) +#define RTC_CNTL_REG1P8_READY_V 0x1 +#define RTC_CNTL_REG1P8_READY_S 24 +/* RTC_CNTL_SDIO_TIEH : R/W ;bitpos:[23] ;default: 1'd1 ; */ +/*description: SW option for SDIO_TIEH. Only active when reg_sdio_force = 1*/ +#define RTC_CNTL_SDIO_TIEH (BIT(23)) +#define RTC_CNTL_SDIO_TIEH_M (BIT(23)) +#define RTC_CNTL_SDIO_TIEH_V 0x1 +#define RTC_CNTL_SDIO_TIEH_S 23 +/* RTC_CNTL_SDIO_FORCE : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: 1: use SW option to control SDIO_REG 0: use state machine*/ +#define RTC_CNTL_SDIO_FORCE (BIT(22)) +#define RTC_CNTL_SDIO_FORCE_M (BIT(22)) +#define RTC_CNTL_SDIO_FORCE_V 0x1 +#define RTC_CNTL_SDIO_FORCE_S 22 +/* RTC_CNTL_SDIO_PD_EN : R/W ;bitpos:[21] ;default: 1'd1 ; */ +/*description: power down SDIO_REG in sleep. Only active when reg_sdio_force = 0*/ +#define RTC_CNTL_SDIO_PD_EN (BIT(21)) +#define RTC_CNTL_SDIO_PD_EN_M (BIT(21)) +#define RTC_CNTL_SDIO_PD_EN_V 0x1 +#define RTC_CNTL_SDIO_PD_EN_S 21 + +#define RTC_CNTL_BIAS_CONF_REG (DR_REG_RTCCNTL_BASE + 0x78) +/* RTC_CNTL_RST_BIAS_I2C : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: RST_BIAS_I2C*/ +#define RTC_CNTL_RST_BIAS_I2C (BIT(31)) +#define RTC_CNTL_RST_BIAS_I2C_M (BIT(31)) +#define RTC_CNTL_RST_BIAS_I2C_V 0x1 +#define RTC_CNTL_RST_BIAS_I2C_S 31 +/* RTC_CNTL_DEC_HEARTBEAT_WIDTH : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: DEC_HEARTBEAT_WIDTH*/ +#define RTC_CNTL_DEC_HEARTBEAT_WIDTH (BIT(30)) +#define RTC_CNTL_DEC_HEARTBEAT_WIDTH_M (BIT(30)) +#define RTC_CNTL_DEC_HEARTBEAT_WIDTH_V 0x1 +#define RTC_CNTL_DEC_HEARTBEAT_WIDTH_S 30 +/* RTC_CNTL_INC_HEARTBEAT_PERIOD : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: INC_HEARTBEAT_PERIOD*/ +#define RTC_CNTL_INC_HEARTBEAT_PERIOD (BIT(29)) +#define RTC_CNTL_INC_HEARTBEAT_PERIOD_M (BIT(29)) +#define RTC_CNTL_INC_HEARTBEAT_PERIOD_V 0x1 +#define RTC_CNTL_INC_HEARTBEAT_PERIOD_S 29 +/* RTC_CNTL_DEC_HEARTBEAT_PERIOD : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: DEC_HEARTBEAT_PERIOD*/ +#define RTC_CNTL_DEC_HEARTBEAT_PERIOD (BIT(28)) +#define RTC_CNTL_DEC_HEARTBEAT_PERIOD_M (BIT(28)) +#define RTC_CNTL_DEC_HEARTBEAT_PERIOD_V 0x1 +#define RTC_CNTL_DEC_HEARTBEAT_PERIOD_S 28 +/* RTC_CNTL_INC_HEARTBEAT_REFRESH : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: INC_HEARTBEAT_REFRESH*/ +#define RTC_CNTL_INC_HEARTBEAT_REFRESH (BIT(27)) +#define RTC_CNTL_INC_HEARTBEAT_REFRESH_M (BIT(27)) +#define RTC_CNTL_INC_HEARTBEAT_REFRESH_V 0x1 +#define RTC_CNTL_INC_HEARTBEAT_REFRESH_S 27 +/* RTC_CNTL_ENB_SCK_XTAL : R/W ;bitpos:[26] ;default: 1'd0 ; */ +/*description: ENB_SCK_XTAL*/ +#define RTC_CNTL_ENB_SCK_XTAL (BIT(26)) +#define RTC_CNTL_ENB_SCK_XTAL_M (BIT(26)) +#define RTC_CNTL_ENB_SCK_XTAL_V 0x1 +#define RTC_CNTL_ENB_SCK_XTAL_S 26 +/* RTC_CNTL_DBG_ATTEN : R/W ;bitpos:[25:24] ;default: 2'b00 ; */ +/*description: DBG_ATTEN*/ +#define RTC_CNTL_DBG_ATTEN 0x00000003 +#define RTC_CNTL_DBG_ATTEN_M ((RTC_CNTL_DBG_ATTEN_V)<<(RTC_CNTL_DBG_ATTEN_S)) +#define RTC_CNTL_DBG_ATTEN_V 0x3 +#define RTC_CNTL_DBG_ATTEN_S 24 +#define RTC_CNTL_DBG_ATTEN_DEFAULT 3 +#define RTC_CNTL_DBG_ATTEN_NODROP 0 +#define RTC_CNTL_REG (DR_REG_RTCCNTL_BASE + 0x7c) +/* RTC_CNTL_FORCE_PU : R/W ;bitpos:[31] ;default: 1'd1 ; */ +/*description: RTC_REG force power up*/ +#define RTC_CNTL_FORCE_PU (BIT(31)) +#define RTC_CNTL_FORCE_PU_M (BIT(31)) +#define RTC_CNTL_FORCE_PU_V 0x1 +#define RTC_CNTL_FORCE_PU_S 31 +/* RTC_CNTL_FORCE_PD : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: RTC_REG force power down (for RTC_REG power down means decrease + the voltage to 0.8v or lower )*/ +#define RTC_CNTL_FORCE_PD (BIT(30)) +#define RTC_CNTL_FORCE_PD_M (BIT(30)) +#define RTC_CNTL_FORCE_PD_V 0x1 +#define RTC_CNTL_FORCE_PD_S 30 +/* RTC_CNTL_DBOOST_FORCE_PU : R/W ;bitpos:[29] ;default: 1'd1 ; */ +/*description: RTC_DBOOST force power up*/ +#define RTC_CNTL_DBOOST_FORCE_PU (BIT(29)) +#define RTC_CNTL_DBOOST_FORCE_PU_M (BIT(29)) +#define RTC_CNTL_DBOOST_FORCE_PU_V 0x1 +#define RTC_CNTL_DBOOST_FORCE_PU_S 29 +/* RTC_CNTL_DBOOST_FORCE_PD : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: RTC_DBOOST force power down*/ +#define RTC_CNTL_DBOOST_FORCE_PD (BIT(28)) +#define RTC_CNTL_DBOOST_FORCE_PD_M (BIT(28)) +#define RTC_CNTL_DBOOST_FORCE_PD_V 0x1 +#define RTC_CNTL_DBOOST_FORCE_PD_S 28 +/* RTC_CNTL_DBIAS_WAK : R/W ;bitpos:[27:25] ;default: 3'd4 ; */ +/*description: RTC_DBIAS during wakeup*/ +#define RTC_CNTL_DBIAS_WAK 0x00000007 +#define RTC_CNTL_DBIAS_WAK_M ((RTC_CNTL_DBIAS_WAK_V)<<(RTC_CNTL_DBIAS_WAK_S)) +#define RTC_CNTL_DBIAS_WAK_V 0x7 +#define RTC_CNTL_DBIAS_WAK_S 25 +/* RTC_CNTL_DBIAS_SLP : R/W ;bitpos:[24:22] ;default: 3'd4 ; */ +/*description: RTC_DBIAS during sleep*/ +#define RTC_CNTL_DBIAS_SLP 0x00000007 +#define RTC_CNTL_DBIAS_SLP_M ((RTC_CNTL_DBIAS_SLP_V)<<(RTC_CNTL_DBIAS_SLP_S)) +#define RTC_CNTL_DBIAS_SLP_V 0x7 +#define RTC_CNTL_DBIAS_SLP_S 22 +/* RTC_CNTL_SCK_DCAP : R/W ;bitpos:[21:14] ;default: 8'd0 ; */ +/*description: SCK_DCAP*/ +#define RTC_CNTL_SCK_DCAP 0x000000FF +#define RTC_CNTL_SCK_DCAP_M ((RTC_CNTL_SCK_DCAP_V)<<(RTC_CNTL_SCK_DCAP_S)) +#define RTC_CNTL_SCK_DCAP_V 0xFF +#define RTC_CNTL_SCK_DCAP_S 14 +#define RTC_CNTL_SCK_DCAP_DEFAULT 255 +/* RTC_CNTL_DIG_DBIAS_WAK : R/W ;bitpos:[13:11] ;default: 3'd4 ; */ +/*description: DIG_REG_DBIAS during wakeup*/ +#define RTC_CNTL_DIG_DBIAS_WAK 0x00000007 +#define RTC_CNTL_DIG_DBIAS_WAK_M ((RTC_CNTL_DIG_DBIAS_WAK_V)<<(RTC_CNTL_DIG_DBIAS_WAK_S)) +#define RTC_CNTL_DIG_DBIAS_WAK_V 0x7 +#define RTC_CNTL_DIG_DBIAS_WAK_S 11 +/* RTC_CNTL_DIG_DBIAS_SLP : R/W ;bitpos:[10:8] ;default: 3'd4 ; */ +/*description: DIG_REG_DBIAS during sleep*/ +#define RTC_CNTL_DIG_DBIAS_SLP 0x00000007 +#define RTC_CNTL_DIG_DBIAS_SLP_M ((RTC_CNTL_DIG_DBIAS_SLP_V)<<(RTC_CNTL_DIG_DBIAS_SLP_S)) +#define RTC_CNTL_DIG_DBIAS_SLP_V 0x7 +#define RTC_CNTL_DIG_DBIAS_SLP_S 8 +/* RTC_CNTL_SCK_DCAP_FORCE : R/W ;bitpos:[7] ;default: 1'd0 ; */ +/*description: N/A*/ +#define RTC_CNTL_SCK_DCAP_FORCE (BIT(7)) +#define RTC_CNTL_SCK_DCAP_FORCE_M (BIT(7)) +#define RTC_CNTL_SCK_DCAP_FORCE_V 0x1 +#define RTC_CNTL_SCK_DCAP_FORCE_S 7 + +/* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP, + * RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values. + * Valid if RTC_CNTL_DBG_ATTEN is 0. + */ +#define RTC_CNTL_DBIAS_0V90 0 +#define RTC_CNTL_DBIAS_0V95 1 +#define RTC_CNTL_DBIAS_1V00 2 +#define RTC_CNTL_DBIAS_1V05 3 +#define RTC_CNTL_DBIAS_1V10 4 +#define RTC_CNTL_DBIAS_1V15 5 +#define RTC_CNTL_DBIAS_1V20 6 +#define RTC_CNTL_DBIAS_1V25 7 + +#define RTC_CNTL_PWC_REG (DR_REG_RTCCNTL_BASE + 0x80) +/* RTC_CNTL_PD_EN : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: enable power down rtc_peri in sleep*/ +#define RTC_CNTL_PD_EN (BIT(20)) +#define RTC_CNTL_PD_EN_M (BIT(20)) +#define RTC_CNTL_PD_EN_V 0x1 +#define RTC_CNTL_PD_EN_S 20 +/* RTC_CNTL_FORCE_PU : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: rtc_peri force power up*/ +#define RTC_CNTL_PWC_FORCE_PU (BIT(19)) +#define RTC_CNTL_PWC_FORCE_PU_M (BIT(19)) +#define RTC_CNTL_PWC_FORCE_PU_V 0x1 +#define RTC_CNTL_PWC_FORCE_PU_S 19 +/* RTC_CNTL_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: rtc_peri force power down*/ +#define RTC_CNTL_PWC_FORCE_PD (BIT(18)) +#define RTC_CNTL_PWC_FORCE_PD_M (BIT(18)) +#define RTC_CNTL_PWC_FORCE_PD_V 0x1 +#define RTC_CNTL_PWC_FORCE_PD_S 18 +/* RTC_CNTL_SLOWMEM_PD_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: enable power down RTC memory in sleep*/ +#define RTC_CNTL_SLOWMEM_PD_EN (BIT(17)) +#define RTC_CNTL_SLOWMEM_PD_EN_M (BIT(17)) +#define RTC_CNTL_SLOWMEM_PD_EN_V 0x1 +#define RTC_CNTL_SLOWMEM_PD_EN_S 17 +/* RTC_CNTL_SLOWMEM_FORCE_PU : R/W ;bitpos:[16] ;default: 1'b1 ; */ +/*description: RTC memory force power up*/ +#define RTC_CNTL_SLOWMEM_FORCE_PU (BIT(16)) +#define RTC_CNTL_SLOWMEM_FORCE_PU_M (BIT(16)) +#define RTC_CNTL_SLOWMEM_FORCE_PU_V 0x1 +#define RTC_CNTL_SLOWMEM_FORCE_PU_S 16 +/* RTC_CNTL_SLOWMEM_FORCE_PD : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: RTC memory force power down*/ +#define RTC_CNTL_SLOWMEM_FORCE_PD (BIT(15)) +#define RTC_CNTL_SLOWMEM_FORCE_PD_M (BIT(15)) +#define RTC_CNTL_SLOWMEM_FORCE_PD_V 0x1 +#define RTC_CNTL_SLOWMEM_FORCE_PD_S 15 +/* RTC_CNTL_FASTMEM_PD_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: enable power down fast RTC memory in sleep*/ +#define RTC_CNTL_FASTMEM_PD_EN (BIT(14)) +#define RTC_CNTL_FASTMEM_PD_EN_M (BIT(14)) +#define RTC_CNTL_FASTMEM_PD_EN_V 0x1 +#define RTC_CNTL_FASTMEM_PD_EN_S 14 +/* RTC_CNTL_FASTMEM_FORCE_PU : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: Fast RTC memory force power up*/ +#define RTC_CNTL_FASTMEM_FORCE_PU (BIT(13)) +#define RTC_CNTL_FASTMEM_FORCE_PU_M (BIT(13)) +#define RTC_CNTL_FASTMEM_FORCE_PU_V 0x1 +#define RTC_CNTL_FASTMEM_FORCE_PU_S 13 +/* RTC_CNTL_FASTMEM_FORCE_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Fast RTC memory force power down*/ +#define RTC_CNTL_FASTMEM_FORCE_PD (BIT(12)) +#define RTC_CNTL_FASTMEM_FORCE_PD_M (BIT(12)) +#define RTC_CNTL_FASTMEM_FORCE_PD_V 0x1 +#define RTC_CNTL_FASTMEM_FORCE_PD_S 12 +/* RTC_CNTL_SLOWMEM_FORCE_LPU : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: RTC memory force no PD*/ +#define RTC_CNTL_SLOWMEM_FORCE_LPU (BIT(11)) +#define RTC_CNTL_SLOWMEM_FORCE_LPU_M (BIT(11)) +#define RTC_CNTL_SLOWMEM_FORCE_LPU_V 0x1 +#define RTC_CNTL_SLOWMEM_FORCE_LPU_S 11 +/* RTC_CNTL_SLOWMEM_FORCE_LPD : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: RTC memory force PD*/ +#define RTC_CNTL_SLOWMEM_FORCE_LPD (BIT(10)) +#define RTC_CNTL_SLOWMEM_FORCE_LPD_M (BIT(10)) +#define RTC_CNTL_SLOWMEM_FORCE_LPD_V 0x1 +#define RTC_CNTL_SLOWMEM_FORCE_LPD_S 10 +/* RTC_CNTL_SLOWMEM_FOLW_CPU : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: 1: RTC memory PD following CPU 0: RTC memory PD following RTC state machine*/ +#define RTC_CNTL_SLOWMEM_FOLW_CPU (BIT(9)) +#define RTC_CNTL_SLOWMEM_FOLW_CPU_M (BIT(9)) +#define RTC_CNTL_SLOWMEM_FOLW_CPU_V 0x1 +#define RTC_CNTL_SLOWMEM_FOLW_CPU_S 9 +/* RTC_CNTL_FASTMEM_FORCE_LPU : R/W ;bitpos:[8] ;default: 1'b1 ; */ +/*description: Fast RTC memory force no PD*/ +#define RTC_CNTL_FASTMEM_FORCE_LPU (BIT(8)) +#define RTC_CNTL_FASTMEM_FORCE_LPU_M (BIT(8)) +#define RTC_CNTL_FASTMEM_FORCE_LPU_V 0x1 +#define RTC_CNTL_FASTMEM_FORCE_LPU_S 8 +/* RTC_CNTL_FASTMEM_FORCE_LPD : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Fast RTC memory force PD*/ +#define RTC_CNTL_FASTMEM_FORCE_LPD (BIT(7)) +#define RTC_CNTL_FASTMEM_FORCE_LPD_M (BIT(7)) +#define RTC_CNTL_FASTMEM_FORCE_LPD_V 0x1 +#define RTC_CNTL_FASTMEM_FORCE_LPD_S 7 +/* RTC_CNTL_FASTMEM_FOLW_CPU : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: 1: Fast RTC memory PD following CPU 0: fast RTC memory PD following + RTC state machine*/ +#define RTC_CNTL_FASTMEM_FOLW_CPU (BIT(6)) +#define RTC_CNTL_FASTMEM_FOLW_CPU_M (BIT(6)) +#define RTC_CNTL_FASTMEM_FOLW_CPU_V 0x1 +#define RTC_CNTL_FASTMEM_FOLW_CPU_S 6 +/* RTC_CNTL_FORCE_NOISO : R/W ;bitpos:[5] ;default: 1'd1 ; */ +/*description: rtc_peri force no ISO*/ +#define RTC_CNTL_FORCE_NOISO (BIT(5)) +#define RTC_CNTL_FORCE_NOISO_M (BIT(5)) +#define RTC_CNTL_FORCE_NOISO_V 0x1 +#define RTC_CNTL_FORCE_NOISO_S 5 +/* RTC_CNTL_FORCE_ISO : R/W ;bitpos:[4] ;default: 1'd0 ; */ +/*description: rtc_peri force ISO*/ +#define RTC_CNTL_FORCE_ISO (BIT(4)) +#define RTC_CNTL_FORCE_ISO_M (BIT(4)) +#define RTC_CNTL_FORCE_ISO_V 0x1 +#define RTC_CNTL_FORCE_ISO_S 4 +/* RTC_CNTL_SLOWMEM_FORCE_ISO : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: RTC memory force ISO*/ +#define RTC_CNTL_SLOWMEM_FORCE_ISO (BIT(3)) +#define RTC_CNTL_SLOWMEM_FORCE_ISO_M (BIT(3)) +#define RTC_CNTL_SLOWMEM_FORCE_ISO_V 0x1 +#define RTC_CNTL_SLOWMEM_FORCE_ISO_S 3 +/* RTC_CNTL_SLOWMEM_FORCE_NOISO : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: RTC memory force no ISO*/ +#define RTC_CNTL_SLOWMEM_FORCE_NOISO (BIT(2)) +#define RTC_CNTL_SLOWMEM_FORCE_NOISO_M (BIT(2)) +#define RTC_CNTL_SLOWMEM_FORCE_NOISO_V 0x1 +#define RTC_CNTL_SLOWMEM_FORCE_NOISO_S 2 +/* RTC_CNTL_FASTMEM_FORCE_ISO : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Fast RTC memory force ISO*/ +#define RTC_CNTL_FASTMEM_FORCE_ISO (BIT(1)) +#define RTC_CNTL_FASTMEM_FORCE_ISO_M (BIT(1)) +#define RTC_CNTL_FASTMEM_FORCE_ISO_V 0x1 +#define RTC_CNTL_FASTMEM_FORCE_ISO_S 1 +/* RTC_CNTL_FASTMEM_FORCE_NOISO : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: Fast RTC memory force no ISO*/ +#define RTC_CNTL_FASTMEM_FORCE_NOISO (BIT(0)) +#define RTC_CNTL_FASTMEM_FORCE_NOISO_M (BIT(0)) +#define RTC_CNTL_FASTMEM_FORCE_NOISO_V 0x1 +#define RTC_CNTL_FASTMEM_FORCE_NOISO_S 0 + +/* Useful groups of RTC_CNTL_PWC_REG bits */ +#define RTC_CNTL_MEM_FORCE_ISO \ + (RTC_CNTL_SLOWMEM_FORCE_ISO | RTC_CNTL_FASTMEM_FORCE_ISO) +#define RTC_CNTL_MEM_FORCE_NOISO \ + (RTC_CNTL_SLOWMEM_FORCE_NOISO | RTC_CNTL_FASTMEM_FORCE_NOISO) +#define RTC_CNTL_MEM_PD_EN \ + (RTC_CNTL_SLOWMEM_PD_EN | RTC_CNTL_FASTMEM_PD_EN) +#define RTC_CNTL_MEM_FORCE_PU \ + (RTC_CNTL_SLOWMEM_FORCE_PU | RTC_CNTL_FASTMEM_FORCE_PU) +#define RTC_CNTL_MEM_FORCE_PD \ + (RTC_CNTL_SLOWMEM_FORCE_PD | RTC_CNTL_FASTMEM_FORCE_PD) +#define RTC_CNTL_MEM_FOLW_CPU \ + (RTC_CNTL_SLOWMEM_FOLW_CPU | RTC_CNTL_FASTMEM_FOLW_CPU) +#define RTC_CNTL_MEM_FORCE_LPU \ + (RTC_CNTL_SLOWMEM_FORCE_LPU | RTC_CNTL_FASTMEM_FORCE_LPU) +#define RTC_CNTL_MEM_FORCE_LPD \ + (RTC_CNTL_SLOWMEM_FORCE_LPD | RTC_CNTL_FASTMEM_FORCE_LPD) + +#define RTC_CNTL_DIG_PWC_REG (DR_REG_RTCCNTL_BASE + 0x84) +/* RTC_CNTL_DG_WRAP_PD_EN : R/W ;bitpos:[31] ;default: 0 ; */ +/*description: enable power down digital core in sleep*/ +#define RTC_CNTL_DG_WRAP_PD_EN (BIT(31)) +#define RTC_CNTL_DG_WRAP_PD_EN_M (BIT(31)) +#define RTC_CNTL_DG_WRAP_PD_EN_V 0x1 +#define RTC_CNTL_DG_WRAP_PD_EN_S 31 +/* RTC_CNTL_WIFI_PD_EN : R/W ;bitpos:[30] ;default: 0 ; */ +/*description: enable power down wifi in sleep*/ +#define RTC_CNTL_WIFI_PD_EN (BIT(30)) +#define RTC_CNTL_WIFI_PD_EN_M (BIT(30)) +#define RTC_CNTL_WIFI_PD_EN_V 0x1 +#define RTC_CNTL_WIFI_PD_EN_S 30 +/* RTC_CNTL_INTER_RAM4_PD_EN : R/W ;bitpos:[29] ;default: 0 ; */ +/*description: enable power down internal SRAM 4 in sleep*/ +#define RTC_CNTL_INTER_RAM4_PD_EN (BIT(29)) +#define RTC_CNTL_INTER_RAM4_PD_EN_M (BIT(29)) +#define RTC_CNTL_INTER_RAM4_PD_EN_V 0x1 +#define RTC_CNTL_INTER_RAM4_PD_EN_S 29 +/* RTC_CNTL_INTER_RAM3_PD_EN : R/W ;bitpos:[28] ;default: 0 ; */ +/*description: enable power down internal SRAM 3 in sleep*/ +#define RTC_CNTL_INTER_RAM3_PD_EN (BIT(28)) +#define RTC_CNTL_INTER_RAM3_PD_EN_M (BIT(28)) +#define RTC_CNTL_INTER_RAM3_PD_EN_V 0x1 +#define RTC_CNTL_INTER_RAM3_PD_EN_S 28 +/* RTC_CNTL_INTER_RAM2_PD_EN : R/W ;bitpos:[27] ;default: 0 ; */ +/*description: enable power down internal SRAM 2 in sleep*/ +#define RTC_CNTL_INTER_RAM2_PD_EN (BIT(27)) +#define RTC_CNTL_INTER_RAM2_PD_EN_M (BIT(27)) +#define RTC_CNTL_INTER_RAM2_PD_EN_V 0x1 +#define RTC_CNTL_INTER_RAM2_PD_EN_S 27 +/* RTC_CNTL_INTER_RAM1_PD_EN : R/W ;bitpos:[26] ;default: 0 ; */ +/*description: enable power down internal SRAM 1 in sleep*/ +#define RTC_CNTL_INTER_RAM1_PD_EN (BIT(26)) +#define RTC_CNTL_INTER_RAM1_PD_EN_M (BIT(26)) +#define RTC_CNTL_INTER_RAM1_PD_EN_V 0x1 +#define RTC_CNTL_INTER_RAM1_PD_EN_S 26 +/* RTC_CNTL_INTER_RAM0_PD_EN : R/W ;bitpos:[25] ;default: 0 ; */ +/*description: enable power down internal SRAM 0 in sleep*/ +#define RTC_CNTL_INTER_RAM0_PD_EN (BIT(25)) +#define RTC_CNTL_INTER_RAM0_PD_EN_M (BIT(25)) +#define RTC_CNTL_INTER_RAM0_PD_EN_V 0x1 +#define RTC_CNTL_INTER_RAM0_PD_EN_S 25 +/* RTC_CNTL_ROM0_PD_EN : R/W ;bitpos:[24] ;default: 0 ; */ +/*description: enable power down ROM in sleep*/ +#define RTC_CNTL_ROM0_PD_EN (BIT(24)) +#define RTC_CNTL_ROM0_PD_EN_M (BIT(24)) +#define RTC_CNTL_ROM0_PD_EN_V 0x1 +#define RTC_CNTL_ROM0_PD_EN_S 24 +/* RTC_CNTL_DG_WRAP_FORCE_PU : R/W ;bitpos:[20] ;default: 1'd1 ; */ +/*description: digital core force power up*/ +#define RTC_CNTL_DG_WRAP_FORCE_PU (BIT(20)) +#define RTC_CNTL_DG_WRAP_FORCE_PU_M (BIT(20)) +#define RTC_CNTL_DG_WRAP_FORCE_PU_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_PU_S 20 +/* RTC_CNTL_DG_WRAP_FORCE_PD : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: digital core force power down*/ +#define RTC_CNTL_DG_WRAP_FORCE_PD (BIT(19)) +#define RTC_CNTL_DG_WRAP_FORCE_PD_M (BIT(19)) +#define RTC_CNTL_DG_WRAP_FORCE_PD_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_PD_S 19 +/* RTC_CNTL_WIFI_FORCE_PU : R/W ;bitpos:[18] ;default: 1'd1 ; */ +/*description: wifi force power up*/ +#define RTC_CNTL_WIFI_FORCE_PU (BIT(18)) +#define RTC_CNTL_WIFI_FORCE_PU_M (BIT(18)) +#define RTC_CNTL_WIFI_FORCE_PU_V 0x1 +#define RTC_CNTL_WIFI_FORCE_PU_S 18 +/* RTC_CNTL_WIFI_FORCE_PD : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: wifi force power down*/ +#define RTC_CNTL_WIFI_FORCE_PD (BIT(17)) +#define RTC_CNTL_WIFI_FORCE_PD_M (BIT(17)) +#define RTC_CNTL_WIFI_FORCE_PD_V 0x1 +#define RTC_CNTL_WIFI_FORCE_PD_S 17 +/* RTC_CNTL_INTER_RAM4_FORCE_PU : R/W ;bitpos:[16] ;default: 1'd1 ; */ +/*description: internal SRAM 4 force power up*/ +#define RTC_CNTL_INTER_RAM4_FORCE_PU (BIT(16)) +#define RTC_CNTL_INTER_RAM4_FORCE_PU_M (BIT(16)) +#define RTC_CNTL_INTER_RAM4_FORCE_PU_V 0x1 +#define RTC_CNTL_INTER_RAM4_FORCE_PU_S 16 +/* RTC_CNTL_INTER_RAM4_FORCE_PD : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: internal SRAM 4 force power down*/ +#define RTC_CNTL_INTER_RAM4_FORCE_PD (BIT(15)) +#define RTC_CNTL_INTER_RAM4_FORCE_PD_M (BIT(15)) +#define RTC_CNTL_INTER_RAM4_FORCE_PD_V 0x1 +#define RTC_CNTL_INTER_RAM4_FORCE_PD_S 15 +/* RTC_CNTL_INTER_RAM3_FORCE_PU : R/W ;bitpos:[14] ;default: 1'd1 ; */ +/*description: internal SRAM 3 force power up*/ +#define RTC_CNTL_INTER_RAM3_FORCE_PU (BIT(14)) +#define RTC_CNTL_INTER_RAM3_FORCE_PU_M (BIT(14)) +#define RTC_CNTL_INTER_RAM3_FORCE_PU_V 0x1 +#define RTC_CNTL_INTER_RAM3_FORCE_PU_S 14 +/* RTC_CNTL_INTER_RAM3_FORCE_PD : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: internal SRAM 3 force power down*/ +#define RTC_CNTL_INTER_RAM3_FORCE_PD (BIT(13)) +#define RTC_CNTL_INTER_RAM3_FORCE_PD_M (BIT(13)) +#define RTC_CNTL_INTER_RAM3_FORCE_PD_V 0x1 +#define RTC_CNTL_INTER_RAM3_FORCE_PD_S 13 +/* RTC_CNTL_INTER_RAM2_FORCE_PU : R/W ;bitpos:[12] ;default: 1'd1 ; */ +/*description: internal SRAM 2 force power up*/ +#define RTC_CNTL_INTER_RAM2_FORCE_PU (BIT(12)) +#define RTC_CNTL_INTER_RAM2_FORCE_PU_M (BIT(12)) +#define RTC_CNTL_INTER_RAM2_FORCE_PU_V 0x1 +#define RTC_CNTL_INTER_RAM2_FORCE_PU_S 12 +/* RTC_CNTL_INTER_RAM2_FORCE_PD : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: internal SRAM 2 force power down*/ +#define RTC_CNTL_INTER_RAM2_FORCE_PD (BIT(11)) +#define RTC_CNTL_INTER_RAM2_FORCE_PD_M (BIT(11)) +#define RTC_CNTL_INTER_RAM2_FORCE_PD_V 0x1 +#define RTC_CNTL_INTER_RAM2_FORCE_PD_S 11 +/* RTC_CNTL_INTER_RAM1_FORCE_PU : R/W ;bitpos:[10] ;default: 1'd1 ; */ +/*description: internal SRAM 1 force power up*/ +#define RTC_CNTL_INTER_RAM1_FORCE_PU (BIT(10)) +#define RTC_CNTL_INTER_RAM1_FORCE_PU_M (BIT(10)) +#define RTC_CNTL_INTER_RAM1_FORCE_PU_V 0x1 +#define RTC_CNTL_INTER_RAM1_FORCE_PU_S 10 +/* RTC_CNTL_INTER_RAM1_FORCE_PD : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: internal SRAM 1 force power down*/ +#define RTC_CNTL_INTER_RAM1_FORCE_PD (BIT(9)) +#define RTC_CNTL_INTER_RAM1_FORCE_PD_M (BIT(9)) +#define RTC_CNTL_INTER_RAM1_FORCE_PD_V 0x1 +#define RTC_CNTL_INTER_RAM1_FORCE_PD_S 9 +/* RTC_CNTL_INTER_RAM0_FORCE_PU : R/W ;bitpos:[8] ;default: 1'd1 ; */ +/*description: internal SRAM 0 force power up*/ +#define RTC_CNTL_INTER_RAM0_FORCE_PU (BIT(8)) +#define RTC_CNTL_INTER_RAM0_FORCE_PU_M (BIT(8)) +#define RTC_CNTL_INTER_RAM0_FORCE_PU_V 0x1 +#define RTC_CNTL_INTER_RAM0_FORCE_PU_S 8 +/* RTC_CNTL_INTER_RAM0_FORCE_PD : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: internal SRAM 0 force power down*/ +#define RTC_CNTL_INTER_RAM0_FORCE_PD (BIT(7)) +#define RTC_CNTL_INTER_RAM0_FORCE_PD_M (BIT(7)) +#define RTC_CNTL_INTER_RAM0_FORCE_PD_V 0x1 +#define RTC_CNTL_INTER_RAM0_FORCE_PD_S 7 +/* RTC_CNTL_ROM0_FORCE_PU : R/W ;bitpos:[6] ;default: 1'd1 ; */ +/*description: ROM force power up*/ +#define RTC_CNTL_ROM0_FORCE_PU (BIT(6)) +#define RTC_CNTL_ROM0_FORCE_PU_M (BIT(6)) +#define RTC_CNTL_ROM0_FORCE_PU_V 0x1 +#define RTC_CNTL_ROM0_FORCE_PU_S 6 +/* RTC_CNTL_ROM0_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: ROM force power down*/ +#define RTC_CNTL_ROM0_FORCE_PD (BIT(5)) +#define RTC_CNTL_ROM0_FORCE_PD_M (BIT(5)) +#define RTC_CNTL_ROM0_FORCE_PD_V 0x1 +#define RTC_CNTL_ROM0_FORCE_PD_S 5 +/* RTC_CNTL_LSLP_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: memories in digital core force no PD in sleep*/ +#define RTC_CNTL_LSLP_MEM_FORCE_PU (BIT(4)) +#define RTC_CNTL_LSLP_MEM_FORCE_PU_M (BIT(4)) +#define RTC_CNTL_LSLP_MEM_FORCE_PU_V 0x1 +#define RTC_CNTL_LSLP_MEM_FORCE_PU_S 4 +/* RTC_CNTL_LSLP_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: memories in digital core force PD in sleep*/ +#define RTC_CNTL_LSLP_MEM_FORCE_PD (BIT(3)) +#define RTC_CNTL_LSLP_MEM_FORCE_PD_M (BIT(3)) +#define RTC_CNTL_LSLP_MEM_FORCE_PD_V 0x1 +#define RTC_CNTL_LSLP_MEM_FORCE_PD_S 3 + +/* Useful groups of RTC_CNTL_DIG_PWC_REG bits */ +#define RTC_CNTL_CPU_ROM_RAM_PD_EN \ + (RTC_CNTL_INTER_RAM4_PD_EN | RTC_CNTL_INTER_RAM3_PD_EN |\ + RTC_CNTL_INTER_RAM2_PD_EN | RTC_CNTL_INTER_RAM1_PD_EN |\ + RTC_CNTL_INTER_RAM0_PD_EN | RTC_CNTL_ROM0_PD_EN) +#define RTC_CNTL_CPU_ROM_RAM_FORCE_PU \ + (RTC_CNTL_INTER_RAM4_FORCE_PU | RTC_CNTL_INTER_RAM3_FORCE_PU |\ + RTC_CNTL_INTER_RAM2_FORCE_PU | RTC_CNTL_INTER_RAM1_FORCE_PU |\ + RTC_CNTL_INTER_RAM0_FORCE_PU | RTC_CNTL_ROM0_FORCE_PU) +#define RTC_CNTL_CPU_ROM_RAM_FORCE_PD \ + (RTC_CNTL_INTER_RAM4_FORCE_PD | RTC_CNTL_INTER_RAM3_FORCE_PD |\ + RTC_CNTL_INTER_RAM2_FORCE_PD | RTC_CNTL_INTER_RAM1_FORCE_PD |\ + RTC_CNTL_INTER_RAM0_FORCE_PD | RTC_CNTL_ROM0_FORCE_PD + +#define RTC_CNTL_DIG_ISO_REG (DR_REG_RTCCNTL_BASE + 0x88) +/* RTC_CNTL_DG_WRAP_FORCE_NOISO : R/W ;bitpos:[31] ;default: 1'd1 ; */ +/*description: digital core force no ISO*/ +#define RTC_CNTL_DG_WRAP_FORCE_NOISO (BIT(31)) +#define RTC_CNTL_DG_WRAP_FORCE_NOISO_M (BIT(31)) +#define RTC_CNTL_DG_WRAP_FORCE_NOISO_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_NOISO_S 31 +/* RTC_CNTL_DG_WRAP_FORCE_ISO : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: digital core force ISO*/ +#define RTC_CNTL_DG_WRAP_FORCE_ISO (BIT(30)) +#define RTC_CNTL_DG_WRAP_FORCE_ISO_M (BIT(30)) +#define RTC_CNTL_DG_WRAP_FORCE_ISO_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_ISO_S 30 +/* RTC_CNTL_WIFI_FORCE_NOISO : R/W ;bitpos:[29] ;default: 1'd1 ; */ +/*description: wifi force no ISO*/ +#define RTC_CNTL_WIFI_FORCE_NOISO (BIT(29)) +#define RTC_CNTL_WIFI_FORCE_NOISO_M (BIT(29)) +#define RTC_CNTL_WIFI_FORCE_NOISO_V 0x1 +#define RTC_CNTL_WIFI_FORCE_NOISO_S 29 +/* RTC_CNTL_WIFI_FORCE_ISO : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: wifi force ISO*/ +#define RTC_CNTL_WIFI_FORCE_ISO (BIT(28)) +#define RTC_CNTL_WIFI_FORCE_ISO_M (BIT(28)) +#define RTC_CNTL_WIFI_FORCE_ISO_V 0x1 +#define RTC_CNTL_WIFI_FORCE_ISO_S 28 +/* RTC_CNTL_INTER_RAM4_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */ +/*description: internal SRAM 4 force no ISO*/ +#define RTC_CNTL_INTER_RAM4_FORCE_NOISO (BIT(27)) +#define RTC_CNTL_INTER_RAM4_FORCE_NOISO_M (BIT(27)) +#define RTC_CNTL_INTER_RAM4_FORCE_NOISO_V 0x1 +#define RTC_CNTL_INTER_RAM4_FORCE_NOISO_S 27 +/* RTC_CNTL_INTER_RAM4_FORCE_ISO : R/W ;bitpos:[26] ;default: 1'd0 ; */ +/*description: internal SRAM 4 force ISO*/ +#define RTC_CNTL_INTER_RAM4_FORCE_ISO (BIT(26)) +#define RTC_CNTL_INTER_RAM4_FORCE_ISO_M (BIT(26)) +#define RTC_CNTL_INTER_RAM4_FORCE_ISO_V 0x1 +#define RTC_CNTL_INTER_RAM4_FORCE_ISO_S 26 +/* RTC_CNTL_INTER_RAM3_FORCE_NOISO : R/W ;bitpos:[25] ;default: 1'd1 ; */ +/*description: internal SRAM 3 force no ISO*/ +#define RTC_CNTL_INTER_RAM3_FORCE_NOISO (BIT(25)) +#define RTC_CNTL_INTER_RAM3_FORCE_NOISO_M (BIT(25)) +#define RTC_CNTL_INTER_RAM3_FORCE_NOISO_V 0x1 +#define RTC_CNTL_INTER_RAM3_FORCE_NOISO_S 25 +/* RTC_CNTL_INTER_RAM3_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */ +/*description: internal SRAM 3 force ISO*/ +#define RTC_CNTL_INTER_RAM3_FORCE_ISO (BIT(24)) +#define RTC_CNTL_INTER_RAM3_FORCE_ISO_M (BIT(24)) +#define RTC_CNTL_INTER_RAM3_FORCE_ISO_V 0x1 +#define RTC_CNTL_INTER_RAM3_FORCE_ISO_S 24 +/* RTC_CNTL_INTER_RAM2_FORCE_NOISO : R/W ;bitpos:[23] ;default: 1'd1 ; */ +/*description: internal SRAM 2 force no ISO*/ +#define RTC_CNTL_INTER_RAM2_FORCE_NOISO (BIT(23)) +#define RTC_CNTL_INTER_RAM2_FORCE_NOISO_M (BIT(23)) +#define RTC_CNTL_INTER_RAM2_FORCE_NOISO_V 0x1 +#define RTC_CNTL_INTER_RAM2_FORCE_NOISO_S 23 +/* RTC_CNTL_INTER_RAM2_FORCE_ISO : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: internal SRAM 2 force ISO*/ +#define RTC_CNTL_INTER_RAM2_FORCE_ISO (BIT(22)) +#define RTC_CNTL_INTER_RAM2_FORCE_ISO_M (BIT(22)) +#define RTC_CNTL_INTER_RAM2_FORCE_ISO_V 0x1 +#define RTC_CNTL_INTER_RAM2_FORCE_ISO_S 22 +/* RTC_CNTL_INTER_RAM1_FORCE_NOISO : R/W ;bitpos:[21] ;default: 1'd1 ; */ +/*description: internal SRAM 1 force no ISO*/ +#define RTC_CNTL_INTER_RAM1_FORCE_NOISO (BIT(21)) +#define RTC_CNTL_INTER_RAM1_FORCE_NOISO_M (BIT(21)) +#define RTC_CNTL_INTER_RAM1_FORCE_NOISO_V 0x1 +#define RTC_CNTL_INTER_RAM1_FORCE_NOISO_S 21 +/* RTC_CNTL_INTER_RAM1_FORCE_ISO : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: internal SRAM 1 force ISO*/ +#define RTC_CNTL_INTER_RAM1_FORCE_ISO (BIT(20)) +#define RTC_CNTL_INTER_RAM1_FORCE_ISO_M (BIT(20)) +#define RTC_CNTL_INTER_RAM1_FORCE_ISO_V 0x1 +#define RTC_CNTL_INTER_RAM1_FORCE_ISO_S 20 +/* RTC_CNTL_INTER_RAM0_FORCE_NOISO : R/W ;bitpos:[19] ;default: 1'd1 ; */ +/*description: internal SRAM 0 force no ISO*/ +#define RTC_CNTL_INTER_RAM0_FORCE_NOISO (BIT(19)) +#define RTC_CNTL_INTER_RAM0_FORCE_NOISO_M (BIT(19)) +#define RTC_CNTL_INTER_RAM0_FORCE_NOISO_V 0x1 +#define RTC_CNTL_INTER_RAM0_FORCE_NOISO_S 19 +/* RTC_CNTL_INTER_RAM0_FORCE_ISO : R/W ;bitpos:[18] ;default: 1'd0 ; */ +/*description: internal SRAM 0 force ISO*/ +#define RTC_CNTL_INTER_RAM0_FORCE_ISO (BIT(18)) +#define RTC_CNTL_INTER_RAM0_FORCE_ISO_M (BIT(18)) +#define RTC_CNTL_INTER_RAM0_FORCE_ISO_V 0x1 +#define RTC_CNTL_INTER_RAM0_FORCE_ISO_S 18 +/* RTC_CNTL_ROM0_FORCE_NOISO : R/W ;bitpos:[17] ;default: 1'd1 ; */ +/*description: ROM force no ISO*/ +#define RTC_CNTL_ROM0_FORCE_NOISO (BIT(17)) +#define RTC_CNTL_ROM0_FORCE_NOISO_M (BIT(17)) +#define RTC_CNTL_ROM0_FORCE_NOISO_V 0x1 +#define RTC_CNTL_ROM0_FORCE_NOISO_S 17 +/* RTC_CNTL_ROM0_FORCE_ISO : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: ROM force ISO*/ +#define RTC_CNTL_ROM0_FORCE_ISO (BIT(16)) +#define RTC_CNTL_ROM0_FORCE_ISO_M (BIT(16)) +#define RTC_CNTL_ROM0_FORCE_ISO_V 0x1 +#define RTC_CNTL_ROM0_FORCE_ISO_S 16 +/* RTC_CNTL_DG_PAD_FORCE_HOLD : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: digital pad force hold*/ +#define RTC_CNTL_DG_PAD_FORCE_HOLD (BIT(15)) +#define RTC_CNTL_DG_PAD_FORCE_HOLD_M (BIT(15)) +#define RTC_CNTL_DG_PAD_FORCE_HOLD_V 0x1 +#define RTC_CNTL_DG_PAD_FORCE_HOLD_S 15 +/* RTC_CNTL_DG_PAD_FORCE_UNHOLD : R/W ;bitpos:[14] ;default: 1'd1 ; */ +/*description: digital pad force un-hold*/ +#define RTC_CNTL_DG_PAD_FORCE_UNHOLD (BIT(14)) +#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_M (BIT(14)) +#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_V 0x1 +#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_S 14 +/* RTC_CNTL_DG_PAD_FORCE_ISO : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: digital pad force ISO*/ +#define RTC_CNTL_DG_PAD_FORCE_ISO (BIT(13)) +#define RTC_CNTL_DG_PAD_FORCE_ISO_M (BIT(13)) +#define RTC_CNTL_DG_PAD_FORCE_ISO_V 0x1 +#define RTC_CNTL_DG_PAD_FORCE_ISO_S 13 +/* RTC_CNTL_DG_PAD_FORCE_NOISO : R/W ;bitpos:[12] ;default: 1'd1 ; */ +/*description: digital pad force no ISO*/ +#define RTC_CNTL_DG_PAD_FORCE_NOISO (BIT(12)) +#define RTC_CNTL_DG_PAD_FORCE_NOISO_M (BIT(12)) +#define RTC_CNTL_DG_PAD_FORCE_NOISO_V 0x1 +#define RTC_CNTL_DG_PAD_FORCE_NOISO_S 12 +/* RTC_CNTL_DG_PAD_AUTOHOLD_EN : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: digital pad enable auto-hold*/ +#define RTC_CNTL_DG_PAD_AUTOHOLD_EN (BIT(11)) +#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_M (BIT(11)) +#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_V 0x1 +#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_S 11 +/* RTC_CNTL_CLR_DG_PAD_AUTOHOLD : WO ;bitpos:[10] ;default: 1'd0 ; */ +/*description: wtite only register to clear digital pad auto-hold*/ +#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD (BIT(10)) +#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_M (BIT(10)) +#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_V 0x1 +#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_S 10 +/* RTC_CNTL_DG_PAD_AUTOHOLD : RO ;bitpos:[9] ;default: 1'd0 ; */ +/*description: read only register to indicate digital pad auto-hold status*/ +#define RTC_CNTL_DG_PAD_AUTOHOLD (BIT(9)) +#define RTC_CNTL_DG_PAD_AUTOHOLD_M (BIT(9)) +#define RTC_CNTL_DG_PAD_AUTOHOLD_V 0x1 +#define RTC_CNTL_DG_PAD_AUTOHOLD_S 9 +/* RTC_CNTL_DIG_ISO_FORCE_ON : R/W ;bitpos:[8] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_DIG_ISO_FORCE_ON (BIT(8)) +#define RTC_CNTL_DIG_ISO_FORCE_ON_M (BIT(8)) +#define RTC_CNTL_DIG_ISO_FORCE_ON_V 0x1 +#define RTC_CNTL_DIG_ISO_FORCE_ON_S 8 +/* RTC_CNTL_DIG_ISO_FORCE_OFF : R/W ;bitpos:[7] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_DIG_ISO_FORCE_OFF (BIT(7)) +#define RTC_CNTL_DIG_ISO_FORCE_OFF_M (BIT(7)) +#define RTC_CNTL_DIG_ISO_FORCE_OFF_V 0x1 +#define RTC_CNTL_DIG_ISO_FORCE_OFF_S 7 + +/* Useful groups of RTC_CNTL_DIG_ISO_REG bits */ +#define RTC_CNTL_CPU_ROM_RAM_FORCE_ISO \ + (RTC_CNTL_INTER_RAM4_FORCE_ISO | RTC_CNTL_INTER_RAM3_FORCE_ISO |\ + RTC_CNTL_INTER_RAM2_FORCE_ISO | RTC_CNTL_INTER_RAM1_FORCE_ISO |\ + RTC_CNTL_INTER_RAM0_FORCE_ISO | RTC_CNTL_ROM0_FORCE_ISO) +#define RTC_CNTL_CPU_ROM_RAM_FORCE_NOISO \ + (RTC_CNTL_INTER_RAM4_FORCE_NOISO | RTC_CNTL_INTER_RAM3_FORCE_NOISO |\ + RTC_CNTL_INTER_RAM2_FORCE_NOISO | RTC_CNTL_INTER_RAM1_FORCE_NOISO |\ + RTC_CNTL_INTER_RAM0_FORCE_NOISO | RTC_CNTL_ROM0_FORCE_NOISO) + +#define RTC_CNTL_WDTCONFIG0_REG (DR_REG_RTCCNTL_BASE + 0x8c) +/* RTC_CNTL_WDT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: enable RTC WDT*/ +#define RTC_CNTL_WDT_EN (BIT(31)) +#define RTC_CNTL_WDT_EN_M (BIT(31)) +#define RTC_CNTL_WDT_EN_V 0x1 +#define RTC_CNTL_WDT_EN_S 31 +/* RTC_CNTL_WDT_STG0 : R/W ;bitpos:[30:28] ;default: 3'h0 ; */ +/*description: 1: interrupt stage en 2: CPU reset stage en 3: system reset + stage en 4: RTC reset stage en*/ +#define RTC_CNTL_WDT_STG0 0x00000007 +#define RTC_CNTL_WDT_STG0_M ((RTC_CNTL_WDT_STG0_V)<<(RTC_CNTL_WDT_STG0_S)) +#define RTC_CNTL_WDT_STG0_V 0x7 +#define RTC_CNTL_WDT_STG0_S 28 +/* RTC_CNTL_WDT_STG1 : R/W ;bitpos:[27:25] ;default: 3'h0 ; */ +/*description: 1: interrupt stage en 2: CPU reset stage en 3: system reset + stage en 4: RTC reset stage en*/ +#define RTC_CNTL_WDT_STG1 0x00000007 +#define RTC_CNTL_WDT_STG1_M ((RTC_CNTL_WDT_STG1_V)<<(RTC_CNTL_WDT_STG1_S)) +#define RTC_CNTL_WDT_STG1_V 0x7 +#define RTC_CNTL_WDT_STG1_S 25 +/* RTC_CNTL_WDT_STG2 : R/W ;bitpos:[24:22] ;default: 3'h0 ; */ +/*description: 1: interrupt stage en 2: CPU reset stage en 3: system reset + stage en 4: RTC reset stage en*/ +#define RTC_CNTL_WDT_STG2 0x00000007 +#define RTC_CNTL_WDT_STG2_M ((RTC_CNTL_WDT_STG2_V)<<(RTC_CNTL_WDT_STG2_S)) +#define RTC_CNTL_WDT_STG2_V 0x7 +#define RTC_CNTL_WDT_STG2_S 22 +/* RTC_CNTL_WDT_STG3 : R/W ;bitpos:[21:19] ;default: 3'h0 ; */ +/*description: 1: interrupt stage en 2: CPU reset stage en 3: system reset + stage en 4: RTC reset stage en*/ +#define RTC_CNTL_WDT_STG3 0x00000007 +#define RTC_CNTL_WDT_STG3_M ((RTC_CNTL_WDT_STG3_V)<<(RTC_CNTL_WDT_STG3_S)) +#define RTC_CNTL_WDT_STG3_V 0x7 +#define RTC_CNTL_WDT_STG3_S 19 +/* RTC_CNTL_WDT_EDGE_INT_EN : R/W ;bitpos:[18] ;default: 1'h0 ; */ +/*description: N/A*/ +#define RTC_CNTL_WDT_EDGE_INT_EN (BIT(18)) +#define RTC_CNTL_WDT_EDGE_INT_EN_M (BIT(18)) +#define RTC_CNTL_WDT_EDGE_INT_EN_V 0x1 +#define RTC_CNTL_WDT_EDGE_INT_EN_S 18 +/* RTC_CNTL_WDT_LEVEL_INT_EN : R/W ;bitpos:[17] ;default: 1'h0 ; */ +/*description: N/A*/ +#define RTC_CNTL_WDT_LEVEL_INT_EN (BIT(17)) +#define RTC_CNTL_WDT_LEVEL_INT_EN_M (BIT(17)) +#define RTC_CNTL_WDT_LEVEL_INT_EN_V 0x1 +#define RTC_CNTL_WDT_LEVEL_INT_EN_S 17 +/* RTC_CNTL_WDT_CPU_RESET_LENGTH : R/W ;bitpos:[16:14] ;default: 3'h1 ; */ +/*description: CPU reset counter length*/ +#define RTC_CNTL_WDT_CPU_RESET_LENGTH 0x00000007 +#define RTC_CNTL_WDT_CPU_RESET_LENGTH_M ((RTC_CNTL_WDT_CPU_RESET_LENGTH_V)<<(RTC_CNTL_WDT_CPU_RESET_LENGTH_S)) +#define RTC_CNTL_WDT_CPU_RESET_LENGTH_V 0x7 +#define RTC_CNTL_WDT_CPU_RESET_LENGTH_S 14 +/* RTC_CNTL_WDT_SYS_RESET_LENGTH : R/W ;bitpos:[13:11] ;default: 3'h1 ; */ +/*description: system reset counter length*/ +#define RTC_CNTL_WDT_SYS_RESET_LENGTH 0x00000007 +#define RTC_CNTL_WDT_SYS_RESET_LENGTH_M ((RTC_CNTL_WDT_SYS_RESET_LENGTH_V)<<(RTC_CNTL_WDT_SYS_RESET_LENGTH_S)) +#define RTC_CNTL_WDT_SYS_RESET_LENGTH_V 0x7 +#define RTC_CNTL_WDT_SYS_RESET_LENGTH_S 11 +/* RTC_CNTL_WDT_FLASHBOOT_MOD_EN : R/W ;bitpos:[10] ;default: 1'h1 ; */ +/*description: enable WDT in flash boot*/ +#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN (BIT(10)) +#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_M (BIT(10)) +#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_V 0x1 +#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_S 10 +/* RTC_CNTL_WDT_PROCPU_RESET_EN : R/W ;bitpos:[9] ;default: 1'd0 ; */ +/*description: enable WDT reset PRO CPU*/ +#define RTC_CNTL_WDT_PROCPU_RESET_EN (BIT(9)) +#define RTC_CNTL_WDT_PROCPU_RESET_EN_M (BIT(9)) +#define RTC_CNTL_WDT_PROCPU_RESET_EN_V 0x1 +#define RTC_CNTL_WDT_PROCPU_RESET_EN_S 9 +/* RTC_CNTL_WDT_APPCPU_RESET_EN : R/W ;bitpos:[8] ;default: 1'd0 ; */ +/*description: enable WDT reset APP CPU*/ +#define RTC_CNTL_WDT_APPCPU_RESET_EN (BIT(8)) +#define RTC_CNTL_WDT_APPCPU_RESET_EN_M (BIT(8)) +#define RTC_CNTL_WDT_APPCPU_RESET_EN_V 0x1 +#define RTC_CNTL_WDT_APPCPU_RESET_EN_S 8 +/* RTC_CNTL_WDT_PAUSE_IN_SLP : R/W ;bitpos:[7] ;default: 1'd1 ; */ +/*description: pause WDT in sleep*/ +#define RTC_CNTL_WDT_PAUSE_IN_SLP (BIT(7)) +#define RTC_CNTL_WDT_PAUSE_IN_SLP_M (BIT(7)) +#define RTC_CNTL_WDT_PAUSE_IN_SLP_V 0x1 +#define RTC_CNTL_WDT_PAUSE_IN_SLP_S 7 +/* RTC_CNTL_WDT_STGX : */ +/*description: stage action selection values */ +#define RTC_WDT_STG_SEL_OFF 0 +#define RTC_WDT_STG_SEL_INT 1 +#define RTC_WDT_STG_SEL_RESET_CPU 2 +#define RTC_WDT_STG_SEL_RESET_SYSTEM 3 +#define RTC_WDT_STG_SEL_RESET_RTC 4 + +#define RTC_CNTL_WDTCONFIG1_REG (DR_REG_RTCCNTL_BASE + 0x90) +/* RTC_CNTL_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd128000 ; */ +/*description: */ +#define RTC_CNTL_WDT_STG0_HOLD 0xFFFFFFFF +#define RTC_CNTL_WDT_STG0_HOLD_M ((RTC_CNTL_WDT_STG0_HOLD_V)<<(RTC_CNTL_WDT_STG0_HOLD_S)) +#define RTC_CNTL_WDT_STG0_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_WDT_STG0_HOLD_S 0 + +#define RTC_CNTL_WDTCONFIG2_REG (DR_REG_RTCCNTL_BASE + 0x94) +/* RTC_CNTL_WDT_STG1_HOLD : R/W ;bitpos:[31:0] ;default: 32'd80000 ; */ +/*description: */ +#define RTC_CNTL_WDT_STG1_HOLD 0xFFFFFFFF +#define RTC_CNTL_WDT_STG1_HOLD_M ((RTC_CNTL_WDT_STG1_HOLD_V)<<(RTC_CNTL_WDT_STG1_HOLD_S)) +#define RTC_CNTL_WDT_STG1_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_WDT_STG1_HOLD_S 0 + +#define RTC_CNTL_WDTCONFIG3_REG (DR_REG_RTCCNTL_BASE + 0x98) +/* RTC_CNTL_WDT_STG2_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */ +/*description: */ +#define RTC_CNTL_WDT_STG2_HOLD 0xFFFFFFFF +#define RTC_CNTL_WDT_STG2_HOLD_M ((RTC_CNTL_WDT_STG2_HOLD_V)<<(RTC_CNTL_WDT_STG2_HOLD_S)) +#define RTC_CNTL_WDT_STG2_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_WDT_STG2_HOLD_S 0 + +#define RTC_CNTL_WDTCONFIG4_REG (DR_REG_RTCCNTL_BASE + 0x9c) +/* RTC_CNTL_WDT_STG3_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */ +/*description: */ +#define RTC_CNTL_WDT_STG3_HOLD 0xFFFFFFFF +#define RTC_CNTL_WDT_STG3_HOLD_M ((RTC_CNTL_WDT_STG3_HOLD_V)<<(RTC_CNTL_WDT_STG3_HOLD_S)) +#define RTC_CNTL_WDT_STG3_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_WDT_STG3_HOLD_S 0 + +#define RTC_CNTL_WDTFEED_REG (DR_REG_RTCCNTL_BASE + 0xa0) +/* RTC_CNTL_WDT_FEED : WO ;bitpos:[31] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_WDT_FEED (BIT(31)) +#define RTC_CNTL_WDT_FEED_M (BIT(31)) +#define RTC_CNTL_WDT_FEED_V 0x1 +#define RTC_CNTL_WDT_FEED_S 31 + +#define RTC_CNTL_WDTWPROTECT_REG (DR_REG_RTCCNTL_BASE + 0xa4) +/* RTC_CNTL_WDT_WKEY : R/W ;bitpos:[31:0] ;default: 32'h50d83aa1 ; */ +/*description: */ +#define RTC_CNTL_WDT_WKEY 0xFFFFFFFF +#define RTC_CNTL_WDT_WKEY_M ((RTC_CNTL_WDT_WKEY_V)<<(RTC_CNTL_WDT_WKEY_S)) +#define RTC_CNTL_WDT_WKEY_V 0xFFFFFFFF +#define RTC_CNTL_WDT_WKEY_S 0 + +#define RTC_CNTL_TEST_MUX_REG (DR_REG_RTCCNTL_BASE + 0xa8) +/* RTC_CNTL_DTEST_RTC : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ +/*description: DTEST_RTC*/ +#define RTC_CNTL_DTEST_RTC 0x00000003 +#define RTC_CNTL_DTEST_RTC_M ((RTC_CNTL_DTEST_RTC_V)<<(RTC_CNTL_DTEST_RTC_S)) +#define RTC_CNTL_DTEST_RTC_V 0x3 +#define RTC_CNTL_DTEST_RTC_S 30 +/* RTC_CNTL_ENT_RTC : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: ENT_RTC*/ +#define RTC_CNTL_ENT_RTC (BIT(29)) +#define RTC_CNTL_ENT_RTC_M (BIT(29)) +#define RTC_CNTL_ENT_RTC_V 0x1 +#define RTC_CNTL_ENT_RTC_S 29 + +#define RTC_CNTL_SW_CPU_STALL_REG (DR_REG_RTCCNTL_BASE + 0xac) +/* RTC_CNTL_SW_STALL_PROCPU_C1 : R/W ;bitpos:[31:26] ;default: 6'b0 ; */ +/*description: {reg_sw_stall_procpu_c1[5:0] reg_sw_stall_procpu_c0[1:0]} == + 0x86 will stall PRO CPU*/ +#define RTC_CNTL_SW_STALL_PROCPU_C1 0x0000003F +#define RTC_CNTL_SW_STALL_PROCPU_C1_M ((RTC_CNTL_SW_STALL_PROCPU_C1_V)<<(RTC_CNTL_SW_STALL_PROCPU_C1_S)) +#define RTC_CNTL_SW_STALL_PROCPU_C1_V 0x3F +#define RTC_CNTL_SW_STALL_PROCPU_C1_S 26 +/* RTC_CNTL_SW_STALL_APPCPU_C1 : R/W ;bitpos:[25:20] ;default: 6'b0 ; */ +/*description: {reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == + 0x86 will stall APP CPU*/ +#define RTC_CNTL_SW_STALL_APPCPU_C1 0x0000003F +#define RTC_CNTL_SW_STALL_APPCPU_C1_M ((RTC_CNTL_SW_STALL_APPCPU_C1_V)<<(RTC_CNTL_SW_STALL_APPCPU_C1_S)) +#define RTC_CNTL_SW_STALL_APPCPU_C1_V 0x3F +#define RTC_CNTL_SW_STALL_APPCPU_C1_S 20 + +#define RTC_CNTL_STORE4_REG (DR_REG_RTCCNTL_BASE + 0xb0) +/* RTC_CNTL_SCRATCH4 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: 32-bit general purpose retention register*/ +#define RTC_CNTL_SCRATCH4 0xFFFFFFFF +#define RTC_CNTL_SCRATCH4_M ((RTC_CNTL_SCRATCH4_V)<<(RTC_CNTL_SCRATCH4_S)) +#define RTC_CNTL_SCRATCH4_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH4_S 0 + +#define RTC_CNTL_STORE5_REG (DR_REG_RTCCNTL_BASE + 0xb4) +/* RTC_CNTL_SCRATCH5 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: 32-bit general purpose retention register*/ +#define RTC_CNTL_SCRATCH5 0xFFFFFFFF +#define RTC_CNTL_SCRATCH5_M ((RTC_CNTL_SCRATCH5_V)<<(RTC_CNTL_SCRATCH5_S)) +#define RTC_CNTL_SCRATCH5_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH5_S 0 + +#define RTC_CNTL_STORE6_REG (DR_REG_RTCCNTL_BASE + 0xb8) +/* RTC_CNTL_SCRATCH6 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: 32-bit general purpose retention register*/ +#define RTC_CNTL_SCRATCH6 0xFFFFFFFF +#define RTC_CNTL_SCRATCH6_M ((RTC_CNTL_SCRATCH6_V)<<(RTC_CNTL_SCRATCH6_S)) +#define RTC_CNTL_SCRATCH6_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH6_S 0 + +#define RTC_CNTL_STORE7_REG (DR_REG_RTCCNTL_BASE + 0xbc) +/* RTC_CNTL_SCRATCH7 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: 32-bit general purpose retention register*/ +#define RTC_CNTL_SCRATCH7 0xFFFFFFFF +#define RTC_CNTL_SCRATCH7_M ((RTC_CNTL_SCRATCH7_V)<<(RTC_CNTL_SCRATCH7_S)) +#define RTC_CNTL_SCRATCH7_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH7_S 0 + +#define RTC_CNTL_LOW_POWER_ST_REG (DR_REG_RTCCNTL_BASE + 0xc0) +/* RTC_CNTL_RDY_FOR_WAKEUP : R/0; bitpos:[19]; default: 0 */ +/*description: 1 if RTC controller is ready to execute WAKE instruction, 0 otherwise */ +#define RTC_CNTL_RDY_FOR_WAKEUP (BIT(19)) +#define RTC_CNTL_RDY_FOR_WAKEUP_M (BIT(19)) +#define RTC_CNTL_RDY_FOR_WAKEUP_V 0x1 +#define RTC_CNTL_RDY_FOR_WAKEUP_S 19 + +/* Compatibility definition */ +#define RTC_CNTL_DIAG0_REG RTC_CNTL_LOW_POWER_ST_REG +/* RTC_CNTL_LOW_POWER_DIAG0 : RO ;bitpos:[31:0] ;default: 0 ; */ +/*description: */ +#define RTC_CNTL_LOW_POWER_DIAG0 0xFFFFFFFF +#define RTC_CNTL_LOW_POWER_DIAG0_M ((RTC_CNTL_LOW_POWER_DIAG0_V)<<(RTC_CNTL_LOW_POWER_DIAG0_S)) +#define RTC_CNTL_LOW_POWER_DIAG0_V 0xFFFFFFFF +#define RTC_CNTL_LOW_POWER_DIAG0_S 0 + +#define RTC_CNTL_DIAG1_REG (DR_REG_RTCCNTL_BASE + 0xc4) +/* RTC_CNTL_LOW_POWER_DIAG1 : RO ;bitpos:[31:0] ;default: 0 ; */ +/*description: */ +#define RTC_CNTL_LOW_POWER_DIAG1 0xFFFFFFFF +#define RTC_CNTL_LOW_POWER_DIAG1_M ((RTC_CNTL_LOW_POWER_DIAG1_V)<<(RTC_CNTL_LOW_POWER_DIAG1_S)) +#define RTC_CNTL_LOW_POWER_DIAG1_V 0xFFFFFFFF +#define RTC_CNTL_LOW_POWER_DIAG1_S 0 + +#define RTC_CNTL_HOLD_FORCE_REG (DR_REG_RTCCNTL_BASE + 0xc8) +/* RTC_CNTL_X32N_HOLD_FORCE : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_X32N_HOLD_FORCE (BIT(17)) +#define RTC_CNTL_X32N_HOLD_FORCE_M (BIT(17)) +#define RTC_CNTL_X32N_HOLD_FORCE_V 0x1 +#define RTC_CNTL_X32N_HOLD_FORCE_S 17 +/* RTC_CNTL_X32P_HOLD_FORCE : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_X32P_HOLD_FORCE (BIT(16)) +#define RTC_CNTL_X32P_HOLD_FORCE_M (BIT(16)) +#define RTC_CNTL_X32P_HOLD_FORCE_V 0x1 +#define RTC_CNTL_X32P_HOLD_FORCE_S 16 +/* RTC_CNTL_TOUCH_PAD7_HOLD_FORCE : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD7_HOLD_FORCE (BIT(15)) +#define RTC_CNTL_TOUCH_PAD7_HOLD_FORCE_M (BIT(15)) +#define RTC_CNTL_TOUCH_PAD7_HOLD_FORCE_V 0x1 +#define RTC_CNTL_TOUCH_PAD7_HOLD_FORCE_S 15 +/* RTC_CNTL_TOUCH_PAD6_HOLD_FORCE : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD6_HOLD_FORCE (BIT(14)) +#define RTC_CNTL_TOUCH_PAD6_HOLD_FORCE_M (BIT(14)) +#define RTC_CNTL_TOUCH_PAD6_HOLD_FORCE_V 0x1 +#define RTC_CNTL_TOUCH_PAD6_HOLD_FORCE_S 14 +/* RTC_CNTL_TOUCH_PAD5_HOLD_FORCE : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD5_HOLD_FORCE (BIT(13)) +#define RTC_CNTL_TOUCH_PAD5_HOLD_FORCE_M (BIT(13)) +#define RTC_CNTL_TOUCH_PAD5_HOLD_FORCE_V 0x1 +#define RTC_CNTL_TOUCH_PAD5_HOLD_FORCE_S 13 +/* RTC_CNTL_TOUCH_PAD4_HOLD_FORCE : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD4_HOLD_FORCE (BIT(12)) +#define RTC_CNTL_TOUCH_PAD4_HOLD_FORCE_M (BIT(12)) +#define RTC_CNTL_TOUCH_PAD4_HOLD_FORCE_V 0x1 +#define RTC_CNTL_TOUCH_PAD4_HOLD_FORCE_S 12 +/* RTC_CNTL_TOUCH_PAD3_HOLD_FORCE : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD3_HOLD_FORCE (BIT(11)) +#define RTC_CNTL_TOUCH_PAD3_HOLD_FORCE_M (BIT(11)) +#define RTC_CNTL_TOUCH_PAD3_HOLD_FORCE_V 0x1 +#define RTC_CNTL_TOUCH_PAD3_HOLD_FORCE_S 11 +/* RTC_CNTL_TOUCH_PAD2_HOLD_FORCE : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD2_HOLD_FORCE (BIT(10)) +#define RTC_CNTL_TOUCH_PAD2_HOLD_FORCE_M (BIT(10)) +#define RTC_CNTL_TOUCH_PAD2_HOLD_FORCE_V 0x1 +#define RTC_CNTL_TOUCH_PAD2_HOLD_FORCE_S 10 +/* RTC_CNTL_TOUCH_PAD1_HOLD_FORCE : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD1_HOLD_FORCE (BIT(9)) +#define RTC_CNTL_TOUCH_PAD1_HOLD_FORCE_M (BIT(9)) +#define RTC_CNTL_TOUCH_PAD1_HOLD_FORCE_V 0x1 +#define RTC_CNTL_TOUCH_PAD1_HOLD_FORCE_S 9 +/* RTC_CNTL_TOUCH_PAD0_HOLD_FORCE : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD0_HOLD_FORCE (BIT(8)) +#define RTC_CNTL_TOUCH_PAD0_HOLD_FORCE_M (BIT(8)) +#define RTC_CNTL_TOUCH_PAD0_HOLD_FORCE_V 0x1 +#define RTC_CNTL_TOUCH_PAD0_HOLD_FORCE_S 8 +/* RTC_CNTL_SENSE4_HOLD_FORCE : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_SENSE4_HOLD_FORCE (BIT(7)) +#define RTC_CNTL_SENSE4_HOLD_FORCE_M (BIT(7)) +#define RTC_CNTL_SENSE4_HOLD_FORCE_V 0x1 +#define RTC_CNTL_SENSE4_HOLD_FORCE_S 7 +/* RTC_CNTL_SENSE3_HOLD_FORCE : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_SENSE3_HOLD_FORCE (BIT(6)) +#define RTC_CNTL_SENSE3_HOLD_FORCE_M (BIT(6)) +#define RTC_CNTL_SENSE3_HOLD_FORCE_V 0x1 +#define RTC_CNTL_SENSE3_HOLD_FORCE_S 6 +/* RTC_CNTL_SENSE2_HOLD_FORCE : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_SENSE2_HOLD_FORCE (BIT(5)) +#define RTC_CNTL_SENSE2_HOLD_FORCE_M (BIT(5)) +#define RTC_CNTL_SENSE2_HOLD_FORCE_V 0x1 +#define RTC_CNTL_SENSE2_HOLD_FORCE_S 5 +/* RTC_CNTL_SENSE1_HOLD_FORCE : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_SENSE1_HOLD_FORCE (BIT(4)) +#define RTC_CNTL_SENSE1_HOLD_FORCE_M (BIT(4)) +#define RTC_CNTL_SENSE1_HOLD_FORCE_V 0x1 +#define RTC_CNTL_SENSE1_HOLD_FORCE_S 4 +/* RTC_CNTL_PDAC2_HOLD_FORCE : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_PDAC2_HOLD_FORCE (BIT(3)) +#define RTC_CNTL_PDAC2_HOLD_FORCE_M (BIT(3)) +#define RTC_CNTL_PDAC2_HOLD_FORCE_V 0x1 +#define RTC_CNTL_PDAC2_HOLD_FORCE_S 3 +/* RTC_CNTL_PDAC1_HOLD_FORCE : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_PDAC1_HOLD_FORCE (BIT(2)) +#define RTC_CNTL_PDAC1_HOLD_FORCE_M (BIT(2)) +#define RTC_CNTL_PDAC1_HOLD_FORCE_V 0x1 +#define RTC_CNTL_PDAC1_HOLD_FORCE_S 2 +/* RTC_CNTL_ADC2_HOLD_FORCE : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_ADC2_HOLD_FORCE (BIT(1)) +#define RTC_CNTL_ADC2_HOLD_FORCE_M (BIT(1)) +#define RTC_CNTL_ADC2_HOLD_FORCE_V 0x1 +#define RTC_CNTL_ADC2_HOLD_FORCE_S 1 +/* RTC_CNTL_ADC1_HOLD_FORCE : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_ADC1_HOLD_FORCE (BIT(0)) +#define RTC_CNTL_ADC1_HOLD_FORCE_M (BIT(0)) +#define RTC_CNTL_ADC1_HOLD_FORCE_V 0x1 +#define RTC_CNTL_ADC1_HOLD_FORCE_S 0 + +#define RTC_CNTL_EXT_WAKEUP1_REG (DR_REG_RTCCNTL_BASE + 0xcc) +/* RTC_CNTL_EXT_WAKEUP1_STATUS_CLR : WO ;bitpos:[18] ;default: 1'd0 ; */ +/*description: clear ext wakeup1 status*/ +#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR (BIT(18)) +#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_M (BIT(18)) +#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_V 0x1 +#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_S 18 +/* RTC_CNTL_EXT_WAKEUP1_SEL : R/W ;bitpos:[17:0] ;default: 18'd0 ; */ +/*description: Bitmap to select RTC pads for ext wakeup1*/ +#define RTC_CNTL_EXT_WAKEUP1_SEL 0x0003FFFF +#define RTC_CNTL_EXT_WAKEUP1_SEL_M ((RTC_CNTL_EXT_WAKEUP1_SEL_V)<<(RTC_CNTL_EXT_WAKEUP1_SEL_S)) +#define RTC_CNTL_EXT_WAKEUP1_SEL_V 0x3FFFF +#define RTC_CNTL_EXT_WAKEUP1_SEL_S 0 + +#define RTC_CNTL_EXT_WAKEUP1_STATUS_REG (DR_REG_RTCCNTL_BASE + 0xd0) +/* RTC_CNTL_EXT_WAKEUP1_STATUS : RO ;bitpos:[17:0] ;default: 18'd0 ; */ +/*description: ext wakeup1 status*/ +#define RTC_CNTL_EXT_WAKEUP1_STATUS 0x0003FFFF +#define RTC_CNTL_EXT_WAKEUP1_STATUS_M ((RTC_CNTL_EXT_WAKEUP1_STATUS_V)<<(RTC_CNTL_EXT_WAKEUP1_STATUS_S)) +#define RTC_CNTL_EXT_WAKEUP1_STATUS_V 0x3FFFF +#define RTC_CNTL_EXT_WAKEUP1_STATUS_S 0 + +#define RTC_CNTL_BROWN_OUT_REG (DR_REG_RTCCNTL_BASE + 0xd4) +/* RTC_CNTL_BROWN_OUT_DET : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: brown out detect*/ +#define RTC_CNTL_BROWN_OUT_DET (BIT(31)) +#define RTC_CNTL_BROWN_OUT_DET_M (BIT(31)) +#define RTC_CNTL_BROWN_OUT_DET_V 0x1 +#define RTC_CNTL_BROWN_OUT_DET_S 31 +/* RTC_CNTL_BROWN_OUT_ENA : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: enable brown out*/ +#define RTC_CNTL_BROWN_OUT_ENA (BIT(30)) +#define RTC_CNTL_BROWN_OUT_ENA_M (BIT(30)) +#define RTC_CNTL_BROWN_OUT_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_ENA_S 30 +/* RTC_CNTL_DBROWN_OUT_THRES : R/W ;bitpos:[29:27] ;default: 3'b010 ; */ +/*description: brown out threshold*/ +#define RTC_CNTL_DBROWN_OUT_THRES 0x00000007 +#define RTC_CNTL_DBROWN_OUT_THRES_M ((RTC_CNTL_DBROWN_OUT_THRES_V)<<(RTC_CNTL_DBROWN_OUT_THRES_S)) +#define RTC_CNTL_DBROWN_OUT_THRES_V 0x7 +#define RTC_CNTL_DBROWN_OUT_THRES_S 27 +/* RTC_CNTL_BROWN_OUT_RST_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: enable brown out reset*/ +#define RTC_CNTL_BROWN_OUT_RST_ENA (BIT(26)) +#define RTC_CNTL_BROWN_OUT_RST_ENA_M (BIT(26)) +#define RTC_CNTL_BROWN_OUT_RST_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_RST_ENA_S 26 +/* RTC_CNTL_BROWN_OUT_RST_WAIT : R/W ;bitpos:[25:16] ;default: 10'h3ff ; */ +/*description: brown out reset wait cycles*/ +#define RTC_CNTL_BROWN_OUT_RST_WAIT 0x000003FF +#define RTC_CNTL_BROWN_OUT_RST_WAIT_M ((RTC_CNTL_BROWN_OUT_RST_WAIT_V)<<(RTC_CNTL_BROWN_OUT_RST_WAIT_S)) +#define RTC_CNTL_BROWN_OUT_RST_WAIT_V 0x3FF +#define RTC_CNTL_BROWN_OUT_RST_WAIT_S 16 +/* RTC_CNTL_BROWN_OUT_PD_RF_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: enable power down RF when brown out happens*/ +#define RTC_CNTL_BROWN_OUT_PD_RF_ENA (BIT(15)) +#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_M (BIT(15)) +#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_S 15 +/* RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: enable close flash when brown out happens*/ +#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA (BIT(14)) +#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_M (BIT(14)) +#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_S 14 + +#define RTC_MEM_CONF (DR_REG_RTCCNTL_BASE + 0x40 * 4) +#define RTC_MEM_CRC_FINISH (BIT(31)) +#define RTC_MEM_CRC_FINISH_M (BIT(31)) +#define RTC_MEM_CRC_FINISH_V 0x1 +#define RTC_MEM_CRC_FINISH_S 31 +#define RTC_MEM_CRC_LEN (0x7ff) +#define RTC_MEM_CRC_LEN_M ((RTC_MEM_CRC_LEN_V)<<(RTC_MEM_CRC_LEN_S)) +#define RTC_MEM_CRC_LEN_V 0x7ff +#define RTC_MEM_CRC_LEN_S 20 +#define RTC_MEM_CRC_ADDR 0x7ff +#define RTC_MEM_CRC_ADDR_M ((RTC_MEM_CRC_ADDR_V)<<(RTC_MEM_CRC_ADDR_S)) +#define RTC_MEM_CRC_ADDR_V 0x7ff +#define RTC_MEM_CRC_ADDR_S 9 +#define RTC_MEM_CRC_START (BIT(8)) +#define RTC_MEM_CRC_START_M (BIT(8)) +#define RTC_MEM_CRC_START_V 0x1 +#define RTC_MEM_CRC_START_S 8 +#define RTC_MEM_PID_CONF 0xff +#define RTC_MEM_PID_CONF_M 0xff +#define RTC_MEM_PID_CONF_V 0xff +#define RTC_MEM_PID_CONF_S 0 + +#define RTC_MEM_CRC_RES (DR_REG_RTCCNTL_BASE + 0x41 * 4) + +#define RTC_CNTL_DATE_REG (DR_REG_RTCCNTL_BASE + 0x13c) +/* RTC_CNTL_CNTL_DATE : R/W ;bitpos:[27:0] ;default: 28'h1604280 ; */ +/*description: */ +#define RTC_CNTL_CNTL_DATE 0x0FFFFFFF +#define RTC_CNTL_CNTL_DATE_M ((RTC_CNTL_CNTL_DATE_V)<<(RTC_CNTL_CNTL_DATE_S)) +#define RTC_CNTL_CNTL_DATE_V 0xFFFFFFF +#define RTC_CNTL_CNTL_DATE_S 0 +#define RTC_CNTL_RTC_CNTL_DATE_VERSION 0x1604280 diff --git a/src/target/esp32/src/clock.c b/src/target/esp32/src/clock.c new file mode 100644 index 0000000..767f717 --- /dev/null +++ b/src/target/esp32/src/clock.c @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 OR MIT + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define MHZ 1000000 + +extern void esp_rom_set_cpu_ticks_per_us(uint32_t ticks_per_us); +extern uint32_t esp_rom_get_cpu_ticks_per_us(void); +extern uint32_t esp_rom_get_detected_xtal_freq(void); + +static uint32_t s_cpu_freq = 0; + +void stub_target_clock_init(void) +{ + REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DBIAS_1V25); + REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, 1U); + s_cpu_freq = 160 * MHZ; + esp_rom_set_cpu_ticks_per_us(s_cpu_freq / MHZ); + WRITE_PERI_REG(SPI_CLOCK_REG(0), 0); +} + +uint32_t stub_target_get_cpu_freq(void) +{ + if (s_cpu_freq == 0) { + return esp_rom_get_cpu_ticks_per_us() * MHZ; + } + return s_cpu_freq; +} diff --git a/src/target/esp32/src/uart.c b/src/target/esp32/src/uart.c index 2879344..af9c20f 100644 --- a/src/target/esp32/src/uart.c +++ b/src/target/esp32/src/uart.c @@ -7,8 +7,10 @@ #include #include #include +#include +#include #include - +#include #include // These functions are defined in the ROM @@ -23,6 +25,7 @@ extern uint32_t esp_rom_get_detected_xtal_freq(void); #define RTC_STORE5 (DR_REG_RTCCNTL_BASE + 0xb4) +#define MHZ 1000000 /* * The symbol 'ets_get_detected_xtal_freq_patch' is defined as: * PROVIDE ( ets_get_detected_xtal_freq_patch = 40065c18 ); @@ -57,6 +60,15 @@ static uint32_t ets_get_detected_xtal_freq_patch() return clock; } +uint32_t stub_target_get_apb_freq(void) +{ + // If APB clock source is PLL, APB is 80MHz, otherwise it is the same as crystal frequency + if (REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL) == 1) { + return 80 * MHZ; + } + return ets_get_detected_xtal_freq_patch(); +} + void stub_target_rom_uart_attach(void *rxBuffer) { (void)rxBuffer; // ESP32 ROM doesn't take parameter @@ -71,14 +83,17 @@ void stub_target_rom_uart_init(uint8_t uart_no, uint32_t clock) void stub_target_uart_init(uint8_t uart_num) { stub_target_rom_uart_attach(NULL); - stub_target_rom_uart_init(uart_num, ets_get_detected_xtal_freq_patch()); + stub_target_rom_uart_init(uart_num, stub_target_get_apb_freq()); esp_rom_uart_set_as_console(uart_num); } void stub_target_uart_rominit_set_baudrate(uint8_t uart_num, uint32_t baudrate) { - uint32_t clock = ets_get_detected_xtal_freq_patch() << 4; - uint32_t divisor = clock / baudrate; + stub_lib_delay_us(5 * 1000); + + uint32_t clk_div = (stub_target_get_apb_freq() << 4) / baudrate; stub_target_uart_wait_idle(uart_num); - esp_rom_uart_div_modify(uart_num, divisor); + esp_rom_uart_div_modify(uart_num, clk_div); + + stub_lib_delay_us(5 * 1000); } diff --git a/src/target/esp32c2/CMakeLists.txt b/src/target/esp32c2/CMakeLists.txt index 985d301..2969334 100644 --- a/src/target/esp32c2/CMakeLists.txt +++ b/src/target/esp32c2/CMakeLists.txt @@ -1,5 +1,6 @@ set(srcs src/uart.c + src/clock.c ) add_library(${ESP_TARGET_LIB} STATIC ${srcs}) diff --git a/src/target/esp32c2/include/soc/system_reg.h b/src/target/esp32c2/include/soc/system_reg.h new file mode 100644 index 0000000..844ecfd --- /dev/null +++ b/src/target/esp32c2/include/soc/system_reg.h @@ -0,0 +1,939 @@ +/** + * SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 OR MIT + */ +#pragma once + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** SYSTEM_CPU_PERI_CLK_EN_REG register + * cpu_peripheral clock gating register + */ +#define SYSTEM_CPU_PERI_CLK_EN_REG (DR_REG_SYSTEM_BASE + 0x0) +/** SYSTEM_CLK_EN_ASSIST_DEBUG : R/W; bitpos: [6]; default: 0; + * Set 1 to open assist_debug module clock + */ +#define SYSTEM_CLK_EN_ASSIST_DEBUG (BIT(6)) +#define SYSTEM_CLK_EN_ASSIST_DEBUG_M (SYSTEM_CLK_EN_ASSIST_DEBUG_V << SYSTEM_CLK_EN_ASSIST_DEBUG_S) +#define SYSTEM_CLK_EN_ASSIST_DEBUG_V 0x00000001U +#define SYSTEM_CLK_EN_ASSIST_DEBUG_S 6 +/** SYSTEM_CLK_EN_DEDICATED_GPIO : R/W; bitpos: [7]; default: 0; + * Set 1 to open dedicated_gpio module clk + */ +#define SYSTEM_CLK_EN_DEDICATED_GPIO (BIT(7)) +#define SYSTEM_CLK_EN_DEDICATED_GPIO_M (SYSTEM_CLK_EN_DEDICATED_GPIO_V << SYSTEM_CLK_EN_DEDICATED_GPIO_S) +#define SYSTEM_CLK_EN_DEDICATED_GPIO_V 0x00000001U +#define SYSTEM_CLK_EN_DEDICATED_GPIO_S 7 + +/** SYSTEM_CPU_PERI_RST_EN_REG register + * cpu_peripheral reset register + */ +#define SYSTEM_CPU_PERI_RST_EN_REG (DR_REG_SYSTEM_BASE + 0x4) +/** SYSTEM_RST_EN_ASSIST_DEBUG : R/W; bitpos: [6]; default: 1; + * Set 1 to let assist_debug module reset + */ +#define SYSTEM_RST_EN_ASSIST_DEBUG (BIT(6)) +#define SYSTEM_RST_EN_ASSIST_DEBUG_M (SYSTEM_RST_EN_ASSIST_DEBUG_V << SYSTEM_RST_EN_ASSIST_DEBUG_S) +#define SYSTEM_RST_EN_ASSIST_DEBUG_V 0x00000001U +#define SYSTEM_RST_EN_ASSIST_DEBUG_S 6 +/** SYSTEM_RST_EN_DEDICATED_GPIO : R/W; bitpos: [7]; default: 1; + * Set 1 to let dedicated_gpio module reset + */ +#define SYSTEM_RST_EN_DEDICATED_GPIO (BIT(7)) +#define SYSTEM_RST_EN_DEDICATED_GPIO_M (SYSTEM_RST_EN_DEDICATED_GPIO_V << SYSTEM_RST_EN_DEDICATED_GPIO_S) +#define SYSTEM_RST_EN_DEDICATED_GPIO_V 0x00000001U +#define SYSTEM_RST_EN_DEDICATED_GPIO_S 7 + +/** SYSTEM_CPU_PER_CONF_REG register + * cpu clock config register + */ +#define SYSTEM_CPU_PER_CONF_REG (DR_REG_SYSTEM_BASE + 0x8) +/** SYSTEM_CPUPERIOD_SEL : R/W; bitpos: [1:0]; default: 0; + * This field used to sel cpu clock frequent. + */ +#define SYSTEM_CPUPERIOD_SEL 0x00000003U +#define SYSTEM_CPUPERIOD_SEL_M (SYSTEM_CPUPERIOD_SEL_V << SYSTEM_CPUPERIOD_SEL_S) +#define SYSTEM_CPUPERIOD_SEL_V 0x00000003U +#define SYSTEM_CPUPERIOD_SEL_S 0 +/** SYSTEM_PLL_FREQ_SEL : R/W; bitpos: [2]; default: 1; + * This field used to sel pll frequent. + */ +#define SYSTEM_PLL_FREQ_SEL (BIT(2)) +#define SYSTEM_PLL_FREQ_SEL_M (SYSTEM_PLL_FREQ_SEL_V << SYSTEM_PLL_FREQ_SEL_S) +#define SYSTEM_PLL_FREQ_SEL_V 0x00000001U +#define SYSTEM_PLL_FREQ_SEL_S 2 +/** SYSTEM_CPU_WAIT_MODE_FORCE_ON : R/W; bitpos: [3]; default: 1; + * Set 1 to force cpu_waiti_clk enable. + */ +#define SYSTEM_CPU_WAIT_MODE_FORCE_ON (BIT(3)) +#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_M (SYSTEM_CPU_WAIT_MODE_FORCE_ON_V << SYSTEM_CPU_WAIT_MODE_FORCE_ON_S) +#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_V 0x00000001U +#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_S 3 +/** SYSTEM_CPU_WAITI_DELAY_NUM : R/W; bitpos: [7:4]; default: 0; + * This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk + * will close + */ +#define SYSTEM_CPU_WAITI_DELAY_NUM 0x0000000FU +#define SYSTEM_CPU_WAITI_DELAY_NUM_M (SYSTEM_CPU_WAITI_DELAY_NUM_V << SYSTEM_CPU_WAITI_DELAY_NUM_S) +#define SYSTEM_CPU_WAITI_DELAY_NUM_V 0x0000000FU +#define SYSTEM_CPU_WAITI_DELAY_NUM_S 4 + +/** SYSTEM_MEM_PD_MASK_REG register + * memory power down mask register + */ +#define SYSTEM_MEM_PD_MASK_REG (DR_REG_SYSTEM_BASE + 0xc) +/** SYSTEM_LSLP_MEM_PD_MASK : R/W; bitpos: [0]; default: 1; + * Set 1 to mask memory power down. + */ +#define SYSTEM_LSLP_MEM_PD_MASK (BIT(0)) +#define SYSTEM_LSLP_MEM_PD_MASK_M (SYSTEM_LSLP_MEM_PD_MASK_V << SYSTEM_LSLP_MEM_PD_MASK_S) +#define SYSTEM_LSLP_MEM_PD_MASK_V 0x00000001U +#define SYSTEM_LSLP_MEM_PD_MASK_S 0 + +/** SYSTEM_PERIP_CLK_EN0_REG register + * peripheral clock gating register + */ +#define SYSTEM_PERIP_CLK_EN0_REG (DR_REG_SYSTEM_BASE + 0x10) +/** SYSTEM_SPI01_CLK_EN : R/W; bitpos: [1]; default: 1; + * Set 1 to enable SPI01 clock + */ +#define SYSTEM_SPI01_CLK_EN (BIT(1)) +#define SYSTEM_SPI01_CLK_EN_M (SYSTEM_SPI01_CLK_EN_V << SYSTEM_SPI01_CLK_EN_S) +#define SYSTEM_SPI01_CLK_EN_V 0x00000001U +#define SYSTEM_SPI01_CLK_EN_S 1 +/** SYSTEM_UART_CLK_EN : R/W; bitpos: [2]; default: 1; + * Set 1 to enable UART clock + */ +#define SYSTEM_UART_CLK_EN (BIT(2)) +#define SYSTEM_UART_CLK_EN_M (SYSTEM_UART_CLK_EN_V << SYSTEM_UART_CLK_EN_S) +#define SYSTEM_UART_CLK_EN_V 0x00000001U +#define SYSTEM_UART_CLK_EN_S 2 +/** SYSTEM_UART1_CLK_EN : R/W; bitpos: [5]; default: 1; + * Set 1 to enable UART1 clock + */ +#define SYSTEM_UART1_CLK_EN (BIT(5)) +#define SYSTEM_UART1_CLK_EN_M (SYSTEM_UART1_CLK_EN_V << SYSTEM_UART1_CLK_EN_S) +#define SYSTEM_UART1_CLK_EN_V 0x00000001U +#define SYSTEM_UART1_CLK_EN_S 5 +/** SYSTEM_SPI2_CLK_EN : R/W; bitpos: [6]; default: 1; + * Set 1 to enable SPI2 clock + */ +#define SYSTEM_SPI2_CLK_EN (BIT(6)) +#define SYSTEM_SPI2_CLK_EN_M (SYSTEM_SPI2_CLK_EN_V << SYSTEM_SPI2_CLK_EN_S) +#define SYSTEM_SPI2_CLK_EN_V 0x00000001U +#define SYSTEM_SPI2_CLK_EN_S 6 +/** SYSTEM_I2C_EXT0_CLK_EN : R/W; bitpos: [7]; default: 0; + * Set 1 to enable I2C_EXT0 clock + */ +#define SYSTEM_I2C_EXT0_CLK_EN (BIT(7)) +#define SYSTEM_I2C_EXT0_CLK_EN_M (SYSTEM_I2C_EXT0_CLK_EN_V << SYSTEM_I2C_EXT0_CLK_EN_S) +#define SYSTEM_I2C_EXT0_CLK_EN_V 0x00000001U +#define SYSTEM_I2C_EXT0_CLK_EN_S 7 +/** SYSTEM_LEDC_CLK_EN : R/W; bitpos: [11]; default: 0; + * Set 1 to enable LEDC clock + */ +#define SYSTEM_LEDC_CLK_EN (BIT(11)) +#define SYSTEM_LEDC_CLK_EN_M (SYSTEM_LEDC_CLK_EN_V << SYSTEM_LEDC_CLK_EN_S) +#define SYSTEM_LEDC_CLK_EN_V 0x00000001U +#define SYSTEM_LEDC_CLK_EN_S 11 +/** SYSTEM_TIMERGROUP_CLK_EN : R/W; bitpos: [13]; default: 1; + * Set 1 to enable TIMERGROUP clock + */ +#define SYSTEM_TIMERGROUP_CLK_EN (BIT(13)) +#define SYSTEM_TIMERGROUP_CLK_EN_M (SYSTEM_TIMERGROUP_CLK_EN_V << SYSTEM_TIMERGROUP_CLK_EN_S) +#define SYSTEM_TIMERGROUP_CLK_EN_V 0x00000001U +#define SYSTEM_TIMERGROUP_CLK_EN_S 13 +/** SYSTEM_UART_MEM_CLK_EN : R/W; bitpos: [24]; default: 1; + * Set 1 to enable UART_MEM clock + */ +#define SYSTEM_UART_MEM_CLK_EN (BIT(24)) +#define SYSTEM_UART_MEM_CLK_EN_M (SYSTEM_UART_MEM_CLK_EN_V << SYSTEM_UART_MEM_CLK_EN_S) +#define SYSTEM_UART_MEM_CLK_EN_V 0x00000001U +#define SYSTEM_UART_MEM_CLK_EN_S 24 +/** SYSTEM_APB_SARADC_CLK_EN : R/W; bitpos: [28]; default: 1; + * Set 1 to enable APB_SARADC clock + */ +#define SYSTEM_APB_SARADC_CLK_EN (BIT(28)) +#define SYSTEM_APB_SARADC_CLK_EN_M (SYSTEM_APB_SARADC_CLK_EN_V << SYSTEM_APB_SARADC_CLK_EN_S) +#define SYSTEM_APB_SARADC_CLK_EN_V 0x00000001U +#define SYSTEM_APB_SARADC_CLK_EN_S 28 +/** SYSTEM_SYSTIMER_CLK_EN : R/W; bitpos: [29]; default: 1; + * Set 1 to enable SYSTEMTIMER clock + */ +#define SYSTEM_SYSTIMER_CLK_EN (BIT(29)) +#define SYSTEM_SYSTIMER_CLK_EN_M (SYSTEM_SYSTIMER_CLK_EN_V << SYSTEM_SYSTIMER_CLK_EN_S) +#define SYSTEM_SYSTIMER_CLK_EN_V 0x00000001U +#define SYSTEM_SYSTIMER_CLK_EN_S 29 +/** SYSTEM_ADC2_ARB_CLK_EN : R/W; bitpos: [30]; default: 1; + * Set 1 to enable ADC2_ARB clock + */ +#define SYSTEM_ADC2_ARB_CLK_EN (BIT(30)) +#define SYSTEM_ADC2_ARB_CLK_EN_M (SYSTEM_ADC2_ARB_CLK_EN_V << SYSTEM_ADC2_ARB_CLK_EN_S) +#define SYSTEM_ADC2_ARB_CLK_EN_V 0x00000001U +#define SYSTEM_ADC2_ARB_CLK_EN_S 30 + +/** SYSTEM_PERIP_CLK_EN1_REG register + * peripheral clock gating register + */ +#define SYSTEM_PERIP_CLK_EN1_REG (DR_REG_SYSTEM_BASE + 0x14) +/** SYSTEM_CRYPTO_ECC_CLK_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to enable ECC clock + */ +#define SYSTEM_CRYPTO_ECC_CLK_EN (BIT(1)) +#define SYSTEM_CRYPTO_ECC_CLK_EN_M (SYSTEM_CRYPTO_ECC_CLK_EN_V << SYSTEM_CRYPTO_ECC_CLK_EN_S) +#define SYSTEM_CRYPTO_ECC_CLK_EN_V 0x00000001U +#define SYSTEM_CRYPTO_ECC_CLK_EN_S 1 +/** SYSTEM_CRYPTO_SHA_CLK_EN : R/W; bitpos: [2]; default: 0; + * Set 1 to enable SHA clock + */ +#define SYSTEM_CRYPTO_SHA_CLK_EN (BIT(2)) +#define SYSTEM_CRYPTO_SHA_CLK_EN_M (SYSTEM_CRYPTO_SHA_CLK_EN_V << SYSTEM_CRYPTO_SHA_CLK_EN_S) +#define SYSTEM_CRYPTO_SHA_CLK_EN_V 0x00000001U +#define SYSTEM_CRYPTO_SHA_CLK_EN_S 2 +/** SYSTEM_DMA_CLK_EN : R/W; bitpos: [6]; default: 0; + * Set 1 to enable DMA clock + */ +#define SYSTEM_DMA_CLK_EN (BIT(6)) +#define SYSTEM_DMA_CLK_EN_M (SYSTEM_DMA_CLK_EN_V << SYSTEM_DMA_CLK_EN_S) +#define SYSTEM_DMA_CLK_EN_V 0x00000001U +#define SYSTEM_DMA_CLK_EN_S 6 +/** SYSTEM_TSENS_CLK_EN : R/W; bitpos: [10]; default: 0; + * Set 1 to enable TSENS clock + */ +#define SYSTEM_TSENS_CLK_EN (BIT(10)) +#define SYSTEM_TSENS_CLK_EN_M (SYSTEM_TSENS_CLK_EN_V << SYSTEM_TSENS_CLK_EN_S) +#define SYSTEM_TSENS_CLK_EN_V 0x00000001U +#define SYSTEM_TSENS_CLK_EN_S 10 + +/** SYSTEM_PERIP_RST_EN0_REG register + * reserved + */ +#define SYSTEM_PERIP_RST_EN0_REG (DR_REG_SYSTEM_BASE + 0x18) +/** SYSTEM_SPI01_RST : R/W; bitpos: [1]; default: 0; + * Set 1 to let SPI01 reset + */ +#define SYSTEM_SPI01_RST (BIT(1)) +#define SYSTEM_SPI01_RST_M (SYSTEM_SPI01_RST_V << SYSTEM_SPI01_RST_S) +#define SYSTEM_SPI01_RST_V 0x00000001U +#define SYSTEM_SPI01_RST_S 1 +/** SYSTEM_UART_RST : R/W; bitpos: [2]; default: 0; + * Set 1 to let UART reset + */ +#define SYSTEM_UART_RST (BIT(2)) +#define SYSTEM_UART_RST_M (SYSTEM_UART_RST_V << SYSTEM_UART_RST_S) +#define SYSTEM_UART_RST_V 0x00000001U +#define SYSTEM_UART_RST_S 2 +/** SYSTEM_UART1_RST : R/W; bitpos: [5]; default: 0; + * Set 1 to let UART1 reset + */ +#define SYSTEM_UART1_RST (BIT(5)) +#define SYSTEM_UART1_RST_M (SYSTEM_UART1_RST_V << SYSTEM_UART1_RST_S) +#define SYSTEM_UART1_RST_V 0x00000001U +#define SYSTEM_UART1_RST_S 5 +/** SYSTEM_SPI2_RST : R/W; bitpos: [6]; default: 0; + * Set 1 to let SPI2 reset + */ +#define SYSTEM_SPI2_RST (BIT(6)) +#define SYSTEM_SPI2_RST_M (SYSTEM_SPI2_RST_V << SYSTEM_SPI2_RST_S) +#define SYSTEM_SPI2_RST_V 0x00000001U +#define SYSTEM_SPI2_RST_S 6 +/** SYSTEM_I2C_EXT0_RST : R/W; bitpos: [7]; default: 0; + * Set 1 to let I2C_EXT0 reset + */ +#define SYSTEM_I2C_EXT0_RST (BIT(7)) +#define SYSTEM_I2C_EXT0_RST_M (SYSTEM_I2C_EXT0_RST_V << SYSTEM_I2C_EXT0_RST_S) +#define SYSTEM_I2C_EXT0_RST_V 0x00000001U +#define SYSTEM_I2C_EXT0_RST_S 7 +/** SYSTEM_LEDC_RST : R/W; bitpos: [11]; default: 0; + * Set 1 to let LEDC reset + */ +#define SYSTEM_LEDC_RST (BIT(11)) +#define SYSTEM_LEDC_RST_M (SYSTEM_LEDC_RST_V << SYSTEM_LEDC_RST_S) +#define SYSTEM_LEDC_RST_V 0x00000001U +#define SYSTEM_LEDC_RST_S 11 +/** SYSTEM_TIMERGROUP_RST : R/W; bitpos: [13]; default: 0; + * Set 1 to let TIMERGROUP reset + */ +#define SYSTEM_TIMERGROUP_RST (BIT(13)) +#define SYSTEM_TIMERGROUP_RST_M (SYSTEM_TIMERGROUP_RST_V << SYSTEM_TIMERGROUP_RST_S) +#define SYSTEM_TIMERGROUP_RST_V 0x00000001U +#define SYSTEM_TIMERGROUP_RST_S 13 +/** SYSTEM_UART_MEM_RST : R/W; bitpos: [24]; default: 0; + * Set 1 to let UART_MEM reset + */ +#define SYSTEM_UART_MEM_RST (BIT(24)) +#define SYSTEM_UART_MEM_RST_M (SYSTEM_UART_MEM_RST_V << SYSTEM_UART_MEM_RST_S) +#define SYSTEM_UART_MEM_RST_V 0x00000001U +#define SYSTEM_UART_MEM_RST_S 24 +/** SYSTEM_APB_SARADC_RST : R/W; bitpos: [28]; default: 0; + * Set 1 to let APB_SARADC reset + */ +#define SYSTEM_APB_SARADC_RST (BIT(28)) +#define SYSTEM_APB_SARADC_RST_M (SYSTEM_APB_SARADC_RST_V << SYSTEM_APB_SARADC_RST_S) +#define SYSTEM_APB_SARADC_RST_V 0x00000001U +#define SYSTEM_APB_SARADC_RST_S 28 +/** SYSTEM_SYSTIMER_RST : R/W; bitpos: [29]; default: 0; + * Set 1 to let SYSTIMER reset + */ +#define SYSTEM_SYSTIMER_RST (BIT(29)) +#define SYSTEM_SYSTIMER_RST_M (SYSTEM_SYSTIMER_RST_V << SYSTEM_SYSTIMER_RST_S) +#define SYSTEM_SYSTIMER_RST_V 0x00000001U +#define SYSTEM_SYSTIMER_RST_S 29 +/** SYSTEM_ADC2_ARB_RST : R/W; bitpos: [30]; default: 0; + * Set 1 to let ADC2_ARB reset + */ +#define SYSTEM_ADC2_ARB_RST (BIT(30)) +#define SYSTEM_ADC2_ARB_RST_M (SYSTEM_ADC2_ARB_RST_V << SYSTEM_ADC2_ARB_RST_S) +#define SYSTEM_ADC2_ARB_RST_V 0x00000001U +#define SYSTEM_ADC2_ARB_RST_S 30 + +/** SYSTEM_PERIP_RST_EN1_REG register + * peripheral reset register + */ +#define SYSTEM_PERIP_RST_EN1_REG (DR_REG_SYSTEM_BASE + 0x1c) +/** SYSTEM_CRYPTO_ECC_RST : R/W; bitpos: [1]; default: 1; + * Set 1 to let CRYPTO_ECC reset + */ +#define SYSTEM_CRYPTO_ECC_RST (BIT(1)) +#define SYSTEM_CRYPTO_ECC_RST_M (SYSTEM_CRYPTO_ECC_RST_V << SYSTEM_CRYPTO_ECC_RST_S) +#define SYSTEM_CRYPTO_ECC_RST_V 0x00000001U +#define SYSTEM_CRYPTO_ECC_RST_S 1 +/** SYSTEM_CRYPTO_SHA_RST : R/W; bitpos: [2]; default: 1; + * Set 1 to let CRYPTO_SHA reset + */ +#define SYSTEM_CRYPTO_SHA_RST (BIT(2)) +#define SYSTEM_CRYPTO_SHA_RST_M (SYSTEM_CRYPTO_SHA_RST_V << SYSTEM_CRYPTO_SHA_RST_S) +#define SYSTEM_CRYPTO_SHA_RST_V 0x00000001U +#define SYSTEM_CRYPTO_SHA_RST_S 2 +/** SYSTEM_DMA_RST : R/W; bitpos: [6]; default: 1; + * Set 1 to let DMA reset + */ +#define SYSTEM_DMA_RST (BIT(6)) +#define SYSTEM_DMA_RST_M (SYSTEM_DMA_RST_V << SYSTEM_DMA_RST_S) +#define SYSTEM_DMA_RST_V 0x00000001U +#define SYSTEM_DMA_RST_S 6 +/** SYSTEM_TSENS_RST : R/W; bitpos: [10]; default: 0; + * Set 1 to let TSENS reset + */ +#define SYSTEM_TSENS_RST (BIT(10)) +#define SYSTEM_TSENS_RST_M (SYSTEM_TSENS_RST_V << SYSTEM_TSENS_RST_S) +#define SYSTEM_TSENS_RST_V 0x00000001U +#define SYSTEM_TSENS_RST_S 10 + +/** SYSTEM_BT_LPCK_DIV_INT_REG register + * clock config register + */ +#define SYSTEM_BT_LPCK_DIV_INT_REG (DR_REG_SYSTEM_BASE + 0x20) +/** SYSTEM_BT_LPCK_DIV_NUM : R/W; bitpos: [11:0]; default: 255; + * This field is lower power clock frequent division factor + */ +#define SYSTEM_BT_LPCK_DIV_NUM 0x00000FFFU +#define SYSTEM_BT_LPCK_DIV_NUM_M (SYSTEM_BT_LPCK_DIV_NUM_V << SYSTEM_BT_LPCK_DIV_NUM_S) +#define SYSTEM_BT_LPCK_DIV_NUM_V 0x00000FFFU +#define SYSTEM_BT_LPCK_DIV_NUM_S 0 + +/** SYSTEM_BT_LPCK_DIV_FRAC_REG register + * low power clock configuration register + */ +#define SYSTEM_BT_LPCK_DIV_FRAC_REG (DR_REG_SYSTEM_BASE + 0x24) +/** SYSTEM_BT_LPCK_DIV_B : R/W; bitpos: [11:0]; default: 1; + * This field is lower power clock frequent division factor b + */ +#define SYSTEM_BT_LPCK_DIV_B 0x00000FFFU +#define SYSTEM_BT_LPCK_DIV_B_M (SYSTEM_BT_LPCK_DIV_B_V << SYSTEM_BT_LPCK_DIV_B_S) +#define SYSTEM_BT_LPCK_DIV_B_V 0x00000FFFU +#define SYSTEM_BT_LPCK_DIV_B_S 0 +/** SYSTEM_BT_LPCK_DIV_A : R/W; bitpos: [23:12]; default: 1; + * This field is lower power clock frequent division factor a + */ +#define SYSTEM_BT_LPCK_DIV_A 0x00000FFFU +#define SYSTEM_BT_LPCK_DIV_A_M (SYSTEM_BT_LPCK_DIV_A_V << SYSTEM_BT_LPCK_DIV_A_S) +#define SYSTEM_BT_LPCK_DIV_A_V 0x00000FFFU +#define SYSTEM_BT_LPCK_DIV_A_S 12 +/** SYSTEM_LPCLK_SEL_RTC_SLOW : R/W; bitpos: [24]; default: 0; + * Set 1 to select rtc-slow clock as rtc low power clock + */ +#define SYSTEM_LPCLK_SEL_RTC_SLOW (BIT(24)) +#define SYSTEM_LPCLK_SEL_RTC_SLOW_M (SYSTEM_LPCLK_SEL_RTC_SLOW_V << SYSTEM_LPCLK_SEL_RTC_SLOW_S) +#define SYSTEM_LPCLK_SEL_RTC_SLOW_V 0x00000001U +#define SYSTEM_LPCLK_SEL_RTC_SLOW_S 24 +/** SYSTEM_LPCLK_SEL_8M : R/W; bitpos: [25]; default: 1; + * Set 1 to select 8m clock as rtc low power clock + */ +#define SYSTEM_LPCLK_SEL_8M (BIT(25)) +#define SYSTEM_LPCLK_SEL_8M_M (SYSTEM_LPCLK_SEL_8M_V << SYSTEM_LPCLK_SEL_8M_S) +#define SYSTEM_LPCLK_SEL_8M_V 0x00000001U +#define SYSTEM_LPCLK_SEL_8M_S 25 +/** SYSTEM_LPCLK_SEL_XTAL : R/W; bitpos: [26]; default: 0; + * Set 1 to select xtal clock as rtc low power clock + */ +#define SYSTEM_LPCLK_SEL_XTAL (BIT(26)) +#define SYSTEM_LPCLK_SEL_XTAL_M (SYSTEM_LPCLK_SEL_XTAL_V << SYSTEM_LPCLK_SEL_XTAL_S) +#define SYSTEM_LPCLK_SEL_XTAL_V 0x00000001U +#define SYSTEM_LPCLK_SEL_XTAL_S 26 +/** SYSTEM_LPCLK_SEL_XTAL32K : R/W; bitpos: [27]; default: 0; + * Set 1 to select xtal32k clock as low power clock + */ +#define SYSTEM_LPCLK_SEL_XTAL32K (BIT(27)) +#define SYSTEM_LPCLK_SEL_XTAL32K_M (SYSTEM_LPCLK_SEL_XTAL32K_V << SYSTEM_LPCLK_SEL_XTAL32K_S) +#define SYSTEM_LPCLK_SEL_XTAL32K_V 0x00000001U +#define SYSTEM_LPCLK_SEL_XTAL32K_S 27 +/** SYSTEM_LPCLK_RTC_EN : R/W; bitpos: [28]; default: 0; + * Set 1 to enable RTC low power clock + */ +#define SYSTEM_LPCLK_RTC_EN (BIT(28)) +#define SYSTEM_LPCLK_RTC_EN_M (SYSTEM_LPCLK_RTC_EN_V << SYSTEM_LPCLK_RTC_EN_S) +#define SYSTEM_LPCLK_RTC_EN_V 0x00000001U +#define SYSTEM_LPCLK_RTC_EN_S 28 + +/** SYSTEM_CPU_INTR_FROM_CPU_0_REG register + * interrupt generate register + */ +#define SYSTEM_CPU_INTR_FROM_CPU_0_REG (DR_REG_SYSTEM_BASE + 0x28) +/** SYSTEM_CPU_INTR_FROM_CPU_0 : R/W; bitpos: [0]; default: 0; + * Set 1 to generate cpu interrupt 0 + */ +#define SYSTEM_CPU_INTR_FROM_CPU_0 (BIT(0)) +#define SYSTEM_CPU_INTR_FROM_CPU_0_M (SYSTEM_CPU_INTR_FROM_CPU_0_V << SYSTEM_CPU_INTR_FROM_CPU_0_S) +#define SYSTEM_CPU_INTR_FROM_CPU_0_V 0x00000001U +#define SYSTEM_CPU_INTR_FROM_CPU_0_S 0 + +/** SYSTEM_CPU_INTR_FROM_CPU_1_REG register + * interrupt generate register + */ +#define SYSTEM_CPU_INTR_FROM_CPU_1_REG (DR_REG_SYSTEM_BASE + 0x2c) +/** SYSTEM_CPU_INTR_FROM_CPU_1 : R/W; bitpos: [0]; default: 0; + * Set 1 to generate cpu interrupt 1 + */ +#define SYSTEM_CPU_INTR_FROM_CPU_1 (BIT(0)) +#define SYSTEM_CPU_INTR_FROM_CPU_1_M (SYSTEM_CPU_INTR_FROM_CPU_1_V << SYSTEM_CPU_INTR_FROM_CPU_1_S) +#define SYSTEM_CPU_INTR_FROM_CPU_1_V 0x00000001U +#define SYSTEM_CPU_INTR_FROM_CPU_1_S 0 + +/** SYSTEM_CPU_INTR_FROM_CPU_2_REG register + * interrupt generate register + */ +#define SYSTEM_CPU_INTR_FROM_CPU_2_REG (DR_REG_SYSTEM_BASE + 0x30) +/** SYSTEM_CPU_INTR_FROM_CPU_2 : R/W; bitpos: [0]; default: 0; + * Set 1 to generate cpu interrupt 2 + */ +#define SYSTEM_CPU_INTR_FROM_CPU_2 (BIT(0)) +#define SYSTEM_CPU_INTR_FROM_CPU_2_M (SYSTEM_CPU_INTR_FROM_CPU_2_V << SYSTEM_CPU_INTR_FROM_CPU_2_S) +#define SYSTEM_CPU_INTR_FROM_CPU_2_V 0x00000001U +#define SYSTEM_CPU_INTR_FROM_CPU_2_S 0 + +/** SYSTEM_CPU_INTR_FROM_CPU_3_REG register + * interrupt generate register + */ +#define SYSTEM_CPU_INTR_FROM_CPU_3_REG (DR_REG_SYSTEM_BASE + 0x34) +/** SYSTEM_CPU_INTR_FROM_CPU_3 : R/W; bitpos: [0]; default: 0; + * Set 1 to generate cpu interrupt 3 + */ +#define SYSTEM_CPU_INTR_FROM_CPU_3 (BIT(0)) +#define SYSTEM_CPU_INTR_FROM_CPU_3_M (SYSTEM_CPU_INTR_FROM_CPU_3_V << SYSTEM_CPU_INTR_FROM_CPU_3_S) +#define SYSTEM_CPU_INTR_FROM_CPU_3_V 0x00000001U +#define SYSTEM_CPU_INTR_FROM_CPU_3_S 0 + +/** SYSTEM_RSA_PD_CTRL_REG register + * rsa memory power control register + */ +#define SYSTEM_RSA_PD_CTRL_REG (DR_REG_SYSTEM_BASE + 0x38) +/** SYSTEM_RSA_MEM_PD : R/W; bitpos: [0]; default: 1; + * Set 1 to power down RSA memory. This bit has the lowest priority.When Digital + * Signature occupies the RSA. This bit is invalid. + */ +#define SYSTEM_RSA_MEM_PD (BIT(0)) +#define SYSTEM_RSA_MEM_PD_M (SYSTEM_RSA_MEM_PD_V << SYSTEM_RSA_MEM_PD_S) +#define SYSTEM_RSA_MEM_PD_V 0x00000001U +#define SYSTEM_RSA_MEM_PD_S 0 +/** SYSTEM_RSA_MEM_FORCE_PU : R/W; bitpos: [1]; default: 0; + * Set 1 to force power up RSA memory. This bit has the second highest priority. + */ +#define SYSTEM_RSA_MEM_FORCE_PU (BIT(1)) +#define SYSTEM_RSA_MEM_FORCE_PU_M (SYSTEM_RSA_MEM_FORCE_PU_V << SYSTEM_RSA_MEM_FORCE_PU_S) +#define SYSTEM_RSA_MEM_FORCE_PU_V 0x00000001U +#define SYSTEM_RSA_MEM_FORCE_PU_S 1 +/** SYSTEM_RSA_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; + * Set 1 to force power down RSA memory. This bit has the highest priority. + */ +#define SYSTEM_RSA_MEM_FORCE_PD (BIT(2)) +#define SYSTEM_RSA_MEM_FORCE_PD_M (SYSTEM_RSA_MEM_FORCE_PD_V << SYSTEM_RSA_MEM_FORCE_PD_S) +#define SYSTEM_RSA_MEM_FORCE_PD_V 0x00000001U +#define SYSTEM_RSA_MEM_FORCE_PD_S 2 + +/** SYSTEM_EDMA_CTRL_REG register + * edma clcok and reset register + */ +#define SYSTEM_EDMA_CTRL_REG (DR_REG_SYSTEM_BASE + 0x3c) +/** SYSTEM_EDMA_CLK_ON : R/W; bitpos: [0]; default: 1; + * Set 1 to enable EDMA clock. + */ +#define SYSTEM_EDMA_CLK_ON (BIT(0)) +#define SYSTEM_EDMA_CLK_ON_M (SYSTEM_EDMA_CLK_ON_V << SYSTEM_EDMA_CLK_ON_S) +#define SYSTEM_EDMA_CLK_ON_V 0x00000001U +#define SYSTEM_EDMA_CLK_ON_S 0 +/** SYSTEM_EDMA_RESET : R/W; bitpos: [1]; default: 0; + * Set 1 to let EDMA reset + */ +#define SYSTEM_EDMA_RESET (BIT(1)) +#define SYSTEM_EDMA_RESET_M (SYSTEM_EDMA_RESET_V << SYSTEM_EDMA_RESET_S) +#define SYSTEM_EDMA_RESET_V 0x00000001U +#define SYSTEM_EDMA_RESET_S 1 + +/** SYSTEM_CACHE_CONTROL_REG register + * cache control register + */ +#define SYSTEM_CACHE_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x40) +/** SYSTEM_ICACHE_CLK_ON : R/W; bitpos: [0]; default: 1; + * Set 1 to enable icache clock + */ +#define SYSTEM_ICACHE_CLK_ON (BIT(0)) +#define SYSTEM_ICACHE_CLK_ON_M (SYSTEM_ICACHE_CLK_ON_V << SYSTEM_ICACHE_CLK_ON_S) +#define SYSTEM_ICACHE_CLK_ON_V 0x00000001U +#define SYSTEM_ICACHE_CLK_ON_S 0 +/** SYSTEM_ICACHE_RESET : R/W; bitpos: [1]; default: 0; + * Set 1 to let icache reset + */ +#define SYSTEM_ICACHE_RESET (BIT(1)) +#define SYSTEM_ICACHE_RESET_M (SYSTEM_ICACHE_RESET_V << SYSTEM_ICACHE_RESET_S) +#define SYSTEM_ICACHE_RESET_V 0x00000001U +#define SYSTEM_ICACHE_RESET_S 1 +/** SYSTEM_DCACHE_CLK_ON : R/W; bitpos: [2]; default: 1; + * Set 1 to enable dcache clock + */ +#define SYSTEM_DCACHE_CLK_ON (BIT(2)) +#define SYSTEM_DCACHE_CLK_ON_M (SYSTEM_DCACHE_CLK_ON_V << SYSTEM_DCACHE_CLK_ON_S) +#define SYSTEM_DCACHE_CLK_ON_V 0x00000001U +#define SYSTEM_DCACHE_CLK_ON_S 2 +/** SYSTEM_DCACHE_RESET : R/W; bitpos: [3]; default: 0; + * Set 1 to let dcache reset + */ +#define SYSTEM_DCACHE_RESET (BIT(3)) +#define SYSTEM_DCACHE_RESET_M (SYSTEM_DCACHE_RESET_V << SYSTEM_DCACHE_RESET_S) +#define SYSTEM_DCACHE_RESET_V 0x00000001U +#define SYSTEM_DCACHE_RESET_S 3 + +/** SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG register + * SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG + */ +#define SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x44) +/** SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT : R/W; bitpos: [0]; default: 0; + * Set 1 to enable the SPI manual encrypt. + */ +#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT (BIT(0)) +#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_M (SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V << SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S) +#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V 0x00000001U +#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S 0 +/** SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT : R/W; bitpos: [1]; default: 0; + * Set 1 to enable download DB encrypt. + */ +#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT (BIT(1)) +#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_M (SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V << SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S) +#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V 0x00000001U +#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S 1 +/** SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT : R/W; bitpos: [2]; default: 0; + * Set 1 to enable download G0CB decrypt + */ +#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT (BIT(2)) +#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_M (SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V << SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S) +#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V 0x00000001U +#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S 2 +/** SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W; bitpos: [3]; default: 0; + * Set 1 to enable download manual encrypt + */ +#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT (BIT(3)) +#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_M (SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V << SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S) +#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001U +#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S 3 + +/** SYSTEM_RTC_FASTMEM_CONFIG_REG register + * fast memory config register + */ +#define SYSTEM_RTC_FASTMEM_CONFIG_REG (DR_REG_SYSTEM_BASE + 0x48) +/** SYSTEM_RTC_MEM_CRC_START : R/W; bitpos: [8]; default: 0; + * Set 1 to start the CRC of RTC memory + */ +#define SYSTEM_RTC_MEM_CRC_START (BIT(8)) +#define SYSTEM_RTC_MEM_CRC_START_M (SYSTEM_RTC_MEM_CRC_START_V << SYSTEM_RTC_MEM_CRC_START_S) +#define SYSTEM_RTC_MEM_CRC_START_V 0x00000001U +#define SYSTEM_RTC_MEM_CRC_START_S 8 +/** SYSTEM_RTC_MEM_CRC_ADDR : R/W; bitpos: [19:9]; default: 0; + * This field is used to set address of RTC memory for CRC. + */ +#define SYSTEM_RTC_MEM_CRC_ADDR 0x000007FFU +#define SYSTEM_RTC_MEM_CRC_ADDR_M (SYSTEM_RTC_MEM_CRC_ADDR_V << SYSTEM_RTC_MEM_CRC_ADDR_S) +#define SYSTEM_RTC_MEM_CRC_ADDR_V 0x000007FFU +#define SYSTEM_RTC_MEM_CRC_ADDR_S 9 +/** SYSTEM_RTC_MEM_CRC_LEN : R/W; bitpos: [30:20]; default: 2047; + * This field is used to set length of RTC memory for CRC based on start address. + */ +#define SYSTEM_RTC_MEM_CRC_LEN 0x000007FFU +#define SYSTEM_RTC_MEM_CRC_LEN_M (SYSTEM_RTC_MEM_CRC_LEN_V << SYSTEM_RTC_MEM_CRC_LEN_S) +#define SYSTEM_RTC_MEM_CRC_LEN_V 0x000007FFU +#define SYSTEM_RTC_MEM_CRC_LEN_S 20 +/** SYSTEM_RTC_MEM_CRC_FINISH : RO; bitpos: [31]; default: 0; + * This bit stores the status of RTC memory CRC.1 means finished. + */ +#define SYSTEM_RTC_MEM_CRC_FINISH (BIT(31)) +#define SYSTEM_RTC_MEM_CRC_FINISH_M (SYSTEM_RTC_MEM_CRC_FINISH_V << SYSTEM_RTC_MEM_CRC_FINISH_S) +#define SYSTEM_RTC_MEM_CRC_FINISH_V 0x00000001U +#define SYSTEM_RTC_MEM_CRC_FINISH_S 31 + +/** SYSTEM_RTC_FASTMEM_CRC_REG register + * reserved + */ +#define SYSTEM_RTC_FASTMEM_CRC_REG (DR_REG_SYSTEM_BASE + 0x4c) +/** SYSTEM_RTC_MEM_CRC_RES : RO; bitpos: [31:0]; default: 0; + * This field stores the CRC result of RTC memory. + */ +#define SYSTEM_RTC_MEM_CRC_RES 0xFFFFFFFFU +#define SYSTEM_RTC_MEM_CRC_RES_M (SYSTEM_RTC_MEM_CRC_RES_V << SYSTEM_RTC_MEM_CRC_RES_S) +#define SYSTEM_RTC_MEM_CRC_RES_V 0xFFFFFFFFU +#define SYSTEM_RTC_MEM_CRC_RES_S 0 + +/** SYSTEM_REDUNDANT_ECO_CTRL_REG register + * eco register + */ +#define SYSTEM_REDUNDANT_ECO_CTRL_REG (DR_REG_SYSTEM_BASE + 0x50) +/** SYSTEM_REDUNDANT_ECO_DRIVE : R/W; bitpos: [0]; default: 0; + * reg_redundant_eco_drive + */ +#define SYSTEM_REDUNDANT_ECO_DRIVE (BIT(0)) +#define SYSTEM_REDUNDANT_ECO_DRIVE_M (SYSTEM_REDUNDANT_ECO_DRIVE_V << SYSTEM_REDUNDANT_ECO_DRIVE_S) +#define SYSTEM_REDUNDANT_ECO_DRIVE_V 0x00000001U +#define SYSTEM_REDUNDANT_ECO_DRIVE_S 0 +/** SYSTEM_REDUNDANT_ECO_RESULT : RO; bitpos: [1]; default: 0; + * reg_redundant_eco_result + */ +#define SYSTEM_REDUNDANT_ECO_RESULT (BIT(1)) +#define SYSTEM_REDUNDANT_ECO_RESULT_M (SYSTEM_REDUNDANT_ECO_RESULT_V << SYSTEM_REDUNDANT_ECO_RESULT_S) +#define SYSTEM_REDUNDANT_ECO_RESULT_V 0x00000001U +#define SYSTEM_REDUNDANT_ECO_RESULT_S 1 + +/** SYSTEM_CLOCK_GATE_REG register + * clock gating register + */ +#define SYSTEM_CLOCK_GATE_REG (DR_REG_SYSTEM_BASE + 0x54) +/** SYSTEM_CLK_EN : R/W; bitpos: [0]; default: 1; + * reg_clk_en + */ +#define SYSTEM_CLK_EN (BIT(0)) +#define SYSTEM_CLK_EN_M (SYSTEM_CLK_EN_V << SYSTEM_CLK_EN_S) +#define SYSTEM_CLK_EN_V 0x00000001U +#define SYSTEM_CLK_EN_S 0 + +/** SYSTEM_SYSCLK_CONF_REG register + * system clock config register + */ +#define SYSTEM_SYSCLK_CONF_REG (DR_REG_SYSTEM_BASE + 0x58) +/** SYSTEM_PRE_DIV_CNT : R/W; bitpos: [9:0]; default: 1; + * This field is used to set the count of prescaler of XTAL_CLK. + */ +#define SYSTEM_PRE_DIV_CNT 0x000003FFU +#define SYSTEM_PRE_DIV_CNT_M (SYSTEM_PRE_DIV_CNT_V << SYSTEM_PRE_DIV_CNT_S) +#define SYSTEM_PRE_DIV_CNT_V 0x000003FFU +#define SYSTEM_PRE_DIV_CNT_S 0 +/** SYSTEM_SOC_CLK_SEL : R/W; bitpos: [11:10]; default: 0; + * This field is used to select soc clock. + */ +#define SYSTEM_SOC_CLK_SEL 0x00000003U +#define SYSTEM_SOC_CLK_SEL_M (SYSTEM_SOC_CLK_SEL_V << SYSTEM_SOC_CLK_SEL_S) +#define SYSTEM_SOC_CLK_SEL_V 0x00000003U +#define SYSTEM_SOC_CLK_SEL_S 10 +/** SYSTEM_CLK_XTAL_FREQ : RO; bitpos: [18:12]; default: 0; + * This field is used to read xtal frequency in MHz. + */ +#define SYSTEM_CLK_XTAL_FREQ 0x0000007FU +#define SYSTEM_CLK_XTAL_FREQ_M (SYSTEM_CLK_XTAL_FREQ_V << SYSTEM_CLK_XTAL_FREQ_S) +#define SYSTEM_CLK_XTAL_FREQ_V 0x0000007FU +#define SYSTEM_CLK_XTAL_FREQ_S 12 +/** SYSTEM_CLK_DIV_EN : RO; bitpos: [19]; default: 0; + * reg_clk_div_en + */ +#define SYSTEM_CLK_DIV_EN (BIT(19)) +#define SYSTEM_CLK_DIV_EN_M (SYSTEM_CLK_DIV_EN_V << SYSTEM_CLK_DIV_EN_S) +#define SYSTEM_CLK_DIV_EN_V 0x00000001U +#define SYSTEM_CLK_DIV_EN_S 19 + +/** SYSTEM_MEM_PVT_REG register + * mem pvt register + */ +#define SYSTEM_MEM_PVT_REG (DR_REG_SYSTEM_BASE + 0x5c) +/** SYSTEM_MEM_PATH_LEN : R/W; bitpos: [3:0]; default: 3; + * reg_mem_path_len + */ +#define SYSTEM_MEM_PATH_LEN 0x0000000FU +#define SYSTEM_MEM_PATH_LEN_M (SYSTEM_MEM_PATH_LEN_V << SYSTEM_MEM_PATH_LEN_S) +#define SYSTEM_MEM_PATH_LEN_V 0x0000000FU +#define SYSTEM_MEM_PATH_LEN_S 0 +/** SYSTEM_MEM_ERR_CNT_CLR : WT; bitpos: [4]; default: 0; + * reg_mem_err_cnt_clr + */ +#define SYSTEM_MEM_ERR_CNT_CLR (BIT(4)) +#define SYSTEM_MEM_ERR_CNT_CLR_M (SYSTEM_MEM_ERR_CNT_CLR_V << SYSTEM_MEM_ERR_CNT_CLR_S) +#define SYSTEM_MEM_ERR_CNT_CLR_V 0x00000001U +#define SYSTEM_MEM_ERR_CNT_CLR_S 4 +/** SYSTEM_MEM_PVT_MONITOR_EN : R/W; bitpos: [5]; default: 0; + * reg_mem_pvt_monitor_en + */ +#define SYSTEM_MEM_PVT_MONITOR_EN (BIT(5)) +#define SYSTEM_MEM_PVT_MONITOR_EN_M (SYSTEM_MEM_PVT_MONITOR_EN_V << SYSTEM_MEM_PVT_MONITOR_EN_S) +#define SYSTEM_MEM_PVT_MONITOR_EN_V 0x00000001U +#define SYSTEM_MEM_PVT_MONITOR_EN_S 5 +/** SYSTEM_MEM_TIMING_ERR_CNT : RO; bitpos: [21:6]; default: 0; + * reg_mem_timing_err_cnt + */ +#define SYSTEM_MEM_TIMING_ERR_CNT 0x0000FFFFU +#define SYSTEM_MEM_TIMING_ERR_CNT_M (SYSTEM_MEM_TIMING_ERR_CNT_V << SYSTEM_MEM_TIMING_ERR_CNT_S) +#define SYSTEM_MEM_TIMING_ERR_CNT_V 0x0000FFFFU +#define SYSTEM_MEM_TIMING_ERR_CNT_S 6 +/** SYSTEM_MEM_VT_SEL : R/W; bitpos: [23:22]; default: 0; + * reg_mem_vt_sel + */ +#define SYSTEM_MEM_VT_SEL 0x00000003U +#define SYSTEM_MEM_VT_SEL_M (SYSTEM_MEM_VT_SEL_V << SYSTEM_MEM_VT_SEL_S) +#define SYSTEM_MEM_VT_SEL_V 0x00000003U +#define SYSTEM_MEM_VT_SEL_S 22 + +/** SYSTEM_COMB_PVT_LVT_CONF_REG register + * mem pvt register + */ +#define SYSTEM_COMB_PVT_LVT_CONF_REG (DR_REG_SYSTEM_BASE + 0x60) +/** SYSTEM_COMB_PATH_LEN_LVT : R/W; bitpos: [5:0]; default: 3; + * reg_comb_path_len_lvt + */ +#define SYSTEM_COMB_PATH_LEN_LVT 0x0000003FU +#define SYSTEM_COMB_PATH_LEN_LVT_M (SYSTEM_COMB_PATH_LEN_LVT_V << SYSTEM_COMB_PATH_LEN_LVT_S) +#define SYSTEM_COMB_PATH_LEN_LVT_V 0x0000003FU +#define SYSTEM_COMB_PATH_LEN_LVT_S 0 +/** SYSTEM_COMB_ERR_CNT_CLR_LVT : WT; bitpos: [6]; default: 0; + * reg_comb_err_cnt_clr_lvt + */ +#define SYSTEM_COMB_ERR_CNT_CLR_LVT (BIT(6)) +#define SYSTEM_COMB_ERR_CNT_CLR_LVT_M (SYSTEM_COMB_ERR_CNT_CLR_LVT_V << SYSTEM_COMB_ERR_CNT_CLR_LVT_S) +#define SYSTEM_COMB_ERR_CNT_CLR_LVT_V 0x00000001U +#define SYSTEM_COMB_ERR_CNT_CLR_LVT_S 6 +/** SYSTEM_COMB_PVT_MONITOR_EN_LVT : R/W; bitpos: [7]; default: 0; + * reg_comb_pvt_monitor_en_lvt + */ +#define SYSTEM_COMB_PVT_MONITOR_EN_LVT (BIT(7)) +#define SYSTEM_COMB_PVT_MONITOR_EN_LVT_M (SYSTEM_COMB_PVT_MONITOR_EN_LVT_V << SYSTEM_COMB_PVT_MONITOR_EN_LVT_S) +#define SYSTEM_COMB_PVT_MONITOR_EN_LVT_V 0x00000001U +#define SYSTEM_COMB_PVT_MONITOR_EN_LVT_S 7 + +/** SYSTEM_COMB_PVT_NVT_CONF_REG register + * mem pvt register + */ +#define SYSTEM_COMB_PVT_NVT_CONF_REG (DR_REG_SYSTEM_BASE + 0x64) +/** SYSTEM_COMB_PATH_LEN_NVT : R/W; bitpos: [5:0]; default: 3; + * reg_comb_path_len_nvt + */ +#define SYSTEM_COMB_PATH_LEN_NVT 0x0000003FU +#define SYSTEM_COMB_PATH_LEN_NVT_M (SYSTEM_COMB_PATH_LEN_NVT_V << SYSTEM_COMB_PATH_LEN_NVT_S) +#define SYSTEM_COMB_PATH_LEN_NVT_V 0x0000003FU +#define SYSTEM_COMB_PATH_LEN_NVT_S 0 +/** SYSTEM_COMB_ERR_CNT_CLR_NVT : WT; bitpos: [6]; default: 0; + * reg_comb_err_cnt_clr_nvt + */ +#define SYSTEM_COMB_ERR_CNT_CLR_NVT (BIT(6)) +#define SYSTEM_COMB_ERR_CNT_CLR_NVT_M (SYSTEM_COMB_ERR_CNT_CLR_NVT_V << SYSTEM_COMB_ERR_CNT_CLR_NVT_S) +#define SYSTEM_COMB_ERR_CNT_CLR_NVT_V 0x00000001U +#define SYSTEM_COMB_ERR_CNT_CLR_NVT_S 6 +/** SYSTEM_COMB_PVT_MONITOR_EN_NVT : R/W; bitpos: [7]; default: 0; + * reg_comb_pvt_monitor_en_nvt + */ +#define SYSTEM_COMB_PVT_MONITOR_EN_NVT (BIT(7)) +#define SYSTEM_COMB_PVT_MONITOR_EN_NVT_M (SYSTEM_COMB_PVT_MONITOR_EN_NVT_V << SYSTEM_COMB_PVT_MONITOR_EN_NVT_S) +#define SYSTEM_COMB_PVT_MONITOR_EN_NVT_V 0x00000001U +#define SYSTEM_COMB_PVT_MONITOR_EN_NVT_S 7 + +/** SYSTEM_COMB_PVT_HVT_CONF_REG register + * mem pvt register + */ +#define SYSTEM_COMB_PVT_HVT_CONF_REG (DR_REG_SYSTEM_BASE + 0x68) +/** SYSTEM_COMB_PATH_LEN_HVT : R/W; bitpos: [5:0]; default: 3; + * reg_comb_path_len_hvt + */ +#define SYSTEM_COMB_PATH_LEN_HVT 0x0000003FU +#define SYSTEM_COMB_PATH_LEN_HVT_M (SYSTEM_COMB_PATH_LEN_HVT_V << SYSTEM_COMB_PATH_LEN_HVT_S) +#define SYSTEM_COMB_PATH_LEN_HVT_V 0x0000003FU +#define SYSTEM_COMB_PATH_LEN_HVT_S 0 +/** SYSTEM_COMB_ERR_CNT_CLR_HVT : WT; bitpos: [6]; default: 0; + * reg_comb_err_cnt_clr_hvt + */ +#define SYSTEM_COMB_ERR_CNT_CLR_HVT (BIT(6)) +#define SYSTEM_COMB_ERR_CNT_CLR_HVT_M (SYSTEM_COMB_ERR_CNT_CLR_HVT_V << SYSTEM_COMB_ERR_CNT_CLR_HVT_S) +#define SYSTEM_COMB_ERR_CNT_CLR_HVT_V 0x00000001U +#define SYSTEM_COMB_ERR_CNT_CLR_HVT_S 6 +/** SYSTEM_COMB_PVT_MONITOR_EN_HVT : R/W; bitpos: [7]; default: 0; + * reg_comb_pvt_monitor_en_hvt + */ +#define SYSTEM_COMB_PVT_MONITOR_EN_HVT (BIT(7)) +#define SYSTEM_COMB_PVT_MONITOR_EN_HVT_M (SYSTEM_COMB_PVT_MONITOR_EN_HVT_V << SYSTEM_COMB_PVT_MONITOR_EN_HVT_S) +#define SYSTEM_COMB_PVT_MONITOR_EN_HVT_V 0x00000001U +#define SYSTEM_COMB_PVT_MONITOR_EN_HVT_S 7 + +/** SYSTEM_COMB_PVT_ERR_LVT_SITE0_REG register + * mem pvt register + */ +#define SYSTEM_COMB_PVT_ERR_LVT_SITE0_REG (DR_REG_SYSTEM_BASE + 0x6c) +/** SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0 : RO; bitpos: [15:0]; default: 0; + * reg_comb_timing_err_cnt_lvt_site0 + */ +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0 0x0000FFFFU +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_M (SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_V << SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_S) +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_V 0x0000FFFFU +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_S 0 + +/** SYSTEM_COMB_PVT_ERR_NVT_SITE0_REG register + * mem pvt register + */ +#define SYSTEM_COMB_PVT_ERR_NVT_SITE0_REG (DR_REG_SYSTEM_BASE + 0x70) +/** SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0 : RO; bitpos: [15:0]; default: 0; + * reg_comb_timing_err_cnt_nvt_site0 + */ +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0 0x0000FFFFU +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_M (SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_V << SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_S) +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_V 0x0000FFFFU +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_S 0 + +/** SYSTEM_COMB_PVT_ERR_HVT_SITE0_REG register + * mem pvt register + */ +#define SYSTEM_COMB_PVT_ERR_HVT_SITE0_REG (DR_REG_SYSTEM_BASE + 0x74) +/** SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0 : RO; bitpos: [15:0]; default: 0; + * reg_comb_timing_err_cnt_hvt_site0 + */ +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0 0x0000FFFFU +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_M (SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_V << SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_S) +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_V 0x0000FFFFU +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_S 0 + +/** SYSTEM_COMB_PVT_ERR_LVT_SITE1_REG register + * mem pvt register + */ +#define SYSTEM_COMB_PVT_ERR_LVT_SITE1_REG (DR_REG_SYSTEM_BASE + 0x78) +/** SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1 : RO; bitpos: [15:0]; default: 0; + * reg_comb_timing_err_cnt_lvt_site1 + */ +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1 0x0000FFFFU +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_M (SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_V << SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_S) +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_V 0x0000FFFFU +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_S 0 + +/** SYSTEM_COMB_PVT_ERR_NVT_SITE1_REG register + * mem pvt register + */ +#define SYSTEM_COMB_PVT_ERR_NVT_SITE1_REG (DR_REG_SYSTEM_BASE + 0x7c) +/** SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1 : RO; bitpos: [15:0]; default: 0; + * reg_comb_timing_err_cnt_nvt_site1 + */ +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1 0x0000FFFFU +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_M (SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_V << SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_S) +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_V 0x0000FFFFU +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_S 0 + +/** SYSTEM_COMB_PVT_ERR_HVT_SITE1_REG register + * mem pvt register + */ +#define SYSTEM_COMB_PVT_ERR_HVT_SITE1_REG (DR_REG_SYSTEM_BASE + 0x80) +/** SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1 : RO; bitpos: [15:0]; default: 0; + * reg_comb_timing_err_cnt_hvt_site1 + */ +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1 0x0000FFFFU +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_M (SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_V << SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_S) +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_V 0x0000FFFFU +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_S 0 + +/** SYSTEM_COMB_PVT_ERR_LVT_SITE2_REG register + * mem pvt register + */ +#define SYSTEM_COMB_PVT_ERR_LVT_SITE2_REG (DR_REG_SYSTEM_BASE + 0x84) +/** SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2 : RO; bitpos: [15:0]; default: 0; + * reg_comb_timing_err_cnt_lvt_site2 + */ +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2 0x0000FFFFU +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_M (SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_V << SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_S) +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_V 0x0000FFFFU +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_S 0 + +/** SYSTEM_COMB_PVT_ERR_NVT_SITE2_REG register + * mem pvt register + */ +#define SYSTEM_COMB_PVT_ERR_NVT_SITE2_REG (DR_REG_SYSTEM_BASE + 0x88) +/** SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2 : RO; bitpos: [15:0]; default: 0; + * reg_comb_timing_err_cnt_nvt_site2 + */ +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2 0x0000FFFFU +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_M (SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_V << SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_S) +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_V 0x0000FFFFU +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_S 0 + +/** SYSTEM_COMB_PVT_ERR_HVT_SITE2_REG register + * mem pvt register + */ +#define SYSTEM_COMB_PVT_ERR_HVT_SITE2_REG (DR_REG_SYSTEM_BASE + 0x8c) +/** SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2 : RO; bitpos: [15:0]; default: 0; + * reg_comb_timing_err_cnt_hvt_site2 + */ +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2 0x0000FFFFU +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_M (SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_V << SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_S) +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_V 0x0000FFFFU +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_S 0 + +/** SYSTEM_COMB_PVT_ERR_LVT_SITE3_REG register + * mem pvt register + */ +#define SYSTEM_COMB_PVT_ERR_LVT_SITE3_REG (DR_REG_SYSTEM_BASE + 0x90) +/** SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3 : RO; bitpos: [15:0]; default: 0; + * reg_comb_timing_err_cnt_lvt_site3 + */ +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3 0x0000FFFFU +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_M (SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_V << SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_S) +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_V 0x0000FFFFU +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_S 0 + +/** SYSTEM_COMB_PVT_ERR_NVT_SITE3_REG register + * mem pvt register + */ +#define SYSTEM_COMB_PVT_ERR_NVT_SITE3_REG (DR_REG_SYSTEM_BASE + 0x94) +/** SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3 : RO; bitpos: [15:0]; default: 0; + * reg_comb_timing_err_cnt_nvt_site3 + */ +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3 0x0000FFFFU +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_M (SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_V << SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_S) +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_V 0x0000FFFFU +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_S 0 + +/** SYSTEM_COMB_PVT_ERR_HVT_SITE3_REG register + * mem pvt register + */ +#define SYSTEM_COMB_PVT_ERR_HVT_SITE3_REG (DR_REG_SYSTEM_BASE + 0x98) +/** SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3 : RO; bitpos: [15:0]; default: 0; + * reg_comb_timing_err_cnt_hvt_site3 + */ +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3 0x0000FFFFU +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_M (SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_V << SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_S) +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_V 0x0000FFFFU +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_S 0 + +/** SYSTEM_REG_DATE_REG register + * Version register + */ +#define SYSTEM_REG_DATE_REG (DR_REG_SYSTEM_BASE + 0xffc) +/** SYSTEM_SYSTEM_REG_DATE : R/W; bitpos: [27:0]; default: 34636176; + * reg_system_reg_date + */ +#define SYSTEM_SYSTEM_REG_DATE 0x0FFFFFFFU +#define SYSTEM_SYSTEM_REG_DATE_M (SYSTEM_SYSTEM_REG_DATE_V << SYSTEM_SYSTEM_REG_DATE_S) +#define SYSTEM_SYSTEM_REG_DATE_V 0x0FFFFFFFU +#define SYSTEM_SYSTEM_REG_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/src/target/esp32c2/ld/esp32c2.rom.api.ld b/src/target/esp32c2/ld/esp32c2.rom.api.ld index 6f9dbf4..594c89e 100644 --- a/src/target/esp32c2/ld/esp32c2.rom.api.ld +++ b/src/target/esp32c2/ld/esp32c2.rom.api.ld @@ -27,11 +27,13 @@ PROVIDE ( esp_rom_uart_putc = ets_write_char_uart ); PROVIDE ( esp_rom_uart_attach = uartAttach ); PROVIDE ( esp_rom_uart_init = Uart_Init ); PROVIDE ( esp_rom_uart_div_modify = uart_div_modify ); + PROVIDE ( esp_rom_uart_rx_intr_handler = uart_rx_intr_handler ); -PROVIDE ( esp_rom_get_apb_freq = ets_get_apb_freq ); -PROVIDE ( esp_rom_get_xtal_freq = ets_get_xtal_freq ); -PROVIDE ( esp_rom_update_cpu_frequency = ets_update_cpu_frequency); -PROVIDE ( esp_rom_get_uart_device = GetUartDevice ); +PROVIDE ( esp_rom_get_xtal_freq = ets_get_xtal_freq ); +PROVIDE ( esp_rom_set_cpu_ticks_per_us = ets_update_cpu_frequency); +PROVIDE ( esp_rom_get_uart_device = GetUartDevice ); +PROVIDE ( esp_rom_get_cpu_ticks_per_us = ets_get_cpu_frequency ); +PROVIDE ( esp_rom_get_apb_freq = ets_get_apb_freq ); PROVIDE ( esp_rom_output_flush_tx = uart_tx_flush ); PROVIDE ( esp_rom_output_tx_one_char = uart_tx_one_char ); diff --git a/src/target/esp32c2/src/clock.c b/src/target/esp32c2/src/clock.c new file mode 100644 index 0000000..5c9f7da --- /dev/null +++ b/src/target/esp32c2/src/clock.c @@ -0,0 +1,59 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 OR MIT + */ + +#include +#include +#include +#include +#include +#include +#include + +#define MHZ 1000000 + +extern uint32_t esp_rom_get_xtal_freq(void); +extern void esp_rom_set_cpu_ticks_per_us(uint32_t ticks_per_us); +extern uint32_t esp_rom_get_cpu_ticks_per_us(void); +extern uint32_t esp_rom_get_apb_freq(void); + +static uint32_t s_cpu_freq = 0; +static uint32_t s_crystal_freq = 0; + +void stub_target_clock_init(void) +{ + // This enables PLL which multiplies the crystal frequency by 12/6 = 2x. + REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL, 1); + REG_SET_FIELD(SYSTEM_CPU_PER_CONF_REG, SYSTEM_PLL_FREQ_SEL, 0); + + /* + ESP32-C2 does not have ROM code to detect the crystal frequency, + so we use the previously auto-synced 115200 baud rate which + is set by previous init code to estimate the crystal frequency. + TODO: Improve this to not depend on the previous init code. + TODO: Increase CPU frequency to at least 80 MHz for 26 MHz crystal. + */ + uint32_t uart_div_int = REG_GET_FIELD(UART_CLKDIV_REG(0), UART_CLKDIV); + uint32_t uart_div_frag = REG_GET_FIELD(UART_CLKDIV_REG(0), UART_CLKDIV_FRAG); + uint32_t uart_div = (uart_div_int << 4) + uart_div_frag; + uint32_t approx_crystal_freq = (uart_div * 115200) >> 4; + + s_crystal_freq = (approx_crystal_freq > (33 * MHZ)) ? (40 * MHZ) : (26 * MHZ); + s_cpu_freq = s_crystal_freq * 2; + esp_rom_set_cpu_ticks_per_us(s_cpu_freq / MHZ); +} + +uint32_t stub_target_get_cpu_freq(void) +{ + if (s_cpu_freq == 0) { + return esp_rom_get_cpu_ticks_per_us() * MHZ; + } + return s_cpu_freq; +} + +uint32_t stub_target_get_apb_freq(void) +{ + return s_crystal_freq; +} diff --git a/src/target/esp32c2/src/uart.c b/src/target/esp32c2/src/uart.c index 2d2f7d0..4664618 100644 --- a/src/target/esp32c2/src/uart.c +++ b/src/target/esp32c2/src/uart.c @@ -8,22 +8,20 @@ #include #include #include +#include +#include #include #include // These functions are defined in the ROM extern void esp_rom_uart_attach(void *rxBuffer); extern void esp_rom_uart_init(uint8_t uart_no, uint32_t clock); -extern uint32_t esp_rom_get_apb_freq(void); -extern void esp_rom_update_cpu_frequency(uint32_t ticks_per_us); extern void esp_rom_uart_set_as_console(uint8_t uart_no); extern uint32_t esp_rom_get_xtal_freq(void); extern void esp_rom_uart_div_modify(uint8_t uart_no, uint32_t divisor); extern void esp_rom_isr_attach(int int_num, void *handler, void *arg); extern void esp_rom_isr_unmask(int int_num); -#define UART_CLK_FREQ_ROM (40 * 1000000) - void stub_target_rom_uart_attach(void *rxBuffer) { esp_rom_uart_attach(rxBuffer); @@ -39,16 +37,19 @@ void stub_target_uart_init(uint8_t uart_num) // Bug for some esp32c2 revisions, does not work with rev v1.0. extern bool g_uart_print; stub_target_rom_uart_attach(NULL); - esp_rom_update_cpu_frequency(esp_rom_get_apb_freq() / 1000000); - stub_target_rom_uart_init(uart_num, UART_CLK_FREQ_ROM); + uint32_t clock = stub_target_get_apb_freq(); + stub_target_rom_uart_init(uart_num, clock); esp_rom_uart_set_as_console(uart_num); g_uart_print = true; } void stub_target_uart_rominit_set_baudrate(uint8_t uart_num, uint32_t baudrate) { - uint32_t clock = esp_rom_get_xtal_freq() << 4; - uint32_t divisor = clock / baudrate; - esp_rom_uart_div_modify(uart_num, divisor); - // TODO: Consider decimal part + stub_lib_delay_us(5 * 1000); + + uint32_t clk_div = (stub_target_get_apb_freq() << 4) / baudrate; + stub_target_uart_wait_idle(uart_num); + esp_rom_uart_div_modify(uart_num, clk_div); + + stub_lib_delay_us(5 * 1000); } diff --git a/src/target/esp32c3/CMakeLists.txt b/src/target/esp32c3/CMakeLists.txt index dbbb4e5..de025ea 100644 --- a/src/target/esp32c3/CMakeLists.txt +++ b/src/target/esp32c3/CMakeLists.txt @@ -1,6 +1,8 @@ set(srcs src/uart.c src/usb_serial_jtag.c + src/security.c + src/clock.c ) add_library(${ESP_TARGET_LIB} STATIC ${srcs}) diff --git a/src/target/esp32c3/include/soc/rtc_cntl_reg.h b/src/target/esp32c3/include/soc/rtc_cntl_reg.h new file mode 100644 index 0000000..361efaf --- /dev/null +++ b/src/target/esp32c3/include/soc/rtc_cntl_reg.h @@ -0,0 +1,2619 @@ +/* + * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 OR MIT + */ +#ifndef _SOC_RTC_CNTL_REG_H_ +#define _SOC_RTC_CNTL_REG_H_ + +#ifdef __cplusplus +extern "C" { +#endif +#include "soc/soc.h" +#define RTC_CNTL_TIME0_REG RTC_CNTL_TIME_LOW0_REG +#define RTC_CNTL_TIME1_REG RTC_CNTL_TIME_HIGH0_REG + +#define RTC_CNTL_OPTIONS0_REG (DR_REG_RTCCNTL_BASE + 0x0000) +/* RTC_CNTL_SW_SYS_RST : WO ;bitpos:[31] ;default: 1'd0 ; */ +/*description: SW system reset*/ +#define RTC_CNTL_SW_SYS_RST (BIT(31)) +#define RTC_CNTL_SW_SYS_RST_M (BIT(31)) +#define RTC_CNTL_SW_SYS_RST_V 0x1 +#define RTC_CNTL_SW_SYS_RST_S 31 +/* RTC_CNTL_DG_WRAP_FORCE_NORST : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: digital core force no reset in deep sleep*/ +#define RTC_CNTL_DG_WRAP_FORCE_NORST (BIT(30)) +#define RTC_CNTL_DG_WRAP_FORCE_NORST_M (BIT(30)) +#define RTC_CNTL_DG_WRAP_FORCE_NORST_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_NORST_S 30 +/* RTC_CNTL_DG_WRAP_FORCE_RST : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: digital wrap force reset in deep sleep*/ +#define RTC_CNTL_DG_WRAP_FORCE_RST (BIT(29)) +#define RTC_CNTL_DG_WRAP_FORCE_RST_M (BIT(29)) +#define RTC_CNTL_DG_WRAP_FORCE_RST_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_RST_S 29 +/* RTC_CNTL_ANALOG_FORCE_NOISO : R/W ;bitpos:[28] ;default: 1'd1 ; */ +/*description: */ +#define RTC_CNTL_ANALOG_FORCE_NOISO (BIT(28)) +#define RTC_CNTL_ANALOG_FORCE_NOISO_M (BIT(28)) +#define RTC_CNTL_ANALOG_FORCE_NOISO_V 0x1 +#define RTC_CNTL_ANALOG_FORCE_NOISO_S 28 +/* RTC_CNTL_PLL_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */ +/*description: */ +#define RTC_CNTL_PLL_FORCE_NOISO (BIT(27)) +#define RTC_CNTL_PLL_FORCE_NOISO_M (BIT(27)) +#define RTC_CNTL_PLL_FORCE_NOISO_V 0x1 +#define RTC_CNTL_PLL_FORCE_NOISO_S 27 +/* RTC_CNTL_XTL_FORCE_NOISO : R/W ;bitpos:[26] ;default: 1'd1 ; */ +/*description: */ +#define RTC_CNTL_XTL_FORCE_NOISO (BIT(26)) +#define RTC_CNTL_XTL_FORCE_NOISO_M (BIT(26)) +#define RTC_CNTL_XTL_FORCE_NOISO_V 0x1 +#define RTC_CNTL_XTL_FORCE_NOISO_S 26 +/* RTC_CNTL_ANALOG_FORCE_ISO : R/W ;bitpos:[25] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_ANALOG_FORCE_ISO (BIT(25)) +#define RTC_CNTL_ANALOG_FORCE_ISO_M (BIT(25)) +#define RTC_CNTL_ANALOG_FORCE_ISO_V 0x1 +#define RTC_CNTL_ANALOG_FORCE_ISO_S 25 +/* RTC_CNTL_PLL_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_PLL_FORCE_ISO (BIT(24)) +#define RTC_CNTL_PLL_FORCE_ISO_M (BIT(24)) +#define RTC_CNTL_PLL_FORCE_ISO_V 0x1 +#define RTC_CNTL_PLL_FORCE_ISO_S 24 +/* RTC_CNTL_XTL_FORCE_ISO : R/W ;bitpos:[23] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_XTL_FORCE_ISO (BIT(23)) +#define RTC_CNTL_XTL_FORCE_ISO_M (BIT(23)) +#define RTC_CNTL_XTL_FORCE_ISO_V 0x1 +#define RTC_CNTL_XTL_FORCE_ISO_S 23 +/* RTC_CNTL_XTL_EXT_CTR_SEL : R/W ;bitpos:[22:20] ;default: 3'd0 ; */ +/*description: */ +#define RTC_CNTL_XTL_EXT_CTR_SEL 0x00000007 +#define RTC_CNTL_XTL_EXT_CTR_SEL_M ((RTC_CNTL_XTL_EXT_CTR_SEL_V)<<(RTC_CNTL_XTL_EXT_CTR_SEL_S)) +#define RTC_CNTL_XTL_EXT_CTR_SEL_V 0x7 +#define RTC_CNTL_XTL_EXT_CTR_SEL_S 20 +/* RTC_CNTL_XTL_EN_WAIT : R/W ;bitpos:[17:14] ;default: 4'd2 ; */ +/*description: wait bias_sleep and current source wakeup*/ +#define RTC_CNTL_XTL_EN_WAIT 0x0000000F +#define RTC_CNTL_XTL_EN_WAIT_M ((RTC_CNTL_XTL_EN_WAIT_V)<<(RTC_CNTL_XTL_EN_WAIT_S)) +#define RTC_CNTL_XTL_EN_WAIT_V 0xF +#define RTC_CNTL_XTL_EN_WAIT_S 14 +/* RTC_CNTL_XTL_FORCE_PU : R/W ;bitpos:[13] ;default: 1'd1 ; */ +/*description: crystall force power up*/ +#define RTC_CNTL_XTL_FORCE_PU (BIT(13)) +#define RTC_CNTL_XTL_FORCE_PU_M (BIT(13)) +#define RTC_CNTL_XTL_FORCE_PU_V 0x1 +#define RTC_CNTL_XTL_FORCE_PU_S 13 +/* RTC_CNTL_XTL_FORCE_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: crystall force power down*/ +#define RTC_CNTL_XTL_FORCE_PD (BIT(12)) +#define RTC_CNTL_XTL_FORCE_PD_M (BIT(12)) +#define RTC_CNTL_XTL_FORCE_PD_V 0x1 +#define RTC_CNTL_XTL_FORCE_PD_S 12 +/* RTC_CNTL_BBPLL_FORCE_PU : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: BB_PLL force power up*/ +#define RTC_CNTL_BBPLL_FORCE_PU (BIT(11)) +#define RTC_CNTL_BBPLL_FORCE_PU_M (BIT(11)) +#define RTC_CNTL_BBPLL_FORCE_PU_V 0x1 +#define RTC_CNTL_BBPLL_FORCE_PU_S 11 +/* RTC_CNTL_BBPLL_FORCE_PD : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: BB_PLL force power down*/ +#define RTC_CNTL_BBPLL_FORCE_PD (BIT(10)) +#define RTC_CNTL_BBPLL_FORCE_PD_M (BIT(10)) +#define RTC_CNTL_BBPLL_FORCE_PD_V 0x1 +#define RTC_CNTL_BBPLL_FORCE_PD_S 10 +/* RTC_CNTL_BBPLL_I2C_FORCE_PU : R/W ;bitpos:[9] ;default: 1'd0 ; */ +/*description: BB_PLL_I2C force power up*/ +#define RTC_CNTL_BBPLL_I2C_FORCE_PU (BIT(9)) +#define RTC_CNTL_BBPLL_I2C_FORCE_PU_M (BIT(9)) +#define RTC_CNTL_BBPLL_I2C_FORCE_PU_V 0x1 +#define RTC_CNTL_BBPLL_I2C_FORCE_PU_S 9 +/* RTC_CNTL_BBPLL_I2C_FORCE_PD : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: BB_PLL _I2C force power down*/ +#define RTC_CNTL_BBPLL_I2C_FORCE_PD (BIT(8)) +#define RTC_CNTL_BBPLL_I2C_FORCE_PD_M (BIT(8)) +#define RTC_CNTL_BBPLL_I2C_FORCE_PD_V 0x1 +#define RTC_CNTL_BBPLL_I2C_FORCE_PD_S 8 +/* RTC_CNTL_BB_I2C_FORCE_PU : R/W ;bitpos:[7] ;default: 1'd0 ; */ +/*description: BB_I2C force power up*/ +#define RTC_CNTL_BB_I2C_FORCE_PU (BIT(7)) +#define RTC_CNTL_BB_I2C_FORCE_PU_M (BIT(7)) +#define RTC_CNTL_BB_I2C_FORCE_PU_V 0x1 +#define RTC_CNTL_BB_I2C_FORCE_PU_S 7 +/* RTC_CNTL_BB_I2C_FORCE_PD : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: BB_I2C force power down*/ +#define RTC_CNTL_BB_I2C_FORCE_PD (BIT(6)) +#define RTC_CNTL_BB_I2C_FORCE_PD_M (BIT(6)) +#define RTC_CNTL_BB_I2C_FORCE_PD_V 0x1 +#define RTC_CNTL_BB_I2C_FORCE_PD_S 6 +/* RTC_CNTL_SW_PROCPU_RST : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: PRO CPU SW reset*/ +#define RTC_CNTL_SW_PROCPU_RST (BIT(5)) +#define RTC_CNTL_SW_PROCPU_RST_M (BIT(5)) +#define RTC_CNTL_SW_PROCPU_RST_V 0x1 +#define RTC_CNTL_SW_PROCPU_RST_S 5 +/* RTC_CNTL_SW_APPCPU_RST : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: APP CPU SW reset*/ +#define RTC_CNTL_SW_APPCPU_RST (BIT(4)) +#define RTC_CNTL_SW_APPCPU_RST_M (BIT(4)) +#define RTC_CNTL_SW_APPCPU_RST_V 0x1 +#define RTC_CNTL_SW_APPCPU_RST_S 4 +/* RTC_CNTL_SW_STALL_PROCPU_C0 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */ +/*description: {reg_sw_stall_procpu_c1[5:0] reg_sw_stall_procpu_c0[1:0]} == + 0x86 will stall PRO CPU*/ +#define RTC_CNTL_SW_STALL_PROCPU_C0 0x00000003 +#define RTC_CNTL_SW_STALL_PROCPU_C0_M ((RTC_CNTL_SW_STALL_PROCPU_C0_V)<<(RTC_CNTL_SW_STALL_PROCPU_C0_S)) +#define RTC_CNTL_SW_STALL_PROCPU_C0_V 0x3 +#define RTC_CNTL_SW_STALL_PROCPU_C0_S 2 +/* RTC_CNTL_SW_STALL_APPCPU_C0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: {reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == + 0x86 will stall APP CPU*/ +#define RTC_CNTL_SW_STALL_APPCPU_C0 0x00000003 +#define RTC_CNTL_SW_STALL_APPCPU_C0_M ((RTC_CNTL_SW_STALL_APPCPU_C0_V)<<(RTC_CNTL_SW_STALL_APPCPU_C0_S)) +#define RTC_CNTL_SW_STALL_APPCPU_C0_V 0x3 +#define RTC_CNTL_SW_STALL_APPCPU_C0_S 0 + +#define RTC_CNTL_SLP_TIMER0_REG (DR_REG_RTCCNTL_BASE + 0x0004) +/* RTC_CNTL_SLP_VAL_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define RTC_CNTL_SLP_VAL_LO 0xFFFFFFFF +#define RTC_CNTL_SLP_VAL_LO_M ((RTC_CNTL_SLP_VAL_LO_V)<<(RTC_CNTL_SLP_VAL_LO_S)) +#define RTC_CNTL_SLP_VAL_LO_V 0xFFFFFFFF +#define RTC_CNTL_SLP_VAL_LO_S 0 + +#define RTC_CNTL_SLP_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x0008) +/* RTC_CNTL_MAIN_TIMER_ALARM_EN : WO ;bitpos:[16] ;default: 1'h0 ; */ +/*description: timer alarm enable bit*/ +#define RTC_CNTL_MAIN_TIMER_ALARM_EN (BIT(16)) +#define RTC_CNTL_MAIN_TIMER_ALARM_EN_M (BIT(16)) +#define RTC_CNTL_MAIN_TIMER_ALARM_EN_V 0x1 +#define RTC_CNTL_MAIN_TIMER_ALARM_EN_S 16 +/* RTC_CNTL_SLP_VAL_HI : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: RTC sleep timer high 16 bits*/ +#define RTC_CNTL_SLP_VAL_HI 0x0000FFFF +#define RTC_CNTL_SLP_VAL_HI_M ((RTC_CNTL_SLP_VAL_HI_V)<<(RTC_CNTL_SLP_VAL_HI_S)) +#define RTC_CNTL_SLP_VAL_HI_V 0xFFFF +#define RTC_CNTL_SLP_VAL_HI_S 0 + +#define RTC_CNTL_TIME_UPDATE_REG (DR_REG_RTCCNTL_BASE + 0x000C) +/* RTC_CNTL_TIME_UPDATE : WO ;bitpos:[31] ;default: 1'h0 ; */ +/*description: Set 1: to update register with RTC timer*/ +#define RTC_CNTL_TIME_UPDATE (BIT(31)) +#define RTC_CNTL_TIME_UPDATE_M (BIT(31)) +#define RTC_CNTL_TIME_UPDATE_V 0x1 +#define RTC_CNTL_TIME_UPDATE_S 31 +/* RTC_CNTL_TIMER_SYS_RST : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: enable to record system reset time*/ +#define RTC_CNTL_TIMER_SYS_RST (BIT(29)) +#define RTC_CNTL_TIMER_SYS_RST_M (BIT(29)) +#define RTC_CNTL_TIMER_SYS_RST_V 0x1 +#define RTC_CNTL_TIMER_SYS_RST_S 29 +/* RTC_CNTL_TIMER_XTL_OFF : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: Enable to record 40M XTAL OFF time*/ +#define RTC_CNTL_TIMER_XTL_OFF (BIT(28)) +#define RTC_CNTL_TIMER_XTL_OFF_M (BIT(28)) +#define RTC_CNTL_TIMER_XTL_OFF_V 0x1 +#define RTC_CNTL_TIMER_XTL_OFF_S 28 +/* RTC_CNTL_TIMER_SYS_STALL : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: Enable to record system stall time*/ +#define RTC_CNTL_TIMER_SYS_STALL (BIT(27)) +#define RTC_CNTL_TIMER_SYS_STALL_M (BIT(27)) +#define RTC_CNTL_TIMER_SYS_STALL_V 0x1 +#define RTC_CNTL_TIMER_SYS_STALL_S 27 + +#define RTC_CNTL_TIME_LOW0_REG (DR_REG_RTCCNTL_BASE + 0x0010) +/* RTC_CNTL_TIMER_VALUE0_LOW : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: RTC timer low 32 bits*/ +#define RTC_CNTL_TIMER_VALUE0_LOW 0xFFFFFFFF +#define RTC_CNTL_TIMER_VALUE0_LOW_M ((RTC_CNTL_TIMER_VALUE0_LOW_V)<<(RTC_CNTL_TIMER_VALUE0_LOW_S)) +#define RTC_CNTL_TIMER_VALUE0_LOW_V 0xFFFFFFFF +#define RTC_CNTL_TIMER_VALUE0_LOW_S 0 + +#define RTC_CNTL_TIME_HIGH0_REG (DR_REG_RTCCNTL_BASE + 0x0014) +/* RTC_CNTL_TIMER_VALUE0_HIGH : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: RTC timer high 16 bits*/ +#define RTC_CNTL_TIMER_VALUE0_HIGH 0x0000FFFF +#define RTC_CNTL_TIMER_VALUE0_HIGH_M ((RTC_CNTL_TIMER_VALUE0_HIGH_V)<<(RTC_CNTL_TIMER_VALUE0_HIGH_S)) +#define RTC_CNTL_TIMER_VALUE0_HIGH_V 0xFFFF +#define RTC_CNTL_TIMER_VALUE0_HIGH_S 0 + +#define RTC_CNTL_STATE0_REG (DR_REG_RTCCNTL_BASE + 0x0018) +/* RTC_CNTL_SLEEP_EN : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: sleep enable bit*/ +#define RTC_CNTL_SLEEP_EN (BIT(31)) +#define RTC_CNTL_SLEEP_EN_M (BIT(31)) +#define RTC_CNTL_SLEEP_EN_V 0x1 +#define RTC_CNTL_SLEEP_EN_S 31 +/* RTC_CNTL_SLP_REJECT : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: leep reject bit*/ +#define RTC_CNTL_SLP_REJECT (BIT(30)) +#define RTC_CNTL_SLP_REJECT_M (BIT(30)) +#define RTC_CNTL_SLP_REJECT_V 0x1 +#define RTC_CNTL_SLP_REJECT_S 30 +/* RTC_CNTL_SLP_WAKEUP : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: leep wakeup bit*/ +#define RTC_CNTL_SLP_WAKEUP (BIT(29)) +#define RTC_CNTL_SLP_WAKEUP_M (BIT(29)) +#define RTC_CNTL_SLP_WAKEUP_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_S 29 +/* RTC_CNTL_SDIO_ACTIVE_IND : RO ;bitpos:[28] ;default: 1'd0 ; */ +/*description: SDIO active indication*/ +#define RTC_CNTL_SDIO_ACTIVE_IND (BIT(28)) +#define RTC_CNTL_SDIO_ACTIVE_IND_M (BIT(28)) +#define RTC_CNTL_SDIO_ACTIVE_IND_V 0x1 +#define RTC_CNTL_SDIO_ACTIVE_IND_S 28 +/* RTC_CNTL_APB2RTC_BRIDGE_SEL : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: 1: APB to RTC using bridge*/ +#define RTC_CNTL_APB2RTC_BRIDGE_SEL (BIT(22)) +#define RTC_CNTL_APB2RTC_BRIDGE_SEL_M (BIT(22)) +#define RTC_CNTL_APB2RTC_BRIDGE_SEL_V 0x1 +#define RTC_CNTL_APB2RTC_BRIDGE_SEL_S 22 +/* RTC_CNTL_SLP_REJECT_CAUSE_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: clear rtc sleep reject cause*/ +#define RTC_CNTL_SLP_REJECT_CAUSE_CLR (BIT(1)) +#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_V 0x1 +#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_S 1 +/* RTC_CNTL_SW_CPU_INT : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: rtc software interrupt to main cpu*/ +#define RTC_CNTL_SW_CPU_INT (BIT(0)) +#define RTC_CNTL_SW_CPU_INT_M (BIT(0)) +#define RTC_CNTL_SW_CPU_INT_V 0x1 +#define RTC_CNTL_SW_CPU_INT_S 0 + +#define RTC_CNTL_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x001C) +/* RTC_CNTL_PLL_BUF_WAIT : R/W ;bitpos:[31:24] ;default: 8'd40 ; */ +/*description: PLL wait cycles in slow_clk_rtc*/ +#define RTC_CNTL_PLL_BUF_WAIT 0x000000FF +#define RTC_CNTL_PLL_BUF_WAIT_M ((RTC_CNTL_PLL_BUF_WAIT_V)<<(RTC_CNTL_PLL_BUF_WAIT_S)) +#define RTC_CNTL_PLL_BUF_WAIT_V 0xFF +#define RTC_CNTL_PLL_BUF_WAIT_S 24 +#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 20 +/* RTC_CNTL_XTL_BUF_WAIT : R/W ;bitpos:[23:14] ;default: 10'd80 ; */ +/*description: XTAL wait cycles in slow_clk_rtc*/ +#define RTC_CNTL_XTL_BUF_WAIT 0x000003FF +#define RTC_CNTL_XTL_BUF_WAIT_M ((RTC_CNTL_XTL_BUF_WAIT_V)<<(RTC_CNTL_XTL_BUF_WAIT_S)) +#define RTC_CNTL_XTL_BUF_WAIT_V 0x3FF +#define RTC_CNTL_XTL_BUF_WAIT_S 14 +#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 100 +/* RTC_CNTL_CK8M_WAIT : R/W ;bitpos:[13:6] ;default: 8'h10 ; */ +/*description: CK8M wait cycles in slow_clk_rtc*/ +#define RTC_CNTL_CK8M_WAIT 0x000000FF +#define RTC_CNTL_CK8M_WAIT_M ((RTC_CNTL_CK8M_WAIT_V)<<(RTC_CNTL_CK8M_WAIT_S)) +#define RTC_CNTL_CK8M_WAIT_V 0xFF +#define RTC_CNTL_CK8M_WAIT_S 6 +/* RTC_CNTL_CPU_STALL_WAIT : R/W ;bitpos:[5:1] ;default: 5'd1 ; */ +/*description: CPU stall wait cycles in fast_clk_rtc*/ +#define RTC_CNTL_CPU_STALL_WAIT 0x0000001F +#define RTC_CNTL_CPU_STALL_WAIT_M ((RTC_CNTL_CPU_STALL_WAIT_V)<<(RTC_CNTL_CPU_STALL_WAIT_S)) +#define RTC_CNTL_CPU_STALL_WAIT_V 0x1F +#define RTC_CNTL_CPU_STALL_WAIT_S 1 +/* RTC_CNTL_CPU_STALL_EN : R/W ;bitpos:[0] ;default: 1'd1 ; */ +/*description: CPU stall enable bit*/ +#define RTC_CNTL_CPU_STALL_EN (BIT(0)) +#define RTC_CNTL_CPU_STALL_EN_M (BIT(0)) +#define RTC_CNTL_CPU_STALL_EN_V 0x1 +#define RTC_CNTL_CPU_STALL_EN_S 0 + +#define RTC_CNTL_TIMER2_REG (DR_REG_RTCCNTL_BASE + 0x0020) +/* RTC_CNTL_MIN_TIME_CK8M_OFF : R/W ;bitpos:[31:24] ;default: 8'h1 ; */ +/*description: minimal cycles in slow_clk_rtc for CK8M in power down state*/ +#define RTC_CNTL_MIN_TIME_CK8M_OFF 0x000000FF +#define RTC_CNTL_MIN_TIME_CK8M_OFF_M ((RTC_CNTL_MIN_TIME_CK8M_OFF_V)<<(RTC_CNTL_MIN_TIME_CK8M_OFF_S)) +#define RTC_CNTL_MIN_TIME_CK8M_OFF_V 0xFF +#define RTC_CNTL_MIN_TIME_CK8M_OFF_S 24 + +#define RTC_CNTL_TIMER3_REG (DR_REG_RTCCNTL_BASE + 0x0024) +/* RTC_CNTL_BT_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h5 ; */ +/*description: */ +#define RTC_CNTL_BT_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_BT_POWERUP_TIMER_M ((RTC_CNTL_BT_POWERUP_TIMER_V)<<(RTC_CNTL_BT_POWERUP_TIMER_S)) +#define RTC_CNTL_BT_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_BT_POWERUP_TIMER_S 25 +/* RTC_CNTL_BT_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h8 ; */ +/*description: */ +#define RTC_CNTL_BT_WAIT_TIMER 0x000001FF +#define RTC_CNTL_BT_WAIT_TIMER_M ((RTC_CNTL_BT_WAIT_TIMER_V)<<(RTC_CNTL_BT_WAIT_TIMER_S)) +#define RTC_CNTL_BT_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_BT_WAIT_TIMER_S 16 +/* RTC_CNTL_WIFI_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */ +/*description: */ +#define RTC_CNTL_WIFI_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_WIFI_POWERUP_TIMER_M ((RTC_CNTL_WIFI_POWERUP_TIMER_V)<<(RTC_CNTL_WIFI_POWERUP_TIMER_S)) +#define RTC_CNTL_WIFI_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_WIFI_POWERUP_TIMER_S 9 +/* RTC_CNTL_WIFI_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */ +/*description: */ +#define RTC_CNTL_WIFI_WAIT_TIMER 0x000001FF +#define RTC_CNTL_WIFI_WAIT_TIMER_M ((RTC_CNTL_WIFI_WAIT_TIMER_V)<<(RTC_CNTL_WIFI_WAIT_TIMER_S)) +#define RTC_CNTL_WIFI_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_WIFI_WAIT_TIMER_S 0 + +#define RTC_CNTL_TIMER4_REG (DR_REG_RTCCNTL_BASE + 0x0028) +/* RTC_CNTL_DG_WRAP_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h8 ; */ +/*description: */ +#define RTC_CNTL_DG_WRAP_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_M ((RTC_CNTL_DG_WRAP_POWERUP_TIMER_V)<<(RTC_CNTL_DG_WRAP_POWERUP_TIMER_S)) +#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_S 25 +/* RTC_CNTL_DG_WRAP_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h20 ; */ +/*description: */ +#define RTC_CNTL_DG_WRAP_WAIT_TIMER 0x000001FF +#define RTC_CNTL_DG_WRAP_WAIT_TIMER_M ((RTC_CNTL_DG_WRAP_WAIT_TIMER_V)<<(RTC_CNTL_DG_WRAP_WAIT_TIMER_S)) +#define RTC_CNTL_DG_WRAP_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_DG_WRAP_WAIT_TIMER_S 16 +/* RTC_CNTL_CPU_TOP_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */ +/*description: */ +#define RTC_CNTL_CPU_TOP_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_CPU_TOP_POWERUP_TIMER_M ((RTC_CNTL_CPU_TOP_POWERUP_TIMER_V)<<(RTC_CNTL_CPU_TOP_POWERUP_TIMER_S)) +#define RTC_CNTL_CPU_TOP_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_CPU_TOP_POWERUP_TIMER_S 9 +/* RTC_CNTL_CPU_TOP_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */ +/*description: */ +#define RTC_CNTL_CPU_TOP_WAIT_TIMER 0x000001FF +#define RTC_CNTL_CPU_TOP_WAIT_TIMER_M ((RTC_CNTL_CPU_TOP_WAIT_TIMER_V)<<(RTC_CNTL_CPU_TOP_WAIT_TIMER_S)) +#define RTC_CNTL_CPU_TOP_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_CPU_TOP_WAIT_TIMER_S 0 + +#define RTC_CNTL_TIMER5_REG (DR_REG_RTCCNTL_BASE + 0x002C) +/* RTC_CNTL_MIN_SLP_VAL : R/W ;bitpos:[15:8] ;default: 8'h80 ; */ +/*description: minimal sleep cycles in slow_clk_rtc*/ +#define RTC_CNTL_MIN_SLP_VAL 0x000000FF +#define RTC_CNTL_MIN_SLP_VAL_M ((RTC_CNTL_MIN_SLP_VAL_V)<<(RTC_CNTL_MIN_SLP_VAL_S)) +#define RTC_CNTL_MIN_SLP_VAL_V 0xFF +#define RTC_CNTL_MIN_SLP_VAL_S 8 + +#define RTC_CNTL_TIMER6_REG (DR_REG_RTCCNTL_BASE + 0x0030) +/* RTC_CNTL_DG_PERI_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h5 ; */ +/*description: */ +#define RTC_CNTL_DG_PERI_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_DG_PERI_POWERUP_TIMER_M ((RTC_CNTL_DG_PERI_POWERUP_TIMER_V)<<(RTC_CNTL_DG_PERI_POWERUP_TIMER_S)) +#define RTC_CNTL_DG_PERI_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_DG_PERI_POWERUP_TIMER_S 25 +/* RTC_CNTL_DG_PERI_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h8 ; */ +/*description: */ +#define RTC_CNTL_DG_PERI_WAIT_TIMER 0x000001FF +#define RTC_CNTL_DG_PERI_WAIT_TIMER_M ((RTC_CNTL_DG_PERI_WAIT_TIMER_V)<<(RTC_CNTL_DG_PERI_WAIT_TIMER_S)) +#define RTC_CNTL_DG_PERI_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_DG_PERI_WAIT_TIMER_S 16 + +#define RTC_CNTL_ANA_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0034) +/* RTC_CNTL_PLL_I2C_PU : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_PLL_I2C_PU (BIT(31)) +#define RTC_CNTL_PLL_I2C_PU_M (BIT(31)) +#define RTC_CNTL_PLL_I2C_PU_V 0x1 +#define RTC_CNTL_PLL_I2C_PU_S 31 +/* RTC_CNTL_CKGEN_I2C_PU : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: 1: CKGEN_I2C power up*/ +#define RTC_CNTL_CKGEN_I2C_PU (BIT(30)) +#define RTC_CNTL_CKGEN_I2C_PU_M (BIT(30)) +#define RTC_CNTL_CKGEN_I2C_PU_V 0x1 +#define RTC_CNTL_CKGEN_I2C_PU_S 30 +/* RTC_CNTL_RFRX_PBUS_PU : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: 1: RFRX_PBUS power up*/ +#define RTC_CNTL_RFRX_PBUS_PU (BIT(28)) +#define RTC_CNTL_RFRX_PBUS_PU_M (BIT(28)) +#define RTC_CNTL_RFRX_PBUS_PU_V 0x1 +#define RTC_CNTL_RFRX_PBUS_PU_S 28 +/* RTC_CNTL_TXRF_I2C_PU : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: 1: TXRF_I2C power up*/ +#define RTC_CNTL_TXRF_I2C_PU (BIT(27)) +#define RTC_CNTL_TXRF_I2C_PU_M (BIT(27)) +#define RTC_CNTL_TXRF_I2C_PU_V 0x1 +#define RTC_CNTL_TXRF_I2C_PU_S 27 +/* RTC_CNTL_PVTMON_PU : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: 1: PVTMON power up*/ +#define RTC_CNTL_PVTMON_PU (BIT(26)) +#define RTC_CNTL_PVTMON_PU_M (BIT(26)) +#define RTC_CNTL_PVTMON_PU_V 0x1 +#define RTC_CNTL_PVTMON_PU_S 26 +/* RTC_CNTL_BBPLL_CAL_SLP_START : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: start BBPLL calibration during sleep*/ +#define RTC_CNTL_BBPLL_CAL_SLP_START (BIT(25)) +#define RTC_CNTL_BBPLL_CAL_SLP_START_M (BIT(25)) +#define RTC_CNTL_BBPLL_CAL_SLP_START_V 0x1 +#define RTC_CNTL_BBPLL_CAL_SLP_START_S 25 +/* RTC_CNTL_PLLA_FORCE_PU : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: PLLA force power up*/ +#define RTC_CNTL_PLLA_FORCE_PU (BIT(24)) +#define RTC_CNTL_PLLA_FORCE_PU_M (BIT(24)) +#define RTC_CNTL_PLLA_FORCE_PU_V 0x1 +#define RTC_CNTL_PLLA_FORCE_PU_S 24 +/* RTC_CNTL_PLLA_FORCE_PD : R/W ;bitpos:[23] ;default: 1'b1 ; */ +/*description: PLLA force power down*/ +#define RTC_CNTL_PLLA_FORCE_PD (BIT(23)) +#define RTC_CNTL_PLLA_FORCE_PD_M (BIT(23)) +#define RTC_CNTL_PLLA_FORCE_PD_V 0x1 +#define RTC_CNTL_PLLA_FORCE_PD_S 23 +/* RTC_CNTL_SAR_I2C_PU : R/W ;bitpos:[22] ;default: 1'b1 ; */ +/*description: PLLA force power up*/ +#define RTC_CNTL_SAR_I2C_PU (BIT(22)) +#define RTC_CNTL_SAR_I2C_PU_M (BIT(22)) +#define RTC_CNTL_SAR_I2C_PU_V 0x1 +#define RTC_CNTL_SAR_I2C_PU_S 22 +/* RTC_CNTL_GLITCH_RST_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_GLITCH_RST_EN (BIT(20)) +#define RTC_CNTL_GLITCH_RST_EN_M (BIT(20)) +#define RTC_CNTL_GLITCH_RST_EN_V 0x1 +#define RTC_CNTL_GLITCH_RST_EN_S 20 +/* RTC_CNTL_I2C_RESET_POR_FORCE_PU : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_I2C_RESET_POR_FORCE_PU (BIT(19)) +#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_M (BIT(19)) +#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_V 0x1 +#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_S 19 +/* RTC_CNTL_I2C_RESET_POR_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b1 ; */ +/*description: */ +#define RTC_CNTL_I2C_RESET_POR_FORCE_PD (BIT(18)) +#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_M (BIT(18)) +#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_V 0x1 +#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_S 18 + +#define RTC_CNTL_RESET_STATE_REG (DR_REG_RTCCNTL_BASE + 0x0038) +/* RTC_CNTL_DRESET_MASK_PROCPU : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_DRESET_MASK_PROCPU (BIT(25)) +#define RTC_CNTL_DRESET_MASK_PROCPU_M (BIT(25)) +#define RTC_CNTL_DRESET_MASK_PROCPU_V 0x1 +#define RTC_CNTL_DRESET_MASK_PROCPU_S 25 +/* RTC_CNTL_DRESET_MASK_APPCPU : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_DRESET_MASK_APPCPU (BIT(24)) +#define RTC_CNTL_DRESET_MASK_APPCPU_M (BIT(24)) +#define RTC_CNTL_DRESET_MASK_APPCPU_V 0x1 +#define RTC_CNTL_DRESET_MASK_APPCPU_S 24 +/* RTC_CNTL_JTAG_RESET_FLAG_CLR_APPCPU : WO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_JTAG_RESET_FLAG_CLR_APPCPU (BIT(23)) +#define RTC_CNTL_JTAG_RESET_FLAG_CLR_APPCPU_M (BIT(23)) +#define RTC_CNTL_JTAG_RESET_FLAG_CLR_APPCPU_V 0x1 +#define RTC_CNTL_JTAG_RESET_FLAG_CLR_APPCPU_S 23 +/* RTC_CNTL_JTAG_RESET_FLAG_CLR_PROCPU : WO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_JTAG_RESET_FLAG_CLR_PROCPU (BIT(22)) +#define RTC_CNTL_JTAG_RESET_FLAG_CLR_PROCPU_M (BIT(22)) +#define RTC_CNTL_JTAG_RESET_FLAG_CLR_PROCPU_V 0x1 +#define RTC_CNTL_JTAG_RESET_FLAG_CLR_PROCPU_S 22 +/* RTC_CNTL_JTAG_RESET_FLAG_APPCPU : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_JTAG_RESET_FLAG_APPCPU (BIT(21)) +#define RTC_CNTL_JTAG_RESET_FLAG_APPCPU_M (BIT(21)) +#define RTC_CNTL_JTAG_RESET_FLAG_APPCPU_V 0x1 +#define RTC_CNTL_JTAG_RESET_FLAG_APPCPU_S 21 +/* RTC_CNTL_JTAG_RESET_FLAG_PROCPU : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_JTAG_RESET_FLAG_PROCPU (BIT(20)) +#define RTC_CNTL_JTAG_RESET_FLAG_PROCPU_M (BIT(20)) +#define RTC_CNTL_JTAG_RESET_FLAG_PROCPU_V 0x1 +#define RTC_CNTL_JTAG_RESET_FLAG_PROCPU_S 20 +/* RTC_CNTL_OCD_HALT_ON_RESET_PROCPU : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: PROCPU OcdHaltOnReset*/ +#define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU (BIT(19)) +#define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU_M (BIT(19)) +#define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU_V 0x1 +#define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU_S 19 +/* RTC_CNTL_OCD_HALT_ON_RESET_APPCPU : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: APPCPU OcdHaltOnReset*/ +#define RTC_CNTL_OCD_HALT_ON_RESET_APPCPU (BIT(18)) +#define RTC_CNTL_OCD_HALT_ON_RESET_APPCPU_M (BIT(18)) +#define RTC_CNTL_OCD_HALT_ON_RESET_APPCPU_V 0x1 +#define RTC_CNTL_OCD_HALT_ON_RESET_APPCPU_S 18 +/* RTC_CNTL_ALL_RESET_FLAG_CLR_APPCPU : WO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: clear APP CPU reset flag*/ +#define RTC_CNTL_ALL_RESET_FLAG_CLR_APPCPU (BIT(17)) +#define RTC_CNTL_ALL_RESET_FLAG_CLR_APPCPU_M (BIT(17)) +#define RTC_CNTL_ALL_RESET_FLAG_CLR_APPCPU_V 0x1 +#define RTC_CNTL_ALL_RESET_FLAG_CLR_APPCPU_S 17 +/* RTC_CNTL_ALL_RESET_FLAG_CLR_PROCPU : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: clear PRO CPU reset_flag*/ +#define RTC_CNTL_ALL_RESET_FLAG_CLR_PROCPU (BIT(16)) +#define RTC_CNTL_ALL_RESET_FLAG_CLR_PROCPU_M (BIT(16)) +#define RTC_CNTL_ALL_RESET_FLAG_CLR_PROCPU_V 0x1 +#define RTC_CNTL_ALL_RESET_FLAG_CLR_PROCPU_S 16 +/* RTC_CNTL_ALL_RESET_FLAG_APPCPU : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: APP CPU reset flag*/ +#define RTC_CNTL_ALL_RESET_FLAG_APPCPU (BIT(15)) +#define RTC_CNTL_ALL_RESET_FLAG_APPCPU_M (BIT(15)) +#define RTC_CNTL_ALL_RESET_FLAG_APPCPU_V 0x1 +#define RTC_CNTL_ALL_RESET_FLAG_APPCPU_S 15 +/* RTC_CNTL_ALL_RESET_FLAG_PROCPU : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: PRO CPU reset_flag*/ +#define RTC_CNTL_ALL_RESET_FLAG_PROCPU (BIT(14)) +#define RTC_CNTL_ALL_RESET_FLAG_PROCPU_M (BIT(14)) +#define RTC_CNTL_ALL_RESET_FLAG_PROCPU_V 0x1 +#define RTC_CNTL_ALL_RESET_FLAG_PROCPU_S 14 +/* RTC_CNTL_STAT_VECTOR_SEL_PROCPU : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: PRO CPU state vector sel*/ +#define RTC_CNTL_STAT_VECTOR_SEL_PROCPU (BIT(13)) +#define RTC_CNTL_STAT_VECTOR_SEL_PROCPU_M (BIT(13)) +#define RTC_CNTL_STAT_VECTOR_SEL_PROCPU_V 0x1 +#define RTC_CNTL_STAT_VECTOR_SEL_PROCPU_S 13 +/* RTC_CNTL_STAT_VECTOR_SEL_APPCPU : R/W ;bitpos:[12] ;default: 1'b1 ; */ +/*description: APP CPU state vector sel*/ +#define RTC_CNTL_STAT_VECTOR_SEL_APPCPU (BIT(12)) +#define RTC_CNTL_STAT_VECTOR_SEL_APPCPU_M (BIT(12)) +#define RTC_CNTL_STAT_VECTOR_SEL_APPCPU_V 0x1 +#define RTC_CNTL_STAT_VECTOR_SEL_APPCPU_S 12 +/* RTC_CNTL_RESET_CAUSE_APPCPU : RO ;bitpos:[11:6] ;default: 0 ; */ +/*description: reset cause of APP CPU*/ +#define RTC_CNTL_RESET_CAUSE_APPCPU 0x0000003F +#define RTC_CNTL_RESET_CAUSE_APPCPU_M ((RTC_CNTL_RESET_CAUSE_APPCPU_V)<<(RTC_CNTL_RESET_CAUSE_APPCPU_S)) +#define RTC_CNTL_RESET_CAUSE_APPCPU_V 0x3F +#define RTC_CNTL_RESET_CAUSE_APPCPU_S 6 +/* RTC_CNTL_RESET_CAUSE_PROCPU : RO ;bitpos:[5:0] ;default: 0 ; */ +/*description: reset cause of PRO CPU*/ +#define RTC_CNTL_RESET_CAUSE_PROCPU 0x0000003F +#define RTC_CNTL_RESET_CAUSE_PROCPU_M ((RTC_CNTL_RESET_CAUSE_PROCPU_V)<<(RTC_CNTL_RESET_CAUSE_PROCPU_S)) +#define RTC_CNTL_RESET_CAUSE_PROCPU_V 0x3F +#define RTC_CNTL_RESET_CAUSE_PROCPU_S 0 + +#define RTC_CNTL_WAKEUP_STATE_REG (DR_REG_RTCCNTL_BASE + 0x003C) +/* RTC_CNTL_WAKEUP_ENA : R/W ;bitpos:[31:15] ;default: 17'b1100 ; */ +/*description: wakeup enable bitmap*/ +#define RTC_CNTL_WAKEUP_ENA 0x0001FFFF +#define RTC_CNTL_WAKEUP_ENA_M ((RTC_CNTL_WAKEUP_ENA_V)<<(RTC_CNTL_WAKEUP_ENA_S)) +#define RTC_CNTL_WAKEUP_ENA_V 0x1FFFF +#define RTC_CNTL_WAKEUP_ENA_S 15 + +#define RTC_CNTL_INT_ENA_REG (DR_REG_RTCCNTL_BASE + 0x0040) +/* RTC_CNTL_BBPLL_CAL_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_BBPLL_CAL_INT_ENA (BIT(20)) +#define RTC_CNTL_BBPLL_CAL_INT_ENA_M (BIT(20)) +#define RTC_CNTL_BBPLL_CAL_INT_ENA_V 0x1 +#define RTC_CNTL_BBPLL_CAL_INT_ENA_S 20 +/* RTC_CNTL_GLITCH_DET_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: enable gitch det interrupt*/ +#define RTC_CNTL_GLITCH_DET_INT_ENA (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ENA_M (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ENA_V 0x1 +#define RTC_CNTL_GLITCH_DET_INT_ENA_S 19 +/* RTC_CNTL_XTAL32K_DEAD_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: enable xtal32k_dead interrupt*/ +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_M (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_V 0x1 +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_S 16 +/* RTC_CNTL_SWD_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: enable super watch dog interrupt*/ +#define RTC_CNTL_SWD_INT_ENA (BIT(15)) +#define RTC_CNTL_SWD_INT_ENA_M (BIT(15)) +#define RTC_CNTL_SWD_INT_ENA_V 0x1 +#define RTC_CNTL_SWD_INT_ENA_S 15 +/* RTC_CNTL_MAIN_TIMER_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: enable RTC main timer interrupt*/ +#define RTC_CNTL_MAIN_TIMER_INT_ENA (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ENA_M (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ENA_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_ENA_S 10 +/* RTC_CNTL_BROWN_OUT_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: enable brown out interrupt*/ +#define RTC_CNTL_BROWN_OUT_INT_ENA (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ENA_M (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_ENA_S 9 +/* RTC_CNTL_WDT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: enable RTC WDT interrupt*/ +#define RTC_CNTL_WDT_INT_ENA (BIT(3)) +#define RTC_CNTL_WDT_INT_ENA_M (BIT(3)) +#define RTC_CNTL_WDT_INT_ENA_V 0x1 +#define RTC_CNTL_WDT_INT_ENA_S 3 +/* RTC_CNTL_SLP_REJECT_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: enable sleep reject interrupt*/ +#define RTC_CNTL_SLP_REJECT_INT_ENA (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ENA_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ENA_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_ENA_S 1 +/* RTC_CNTL_SLP_WAKEUP_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: enable sleep wakeup interrupt*/ +#define RTC_CNTL_SLP_WAKEUP_INT_ENA (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_S 0 + +#define RTC_CNTL_INT_RAW_REG (DR_REG_RTCCNTL_BASE + 0x0044) +/* RTC_CNTL_BBPLL_CAL_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_BBPLL_CAL_INT_RAW (BIT(20)) +#define RTC_CNTL_BBPLL_CAL_INT_RAW_M (BIT(20)) +#define RTC_CNTL_BBPLL_CAL_INT_RAW_V 0x1 +#define RTC_CNTL_BBPLL_CAL_INT_RAW_S 20 +/* RTC_CNTL_GLITCH_DET_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: glitch_det_interrupt_raw*/ +#define RTC_CNTL_GLITCH_DET_INT_RAW (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_RAW_M (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_RAW_V 0x1 +#define RTC_CNTL_GLITCH_DET_INT_RAW_S 19 +/* RTC_CNTL_XTAL32K_DEAD_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: xtal32k dead detection interrupt raw*/ +#define RTC_CNTL_XTAL32K_DEAD_INT_RAW (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_RAW_M (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_RAW_V 0x1 +#define RTC_CNTL_XTAL32K_DEAD_INT_RAW_S 16 +/* RTC_CNTL_SWD_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: super watch dog interrupt raw*/ +#define RTC_CNTL_SWD_INT_RAW (BIT(15)) +#define RTC_CNTL_SWD_INT_RAW_M (BIT(15)) +#define RTC_CNTL_SWD_INT_RAW_V 0x1 +#define RTC_CNTL_SWD_INT_RAW_S 15 +/* RTC_CNTL_MAIN_TIMER_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: RTC main timer interrupt raw*/ +#define RTC_CNTL_MAIN_TIMER_INT_RAW (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_RAW_M (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_RAW_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_RAW_S 10 +/* RTC_CNTL_BROWN_OUT_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: brown out interrupt raw*/ +#define RTC_CNTL_BROWN_OUT_INT_RAW (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_RAW_M (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_RAW_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_RAW_S 9 +/* RTC_CNTL_WDT_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: RTC WDT interrupt raw*/ +#define RTC_CNTL_WDT_INT_RAW (BIT(3)) +#define RTC_CNTL_WDT_INT_RAW_M (BIT(3)) +#define RTC_CNTL_WDT_INT_RAW_V 0x1 +#define RTC_CNTL_WDT_INT_RAW_S 3 +/* RTC_CNTL_SLP_REJECT_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: sleep reject interrupt raw*/ +#define RTC_CNTL_SLP_REJECT_INT_RAW (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_RAW_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_RAW_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_RAW_S 1 +/* RTC_CNTL_SLP_WAKEUP_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: sleep wakeup interrupt raw*/ +#define RTC_CNTL_SLP_WAKEUP_INT_RAW (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_RAW_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_RAW_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_RAW_S 0 + +#define RTC_CNTL_INT_ST_REG (DR_REG_RTCCNTL_BASE + 0x0048) +/* RTC_CNTL_BBPLL_CAL_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_BBPLL_CAL_INT_ST (BIT(20)) +#define RTC_CNTL_BBPLL_CAL_INT_ST_M (BIT(20)) +#define RTC_CNTL_BBPLL_CAL_INT_ST_V 0x1 +#define RTC_CNTL_BBPLL_CAL_INT_ST_S 20 +/* RTC_CNTL_GLITCH_DET_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: glitch_det_interrupt state*/ +#define RTC_CNTL_GLITCH_DET_INT_ST (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ST_M (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ST_V 0x1 +#define RTC_CNTL_GLITCH_DET_INT_ST_S 19 +/* RTC_CNTL_XTAL32K_DEAD_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: xtal32k dead detection interrupt state*/ +#define RTC_CNTL_XTAL32K_DEAD_INT_ST (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ST_M (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ST_V 0x1 +#define RTC_CNTL_XTAL32K_DEAD_INT_ST_S 16 +/* RTC_CNTL_SWD_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: super watch dog interrupt state*/ +#define RTC_CNTL_SWD_INT_ST (BIT(15)) +#define RTC_CNTL_SWD_INT_ST_M (BIT(15)) +#define RTC_CNTL_SWD_INT_ST_V 0x1 +#define RTC_CNTL_SWD_INT_ST_S 15 +/* RTC_CNTL_MAIN_TIMER_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: RTC main timer interrupt state*/ +#define RTC_CNTL_MAIN_TIMER_INT_ST (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ST_M (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ST_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_ST_S 10 +/* RTC_CNTL_BROWN_OUT_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: brown out interrupt state*/ +#define RTC_CNTL_BROWN_OUT_INT_ST (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ST_M (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ST_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_ST_S 9 +/* RTC_CNTL_WDT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: RTC WDT interrupt state*/ +#define RTC_CNTL_WDT_INT_ST (BIT(3)) +#define RTC_CNTL_WDT_INT_ST_M (BIT(3)) +#define RTC_CNTL_WDT_INT_ST_V 0x1 +#define RTC_CNTL_WDT_INT_ST_S 3 +/* RTC_CNTL_SLP_REJECT_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: sleep reject interrupt state*/ +#define RTC_CNTL_SLP_REJECT_INT_ST (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ST_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ST_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_ST_S 1 +/* RTC_CNTL_SLP_WAKEUP_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: sleep wakeup interrupt state*/ +#define RTC_CNTL_SLP_WAKEUP_INT_ST (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ST_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ST_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_ST_S 0 + +#define RTC_CNTL_INT_CLR_REG (DR_REG_RTCCNTL_BASE + 0x004C) +/* RTC_CNTL_BBPLL_CAL_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_BBPLL_CAL_INT_CLR (BIT(20)) +#define RTC_CNTL_BBPLL_CAL_INT_CLR_M (BIT(20)) +#define RTC_CNTL_BBPLL_CAL_INT_CLR_V 0x1 +#define RTC_CNTL_BBPLL_CAL_INT_CLR_S 20 +/* RTC_CNTL_GLITCH_DET_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: Clear glitch det interrupt state*/ +#define RTC_CNTL_GLITCH_DET_INT_CLR (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_CLR_M (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_CLR_V 0x1 +#define RTC_CNTL_GLITCH_DET_INT_CLR_S 19 +/* RTC_CNTL_XTAL32K_DEAD_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: Clear RTC WDT interrupt state*/ +#define RTC_CNTL_XTAL32K_DEAD_INT_CLR (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_CLR_M (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_CLR_V 0x1 +#define RTC_CNTL_XTAL32K_DEAD_INT_CLR_S 16 +/* RTC_CNTL_SWD_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: Clear super watch dog interrupt state*/ +#define RTC_CNTL_SWD_INT_CLR (BIT(15)) +#define RTC_CNTL_SWD_INT_CLR_M (BIT(15)) +#define RTC_CNTL_SWD_INT_CLR_V 0x1 +#define RTC_CNTL_SWD_INT_CLR_S 15 +/* RTC_CNTL_MAIN_TIMER_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: Clear RTC main timer interrupt state*/ +#define RTC_CNTL_MAIN_TIMER_INT_CLR (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_CLR_M (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_CLR_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_CLR_S 10 +/* RTC_CNTL_BROWN_OUT_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Clear brown out interrupt state*/ +#define RTC_CNTL_BROWN_OUT_INT_CLR (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_CLR_M (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_CLR_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_CLR_S 9 +/* RTC_CNTL_WDT_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Clear RTC WDT interrupt state*/ +#define RTC_CNTL_WDT_INT_CLR (BIT(3)) +#define RTC_CNTL_WDT_INT_CLR_M (BIT(3)) +#define RTC_CNTL_WDT_INT_CLR_V 0x1 +#define RTC_CNTL_WDT_INT_CLR_S 3 +/* RTC_CNTL_SLP_REJECT_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Clear sleep reject interrupt state*/ +#define RTC_CNTL_SLP_REJECT_INT_CLR (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_CLR_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_CLR_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_CLR_S 1 +/* RTC_CNTL_SLP_WAKEUP_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Clear sleep wakeup interrupt state*/ +#define RTC_CNTL_SLP_WAKEUP_INT_CLR (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_CLR_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_CLR_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_CLR_S 0 + +#define RTC_CNTL_STORE0_REG (DR_REG_RTCCNTL_BASE + 0x0050) +/* RTC_CNTL_SCRATCH0 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: */ +#define RTC_CNTL_SCRATCH0 0xFFFFFFFF +#define RTC_CNTL_SCRATCH0_M ((RTC_CNTL_SCRATCH0_V)<<(RTC_CNTL_SCRATCH0_S)) +#define RTC_CNTL_SCRATCH0_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH0_S 0 + +#define RTC_CNTL_STORE1_REG (DR_REG_RTCCNTL_BASE + 0x0054) +/* RTC_CNTL_SCRATCH1 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: */ +#define RTC_CNTL_SCRATCH1 0xFFFFFFFF +#define RTC_CNTL_SCRATCH1_M ((RTC_CNTL_SCRATCH1_V)<<(RTC_CNTL_SCRATCH1_S)) +#define RTC_CNTL_SCRATCH1_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH1_S 0 + +#define RTC_CNTL_STORE2_REG (DR_REG_RTCCNTL_BASE + 0x0058) +/* RTC_CNTL_SCRATCH2 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: */ +#define RTC_CNTL_SCRATCH2 0xFFFFFFFF +#define RTC_CNTL_SCRATCH2_M ((RTC_CNTL_SCRATCH2_V)<<(RTC_CNTL_SCRATCH2_S)) +#define RTC_CNTL_SCRATCH2_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH2_S 0 + +#define RTC_CNTL_STORE3_REG (DR_REG_RTCCNTL_BASE + 0x005C) +/* RTC_CNTL_SCRATCH3 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: */ +#define RTC_CNTL_SCRATCH3 0xFFFFFFFF +#define RTC_CNTL_SCRATCH3_M ((RTC_CNTL_SCRATCH3_V)<<(RTC_CNTL_SCRATCH3_S)) +#define RTC_CNTL_SCRATCH3_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH3_S 0 + +#define RTC_CNTL_EXT_XTL_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0060) +/* RTC_CNTL_XTL_EXT_CTR_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_XTL_EXT_CTR_EN (BIT(31)) +#define RTC_CNTL_XTL_EXT_CTR_EN_M (BIT(31)) +#define RTC_CNTL_XTL_EXT_CTR_EN_V 0x1 +#define RTC_CNTL_XTL_EXT_CTR_EN_S 31 +/* RTC_CNTL_XTL_EXT_CTR_LV : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: 0: power down XTAL at high level*/ +#define RTC_CNTL_XTL_EXT_CTR_LV (BIT(30)) +#define RTC_CNTL_XTL_EXT_CTR_LV_M (BIT(30)) +#define RTC_CNTL_XTL_EXT_CTR_LV_V 0x1 +#define RTC_CNTL_XTL_EXT_CTR_LV_S 30 +/* RTC_CNTL_XTAL32K_GPIO_SEL : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: XTAL_32K sel. 0: external XTAL_32K*/ +#define RTC_CNTL_XTAL32K_GPIO_SEL (BIT(23)) +#define RTC_CNTL_XTAL32K_GPIO_SEL_M (BIT(23)) +#define RTC_CNTL_XTAL32K_GPIO_SEL_V 0x1 +#define RTC_CNTL_XTAL32K_GPIO_SEL_S 23 +/* RTC_CNTL_WDT_STATE : RO ;bitpos:[22:20] ;default: 3'h0 ; */ +/*description: state of 32k_wdt*/ +#define RTC_CNTL_WDT_STATE 0x00000007 +#define RTC_CNTL_WDT_STATE_M ((RTC_CNTL_WDT_STATE_V)<<(RTC_CNTL_WDT_STATE_S)) +#define RTC_CNTL_WDT_STATE_V 0x7 +#define RTC_CNTL_WDT_STATE_S 20 +/* RTC_CNTL_DAC_XTAL_32K : R/W ;bitpos:[19:17] ;default: 3'd3 ; */ +/*description: DAC_XTAL_32K*/ +#define RTC_CNTL_DAC_XTAL_32K 0x00000007 +#define RTC_CNTL_DAC_XTAL_32K_M ((RTC_CNTL_DAC_XTAL_32K_V)<<(RTC_CNTL_DAC_XTAL_32K_S)) +#define RTC_CNTL_DAC_XTAL_32K_V 0x7 +#define RTC_CNTL_DAC_XTAL_32K_S 17 +/* RTC_CNTL_XPD_XTAL_32K : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: XPD_XTAL_32K*/ +#define RTC_CNTL_XPD_XTAL_32K (BIT(16)) +#define RTC_CNTL_XPD_XTAL_32K_M (BIT(16)) +#define RTC_CNTL_XPD_XTAL_32K_V 0x1 +#define RTC_CNTL_XPD_XTAL_32K_S 16 +/* RTC_CNTL_DRES_XTAL_32K : R/W ;bitpos:[15:13] ;default: 3'd3 ; */ +/*description: DRES_XTAL_32K*/ +#define RTC_CNTL_DRES_XTAL_32K 0x00000007 +#define RTC_CNTL_DRES_XTAL_32K_M ((RTC_CNTL_DRES_XTAL_32K_V)<<(RTC_CNTL_DRES_XTAL_32K_S)) +#define RTC_CNTL_DRES_XTAL_32K_V 0x7 +#define RTC_CNTL_DRES_XTAL_32K_S 13 +/* RTC_CNTL_DGM_XTAL_32K : R/W ;bitpos:[12:10] ;default: 3'd3 ; */ +/*description: xtal_32k gm control*/ +#define RTC_CNTL_DGM_XTAL_32K 0x00000007 +#define RTC_CNTL_DGM_XTAL_32K_M ((RTC_CNTL_DGM_XTAL_32K_V)<<(RTC_CNTL_DGM_XTAL_32K_S)) +#define RTC_CNTL_DGM_XTAL_32K_V 0x7 +#define RTC_CNTL_DGM_XTAL_32K_S 10 +/* RTC_CNTL_DBUF_XTAL_32K : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: 0: single-end buffer 1: differential buffer*/ +#define RTC_CNTL_DBUF_XTAL_32K (BIT(9)) +#define RTC_CNTL_DBUF_XTAL_32K_M (BIT(9)) +#define RTC_CNTL_DBUF_XTAL_32K_V 0x1 +#define RTC_CNTL_DBUF_XTAL_32K_S 9 +/* RTC_CNTL_ENCKINIT_XTAL_32K : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: apply an internal clock to help xtal 32k to start*/ +#define RTC_CNTL_ENCKINIT_XTAL_32K (BIT(8)) +#define RTC_CNTL_ENCKINIT_XTAL_32K_M (BIT(8)) +#define RTC_CNTL_ENCKINIT_XTAL_32K_V 0x1 +#define RTC_CNTL_ENCKINIT_XTAL_32K_S 8 +/* RTC_CNTL_XTAL32K_XPD_FORCE : R/W ;bitpos:[7] ;default: 1'b1 ; */ +/*description: Xtal 32k xpd control by sw or fsm*/ +#define RTC_CNTL_XTAL32K_XPD_FORCE (BIT(7)) +#define RTC_CNTL_XTAL32K_XPD_FORCE_M (BIT(7)) +#define RTC_CNTL_XTAL32K_XPD_FORCE_V 0x1 +#define RTC_CNTL_XTAL32K_XPD_FORCE_S 7 +/* RTC_CNTL_XTAL32K_AUTO_RETURN : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: xtal 32k switch back xtal when xtal is restarted*/ +#define RTC_CNTL_XTAL32K_AUTO_RETURN (BIT(6)) +#define RTC_CNTL_XTAL32K_AUTO_RETURN_M (BIT(6)) +#define RTC_CNTL_XTAL32K_AUTO_RETURN_V 0x1 +#define RTC_CNTL_XTAL32K_AUTO_RETURN_S 6 +/* RTC_CNTL_XTAL32K_AUTO_RESTART : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: xtal 32k restart xtal when xtal is dead*/ +#define RTC_CNTL_XTAL32K_AUTO_RESTART (BIT(5)) +#define RTC_CNTL_XTAL32K_AUTO_RESTART_M (BIT(5)) +#define RTC_CNTL_XTAL32K_AUTO_RESTART_V 0x1 +#define RTC_CNTL_XTAL32K_AUTO_RESTART_S 5 +/* RTC_CNTL_XTAL32K_AUTO_BACKUP : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: xtal 32k switch to back up clock when xtal is dead*/ +#define RTC_CNTL_XTAL32K_AUTO_BACKUP (BIT(4)) +#define RTC_CNTL_XTAL32K_AUTO_BACKUP_M (BIT(4)) +#define RTC_CNTL_XTAL32K_AUTO_BACKUP_V 0x1 +#define RTC_CNTL_XTAL32K_AUTO_BACKUP_S 4 +/* RTC_CNTL_XTAL32K_EXT_CLK_FO : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: xtal 32k external xtal clock force on*/ +#define RTC_CNTL_XTAL32K_EXT_CLK_FO (BIT(3)) +#define RTC_CNTL_XTAL32K_EXT_CLK_FO_M (BIT(3)) +#define RTC_CNTL_XTAL32K_EXT_CLK_FO_V 0x1 +#define RTC_CNTL_XTAL32K_EXT_CLK_FO_S 3 +/* RTC_CNTL_XTAL32K_WDT_RESET : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: xtal 32k watch dog sw reset*/ +#define RTC_CNTL_XTAL32K_WDT_RESET (BIT(2)) +#define RTC_CNTL_XTAL32K_WDT_RESET_M (BIT(2)) +#define RTC_CNTL_XTAL32K_WDT_RESET_V 0x1 +#define RTC_CNTL_XTAL32K_WDT_RESET_S 2 +/* RTC_CNTL_XTAL32K_WDT_CLK_FO : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: xtal 32k watch dog clock force on*/ +#define RTC_CNTL_XTAL32K_WDT_CLK_FO (BIT(1)) +#define RTC_CNTL_XTAL32K_WDT_CLK_FO_M (BIT(1)) +#define RTC_CNTL_XTAL32K_WDT_CLK_FO_V 0x1 +#define RTC_CNTL_XTAL32K_WDT_CLK_FO_S 1 +/* RTC_CNTL_XTAL32K_WDT_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: xtal 32k watch dog enable*/ +#define RTC_CNTL_XTAL32K_WDT_EN (BIT(0)) +#define RTC_CNTL_XTAL32K_WDT_EN_M (BIT(0)) +#define RTC_CNTL_XTAL32K_WDT_EN_V 0x1 +#define RTC_CNTL_XTAL32K_WDT_EN_S 0 + +#define RTC_CNTL_EXT_WAKEUP_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0064) +/* RTC_CNTL_GPIO_WAKEUP_FILTER : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: enable filter for gpio wakeup event*/ +#define RTC_CNTL_GPIO_WAKEUP_FILTER (BIT(31)) +#define RTC_CNTL_GPIO_WAKEUP_FILTER_M (BIT(31)) +#define RTC_CNTL_GPIO_WAKEUP_FILTER_V 0x1 +#define RTC_CNTL_GPIO_WAKEUP_FILTER_S 31 + +#define RTC_CNTL_SLP_REJECT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0068) +/* RTC_CNTL_DEEP_SLP_REJECT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: enable reject for deep sleep*/ +#define RTC_CNTL_DEEP_SLP_REJECT_EN (BIT(31)) +#define RTC_CNTL_DEEP_SLP_REJECT_EN_M (BIT(31)) +#define RTC_CNTL_DEEP_SLP_REJECT_EN_V 0x1 +#define RTC_CNTL_DEEP_SLP_REJECT_EN_S 31 +/* RTC_CNTL_LIGHT_SLP_REJECT_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: enable reject for light sleep*/ +#define RTC_CNTL_LIGHT_SLP_REJECT_EN (BIT(30)) +#define RTC_CNTL_LIGHT_SLP_REJECT_EN_M (BIT(30)) +#define RTC_CNTL_LIGHT_SLP_REJECT_EN_V 0x1 +#define RTC_CNTL_LIGHT_SLP_REJECT_EN_S 30 +/* RTC_CNTL_SLEEP_REJECT_ENA : R/W ;bitpos:[29:12] ;default: 17'd0 ; */ +/*description: sleep reject enable*/ +#define RTC_CNTL_SLEEP_REJECT_ENA 0x0003FFFF +#define RTC_CNTL_SLEEP_REJECT_ENA_M ((RTC_CNTL_SLEEP_REJECT_ENA_V)<<(RTC_CNTL_SLEEP_REJECT_ENA_S)) +#define RTC_CNTL_SLEEP_REJECT_ENA_V 0x3FFFF +#define RTC_CNTL_SLEEP_REJECT_ENA_S 12 + +#define RTC_CNTL_CPU_PERIOD_CONF_REG (DR_REG_RTCCNTL_BASE + 0x006C) +/* RTC_CNTL_CPUPERIOD_SEL : R/W ;bitpos:[31:30] ;default: 2'b00 ; */ +/*description: */ +#define RTC_CNTL_CPUPERIOD_SEL 0x00000003 +#define RTC_CNTL_CPUPERIOD_SEL_M ((RTC_CNTL_CPUPERIOD_SEL_V)<<(RTC_CNTL_CPUPERIOD_SEL_S)) +#define RTC_CNTL_CPUPERIOD_SEL_V 0x3 +#define RTC_CNTL_CPUPERIOD_SEL_S 30 +/* RTC_CNTL_CPUSEL_CONF : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: CPU sel option*/ +#define RTC_CNTL_CPUSEL_CONF (BIT(29)) +#define RTC_CNTL_CPUSEL_CONF_M (BIT(29)) +#define RTC_CNTL_CPUSEL_CONF_V 0x1 +#define RTC_CNTL_CPUSEL_CONF_S 29 + +#define RTC_CNTL_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0070) +/* RTC_CNTL_ANA_CLK_RTC_SEL : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ +/*description: */ +#define RTC_CNTL_ANA_CLK_RTC_SEL 0x00000003 +#define RTC_CNTL_ANA_CLK_RTC_SEL_M ((RTC_CNTL_ANA_CLK_RTC_SEL_V)<<(RTC_CNTL_ANA_CLK_RTC_SEL_S)) +#define RTC_CNTL_ANA_CLK_RTC_SEL_V 0x3 +#define RTC_CNTL_ANA_CLK_RTC_SEL_S 30 +/* RTC_CNTL_FAST_CLK_RTC_SEL : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: fast_clk_rtc sel. 0: XTAL div 2*/ +#define RTC_CNTL_FAST_CLK_RTC_SEL (BIT(29)) +#define RTC_CNTL_FAST_CLK_RTC_SEL_M (BIT(29)) +#define RTC_CNTL_FAST_CLK_RTC_SEL_V 0x1 +#define RTC_CNTL_FAST_CLK_RTC_SEL_S 29 +/* RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING : R/W ;bitpos:[28] ;default: 1'b1 ; */ +/*description: */ +#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING (BIT(28)) +#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_M (BIT(28)) +#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_V 0x1 +#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_S 28 +/* RTC_CNTL_XTAL_GLOBAL_FORCE_GATING : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING (BIT(27)) +#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_M (BIT(27)) +#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_V 0x1 +#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_S 27 +/* RTC_CNTL_CK8M_FORCE_PU : R/W ;bitpos:[26] ;default: 1'd0 ; */ +/*description: CK8M force power up*/ +#define RTC_CNTL_CK8M_FORCE_PU (BIT(26)) +#define RTC_CNTL_CK8M_FORCE_PU_M (BIT(26)) +#define RTC_CNTL_CK8M_FORCE_PU_V 0x1 +#define RTC_CNTL_CK8M_FORCE_PU_S 26 +/* RTC_CNTL_CK8M_FORCE_PD : R/W ;bitpos:[25] ;default: 1'd0 ; */ +/*description: CK8M force power down*/ +#define RTC_CNTL_CK8M_FORCE_PD (BIT(25)) +#define RTC_CNTL_CK8M_FORCE_PD_M (BIT(25)) +#define RTC_CNTL_CK8M_FORCE_PD_V 0x1 +#define RTC_CNTL_CK8M_FORCE_PD_S 25 +/* RTC_CNTL_CK8M_DFREQ : R/W ;bitpos:[24:17] ;default: 8'd172 ; */ +/*description: CK8M_DFREQ*/ +#define RTC_CNTL_CK8M_DFREQ 0x000000FF +#define RTC_CNTL_CK8M_DFREQ_M ((RTC_CNTL_CK8M_DFREQ_V)<<(RTC_CNTL_CK8M_DFREQ_S)) +#define RTC_CNTL_CK8M_DFREQ_V 0xFF +#define RTC_CNTL_CK8M_DFREQ_S 17 +/* RTC_CNTL_CK8M_FORCE_NOGATING : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: CK8M force no gating during sleep*/ +#define RTC_CNTL_CK8M_FORCE_NOGATING (BIT(16)) +#define RTC_CNTL_CK8M_FORCE_NOGATING_M (BIT(16)) +#define RTC_CNTL_CK8M_FORCE_NOGATING_V 0x1 +#define RTC_CNTL_CK8M_FORCE_NOGATING_S 16 +/* RTC_CNTL_XTAL_FORCE_NOGATING : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: XTAL force no gating during sleep*/ +#define RTC_CNTL_XTAL_FORCE_NOGATING (BIT(15)) +#define RTC_CNTL_XTAL_FORCE_NOGATING_M (BIT(15)) +#define RTC_CNTL_XTAL_FORCE_NOGATING_V 0x1 +#define RTC_CNTL_XTAL_FORCE_NOGATING_S 15 +/* RTC_CNTL_CK8M_DIV_SEL : R/W ;bitpos:[14:12] ;default: 3'd3 ; */ +/*description: divider = reg_ck8m_div_sel + 1*/ +#define RTC_CNTL_CK8M_DIV_SEL 0x00000007 +#define RTC_CNTL_CK8M_DIV_SEL_M ((RTC_CNTL_CK8M_DIV_SEL_V)<<(RTC_CNTL_CK8M_DIV_SEL_S)) +#define RTC_CNTL_CK8M_DIV_SEL_V 0x7 +#define RTC_CNTL_CK8M_DIV_SEL_S 12 +/* RTC_CNTL_DIG_CLK8M_EN : R/W ;bitpos:[10] ;default: 1'd0 ; */ +/*description: enable CK8M for digital core (no relationship with RTC core)*/ +#define RTC_CNTL_DIG_CLK8M_EN (BIT(10)) +#define RTC_CNTL_DIG_CLK8M_EN_M (BIT(10)) +#define RTC_CNTL_DIG_CLK8M_EN_V 0x1 +#define RTC_CNTL_DIG_CLK8M_EN_S 10 +/* RTC_CNTL_DIG_CLK8M_D256_EN : R/W ;bitpos:[9] ;default: 1'd1 ; */ +/*description: enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/ +#define RTC_CNTL_DIG_CLK8M_D256_EN (BIT(9)) +#define RTC_CNTL_DIG_CLK8M_D256_EN_M (BIT(9)) +#define RTC_CNTL_DIG_CLK8M_D256_EN_V 0x1 +#define RTC_CNTL_DIG_CLK8M_D256_EN_S 9 +/* RTC_CNTL_DIG_XTAL32K_EN : R/W ;bitpos:[8] ;default: 1'd0 ; */ +/*description: enable CK_XTAL_32K for digital core (no relationship with RTC core)*/ +#define RTC_CNTL_DIG_XTAL32K_EN (BIT(8)) +#define RTC_CNTL_DIG_XTAL32K_EN_M (BIT(8)) +#define RTC_CNTL_DIG_XTAL32K_EN_V 0x1 +#define RTC_CNTL_DIG_XTAL32K_EN_S 8 +/* RTC_CNTL_ENB_CK8M_DIV : R/W ;bitpos:[7] ;default: 1'd0 ; */ +/*description: 1: CK8M_D256_OUT is actually CK8M*/ +#define RTC_CNTL_ENB_CK8M_DIV (BIT(7)) +#define RTC_CNTL_ENB_CK8M_DIV_M (BIT(7)) +#define RTC_CNTL_ENB_CK8M_DIV_V 0x1 +#define RTC_CNTL_ENB_CK8M_DIV_S 7 +/* RTC_CNTL_ENB_CK8M : R/W ;bitpos:[6] ;default: 1'd0 ; */ +/*description: disable CK8M and CK8M_D256_OUT*/ +#define RTC_CNTL_ENB_CK8M (BIT(6)) +#define RTC_CNTL_ENB_CK8M_M (BIT(6)) +#define RTC_CNTL_ENB_CK8M_V 0x1 +#define RTC_CNTL_ENB_CK8M_S 6 +/* RTC_CNTL_CK8M_DIV : R/W ;bitpos:[5:4] ;default: 2'b01 ; */ +/*description: CK8M_D256_OUT divider. 00: div128*/ +#define RTC_CNTL_CK8M_DIV 0x00000003 +#define RTC_CNTL_CK8M_DIV_M ((RTC_CNTL_CK8M_DIV_V)<<(RTC_CNTL_CK8M_DIV_S)) +#define RTC_CNTL_CK8M_DIV_V 0x3 +#define RTC_CNTL_CK8M_DIV_S 4 +/* RTC_CNTL_CK8M_DIV_SEL_VLD : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel*/ +#define RTC_CNTL_CK8M_DIV_SEL_VLD (BIT(3)) +#define RTC_CNTL_CK8M_DIV_SEL_VLD_M (BIT(3)) +#define RTC_CNTL_CK8M_DIV_SEL_VLD_V 0x1 +#define RTC_CNTL_CK8M_DIV_SEL_VLD_S 3 +/* RTC_CNTL_EFUSE_CLK_FORCE_NOGATING : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING (BIT(2)) +#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_M (BIT(2)) +#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_V 0x1 +#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_S 2 +/* RTC_CNTL_EFUSE_CLK_FORCE_GATING : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_EFUSE_CLK_FORCE_GATING (BIT(1)) +#define RTC_CNTL_EFUSE_CLK_FORCE_GATING_M (BIT(1)) +#define RTC_CNTL_EFUSE_CLK_FORCE_GATING_V 0x1 +#define RTC_CNTL_EFUSE_CLK_FORCE_GATING_S 1 + +#define RTC_CNTL_SLOW_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0074) +/* RTC_CNTL_SLOW_CLK_NEXT_EDGE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_SLOW_CLK_NEXT_EDGE (BIT(31)) +#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_M (BIT(31)) +#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_V 0x1 +#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_S 31 +/* RTC_CNTL_ANA_CLK_DIV : R/W ;bitpos:[30:23] ;default: 8'd0 ; */ +/*description: */ +#define RTC_CNTL_ANA_CLK_DIV 0x000000FF +#define RTC_CNTL_ANA_CLK_DIV_M ((RTC_CNTL_ANA_CLK_DIV_V)<<(RTC_CNTL_ANA_CLK_DIV_S)) +#define RTC_CNTL_ANA_CLK_DIV_V 0xFF +#define RTC_CNTL_ANA_CLK_DIV_S 23 +/* RTC_CNTL_ANA_CLK_DIV_VLD : R/W ;bitpos:[22] ;default: 1'b1 ; */ +/*description: used to sync div bus. clear vld before set reg_rtc_ana_clk_div*/ +#define RTC_CNTL_ANA_CLK_DIV_VLD (BIT(22)) +#define RTC_CNTL_ANA_CLK_DIV_VLD_M (BIT(22)) +#define RTC_CNTL_ANA_CLK_DIV_VLD_V 0x1 +#define RTC_CNTL_ANA_CLK_DIV_VLD_S 22 + +#define RTC_CNTL_SDIO_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0078) +/* RTC_CNTL_XPD_SDIO_REG : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_XPD_SDIO_REG (BIT(31)) +#define RTC_CNTL_XPD_SDIO_REG_M (BIT(31)) +#define RTC_CNTL_XPD_SDIO_REG_V 0x1 +#define RTC_CNTL_XPD_SDIO_REG_S 31 +/* RTC_CNTL_DREFH_SDIO : R/W ;bitpos:[30:29] ;default: 2'b00 ; */ +/*description: SW option for DREFH_SDIO. Only active when reg_sdio_force = 1*/ +#define RTC_CNTL_DREFH_SDIO 0x00000003 +#define RTC_CNTL_DREFH_SDIO_M ((RTC_CNTL_DREFH_SDIO_V)<<(RTC_CNTL_DREFH_SDIO_S)) +#define RTC_CNTL_DREFH_SDIO_V 0x3 +#define RTC_CNTL_DREFH_SDIO_S 29 +/* RTC_CNTL_DREFM_SDIO : R/W ;bitpos:[28:27] ;default: 2'b01 ; */ +/*description: SW option for DREFM_SDIO. Only active when reg_sdio_force = 1*/ +#define RTC_CNTL_DREFM_SDIO 0x00000003 +#define RTC_CNTL_DREFM_SDIO_M ((RTC_CNTL_DREFM_SDIO_V)<<(RTC_CNTL_DREFM_SDIO_S)) +#define RTC_CNTL_DREFM_SDIO_V 0x3 +#define RTC_CNTL_DREFM_SDIO_S 27 +/* RTC_CNTL_DREFL_SDIO : R/W ;bitpos:[26:25] ;default: 2'b01 ; */ +/*description: SW option for DREFL_SDIO. Only active when reg_sdio_force = 1*/ +#define RTC_CNTL_DREFL_SDIO 0x00000003 +#define RTC_CNTL_DREFL_SDIO_M ((RTC_CNTL_DREFL_SDIO_V)<<(RTC_CNTL_DREFL_SDIO_S)) +#define RTC_CNTL_DREFL_SDIO_V 0x3 +#define RTC_CNTL_DREFL_SDIO_S 25 +/* RTC_CNTL_REG1P8_READY : RO ;bitpos:[24] ;default: 1'd0 ; */ +/*description: read only register for REG1P8_READY*/ +#define RTC_CNTL_REG1P8_READY (BIT(24)) +#define RTC_CNTL_REG1P8_READY_M (BIT(24)) +#define RTC_CNTL_REG1P8_READY_V 0x1 +#define RTC_CNTL_REG1P8_READY_S 24 +/* RTC_CNTL_SDIO_TIEH : R/W ;bitpos:[23] ;default: 1'd1 ; */ +/*description: SW option for SDIO_TIEH. Only active when reg_sdio_force = 1*/ +#define RTC_CNTL_SDIO_TIEH (BIT(23)) +#define RTC_CNTL_SDIO_TIEH_M (BIT(23)) +#define RTC_CNTL_SDIO_TIEH_V 0x1 +#define RTC_CNTL_SDIO_TIEH_S 23 +/* RTC_CNTL_SDIO_FORCE : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: 1: use SW option to control SDIO_REG*/ +#define RTC_CNTL_SDIO_FORCE (BIT(22)) +#define RTC_CNTL_SDIO_FORCE_M (BIT(22)) +#define RTC_CNTL_SDIO_FORCE_V 0x1 +#define RTC_CNTL_SDIO_FORCE_S 22 +/* RTC_CNTL_SDIO_PD_EN : R/W ;bitpos:[21] ;default: 1'd1 ; */ +/*description: power down SDIO_REG in sleep. Only active when reg_sdio_force = 0*/ +#define RTC_CNTL_SDIO_PD_EN (BIT(21)) +#define RTC_CNTL_SDIO_PD_EN_M (BIT(21)) +#define RTC_CNTL_SDIO_PD_EN_V 0x1 +#define RTC_CNTL_SDIO_PD_EN_S 21 +/* RTC_CNTL_SDIO_ENCURLIM : R/W ;bitpos:[20] ;default: 1'd1 ; */ +/*description: enable current limit*/ +#define RTC_CNTL_SDIO_ENCURLIM (BIT(20)) +#define RTC_CNTL_SDIO_ENCURLIM_M (BIT(20)) +#define RTC_CNTL_SDIO_ENCURLIM_V 0x1 +#define RTC_CNTL_SDIO_ENCURLIM_S 20 +/* RTC_CNTL_SDIO_MODECURLIM : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: select current limit mode*/ +#define RTC_CNTL_SDIO_MODECURLIM (BIT(19)) +#define RTC_CNTL_SDIO_MODECURLIM_M (BIT(19)) +#define RTC_CNTL_SDIO_MODECURLIM_V 0x1 +#define RTC_CNTL_SDIO_MODECURLIM_S 19 +/* RTC_CNTL_SDIO_DCURLIM : R/W ;bitpos:[18:16] ;default: 3'd0 ; */ +/*description: tune current limit threshold when tieh = 0. About 800mA/(8+d)*/ +#define RTC_CNTL_SDIO_DCURLIM 0x00000007 +#define RTC_CNTL_SDIO_DCURLIM_M ((RTC_CNTL_SDIO_DCURLIM_V)<<(RTC_CNTL_SDIO_DCURLIM_S)) +#define RTC_CNTL_SDIO_DCURLIM_V 0x7 +#define RTC_CNTL_SDIO_DCURLIM_S 16 +/* RTC_CNTL_SDIO_EN_INITI : R/W ;bitpos:[15] ;default: 1'd1 ; */ +/*description: 0 to set init[1:0]=0*/ +#define RTC_CNTL_SDIO_EN_INITI (BIT(15)) +#define RTC_CNTL_SDIO_EN_INITI_M (BIT(15)) +#define RTC_CNTL_SDIO_EN_INITI_V 0x1 +#define RTC_CNTL_SDIO_EN_INITI_S 15 +/* RTC_CNTL_SDIO_INITI : R/W ;bitpos:[14:13] ;default: 2'd1 ; */ +/*description: add resistor from ldo output to ground. 0: no res*/ +#define RTC_CNTL_SDIO_INITI 0x00000003 +#define RTC_CNTL_SDIO_INITI_M ((RTC_CNTL_SDIO_INITI_V)<<(RTC_CNTL_SDIO_INITI_S)) +#define RTC_CNTL_SDIO_INITI_V 0x3 +#define RTC_CNTL_SDIO_INITI_S 13 +/* RTC_CNTL_SDIO_DCAP : R/W ;bitpos:[12:11] ;default: 2'b11 ; */ +/*description: ability to prevent LDO from overshoot*/ +#define RTC_CNTL_SDIO_DCAP 0x00000003 +#define RTC_CNTL_SDIO_DCAP_M ((RTC_CNTL_SDIO_DCAP_V)<<(RTC_CNTL_SDIO_DCAP_S)) +#define RTC_CNTL_SDIO_DCAP_V 0x3 +#define RTC_CNTL_SDIO_DCAP_S 11 +/* RTC_CNTL_SDIO_DTHDRV : R/W ;bitpos:[10:9] ;default: 2'b11 ; */ +/*description: Tieh = 1 mode drive ability. Initially set to 0 to limit charge current*/ +#define RTC_CNTL_SDIO_DTHDRV 0x00000003 +#define RTC_CNTL_SDIO_DTHDRV_M ((RTC_CNTL_SDIO_DTHDRV_V)<<(RTC_CNTL_SDIO_DTHDRV_S)) +#define RTC_CNTL_SDIO_DTHDRV_V 0x3 +#define RTC_CNTL_SDIO_DTHDRV_S 9 +/* RTC_CNTL_SDIO_TIMER_TARGET : R/W ;bitpos:[7:0] ;default: 8'd10 ; */ +/*description: timer count to apply reg_sdio_dcap after sdio power on*/ +#define RTC_CNTL_SDIO_TIMER_TARGET 0x000000FF +#define RTC_CNTL_SDIO_TIMER_TARGET_M ((RTC_CNTL_SDIO_TIMER_TARGET_V)<<(RTC_CNTL_SDIO_TIMER_TARGET_S)) +#define RTC_CNTL_SDIO_TIMER_TARGET_V 0xFF +#define RTC_CNTL_SDIO_TIMER_TARGET_S 0 + +#define RTC_CNTL_BIAS_CONF_REG (DR_REG_RTCCNTL_BASE + 0x007C) +/* RTC_CNTL_DBG_ATTEN_MONITOR : R/W ;bitpos:[25:22] ;default: 4'd0 ; */ +/*description: DBG_ATTEN when rtc in monitor state*/ +#define RTC_CNTL_DBG_ATTEN_MONITOR 0x0000000F +#define RTC_CNTL_DBG_ATTEN_MONITOR_M ((RTC_CNTL_DBG_ATTEN_MONITOR_V)<<(RTC_CNTL_DBG_ATTEN_MONITOR_S)) +#define RTC_CNTL_DBG_ATTEN_MONITOR_V 0xF +#define RTC_CNTL_DBG_ATTEN_MONITOR_S 22 +/* RTC_CNTL_DBG_ATTEN_DEEP_SLP : R/W ;bitpos:[21:18] ;default: 4'd0 ; */ +/*description: DBG_ATTEN when rtc in sleep state*/ +#define RTC_CNTL_DBG_ATTEN_DEEP_SLP 0x0000000F +#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_M ((RTC_CNTL_DBG_ATTEN_DEEP_SLP_V)<<(RTC_CNTL_DBG_ATTEN_DEEP_SLP_S)) +#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_V 0xF +#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_S 18 +/* RTC_CNTL_BIAS_SLEEP_MONITOR : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: bias_sleep when rtc in monitor state*/ +#define RTC_CNTL_BIAS_SLEEP_MONITOR (BIT(17)) +#define RTC_CNTL_BIAS_SLEEP_MONITOR_M (BIT(17)) +#define RTC_CNTL_BIAS_SLEEP_MONITOR_V 0x1 +#define RTC_CNTL_BIAS_SLEEP_MONITOR_S 17 +/* RTC_CNTL_BIAS_SLEEP_DEEP_SLP : R/W ;bitpos:[16] ;default: 1'b1 ; */ +/*description: bias_sleep when rtc in sleep_state*/ +#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP (BIT(16)) +#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_M (BIT(16)) +#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_V 0x1 +#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_S 16 +/* RTC_CNTL_PD_CUR_MONITOR : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: xpd cur when rtc in monitor state*/ +#define RTC_CNTL_PD_CUR_MONITOR (BIT(15)) +#define RTC_CNTL_PD_CUR_MONITOR_M (BIT(15)) +#define RTC_CNTL_PD_CUR_MONITOR_V 0x1 +#define RTC_CNTL_PD_CUR_MONITOR_S 15 +/* RTC_CNTL_PD_CUR_DEEP_SLP : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: xpd cur when rtc in sleep_state*/ +#define RTC_CNTL_PD_CUR_DEEP_SLP (BIT(14)) +#define RTC_CNTL_PD_CUR_DEEP_SLP_M (BIT(14)) +#define RTC_CNTL_PD_CUR_DEEP_SLP_V 0x1 +#define RTC_CNTL_PD_CUR_DEEP_SLP_S 14 +/* RTC_CNTL_BIAS_BUF_MONITOR : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_BIAS_BUF_MONITOR (BIT(13)) +#define RTC_CNTL_BIAS_BUF_MONITOR_M (BIT(13)) +#define RTC_CNTL_BIAS_BUF_MONITOR_V 0x1 +#define RTC_CNTL_BIAS_BUF_MONITOR_S 13 +/* RTC_CNTL_BIAS_BUF_DEEP_SLP : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_BIAS_BUF_DEEP_SLP (BIT(12)) +#define RTC_CNTL_BIAS_BUF_DEEP_SLP_M (BIT(12)) +#define RTC_CNTL_BIAS_BUF_DEEP_SLP_V 0x1 +#define RTC_CNTL_BIAS_BUF_DEEP_SLP_S 12 +/* RTC_CNTL_BIAS_BUF_WAKE : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: */ +#define RTC_CNTL_BIAS_BUF_WAKE (BIT(11)) +#define RTC_CNTL_BIAS_BUF_WAKE_M (BIT(11)) +#define RTC_CNTL_BIAS_BUF_WAKE_V 0x1 +#define RTC_CNTL_BIAS_BUF_WAKE_S 11 +/* RTC_CNTL_BIAS_BUF_IDLE : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_BIAS_BUF_IDLE (BIT(10)) +#define RTC_CNTL_BIAS_BUF_IDLE_M (BIT(10)) +#define RTC_CNTL_BIAS_BUF_IDLE_V 0x1 +#define RTC_CNTL_BIAS_BUF_IDLE_S 10 +/* RTC_CNTL_DG_VDD_DRV_B_SLP_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_DG_VDD_DRV_B_SLP_EN (BIT(8)) +#define RTC_CNTL_DG_VDD_DRV_B_SLP_EN_M (BIT(8)) +#define RTC_CNTL_DG_VDD_DRV_B_SLP_EN_V 0x1 +#define RTC_CNTL_DG_VDD_DRV_B_SLP_EN_S 8 +/* RTC_CNTL_DG_VDD_DRV_B_SLP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define RTC_CNTL_DG_VDD_DRV_B_SLP 0x000000FF +#define RTC_CNTL_DG_VDD_DRV_B_SLP_M ((RTC_CNTL_DG_VDD_DRV_B_SLP_V)<<(RTC_CNTL_DG_VDD_DRV_B_SLP_S)) +#define RTC_CNTL_DG_VDD_DRV_B_SLP_V 0xFF +#define RTC_CNTL_DG_VDD_DRV_B_SLP_S 0 + +#define RTC_CNTL_REG (DR_REG_RTCCNTL_BASE + 0x0080) +/* RTC_CNTL_REGULATOR_FORCE_PU : R/W ;bitpos:[31] ;default: 1'd1 ; */ +/*description: */ +#define RTC_CNTL_REGULATOR_FORCE_PU (BIT(31)) +#define RTC_CNTL_REGULATOR_FORCE_PU_M (BIT(31)) +#define RTC_CNTL_REGULATOR_FORCE_PU_V 0x1 +#define RTC_CNTL_REGULATOR_FORCE_PU_S 31 +/* RTC_CNTL_REGULATOR_FORCE_PD : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: RTC_REG force power down (for RTC_REG power down means decrease + the voltage to 0.8v or lower )*/ +#define RTC_CNTL_REGULATOR_FORCE_PD (BIT(30)) +#define RTC_CNTL_REGULATOR_FORCE_PD_M (BIT(30)) +#define RTC_CNTL_REGULATOR_FORCE_PD_V 0x1 +#define RTC_CNTL_REGULATOR_FORCE_PD_S 30 +/* RTC_CNTL_DBOOST_FORCE_PU : R/W ;bitpos:[29] ;default: 1'd1 ; */ +/*description: RTC_DBOOST force power up*/ +#define RTC_CNTL_DBOOST_FORCE_PU (BIT(29)) +#define RTC_CNTL_DBOOST_FORCE_PU_M (BIT(29)) +#define RTC_CNTL_DBOOST_FORCE_PU_V 0x1 +#define RTC_CNTL_DBOOST_FORCE_PU_S 29 +/* RTC_CNTL_DBOOST_FORCE_PD : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: RTC_DBOOST force power down*/ +#define RTC_CNTL_DBOOST_FORCE_PD (BIT(28)) +#define RTC_CNTL_DBOOST_FORCE_PD_M (BIT(28)) +#define RTC_CNTL_DBOOST_FORCE_PD_V 0x1 +#define RTC_CNTL_DBOOST_FORCE_PD_S 28 + +/* RTC_CNTL_SCK_DCAP : R/W ;bitpos:[21:14] ;default: 8'd0 ; */ +/*description: SCK_DCAP*/ +#define RTC_CNTL_SCK_DCAP 0x000000FF +#define RTC_CNTL_SCK_DCAP_M ((RTC_CNTL_SCK_DCAP_V)<<(RTC_CNTL_SCK_DCAP_S)) +#define RTC_CNTL_SCK_DCAP_V 0xFF +#define RTC_CNTL_SCK_DCAP_S 14 +#define RTC_CNTL_SCK_DCAP_DEFAULT 255 +/* RTC_CNTL_DIG_CAL_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_DIG_CAL_EN (BIT(7)) +#define RTC_CNTL_DIG_CAL_EN_M (BIT(7)) +#define RTC_CNTL_DIG_CAL_EN_V 0x1 +#define RTC_CNTL_DIG_CAL_EN_S 7 + +#define RTC_CNTL_PWC_REG (DR_REG_RTCCNTL_BASE + 0x0084) +/* RTC_CNTL_PAD_FORCE_HOLD : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: rtc pad force hold*/ +#define RTC_CNTL_PAD_FORCE_HOLD (BIT(21)) +#define RTC_CNTL_PAD_FORCE_HOLD_M (BIT(21)) +#define RTC_CNTL_PAD_FORCE_HOLD_V 0x1 +#define RTC_CNTL_PAD_FORCE_HOLD_S 21 + +#define RTC_CNTL_DIG_PWC_REG (DR_REG_RTCCNTL_BASE + 0x0088) +/* RTC_CNTL_DG_WRAP_PD_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_DG_WRAP_PD_EN (BIT(31)) +#define RTC_CNTL_DG_WRAP_PD_EN_M (BIT(31)) +#define RTC_CNTL_DG_WRAP_PD_EN_V 0x1 +#define RTC_CNTL_DG_WRAP_PD_EN_S 31 +/* RTC_CNTL_WIFI_PD_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: enable power down wifi in sleep*/ +#define RTC_CNTL_WIFI_PD_EN (BIT(30)) +#define RTC_CNTL_WIFI_PD_EN_M (BIT(30)) +#define RTC_CNTL_WIFI_PD_EN_V 0x1 +#define RTC_CNTL_WIFI_PD_EN_S 30 +/* RTC_CNTL_CPU_TOP_PD_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_CPU_TOP_PD_EN (BIT(29)) +#define RTC_CNTL_CPU_TOP_PD_EN_M (BIT(29)) +#define RTC_CNTL_CPU_TOP_PD_EN_V 0x1 +#define RTC_CNTL_CPU_TOP_PD_EN_S 29 +/* RTC_CNTL_DG_PERI_PD_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_DG_PERI_PD_EN (BIT(28)) +#define RTC_CNTL_DG_PERI_PD_EN_M (BIT(28)) +#define RTC_CNTL_DG_PERI_PD_EN_V 0x1 +#define RTC_CNTL_DG_PERI_PD_EN_S 28 +/* RTC_CNTL_BT_PD_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_BT_PD_EN (BIT(27)) +#define RTC_CNTL_BT_PD_EN_M (BIT(27)) +#define RTC_CNTL_BT_PD_EN_V 0x1 +#define RTC_CNTL_BT_PD_EN_S 27 +/* RTC_CNTL_CPU_TOP_FORCE_PU : R/W ;bitpos:[22] ;default: 1'b1 ; */ +/*description: */ +#define RTC_CNTL_CPU_TOP_FORCE_PU (BIT(22)) +#define RTC_CNTL_CPU_TOP_FORCE_PU_M (BIT(22)) +#define RTC_CNTL_CPU_TOP_FORCE_PU_V 0x1 +#define RTC_CNTL_CPU_TOP_FORCE_PU_S 22 +/* RTC_CNTL_CPU_TOP_FORCE_PD : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_CPU_TOP_FORCE_PD (BIT(21)) +#define RTC_CNTL_CPU_TOP_FORCE_PD_M (BIT(21)) +#define RTC_CNTL_CPU_TOP_FORCE_PD_V 0x1 +#define RTC_CNTL_CPU_TOP_FORCE_PD_S 21 +/* RTC_CNTL_DG_WRAP_FORCE_PU : R/W ;bitpos:[20] ;default: 1'd1 ; */ +/*description: digital core force power up*/ +#define RTC_CNTL_DG_WRAP_FORCE_PU (BIT(20)) +#define RTC_CNTL_DG_WRAP_FORCE_PU_M (BIT(20)) +#define RTC_CNTL_DG_WRAP_FORCE_PU_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_PU_S 20 +/* RTC_CNTL_DG_WRAP_FORCE_PD : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: digital core force power down*/ +#define RTC_CNTL_DG_WRAP_FORCE_PD (BIT(19)) +#define RTC_CNTL_DG_WRAP_FORCE_PD_M (BIT(19)) +#define RTC_CNTL_DG_WRAP_FORCE_PD_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_PD_S 19 +/* RTC_CNTL_WIFI_FORCE_PU : R/W ;bitpos:[18] ;default: 1'd1 ; */ +/*description: wifi force power up*/ +#define RTC_CNTL_WIFI_FORCE_PU (BIT(18)) +#define RTC_CNTL_WIFI_FORCE_PU_M (BIT(18)) +#define RTC_CNTL_WIFI_FORCE_PU_V 0x1 +#define RTC_CNTL_WIFI_FORCE_PU_S 18 +/* RTC_CNTL_WIFI_FORCE_PD : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: wifi force power down*/ +#define RTC_CNTL_WIFI_FORCE_PD (BIT(17)) +#define RTC_CNTL_WIFI_FORCE_PD_M (BIT(17)) +#define RTC_CNTL_WIFI_FORCE_PD_V 0x1 +#define RTC_CNTL_WIFI_FORCE_PD_S 17 +/* RTC_CNTL_FASTMEM_FORCE_LPU : R/W ;bitpos:[16] ;default: 1'b1 ; */ +/*description: */ +#define RTC_CNTL_FASTMEM_FORCE_LPU (BIT(16)) +#define RTC_CNTL_FASTMEM_FORCE_LPU_M (BIT(16)) +#define RTC_CNTL_FASTMEM_FORCE_LPU_V 0x1 +#define RTC_CNTL_FASTMEM_FORCE_LPU_S 16 +/* RTC_CNTL_FASTMEM_FORCE_LPD : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_FASTMEM_FORCE_LPD (BIT(15)) +#define RTC_CNTL_FASTMEM_FORCE_LPD_M (BIT(15)) +#define RTC_CNTL_FASTMEM_FORCE_LPD_V 0x1 +#define RTC_CNTL_FASTMEM_FORCE_LPD_S 15 +/* RTC_CNTL_DG_PERI_FORCE_PU : R/W ;bitpos:[14] ;default: 1'b1 ; */ +/*description: */ +#define RTC_CNTL_DG_PERI_FORCE_PU (BIT(14)) +#define RTC_CNTL_DG_PERI_FORCE_PU_M (BIT(14)) +#define RTC_CNTL_DG_PERI_FORCE_PU_V 0x1 +#define RTC_CNTL_DG_PERI_FORCE_PU_S 14 +/* RTC_CNTL_DG_PERI_FORCE_PD : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_DG_PERI_FORCE_PD (BIT(13)) +#define RTC_CNTL_DG_PERI_FORCE_PD_M (BIT(13)) +#define RTC_CNTL_DG_PERI_FORCE_PD_V 0x1 +#define RTC_CNTL_DG_PERI_FORCE_PD_S 13 +/* RTC_CNTL_BT_FORCE_PU : R/W ;bitpos:[12] ;default: 1'd1 ; */ +/*description: */ +#define RTC_CNTL_BT_FORCE_PU (BIT(12)) +#define RTC_CNTL_BT_FORCE_PU_M (BIT(12)) +#define RTC_CNTL_BT_FORCE_PU_V 0x1 +#define RTC_CNTL_BT_FORCE_PU_S 12 +/* RTC_CNTL_BT_FORCE_PD : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_BT_FORCE_PD (BIT(11)) +#define RTC_CNTL_BT_FORCE_PD_M (BIT(11)) +#define RTC_CNTL_BT_FORCE_PD_V 0x1 +#define RTC_CNTL_BT_FORCE_PD_S 11 +/* RTC_CNTL_LSLP_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: memories in digital core force no PD in sleep*/ +#define RTC_CNTL_LSLP_MEM_FORCE_PU (BIT(4)) +#define RTC_CNTL_LSLP_MEM_FORCE_PU_M (BIT(4)) +#define RTC_CNTL_LSLP_MEM_FORCE_PU_V 0x1 +#define RTC_CNTL_LSLP_MEM_FORCE_PU_S 4 +/* RTC_CNTL_LSLP_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: memories in digital core force PD in sleep*/ +#define RTC_CNTL_LSLP_MEM_FORCE_PD (BIT(3)) +#define RTC_CNTL_LSLP_MEM_FORCE_PD_M (BIT(3)) +#define RTC_CNTL_LSLP_MEM_FORCE_PD_V 0x1 +#define RTC_CNTL_LSLP_MEM_FORCE_PD_S 3 +/* RTC_CNTL_VDD_SPI_PWR_FORCE : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_VDD_SPI_PWR_FORCE (BIT(2)) +#define RTC_CNTL_VDD_SPI_PWR_FORCE_M (BIT(2)) +#define RTC_CNTL_VDD_SPI_PWR_FORCE_V 0x1 +#define RTC_CNTL_VDD_SPI_PWR_FORCE_S 2 +/* RTC_CNTL_VDD_SPI_PWR_DRV : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: */ +#define RTC_CNTL_VDD_SPI_PWR_DRV 0x00000003 +#define RTC_CNTL_VDD_SPI_PWR_DRV_M ((RTC_CNTL_VDD_SPI_PWR_DRV_V)<<(RTC_CNTL_VDD_SPI_PWR_DRV_S)) +#define RTC_CNTL_VDD_SPI_PWR_DRV_V 0x3 +#define RTC_CNTL_VDD_SPI_PWR_DRV_S 0 + +#define RTC_CNTL_DIG_ISO_REG (DR_REG_RTCCNTL_BASE + 0x008C) +/* RTC_CNTL_DG_WRAP_FORCE_NOISO : R/W ;bitpos:[31] ;default: 1'd1 ; */ +/*description: */ +#define RTC_CNTL_DG_WRAP_FORCE_NOISO (BIT(31)) +#define RTC_CNTL_DG_WRAP_FORCE_NOISO_M (BIT(31)) +#define RTC_CNTL_DG_WRAP_FORCE_NOISO_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_NOISO_S 31 +/* RTC_CNTL_DG_WRAP_FORCE_ISO : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: digital core force ISO*/ +#define RTC_CNTL_DG_WRAP_FORCE_ISO (BIT(30)) +#define RTC_CNTL_DG_WRAP_FORCE_ISO_M (BIT(30)) +#define RTC_CNTL_DG_WRAP_FORCE_ISO_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_ISO_S 30 +/* RTC_CNTL_WIFI_FORCE_NOISO : R/W ;bitpos:[29] ;default: 1'd1 ; */ +/*description: wifi force no ISO*/ +#define RTC_CNTL_WIFI_FORCE_NOISO (BIT(29)) +#define RTC_CNTL_WIFI_FORCE_NOISO_M (BIT(29)) +#define RTC_CNTL_WIFI_FORCE_NOISO_V 0x1 +#define RTC_CNTL_WIFI_FORCE_NOISO_S 29 +/* RTC_CNTL_WIFI_FORCE_ISO : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: wifi force ISO*/ +#define RTC_CNTL_WIFI_FORCE_ISO (BIT(28)) +#define RTC_CNTL_WIFI_FORCE_ISO_M (BIT(28)) +#define RTC_CNTL_WIFI_FORCE_ISO_V 0x1 +#define RTC_CNTL_WIFI_FORCE_ISO_S 28 +/* RTC_CNTL_CPU_TOP_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */ +/*description: cpu force no ISO*/ +#define RTC_CNTL_CPU_TOP_FORCE_NOISO (BIT(27)) +#define RTC_CNTL_CPU_TOP_FORCE_NOISO_M (BIT(27)) +#define RTC_CNTL_CPU_TOP_FORCE_NOISO_V 0x1 +#define RTC_CNTL_CPU_TOP_FORCE_NOISO_S 27 +/* RTC_CNTL_CPU_TOP_FORCE_ISO : R/W ;bitpos:[26] ;default: 1'd0 ; */ +/*description: cpu force ISO*/ +#define RTC_CNTL_CPU_TOP_FORCE_ISO (BIT(26)) +#define RTC_CNTL_CPU_TOP_FORCE_ISO_M (BIT(26)) +#define RTC_CNTL_CPU_TOP_FORCE_ISO_V 0x1 +#define RTC_CNTL_CPU_TOP_FORCE_ISO_S 26 +/* RTC_CNTL_DG_PERI_FORCE_NOISO : R/W ;bitpos:[25] ;default: 1'd1 ; */ +/*description: */ +#define RTC_CNTL_DG_PERI_FORCE_NOISO (BIT(25)) +#define RTC_CNTL_DG_PERI_FORCE_NOISO_M (BIT(25)) +#define RTC_CNTL_DG_PERI_FORCE_NOISO_V 0x1 +#define RTC_CNTL_DG_PERI_FORCE_NOISO_S 25 +/* RTC_CNTL_DG_PERI_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_DG_PERI_FORCE_ISO (BIT(24)) +#define RTC_CNTL_DG_PERI_FORCE_ISO_M (BIT(24)) +#define RTC_CNTL_DG_PERI_FORCE_ISO_V 0x1 +#define RTC_CNTL_DG_PERI_FORCE_ISO_S 24 +/* RTC_CNTL_BT_FORCE_NOISO : R/W ;bitpos:[23] ;default: 1'd1 ; */ +/*description: */ +#define RTC_CNTL_BT_FORCE_NOISO (BIT(23)) +#define RTC_CNTL_BT_FORCE_NOISO_M (BIT(23)) +#define RTC_CNTL_BT_FORCE_NOISO_V 0x1 +#define RTC_CNTL_BT_FORCE_NOISO_S 23 +/* RTC_CNTL_BT_FORCE_ISO : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_BT_FORCE_ISO (BIT(22)) +#define RTC_CNTL_BT_FORCE_ISO_M (BIT(22)) +#define RTC_CNTL_BT_FORCE_ISO_V 0x1 +#define RTC_CNTL_BT_FORCE_ISO_S 22 +/* RTC_CNTL_DG_PAD_FORCE_HOLD : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: digital pad force hold*/ +#define RTC_CNTL_DG_PAD_FORCE_HOLD (BIT(15)) +#define RTC_CNTL_DG_PAD_FORCE_HOLD_M (BIT(15)) +#define RTC_CNTL_DG_PAD_FORCE_HOLD_V 0x1 +#define RTC_CNTL_DG_PAD_FORCE_HOLD_S 15 +/* RTC_CNTL_DG_PAD_FORCE_UNHOLD : R/W ;bitpos:[14] ;default: 1'd1 ; */ +/*description: digital pad force un-hold*/ +#define RTC_CNTL_DG_PAD_FORCE_UNHOLD (BIT(14)) +#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_M (BIT(14)) +#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_V 0x1 +#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_S 14 +/* RTC_CNTL_DG_PAD_FORCE_ISO : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: digital pad force ISO*/ +#define RTC_CNTL_DG_PAD_FORCE_ISO (BIT(13)) +#define RTC_CNTL_DG_PAD_FORCE_ISO_M (BIT(13)) +#define RTC_CNTL_DG_PAD_FORCE_ISO_V 0x1 +#define RTC_CNTL_DG_PAD_FORCE_ISO_S 13 +/* RTC_CNTL_DG_PAD_FORCE_NOISO : R/W ;bitpos:[12] ;default: 1'd1 ; */ +/*description: digital pad force no ISO*/ +#define RTC_CNTL_DG_PAD_FORCE_NOISO (BIT(12)) +#define RTC_CNTL_DG_PAD_FORCE_NOISO_M (BIT(12)) +#define RTC_CNTL_DG_PAD_FORCE_NOISO_V 0x1 +#define RTC_CNTL_DG_PAD_FORCE_NOISO_S 12 +/* RTC_CNTL_DG_PAD_AUTOHOLD_EN : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: digital pad enable auto-hold*/ +#define RTC_CNTL_DG_PAD_AUTOHOLD_EN (BIT(11)) +#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_M (BIT(11)) +#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_V 0x1 +#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_S 11 +/* RTC_CNTL_CLR_DG_PAD_AUTOHOLD : WO ;bitpos:[10] ;default: 1'd0 ; */ +/*description: wtite only register to clear digital pad auto-hold*/ +#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD (BIT(10)) +#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_M (BIT(10)) +#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_V 0x1 +#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_S 10 +/* RTC_CNTL_DG_PAD_AUTOHOLD : RO ;bitpos:[9] ;default: 1'd0 ; */ +/*description: read only register to indicate digital pad auto-hold status*/ +#define RTC_CNTL_DG_PAD_AUTOHOLD (BIT(9)) +#define RTC_CNTL_DG_PAD_AUTOHOLD_M (BIT(9)) +#define RTC_CNTL_DG_PAD_AUTOHOLD_V 0x1 +#define RTC_CNTL_DG_PAD_AUTOHOLD_S 9 +/* RTC_CNTL_DIG_ISO_FORCE_ON : R/W ;bitpos:[8] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_DIG_ISO_FORCE_ON (BIT(8)) +#define RTC_CNTL_DIG_ISO_FORCE_ON_M (BIT(8)) +#define RTC_CNTL_DIG_ISO_FORCE_ON_V 0x1 +#define RTC_CNTL_DIG_ISO_FORCE_ON_S 8 +/* RTC_CNTL_DIG_ISO_FORCE_OFF : R/W ;bitpos:[7] ;default: 1'd1 ; */ +/*description: */ +#define RTC_CNTL_DIG_ISO_FORCE_OFF (BIT(7)) +#define RTC_CNTL_DIG_ISO_FORCE_OFF_M (BIT(7)) +#define RTC_CNTL_DIG_ISO_FORCE_OFF_V 0x1 +#define RTC_CNTL_DIG_ISO_FORCE_OFF_S 7 + +#define RTC_CNTL_WDTCONFIG0_REG (DR_REG_RTCCNTL_BASE + 0x0090) +/* RTC_CNTL_WDT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: */ +#define RTC_CNTL_WDT_EN (BIT(31)) +#define RTC_CNTL_WDT_EN_M (BIT(31)) +#define RTC_CNTL_WDT_EN_V 0x1 +#define RTC_CNTL_WDT_EN_S 31 +/* RTC_CNTL_WDT_STG0 : R/W ;bitpos:[30:28] ;default: 3'h0 ; */ +/*description: 1: interrupt stage en*/ +#define RTC_CNTL_WDT_STG0 0x00000007 +#define RTC_CNTL_WDT_STG0_M ((RTC_CNTL_WDT_STG0_V)<<(RTC_CNTL_WDT_STG0_S)) +#define RTC_CNTL_WDT_STG0_V 0x7 +#define RTC_CNTL_WDT_STG0_S 28 +/* RTC_CNTL_WDT_STG1 : R/W ;bitpos:[27:25] ;default: 3'h0 ; */ +/*description: 1: interrupt stage en*/ +#define RTC_CNTL_WDT_STG1 0x00000007 +#define RTC_CNTL_WDT_STG1_M ((RTC_CNTL_WDT_STG1_V)<<(RTC_CNTL_WDT_STG1_S)) +#define RTC_CNTL_WDT_STG1_V 0x7 +#define RTC_CNTL_WDT_STG1_S 25 +/* RTC_CNTL_WDT_STG2 : R/W ;bitpos:[24:22] ;default: 3'h0 ; */ +/*description: 1: interrupt stage en*/ +#define RTC_CNTL_WDT_STG2 0x00000007 +#define RTC_CNTL_WDT_STG2_M ((RTC_CNTL_WDT_STG2_V)<<(RTC_CNTL_WDT_STG2_S)) +#define RTC_CNTL_WDT_STG2_V 0x7 +#define RTC_CNTL_WDT_STG2_S 22 +/* RTC_CNTL_WDT_STG3 : R/W ;bitpos:[21:19] ;default: 3'h0 ; */ +/*description: 1: interrupt stage en*/ +#define RTC_CNTL_WDT_STG3 0x00000007 +#define RTC_CNTL_WDT_STG3_M ((RTC_CNTL_WDT_STG3_V)<<(RTC_CNTL_WDT_STG3_S)) +#define RTC_CNTL_WDT_STG3_V 0x7 +#define RTC_CNTL_WDT_STG3_S 19 +/* RTC_CNTL_WDT_STGX : */ +/*description: stage action selection values */ +#define RTC_WDT_STG_SEL_OFF 0 +#define RTC_WDT_STG_SEL_INT 1 +#define RTC_WDT_STG_SEL_RESET_CPU 2 +#define RTC_WDT_STG_SEL_RESET_SYSTEM 3 +#define RTC_WDT_STG_SEL_RESET_RTC 4 + +/* RTC_CNTL_WDT_CPU_RESET_LENGTH : R/W ;bitpos:[18:16] ;default: 3'h1 ; */ +/*description: CPU reset counter length*/ +#define RTC_CNTL_WDT_CPU_RESET_LENGTH 0x00000007 +#define RTC_CNTL_WDT_CPU_RESET_LENGTH_M ((RTC_CNTL_WDT_CPU_RESET_LENGTH_V)<<(RTC_CNTL_WDT_CPU_RESET_LENGTH_S)) +#define RTC_CNTL_WDT_CPU_RESET_LENGTH_V 0x7 +#define RTC_CNTL_WDT_CPU_RESET_LENGTH_S 16 +/* RTC_CNTL_WDT_SYS_RESET_LENGTH : R/W ;bitpos:[15:13] ;default: 3'h1 ; */ +/*description: system reset counter length*/ +#define RTC_CNTL_WDT_SYS_RESET_LENGTH 0x00000007 +#define RTC_CNTL_WDT_SYS_RESET_LENGTH_M ((RTC_CNTL_WDT_SYS_RESET_LENGTH_V)<<(RTC_CNTL_WDT_SYS_RESET_LENGTH_S)) +#define RTC_CNTL_WDT_SYS_RESET_LENGTH_V 0x7 +#define RTC_CNTL_WDT_SYS_RESET_LENGTH_S 13 +/* RTC_CNTL_WDT_FLASHBOOT_MOD_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */ +/*description: enable WDT in flash boot*/ +#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN (BIT(12)) +#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_M (BIT(12)) +#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_V 0x1 +#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_S 12 +/* RTC_CNTL_WDT_PROCPU_RESET_EN : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: enable WDT reset PRO CPU*/ +#define RTC_CNTL_WDT_PROCPU_RESET_EN (BIT(11)) +#define RTC_CNTL_WDT_PROCPU_RESET_EN_M (BIT(11)) +#define RTC_CNTL_WDT_PROCPU_RESET_EN_V 0x1 +#define RTC_CNTL_WDT_PROCPU_RESET_EN_S 11 +/* RTC_CNTL_WDT_APPCPU_RESET_EN : R/W ;bitpos:[10] ;default: 1'd0 ; */ +/*description: enable WDT reset APP CPU*/ +#define RTC_CNTL_WDT_APPCPU_RESET_EN (BIT(10)) +#define RTC_CNTL_WDT_APPCPU_RESET_EN_M (BIT(10)) +#define RTC_CNTL_WDT_APPCPU_RESET_EN_V 0x1 +#define RTC_CNTL_WDT_APPCPU_RESET_EN_S 10 +/* RTC_CNTL_WDT_PAUSE_IN_SLP : R/W ;bitpos:[9] ;default: 1'd1 ; */ +/*description: pause WDT in sleep*/ +#define RTC_CNTL_WDT_PAUSE_IN_SLP (BIT(9)) +#define RTC_CNTL_WDT_PAUSE_IN_SLP_M (BIT(9)) +#define RTC_CNTL_WDT_PAUSE_IN_SLP_V 0x1 +#define RTC_CNTL_WDT_PAUSE_IN_SLP_S 9 +/* RTC_CNTL_WDT_CHIP_RESET_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: wdt reset whole chip enable*/ +#define RTC_CNTL_WDT_CHIP_RESET_EN (BIT(8)) +#define RTC_CNTL_WDT_CHIP_RESET_EN_M (BIT(8)) +#define RTC_CNTL_WDT_CHIP_RESET_EN_V 0x1 +#define RTC_CNTL_WDT_CHIP_RESET_EN_S 8 +/* RTC_CNTL_WDT_CHIP_RESET_WIDTH : R/W ;bitpos:[7:0] ;default: 8'd20 ; */ +/*description: chip reset siginal pulse width*/ +#define RTC_CNTL_WDT_CHIP_RESET_WIDTH 0x000000FF +#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_M ((RTC_CNTL_WDT_CHIP_RESET_WIDTH_V)<<(RTC_CNTL_WDT_CHIP_RESET_WIDTH_S)) +#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_V 0xFF +#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_S 0 + +#define RTC_CNTL_WDTCONFIG1_REG (DR_REG_RTCCNTL_BASE + 0x0094) +/* RTC_CNTL_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd200000 ; */ +/*description: */ +#define RTC_CNTL_WDT_STG0_HOLD 0xFFFFFFFF +#define RTC_CNTL_WDT_STG0_HOLD_M ((RTC_CNTL_WDT_STG0_HOLD_V)<<(RTC_CNTL_WDT_STG0_HOLD_S)) +#define RTC_CNTL_WDT_STG0_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_WDT_STG0_HOLD_S 0 + +#define RTC_CNTL_WDTCONFIG2_REG (DR_REG_RTCCNTL_BASE + 0x0098) +/* RTC_CNTL_WDT_STG1_HOLD : R/W ;bitpos:[31:0] ;default: 32'd80000 ; */ +/*description: */ +#define RTC_CNTL_WDT_STG1_HOLD 0xFFFFFFFF +#define RTC_CNTL_WDT_STG1_HOLD_M ((RTC_CNTL_WDT_STG1_HOLD_V)<<(RTC_CNTL_WDT_STG1_HOLD_S)) +#define RTC_CNTL_WDT_STG1_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_WDT_STG1_HOLD_S 0 + +#define RTC_CNTL_WDTCONFIG3_REG (DR_REG_RTCCNTL_BASE + 0x009C) +/* RTC_CNTL_WDT_STG2_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */ +/*description: */ +#define RTC_CNTL_WDT_STG2_HOLD 0xFFFFFFFF +#define RTC_CNTL_WDT_STG2_HOLD_M ((RTC_CNTL_WDT_STG2_HOLD_V)<<(RTC_CNTL_WDT_STG2_HOLD_S)) +#define RTC_CNTL_WDT_STG2_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_WDT_STG2_HOLD_S 0 + +#define RTC_CNTL_WDTCONFIG4_REG (DR_REG_RTCCNTL_BASE + 0x00A0) +/* RTC_CNTL_WDT_STG3_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */ +/*description: */ +#define RTC_CNTL_WDT_STG3_HOLD 0xFFFFFFFF +#define RTC_CNTL_WDT_STG3_HOLD_M ((RTC_CNTL_WDT_STG3_HOLD_V)<<(RTC_CNTL_WDT_STG3_HOLD_S)) +#define RTC_CNTL_WDT_STG3_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_WDT_STG3_HOLD_S 0 + +#define RTC_CNTL_WDTFEED_REG (DR_REG_RTCCNTL_BASE + 0x00A4) +/* RTC_CNTL_WDT_FEED : WO ;bitpos:[31] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_WDT_FEED (BIT(31)) +#define RTC_CNTL_WDT_FEED_M (BIT(31)) +#define RTC_CNTL_WDT_FEED_V 0x1 +#define RTC_CNTL_WDT_FEED_S 31 + +#define RTC_CNTL_WDTWPROTECT_REG (DR_REG_RTCCNTL_BASE + 0x00A8) +/* RTC_CNTL_WDT_WKEY : R/W ;bitpos:[31:0] ;default: 32'h50d83aa1 ; */ +/*description: */ +#define RTC_CNTL_WDT_WKEY 0xFFFFFFFF +#define RTC_CNTL_WDT_WKEY_M ((RTC_CNTL_WDT_WKEY_V)<<(RTC_CNTL_WDT_WKEY_S)) +#define RTC_CNTL_WDT_WKEY_V 0xFFFFFFFF +#define RTC_CNTL_WDT_WKEY_S 0 + +#define RTC_CNTL_SWD_CONF_REG (DR_REG_RTCCNTL_BASE + 0x00AC) +/* RTC_CNTL_SWD_AUTO_FEED_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: automatically feed swd when int comes*/ +#define RTC_CNTL_SWD_AUTO_FEED_EN (BIT(31)) +#define RTC_CNTL_SWD_AUTO_FEED_EN_M (BIT(31)) +#define RTC_CNTL_SWD_AUTO_FEED_EN_V 0x1 +#define RTC_CNTL_SWD_AUTO_FEED_EN_S 31 +/* RTC_CNTL_SWD_DISABLE : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: disable SWD*/ +#define RTC_CNTL_SWD_DISABLE (BIT(30)) +#define RTC_CNTL_SWD_DISABLE_M (BIT(30)) +#define RTC_CNTL_SWD_DISABLE_V 0x1 +#define RTC_CNTL_SWD_DISABLE_S 30 +/* RTC_CNTL_SWD_FEED : WO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: Sw feed swd*/ +#define RTC_CNTL_SWD_FEED (BIT(29)) +#define RTC_CNTL_SWD_FEED_M (BIT(29)) +#define RTC_CNTL_SWD_FEED_V 0x1 +#define RTC_CNTL_SWD_FEED_S 29 +/* RTC_CNTL_SWD_RST_FLAG_CLR : WO ;bitpos:[28] ;default: 1'b0 ; */ +/*description: reset swd reset flag*/ +#define RTC_CNTL_SWD_RST_FLAG_CLR (BIT(28)) +#define RTC_CNTL_SWD_RST_FLAG_CLR_M (BIT(28)) +#define RTC_CNTL_SWD_RST_FLAG_CLR_V 0x1 +#define RTC_CNTL_SWD_RST_FLAG_CLR_S 28 +/* RTC_CNTL_SWD_SIGNAL_WIDTH : R/W ;bitpos:[27:18] ;default: 10'd300 ; */ +/*description: adjust signal width send to swd*/ +#define RTC_CNTL_SWD_SIGNAL_WIDTH 0x000003FF +#define RTC_CNTL_SWD_SIGNAL_WIDTH_M ((RTC_CNTL_SWD_SIGNAL_WIDTH_V)<<(RTC_CNTL_SWD_SIGNAL_WIDTH_S)) +#define RTC_CNTL_SWD_SIGNAL_WIDTH_V 0x3FF +#define RTC_CNTL_SWD_SIGNAL_WIDTH_S 18 +/* RTC_CNTL_SWD_BYPASS_RST : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_SWD_BYPASS_RST (BIT(17)) +#define RTC_CNTL_SWD_BYPASS_RST_M (BIT(17)) +#define RTC_CNTL_SWD_BYPASS_RST_V 0x1 +#define RTC_CNTL_SWD_BYPASS_RST_S 17 +/* RTC_CNTL_SWD_FEED_INT : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: swd interrupt for feeding*/ +#define RTC_CNTL_SWD_FEED_INT (BIT(1)) +#define RTC_CNTL_SWD_FEED_INT_M (BIT(1)) +#define RTC_CNTL_SWD_FEED_INT_V 0x1 +#define RTC_CNTL_SWD_FEED_INT_S 1 +/* RTC_CNTL_SWD_RESET_FLAG : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: swd reset flag*/ +#define RTC_CNTL_SWD_RESET_FLAG (BIT(0)) +#define RTC_CNTL_SWD_RESET_FLAG_M (BIT(0)) +#define RTC_CNTL_SWD_RESET_FLAG_V 0x1 +#define RTC_CNTL_SWD_RESET_FLAG_S 0 + +#define RTC_CNTL_SWD_WPROTECT_REG (DR_REG_RTCCNTL_BASE + 0x00B0) +/* RTC_CNTL_SWD_WKEY : R/W ;bitpos:[31:0] ;default: 32'h8f1d312a ; */ +/*description: */ +#define RTC_CNTL_SWD_WKEY 0xFFFFFFFF +#define RTC_CNTL_SWD_WKEY_M ((RTC_CNTL_SWD_WKEY_V)<<(RTC_CNTL_SWD_WKEY_S)) +#define RTC_CNTL_SWD_WKEY_V 0xFFFFFFFF +#define RTC_CNTL_SWD_WKEY_S 0 + +#define RTC_CNTL_SW_CPU_STALL_REG (DR_REG_RTCCNTL_BASE + 0x00B4) +/* RTC_CNTL_SW_STALL_PROCPU_C1 : R/W ;bitpos:[31:26] ;default: 6'b0 ; */ +/*description: */ +#define RTC_CNTL_SW_STALL_PROCPU_C1 0x0000003F +#define RTC_CNTL_SW_STALL_PROCPU_C1_M ((RTC_CNTL_SW_STALL_PROCPU_C1_V)<<(RTC_CNTL_SW_STALL_PROCPU_C1_S)) +#define RTC_CNTL_SW_STALL_PROCPU_C1_V 0x3F +#define RTC_CNTL_SW_STALL_PROCPU_C1_S 26 +/* RTC_CNTL_SW_STALL_APPCPU_C1 : R/W ;bitpos:[25:20] ;default: 6'b0 ; */ +/*description: {reg_sw_stall_appcpu_c1[5:0]*/ +#define RTC_CNTL_SW_STALL_APPCPU_C1 0x0000003F +#define RTC_CNTL_SW_STALL_APPCPU_C1_M ((RTC_CNTL_SW_STALL_APPCPU_C1_V)<<(RTC_CNTL_SW_STALL_APPCPU_C1_S)) +#define RTC_CNTL_SW_STALL_APPCPU_C1_V 0x3F +#define RTC_CNTL_SW_STALL_APPCPU_C1_S 20 + +#define RTC_CNTL_STORE4_REG (DR_REG_RTCCNTL_BASE + 0x00B8) +/* RTC_CNTL_SCRATCH4 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: */ +#define RTC_CNTL_SCRATCH4 0xFFFFFFFF +#define RTC_CNTL_SCRATCH4_M ((RTC_CNTL_SCRATCH4_V)<<(RTC_CNTL_SCRATCH4_S)) +#define RTC_CNTL_SCRATCH4_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH4_S 0 + +#define RTC_CNTL_STORE5_REG (DR_REG_RTCCNTL_BASE + 0x00BC) +/* RTC_CNTL_SCRATCH5 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: */ +#define RTC_CNTL_SCRATCH5 0xFFFFFFFF +#define RTC_CNTL_SCRATCH5_M ((RTC_CNTL_SCRATCH5_V)<<(RTC_CNTL_SCRATCH5_S)) +#define RTC_CNTL_SCRATCH5_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH5_S 0 + +#define RTC_CNTL_STORE6_REG (DR_REG_RTCCNTL_BASE + 0x00C0) +/* RTC_CNTL_SCRATCH6 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: */ +#define RTC_CNTL_SCRATCH6 0xFFFFFFFF +#define RTC_CNTL_SCRATCH6_M ((RTC_CNTL_SCRATCH6_V)<<(RTC_CNTL_SCRATCH6_S)) +#define RTC_CNTL_SCRATCH6_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH6_S 0 + +#define RTC_CNTL_STORE7_REG (DR_REG_RTCCNTL_BASE + 0x00C4) +/* RTC_CNTL_SCRATCH7 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: */ +#define RTC_CNTL_SCRATCH7 0xFFFFFFFF +#define RTC_CNTL_SCRATCH7_M ((RTC_CNTL_SCRATCH7_V)<<(RTC_CNTL_SCRATCH7_S)) +#define RTC_CNTL_SCRATCH7_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH7_S 0 + +#define RTC_CNTL_LOW_POWER_ST_REG (DR_REG_RTCCNTL_BASE + 0x00C8) +/* RTC_CNTL_MAIN_STATE : RO ;bitpos:[31:28] ;default: 4'd0 ; */ +/*description: rtc main state machine status*/ +#define RTC_CNTL_MAIN_STATE 0x0000000F +#define RTC_CNTL_MAIN_STATE_M ((RTC_CNTL_MAIN_STATE_V)<<(RTC_CNTL_MAIN_STATE_S)) +#define RTC_CNTL_MAIN_STATE_V 0xF +#define RTC_CNTL_MAIN_STATE_S 28 +/* RTC_CNTL_MAIN_STATE_IN_IDLE : RO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: rtc main state machine is in idle state*/ +#define RTC_CNTL_MAIN_STATE_IN_IDLE (BIT(27)) +#define RTC_CNTL_MAIN_STATE_IN_IDLE_M (BIT(27)) +#define RTC_CNTL_MAIN_STATE_IN_IDLE_V 0x1 +#define RTC_CNTL_MAIN_STATE_IN_IDLE_S 27 +/* RTC_CNTL_MAIN_STATE_IN_SLP : RO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: rtc main state machine is in sleep state*/ +#define RTC_CNTL_MAIN_STATE_IN_SLP (BIT(26)) +#define RTC_CNTL_MAIN_STATE_IN_SLP_M (BIT(26)) +#define RTC_CNTL_MAIN_STATE_IN_SLP_V 0x1 +#define RTC_CNTL_MAIN_STATE_IN_SLP_S 26 +/* RTC_CNTL_MAIN_STATE_IN_WAIT_XTL : RO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: rtc main state machine is in wait xtal state*/ +#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL (BIT(25)) +#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_M (BIT(25)) +#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_V 0x1 +#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_S 25 +/* RTC_CNTL_MAIN_STATE_IN_WAIT_PLL : RO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: rtc main state machine is in wait pll state*/ +#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL (BIT(24)) +#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_M (BIT(24)) +#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_V 0x1 +#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_S 24 +/* RTC_CNTL_MAIN_STATE_IN_WAIT_8M : RO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: rtc main state machine is in wait 8m state*/ +#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M (BIT(23)) +#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_M (BIT(23)) +#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_V 0x1 +#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_S 23 +/* RTC_CNTL_IN_LOW_POWER_STATE : RO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: rtc main state machine is in the states of low power*/ +#define RTC_CNTL_IN_LOW_POWER_STATE (BIT(22)) +#define RTC_CNTL_IN_LOW_POWER_STATE_M (BIT(22)) +#define RTC_CNTL_IN_LOW_POWER_STATE_V 0x1 +#define RTC_CNTL_IN_LOW_POWER_STATE_S 22 +/* RTC_CNTL_IN_WAKEUP_STATE : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: rtc main state machine is in the states of wakeup process*/ +#define RTC_CNTL_IN_WAKEUP_STATE (BIT(21)) +#define RTC_CNTL_IN_WAKEUP_STATE_M (BIT(21)) +#define RTC_CNTL_IN_WAKEUP_STATE_V 0x1 +#define RTC_CNTL_IN_WAKEUP_STATE_S 21 +/* RTC_CNTL_MAIN_STATE_WAIT_END : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: rtc main state machine has been waited for some cycles*/ +#define RTC_CNTL_MAIN_STATE_WAIT_END (BIT(20)) +#define RTC_CNTL_MAIN_STATE_WAIT_END_M (BIT(20)) +#define RTC_CNTL_MAIN_STATE_WAIT_END_V 0x1 +#define RTC_CNTL_MAIN_STATE_WAIT_END_S 20 +/* RTC_CNTL_RDY_FOR_WAKEUP : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: rtc is ready to receive wake up trigger from wake up source*/ +#define RTC_CNTL_RDY_FOR_WAKEUP (BIT(19)) +#define RTC_CNTL_RDY_FOR_WAKEUP_M (BIT(19)) +#define RTC_CNTL_RDY_FOR_WAKEUP_V 0x1 +#define RTC_CNTL_RDY_FOR_WAKEUP_S 19 +/* RTC_CNTL_MAIN_STATE_PLL_ON : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: rtc main state machine is in states that pll should be running*/ +#define RTC_CNTL_MAIN_STATE_PLL_ON (BIT(18)) +#define RTC_CNTL_MAIN_STATE_PLL_ON_M (BIT(18)) +#define RTC_CNTL_MAIN_STATE_PLL_ON_V 0x1 +#define RTC_CNTL_MAIN_STATE_PLL_ON_S 18 +/* RTC_CNTL_MAIN_STATE_XTAL_ISO : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: no use any more*/ +#define RTC_CNTL_MAIN_STATE_XTAL_ISO (BIT(17)) +#define RTC_CNTL_MAIN_STATE_XTAL_ISO_M (BIT(17)) +#define RTC_CNTL_MAIN_STATE_XTAL_ISO_V 0x1 +#define RTC_CNTL_MAIN_STATE_XTAL_ISO_S 17 +/* RTC_CNTL_COCPU_STATE_DONE : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: ulp/cocpu is done*/ +#define RTC_CNTL_COCPU_STATE_DONE (BIT(16)) +#define RTC_CNTL_COCPU_STATE_DONE_M (BIT(16)) +#define RTC_CNTL_COCPU_STATE_DONE_V 0x1 +#define RTC_CNTL_COCPU_STATE_DONE_S 16 +/* RTC_CNTL_COCPU_STATE_SLP : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: ulp/cocpu is in sleep state*/ +#define RTC_CNTL_COCPU_STATE_SLP (BIT(15)) +#define RTC_CNTL_COCPU_STATE_SLP_M (BIT(15)) +#define RTC_CNTL_COCPU_STATE_SLP_V 0x1 +#define RTC_CNTL_COCPU_STATE_SLP_S 15 +/* RTC_CNTL_COCPU_STATE_SWITCH : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: ulp/cocpu is about to working. Switch rtc main state*/ +#define RTC_CNTL_COCPU_STATE_SWITCH (BIT(14)) +#define RTC_CNTL_COCPU_STATE_SWITCH_M (BIT(14)) +#define RTC_CNTL_COCPU_STATE_SWITCH_V 0x1 +#define RTC_CNTL_COCPU_STATE_SWITCH_S 14 +/* RTC_CNTL_COCPU_STATE_START : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: ulp/cocpu should start to work*/ +#define RTC_CNTL_COCPU_STATE_START (BIT(13)) +#define RTC_CNTL_COCPU_STATE_START_M (BIT(13)) +#define RTC_CNTL_COCPU_STATE_START_V 0x1 +#define RTC_CNTL_COCPU_STATE_START_S 13 +/* RTC_CNTL_TOUCH_STATE_DONE : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: touch is done*/ +#define RTC_CNTL_TOUCH_STATE_DONE (BIT(12)) +#define RTC_CNTL_TOUCH_STATE_DONE_M (BIT(12)) +#define RTC_CNTL_TOUCH_STATE_DONE_V 0x1 +#define RTC_CNTL_TOUCH_STATE_DONE_S 12 +/* RTC_CNTL_TOUCH_STATE_SLP : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: touch is in sleep state*/ +#define RTC_CNTL_TOUCH_STATE_SLP (BIT(11)) +#define RTC_CNTL_TOUCH_STATE_SLP_M (BIT(11)) +#define RTC_CNTL_TOUCH_STATE_SLP_V 0x1 +#define RTC_CNTL_TOUCH_STATE_SLP_S 11 +/* RTC_CNTL_TOUCH_STATE_SWITCH : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: touch is about to working. Switch rtc main state*/ +#define RTC_CNTL_TOUCH_STATE_SWITCH (BIT(10)) +#define RTC_CNTL_TOUCH_STATE_SWITCH_M (BIT(10)) +#define RTC_CNTL_TOUCH_STATE_SWITCH_V 0x1 +#define RTC_CNTL_TOUCH_STATE_SWITCH_S 10 +/* RTC_CNTL_TOUCH_STATE_START : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: touch should start to work*/ +#define RTC_CNTL_TOUCH_STATE_START (BIT(9)) +#define RTC_CNTL_TOUCH_STATE_START_M (BIT(9)) +#define RTC_CNTL_TOUCH_STATE_START_V 0x1 +#define RTC_CNTL_TOUCH_STATE_START_S 9 +/* RTC_CNTL_XPD_DIG : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: digital wrap power down*/ +#define RTC_CNTL_XPD_DIG (BIT(8)) +#define RTC_CNTL_XPD_DIG_M (BIT(8)) +#define RTC_CNTL_XPD_DIG_V 0x1 +#define RTC_CNTL_XPD_DIG_S 8 +/* RTC_CNTL_DIG_ISO : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: digital wrap iso*/ +#define RTC_CNTL_DIG_ISO (BIT(7)) +#define RTC_CNTL_DIG_ISO_M (BIT(7)) +#define RTC_CNTL_DIG_ISO_V 0x1 +#define RTC_CNTL_DIG_ISO_S 7 +/* RTC_CNTL_XPD_WIFI : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: wifi wrap power down*/ +#define RTC_CNTL_XPD_WIFI (BIT(6)) +#define RTC_CNTL_XPD_WIFI_M (BIT(6)) +#define RTC_CNTL_XPD_WIFI_V 0x1 +#define RTC_CNTL_XPD_WIFI_S 6 +/* RTC_CNTL_WIFI_ISO : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: wifi iso*/ +#define RTC_CNTL_WIFI_ISO (BIT(5)) +#define RTC_CNTL_WIFI_ISO_M (BIT(5)) +#define RTC_CNTL_WIFI_ISO_V 0x1 +#define RTC_CNTL_WIFI_ISO_S 5 +/* RTC_CNTL_XPD_RTC_PERI : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: rtc peripheral power down*/ +#define RTC_CNTL_XPD_RTC_PERI (BIT(4)) +#define RTC_CNTL_XPD_RTC_PERI_M (BIT(4)) +#define RTC_CNTL_XPD_RTC_PERI_V 0x1 +#define RTC_CNTL_XPD_RTC_PERI_S 4 +/* RTC_CNTL_PERI_ISO : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: rtc peripheral iso*/ +#define RTC_CNTL_PERI_ISO (BIT(3)) +#define RTC_CNTL_PERI_ISO_M (BIT(3)) +#define RTC_CNTL_PERI_ISO_V 0x1 +#define RTC_CNTL_PERI_ISO_S 3 +/* RTC_CNTL_XPD_DIG_DCDC : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: External DCDC power down*/ +#define RTC_CNTL_XPD_DIG_DCDC (BIT(2)) +#define RTC_CNTL_XPD_DIG_DCDC_M (BIT(2)) +#define RTC_CNTL_XPD_DIG_DCDC_V 0x1 +#define RTC_CNTL_XPD_DIG_DCDC_S 2 +/* RTC_CNTL_XPD_ROM0 : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: rom0 power down*/ +#define RTC_CNTL_XPD_ROM0 (BIT(0)) +#define RTC_CNTL_XPD_ROM0_M (BIT(0)) +#define RTC_CNTL_XPD_ROM0_V 0x1 +#define RTC_CNTL_XPD_ROM0_S 0 + +#define RTC_CNTL_DIAG0_REG (DR_REG_RTCCNTL_BASE + 0x00CC) +/* RTC_CNTL_LOW_POWER_DIAG1 : RO ;bitpos:[31:0] ;default: 0 ; */ +/*description: */ +#define RTC_CNTL_LOW_POWER_DIAG1 0xFFFFFFFF +#define RTC_CNTL_LOW_POWER_DIAG1_M ((RTC_CNTL_LOW_POWER_DIAG1_V)<<(RTC_CNTL_LOW_POWER_DIAG1_S)) +#define RTC_CNTL_LOW_POWER_DIAG1_V 0xFFFFFFFF +#define RTC_CNTL_LOW_POWER_DIAG1_S 0 + +#define RTC_CNTL_PAD_HOLD_REG (DR_REG_RTCCNTL_BASE + 0x00D0) +/* RTC_CNTL_GPIO_PIN5_HOLD : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_PIN5_HOLD (BIT(5)) +#define RTC_CNTL_GPIO_PIN5_HOLD_M (BIT(5)) +#define RTC_CNTL_GPIO_PIN5_HOLD_V 0x1 +#define RTC_CNTL_GPIO_PIN5_HOLD_S 5 +/* RTC_CNTL_GPIO_PIN4_HOLD : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_PIN4_HOLD (BIT(4)) +#define RTC_CNTL_GPIO_PIN4_HOLD_M (BIT(4)) +#define RTC_CNTL_GPIO_PIN4_HOLD_V 0x1 +#define RTC_CNTL_GPIO_PIN4_HOLD_S 4 +/* RTC_CNTL_GPIO_PIN3_HOLD : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_PIN3_HOLD (BIT(3)) +#define RTC_CNTL_GPIO_PIN3_HOLD_M (BIT(3)) +#define RTC_CNTL_GPIO_PIN3_HOLD_V 0x1 +#define RTC_CNTL_GPIO_PIN3_HOLD_S 3 +/* RTC_CNTL_GPIO_PIN2_HOLD : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_PIN2_HOLD (BIT(2)) +#define RTC_CNTL_GPIO_PIN2_HOLD_M (BIT(2)) +#define RTC_CNTL_GPIO_PIN2_HOLD_V 0x1 +#define RTC_CNTL_GPIO_PIN2_HOLD_S 2 +/* RTC_CNTL_GPIO_PIN1_HOLD : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_PIN1_HOLD (BIT(1)) +#define RTC_CNTL_GPIO_PIN1_HOLD_M (BIT(1)) +#define RTC_CNTL_GPIO_PIN1_HOLD_V 0x1 +#define RTC_CNTL_GPIO_PIN1_HOLD_S 1 +/* RTC_CNTL_GPIO_PIN0_HOLD : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_PIN0_HOLD (BIT(0)) +#define RTC_CNTL_GPIO_PIN0_HOLD_M (BIT(0)) +#define RTC_CNTL_GPIO_PIN0_HOLD_V 0x1 +#define RTC_CNTL_GPIO_PIN0_HOLD_S 0 + +#define RTC_CNTL_DIG_PAD_HOLD_REG (DR_REG_RTCCNTL_BASE + 0x00D4) +/* RTC_CNTL_DIG_PAD_HOLD : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define RTC_CNTL_DIG_PAD_HOLD 0xFFFFFFFF +#define RTC_CNTL_DIG_PAD_HOLD_M ((RTC_CNTL_DIG_PAD_HOLD_V)<<(RTC_CNTL_DIG_PAD_HOLD_S)) +#define RTC_CNTL_DIG_PAD_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_DIG_PAD_HOLD_S 0 + +#define RTC_CNTL_BROWN_OUT_REG (DR_REG_RTCCNTL_BASE + 0x00D8) +/* RTC_CNTL_BROWN_OUT_DET : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_BROWN_OUT_DET (BIT(31)) +#define RTC_CNTL_BROWN_OUT_DET_M (BIT(31)) +#define RTC_CNTL_BROWN_OUT_DET_V 0x1 +#define RTC_CNTL_BROWN_OUT_DET_S 31 +/* RTC_CNTL_BROWN_OUT_ENA : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: enable brown out*/ +#define RTC_CNTL_BROWN_OUT_ENA (BIT(30)) +#define RTC_CNTL_BROWN_OUT_ENA_M (BIT(30)) +#define RTC_CNTL_BROWN_OUT_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_ENA_S 30 +/* RTC_CNTL_BROWN_OUT_CNT_CLR : WO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: clear brown out counter*/ +#define RTC_CNTL_BROWN_OUT_CNT_CLR (BIT(29)) +#define RTC_CNTL_BROWN_OUT_CNT_CLR_M (BIT(29)) +#define RTC_CNTL_BROWN_OUT_CNT_CLR_V 0x1 +#define RTC_CNTL_BROWN_OUT_CNT_CLR_S 29 +/* RTC_CNTL_BROWN_OUT_ANA_RST_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_BROWN_OUT_ANA_RST_EN (BIT(28)) +#define RTC_CNTL_BROWN_OUT_ANA_RST_EN_M (BIT(28)) +#define RTC_CNTL_BROWN_OUT_ANA_RST_EN_V 0x1 +#define RTC_CNTL_BROWN_OUT_ANA_RST_EN_S 28 +/* RTC_CNTL_BROWN_OUT_RST_SEL : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: 1: 4-pos reset*/ +#define RTC_CNTL_BROWN_OUT_RST_SEL (BIT(27)) +#define RTC_CNTL_BROWN_OUT_RST_SEL_M (BIT(27)) +#define RTC_CNTL_BROWN_OUT_RST_SEL_V 0x1 +#define RTC_CNTL_BROWN_OUT_RST_SEL_S 27 +/* RTC_CNTL_BROWN_OUT_RST_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: enable brown out reset*/ +#define RTC_CNTL_BROWN_OUT_RST_ENA (BIT(26)) +#define RTC_CNTL_BROWN_OUT_RST_ENA_M (BIT(26)) +#define RTC_CNTL_BROWN_OUT_RST_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_RST_ENA_S 26 +/* RTC_CNTL_BROWN_OUT_RST_WAIT : R/W ;bitpos:[25:16] ;default: 10'h3ff ; */ +/*description: brown out reset wait cycles*/ +#define RTC_CNTL_BROWN_OUT_RST_WAIT 0x000003FF +#define RTC_CNTL_BROWN_OUT_RST_WAIT_M ((RTC_CNTL_BROWN_OUT_RST_WAIT_V)<<(RTC_CNTL_BROWN_OUT_RST_WAIT_S)) +#define RTC_CNTL_BROWN_OUT_RST_WAIT_V 0x3FF +#define RTC_CNTL_BROWN_OUT_RST_WAIT_S 16 +/* RTC_CNTL_BROWN_OUT_PD_RF_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: enable power down RF when brown out happens*/ +#define RTC_CNTL_BROWN_OUT_PD_RF_ENA (BIT(15)) +#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_M (BIT(15)) +#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_S 15 +/* RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: enable close flash when brown out happens*/ +#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA (BIT(14)) +#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_M (BIT(14)) +#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_S 14 +/* RTC_CNTL_BROWN_OUT_INT_WAIT : R/W ;bitpos:[13:4] ;default: 10'h1 ; */ +/*description: brown out interrupt wait cycles*/ +#define RTC_CNTL_BROWN_OUT_INT_WAIT 0x000003FF +#define RTC_CNTL_BROWN_OUT_INT_WAIT_M ((RTC_CNTL_BROWN_OUT_INT_WAIT_V)<<(RTC_CNTL_BROWN_OUT_INT_WAIT_S)) +#define RTC_CNTL_BROWN_OUT_INT_WAIT_V 0x3FF +#define RTC_CNTL_BROWN_OUT_INT_WAIT_S 4 + +#define RTC_CNTL_TIME_LOW1_REG (DR_REG_RTCCNTL_BASE + 0x00DC) +/* RTC_CNTL_TIMER_VALUE1_LOW : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: RTC timer low 32 bits*/ +#define RTC_CNTL_TIMER_VALUE1_LOW 0xFFFFFFFF +#define RTC_CNTL_TIMER_VALUE1_LOW_M ((RTC_CNTL_TIMER_VALUE1_LOW_V)<<(RTC_CNTL_TIMER_VALUE1_LOW_S)) +#define RTC_CNTL_TIMER_VALUE1_LOW_V 0xFFFFFFFF +#define RTC_CNTL_TIMER_VALUE1_LOW_S 0 + +#define RTC_CNTL_TIME_HIGH1_REG (DR_REG_RTCCNTL_BASE + 0x00E0) +/* RTC_CNTL_TIMER_VALUE1_HIGH : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: RTC timer high 16 bits*/ +#define RTC_CNTL_TIMER_VALUE1_HIGH 0x0000FFFF +#define RTC_CNTL_TIMER_VALUE1_HIGH_M ((RTC_CNTL_TIMER_VALUE1_HIGH_V)<<(RTC_CNTL_TIMER_VALUE1_HIGH_S)) +#define RTC_CNTL_TIMER_VALUE1_HIGH_V 0xFFFF +#define RTC_CNTL_TIMER_VALUE1_HIGH_S 0 + +#define RTC_CNTL_XTAL32K_CLK_FACTOR_REG (DR_REG_RTCCNTL_BASE + 0x00E4) +/* RTC_CNTL_XTAL32K_CLK_FACTOR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: xtal 32k watch dog backup clock factor*/ +#define RTC_CNTL_XTAL32K_CLK_FACTOR 0xFFFFFFFF +#define RTC_CNTL_XTAL32K_CLK_FACTOR_M ((RTC_CNTL_XTAL32K_CLK_FACTOR_V)<<(RTC_CNTL_XTAL32K_CLK_FACTOR_S)) +#define RTC_CNTL_XTAL32K_CLK_FACTOR_V 0xFFFFFFFF +#define RTC_CNTL_XTAL32K_CLK_FACTOR_S 0 + +#define RTC_CNTL_XTAL32K_CONF_REG (DR_REG_RTCCNTL_BASE + 0x00E8) +/* RTC_CNTL_XTAL32K_STABLE_THRES : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ +/*description: if restarted xtal32k period is smaller than this*/ +#define RTC_CNTL_XTAL32K_STABLE_THRES 0x0000000F +#define RTC_CNTL_XTAL32K_STABLE_THRES_M ((RTC_CNTL_XTAL32K_STABLE_THRES_V)<<(RTC_CNTL_XTAL32K_STABLE_THRES_S)) +#define RTC_CNTL_XTAL32K_STABLE_THRES_V 0xF +#define RTC_CNTL_XTAL32K_STABLE_THRES_S 28 +/* RTC_CNTL_XTAL32K_WDT_TIMEOUT : R/W ;bitpos:[27:20] ;default: 8'hff ; */ +/*description: If no clock detected for this amount of time*/ +#define RTC_CNTL_XTAL32K_WDT_TIMEOUT 0x000000FF +#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_M ((RTC_CNTL_XTAL32K_WDT_TIMEOUT_V)<<(RTC_CNTL_XTAL32K_WDT_TIMEOUT_S)) +#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_V 0xFF +#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_S 20 +/* RTC_CNTL_XTAL32K_RESTART_WAIT : R/W ;bitpos:[19:4] ;default: 16'h0 ; */ +/*description: cycles to wait to repower on xtal 32k*/ +#define RTC_CNTL_XTAL32K_RESTART_WAIT 0x0000FFFF +#define RTC_CNTL_XTAL32K_RESTART_WAIT_M ((RTC_CNTL_XTAL32K_RESTART_WAIT_V)<<(RTC_CNTL_XTAL32K_RESTART_WAIT_S)) +#define RTC_CNTL_XTAL32K_RESTART_WAIT_V 0xFFFF +#define RTC_CNTL_XTAL32K_RESTART_WAIT_S 4 +/* RTC_CNTL_XTAL32K_RETURN_WAIT : R/W ;bitpos:[3:0] ;default: 4'h0 ; */ +/*description: cycles to wait to return normal xtal 32k*/ +#define RTC_CNTL_XTAL32K_RETURN_WAIT 0x0000000F +#define RTC_CNTL_XTAL32K_RETURN_WAIT_M ((RTC_CNTL_XTAL32K_RETURN_WAIT_V)<<(RTC_CNTL_XTAL32K_RETURN_WAIT_S)) +#define RTC_CNTL_XTAL32K_RETURN_WAIT_V 0xF +#define RTC_CNTL_XTAL32K_RETURN_WAIT_S 0 + +#define RTC_CNTL_USB_CONF_REG (DR_REG_RTCCNTL_BASE + 0x00EC) +/* RTC_CNTL_IO_MUX_RESET_DISABLE : R/W ;bitpos:[18] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_IO_MUX_RESET_DISABLE (BIT(18)) +#define RTC_CNTL_IO_MUX_RESET_DISABLE_M (BIT(18)) +#define RTC_CNTL_IO_MUX_RESET_DISABLE_V 0x1 +#define RTC_CNTL_IO_MUX_RESET_DISABLE_S 18 + +#define RTC_CNTL_SLP_REJECT_CAUSE_REG (DR_REG_RTCCNTL_BASE + 0x00F0) +/* RTC_CNTL_REJECT_CAUSE : RO ;bitpos:[17:0] ;default: 18'd0 ; */ +/*description: sleep reject cause*/ +#define RTC_CNTL_REJECT_CAUSE 0x0003FFFF +#define RTC_CNTL_REJECT_CAUSE_M ((RTC_CNTL_REJECT_CAUSE_V)<<(RTC_CNTL_REJECT_CAUSE_S)) +#define RTC_CNTL_REJECT_CAUSE_V 0x3FFFF +#define RTC_CNTL_REJECT_CAUSE_S 0 + +#define RTC_CNTL_OPTION1_REG (DR_REG_RTCCNTL_BASE + 0x00F4) +/* RTC_CNTL_FORCE_DOWNLOAD_BOOT : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_FORCE_DOWNLOAD_BOOT (BIT(0)) +#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_M (BIT(0)) +#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_V 0x1 +#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_S 0 + +#define RTC_CNTL_SLP_WAKEUP_CAUSE_REG (DR_REG_RTCCNTL_BASE + 0x00F8) +/* RTC_CNTL_WAKEUP_CAUSE : RO ;bitpos:[16:0] ;default: 17'd0 ; */ +/*description: sleep wakeup cause*/ +#define RTC_CNTL_WAKEUP_CAUSE 0x0001FFFF +#define RTC_CNTL_WAKEUP_CAUSE_M ((RTC_CNTL_WAKEUP_CAUSE_V)<<(RTC_CNTL_WAKEUP_CAUSE_S)) +#define RTC_CNTL_WAKEUP_CAUSE_V 0x1FFFF +#define RTC_CNTL_WAKEUP_CAUSE_S 0 + +#define RTC_CNTL_ULP_CP_TIMER_1_REG (DR_REG_RTCCNTL_BASE + 0x00FC) +/* RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE : R/W ;bitpos:[31:8] ;default: 24'd200 ; */ +/*description: sleep cycles for ULP-coprocessor timer*/ +#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE 0x00FFFFFF +#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_M ((RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V)<<(RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S)) +#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V 0xFFFFFF +#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S 8 + +#define RTC_CNTL_INT_ENA_W1TS_REG (DR_REG_RTCCNTL_BASE + 0x0100) +/* RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS : WO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS (BIT(20)) +#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS_M (BIT(20)) +#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS_S 20 +/* RTC_CNTL_GLITCH_DET_INT_ENA_W1TS : WO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: enable gitch det interrupt*/ +#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_M (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_S 19 +/* RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: enable xtal32k_dead interrupt*/ +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_M (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_S 16 +/* RTC_CNTL_SWD_INT_ENA_W1TS : WO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: enable super watch dog interrupt*/ +#define RTC_CNTL_SWD_INT_ENA_W1TS (BIT(15)) +#define RTC_CNTL_SWD_INT_ENA_W1TS_M (BIT(15)) +#define RTC_CNTL_SWD_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_SWD_INT_ENA_W1TS_S 15 +/* RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS : WO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: enable RTC main timer interrupt*/ +#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_M (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_S 10 +/* RTC_CNTL_BROWN_OUT_INT_ENA_W1TS : WO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: enable brown out interrupt*/ +#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_M (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_S 9 +/* RTC_CNTL_WDT_INT_ENA_W1TS : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: enable RTC WDT interrupt*/ +#define RTC_CNTL_WDT_INT_ENA_W1TS (BIT(3)) +#define RTC_CNTL_WDT_INT_ENA_W1TS_M (BIT(3)) +#define RTC_CNTL_WDT_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_WDT_INT_ENA_W1TS_S 3 +/* RTC_CNTL_SLP_REJECT_INT_ENA_W1TS : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: enable sleep reject interrupt*/ +#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_S 1 +/* RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: enable sleep wakeup interrupt*/ +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_S 0 + +#define RTC_CNTL_INT_ENA_W1TC_REG (DR_REG_RTCCNTL_BASE + 0x0104) +/* RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC : WO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC (BIT(20)) +#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC_M (BIT(20)) +#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC_S 20 +/* RTC_CNTL_GLITCH_DET_INT_ENA_W1TC : WO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: enable gitch det interrupt*/ +#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_M (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_S 19 +/* RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: enable xtal32k_dead interrupt*/ +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_M (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_S 16 +/* RTC_CNTL_SWD_INT_ENA_W1TC : WO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: enable super watch dog interrupt*/ +#define RTC_CNTL_SWD_INT_ENA_W1TC (BIT(15)) +#define RTC_CNTL_SWD_INT_ENA_W1TC_M (BIT(15)) +#define RTC_CNTL_SWD_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_SWD_INT_ENA_W1TC_S 15 +/* RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC : WO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: enable RTC main timer interrupt*/ +#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_M (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_S 10 +/* RTC_CNTL_BROWN_OUT_INT_ENA_W1TC : WO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: enable brown out interrupt*/ +#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_M (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_S 9 +/* RTC_CNTL_WDT_INT_ENA_W1TC : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: enable RTC WDT interrupt*/ +#define RTC_CNTL_WDT_INT_ENA_W1TC (BIT(3)) +#define RTC_CNTL_WDT_INT_ENA_W1TC_M (BIT(3)) +#define RTC_CNTL_WDT_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_WDT_INT_ENA_W1TC_S 3 +/* RTC_CNTL_SLP_REJECT_INT_ENA_W1TC : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: enable sleep reject interrupt*/ +#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_S 1 +/* RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: enable sleep wakeup interrupt*/ +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_S 0 + +#define RTC_CNTL_RETENTION_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x0108) +/* RTC_CNTL_RETENTION_WAIT : R/W ;bitpos:[31:27] ;default: 5'd20 ; */ +/*description: wait cycles for rention operation*/ +#define RTC_CNTL_RETENTION_WAIT 0x0000001F +#define RTC_CNTL_RETENTION_WAIT_M ((RTC_CNTL_RETENTION_WAIT_V)<<(RTC_CNTL_RETENTION_WAIT_S)) +#define RTC_CNTL_RETENTION_WAIT_V 0x1F +#define RTC_CNTL_RETENTION_WAIT_S 27 +/* RTC_CNTL_RETENTION_EN : R/W ;bitpos:[26] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_RETENTION_EN (BIT(26)) +#define RTC_CNTL_RETENTION_EN_M (BIT(26)) +#define RTC_CNTL_RETENTION_EN_V 0x1 +#define RTC_CNTL_RETENTION_EN_S 26 +/* RTC_CNTL_RETENTION_CLKOFF_WAIT : R/W ;bitpos:[25:22] ;default: 4'd3 ; */ +/*description: */ +#define RTC_CNTL_RETENTION_CLKOFF_WAIT 0x0000000F +#define RTC_CNTL_RETENTION_CLKOFF_WAIT_M ((RTC_CNTL_RETENTION_CLKOFF_WAIT_V)<<(RTC_CNTL_RETENTION_CLKOFF_WAIT_S)) +#define RTC_CNTL_RETENTION_CLKOFF_WAIT_V 0xF +#define RTC_CNTL_RETENTION_CLKOFF_WAIT_S 22 +/* RTC_CNTL_RETENTION_DONE_WAIT : R/W ;bitpos:[21:19] ;default: 3'd2 ; */ +/*description: */ +#define RTC_CNTL_RETENTION_DONE_WAIT 0x00000007 +#define RTC_CNTL_RETENTION_DONE_WAIT_M ((RTC_CNTL_RETENTION_DONE_WAIT_V)<<(RTC_CNTL_RETENTION_DONE_WAIT_S)) +#define RTC_CNTL_RETENTION_DONE_WAIT_V 0x7 +#define RTC_CNTL_RETENTION_DONE_WAIT_S 19 +/* RTC_CNTL_RETENTION_CLK_SEL : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_RETENTION_CLK_SEL (BIT(18)) +#define RTC_CNTL_RETENTION_CLK_SEL_M (BIT(18)) +#define RTC_CNTL_RETENTION_CLK_SEL_V 0x1 +#define RTC_CNTL_RETENTION_CLK_SEL_S 18 + +#define RTC_CNTL_FIB_SEL_REG (DR_REG_RTCCNTL_BASE + 0x010C) +/* RTC_CNTL_FIB_SEL : R/W ;bitpos:[2:0] ;default: 3'd7 ; */ +/*description: select use analog fib signal*/ +#define RTC_CNTL_FIB_SEL 0x00000007 +#define RTC_CNTL_FIB_SEL_M ((RTC_CNTL_FIB_SEL_V)<<(RTC_CNTL_FIB_SEL_S)) +#define RTC_CNTL_FIB_SEL_V 0x7 +#define RTC_CNTL_FIB_SEL_S 0 + +#define RTC_CNTL_FIB_GLITCH_RST BIT(0) +#define RTC_CNTL_FIB_BOD_RST BIT(1) +#define RTC_CNTL_FIB_SUPER_WDT_RST BIT(2) + +#define RTC_CNTL_GPIO_WAKEUP_REG (DR_REG_RTCCNTL_BASE + 0x0110) +/* RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE (BIT(31)) +#define RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_M (BIT(31)) +#define RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_V 0x1 +#define RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_S 31 +/* RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE (BIT(30)) +#define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE_M (BIT(30)) +#define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE_V 0x1 +#define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE_S 30 +/* RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE (BIT(29)) +#define RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE_M (BIT(29)) +#define RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE_V 0x1 +#define RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE_S 29 +/* RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE (BIT(28)) +#define RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE_M (BIT(28)) +#define RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE_V 0x1 +#define RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE_S 28 +/* RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE (BIT(27)) +#define RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE_M (BIT(27)) +#define RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE_V 0x1 +#define RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE_S 27 +/* RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE (BIT(26)) +#define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE_M (BIT(26)) +#define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE_V 0x1 +#define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE_S 26 +/* RTC_CNTL_GPIO_PIN0_INT_TYPE : R/W ;bitpos:[25:23] ;default: 3'd0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_PIN0_INT_TYPE 0x00000007 +#define RTC_CNTL_GPIO_PIN0_INT_TYPE_M ((RTC_CNTL_GPIO_PIN0_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN0_INT_TYPE_S)) +#define RTC_CNTL_GPIO_PIN0_INT_TYPE_V 0x7 +#define RTC_CNTL_GPIO_PIN0_INT_TYPE_S 23 +/* RTC_CNTL_GPIO_PIN1_INT_TYPE : R/W ;bitpos:[22:20] ;default: 3'd0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_PIN1_INT_TYPE 0x00000007 +#define RTC_CNTL_GPIO_PIN1_INT_TYPE_M ((RTC_CNTL_GPIO_PIN1_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN1_INT_TYPE_S)) +#define RTC_CNTL_GPIO_PIN1_INT_TYPE_V 0x7 +#define RTC_CNTL_GPIO_PIN1_INT_TYPE_S 20 +/* RTC_CNTL_GPIO_PIN2_INT_TYPE : R/W ;bitpos:[19:17] ;default: 3'd0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_PIN2_INT_TYPE 0x00000007 +#define RTC_CNTL_GPIO_PIN2_INT_TYPE_M ((RTC_CNTL_GPIO_PIN2_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN2_INT_TYPE_S)) +#define RTC_CNTL_GPIO_PIN2_INT_TYPE_V 0x7 +#define RTC_CNTL_GPIO_PIN2_INT_TYPE_S 17 +/* RTC_CNTL_GPIO_PIN3_INT_TYPE : R/W ;bitpos:[16:14] ;default: 3'd0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_PIN3_INT_TYPE 0x00000007 +#define RTC_CNTL_GPIO_PIN3_INT_TYPE_M ((RTC_CNTL_GPIO_PIN3_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN3_INT_TYPE_S)) +#define RTC_CNTL_GPIO_PIN3_INT_TYPE_V 0x7 +#define RTC_CNTL_GPIO_PIN3_INT_TYPE_S 14 +/* RTC_CNTL_GPIO_PIN4_INT_TYPE : R/W ;bitpos:[13:11] ;default: 3'd0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_PIN4_INT_TYPE 0x00000007 +#define RTC_CNTL_GPIO_PIN4_INT_TYPE_M ((RTC_CNTL_GPIO_PIN4_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN4_INT_TYPE_S)) +#define RTC_CNTL_GPIO_PIN4_INT_TYPE_V 0x7 +#define RTC_CNTL_GPIO_PIN4_INT_TYPE_S 11 +/* RTC_CNTL_GPIO_PIN5_INT_TYPE : R/W ;bitpos:[10:8] ;default: 3'd0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_PIN5_INT_TYPE 0x00000007 +#define RTC_CNTL_GPIO_PIN5_INT_TYPE_M ((RTC_CNTL_GPIO_PIN5_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN5_INT_TYPE_S)) +#define RTC_CNTL_GPIO_PIN5_INT_TYPE_V 0x7 +#define RTC_CNTL_GPIO_PIN5_INT_TYPE_S 8 +/* RTC_CNTL_GPIO_PIN_CLK_GATE : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_PIN_CLK_GATE (BIT(7)) +#define RTC_CNTL_GPIO_PIN_CLK_GATE_M (BIT(7)) +#define RTC_CNTL_GPIO_PIN_CLK_GATE_V 0x1 +#define RTC_CNTL_GPIO_PIN_CLK_GATE_S 7 +/* RTC_CNTL_GPIO_WAKEUP_STATUS_CLR : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_WAKEUP_STATUS_CLR (BIT(6)) +#define RTC_CNTL_GPIO_WAKEUP_STATUS_CLR_M (BIT(6)) +#define RTC_CNTL_GPIO_WAKEUP_STATUS_CLR_V 0x1 +#define RTC_CNTL_GPIO_WAKEUP_STATUS_CLR_S 6 +/* RTC_CNTL_GPIO_WAKEUP_STATUS : RO ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_WAKEUP_STATUS 0x0000003F +#define RTC_CNTL_GPIO_WAKEUP_STATUS_M ((RTC_CNTL_GPIO_WAKEUP_STATUS_V)<<(RTC_CNTL_GPIO_WAKEUP_STATUS_S)) +#define RTC_CNTL_GPIO_WAKEUP_STATUS_V 0x3F +#define RTC_CNTL_GPIO_WAKEUP_STATUS_S 0 + +#define RTC_CNTL_DBG_SEL_REG (DR_REG_RTCCNTL_BASE + 0x0114) +/* RTC_CNTL_DEBUG_SEL4 : R/W ;bitpos:[31:27] ;default: 5'd0 ; */ +/*description: */ +#define RTC_CNTL_DEBUG_SEL4 0x0000001F +#define RTC_CNTL_DEBUG_SEL4_M ((RTC_CNTL_DEBUG_SEL4_V)<<(RTC_CNTL_DEBUG_SEL4_S)) +#define RTC_CNTL_DEBUG_SEL4_V 0x1F +#define RTC_CNTL_DEBUG_SEL4_S 27 +/* RTC_CNTL_DEBUG_SEL3 : R/W ;bitpos:[26:22] ;default: 5'd0 ; */ +/*description: */ +#define RTC_CNTL_DEBUG_SEL3 0x0000001F +#define RTC_CNTL_DEBUG_SEL3_M ((RTC_CNTL_DEBUG_SEL3_V)<<(RTC_CNTL_DEBUG_SEL3_S)) +#define RTC_CNTL_DEBUG_SEL3_V 0x1F +#define RTC_CNTL_DEBUG_SEL3_S 22 +/* RTC_CNTL_DEBUG_SEL2 : R/W ;bitpos:[21:17] ;default: 5'd0 ; */ +/*description: */ +#define RTC_CNTL_DEBUG_SEL2 0x0000001F +#define RTC_CNTL_DEBUG_SEL2_M ((RTC_CNTL_DEBUG_SEL2_V)<<(RTC_CNTL_DEBUG_SEL2_S)) +#define RTC_CNTL_DEBUG_SEL2_V 0x1F +#define RTC_CNTL_DEBUG_SEL2_S 17 +/* RTC_CNTL_DEBUG_SEL1 : R/W ;bitpos:[16:12] ;default: 5'd0 ; */ +/*description: */ +#define RTC_CNTL_DEBUG_SEL1 0x0000001F +#define RTC_CNTL_DEBUG_SEL1_M ((RTC_CNTL_DEBUG_SEL1_V)<<(RTC_CNTL_DEBUG_SEL1_S)) +#define RTC_CNTL_DEBUG_SEL1_V 0x1F +#define RTC_CNTL_DEBUG_SEL1_S 12 +/* RTC_CNTL_DEBUG_SEL0 : R/W ;bitpos:[11:7] ;default: 5'd0 ; */ +/*description: */ +#define RTC_CNTL_DEBUG_SEL0 0x0000001F +#define RTC_CNTL_DEBUG_SEL0_M ((RTC_CNTL_DEBUG_SEL0_V)<<(RTC_CNTL_DEBUG_SEL0_S)) +#define RTC_CNTL_DEBUG_SEL0_V 0x1F +#define RTC_CNTL_DEBUG_SEL0_S 7 +/* RTC_CNTL_DEBUG_BIT_SEL : R/W ;bitpos:[6:2] ;default: 5'd0 ; */ +/*description: */ +#define RTC_CNTL_DEBUG_BIT_SEL 0x0000001F +#define RTC_CNTL_DEBUG_BIT_SEL_M ((RTC_CNTL_DEBUG_BIT_SEL_V)<<(RTC_CNTL_DEBUG_BIT_SEL_S)) +#define RTC_CNTL_DEBUG_BIT_SEL_V 0x1F +#define RTC_CNTL_DEBUG_BIT_SEL_S 2 +/* RTC_CNTL_DEBUG_12M_NO_GATING : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_DEBUG_12M_NO_GATING (BIT(1)) +#define RTC_CNTL_DEBUG_12M_NO_GATING_M (BIT(1)) +#define RTC_CNTL_DEBUG_12M_NO_GATING_V 0x1 +#define RTC_CNTL_DEBUG_12M_NO_GATING_S 1 + +#define RTC_CNTL_DBG_MAP_REG (DR_REG_RTCCNTL_BASE + 0x0118) +/* RTC_CNTL_GPIO_PIN0_FUN_SEL : R/W ;bitpos:[31:28] ;default: 4'd0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_PIN0_FUN_SEL 0x0000000F +#define RTC_CNTL_GPIO_PIN0_FUN_SEL_M ((RTC_CNTL_GPIO_PIN0_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN0_FUN_SEL_S)) +#define RTC_CNTL_GPIO_PIN0_FUN_SEL_V 0xF +#define RTC_CNTL_GPIO_PIN0_FUN_SEL_S 28 +/* RTC_CNTL_GPIO_PIN1_FUN_SEL : R/W ;bitpos:[27:24] ;default: 4'd0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_PIN1_FUN_SEL 0x0000000F +#define RTC_CNTL_GPIO_PIN1_FUN_SEL_M ((RTC_CNTL_GPIO_PIN1_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN1_FUN_SEL_S)) +#define RTC_CNTL_GPIO_PIN1_FUN_SEL_V 0xF +#define RTC_CNTL_GPIO_PIN1_FUN_SEL_S 24 +/* RTC_CNTL_GPIO_PIN2_FUN_SEL : R/W ;bitpos:[23:20] ;default: 4'd0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_PIN2_FUN_SEL 0x0000000F +#define RTC_CNTL_GPIO_PIN2_FUN_SEL_M ((RTC_CNTL_GPIO_PIN2_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN2_FUN_SEL_S)) +#define RTC_CNTL_GPIO_PIN2_FUN_SEL_V 0xF +#define RTC_CNTL_GPIO_PIN2_FUN_SEL_S 20 +/* RTC_CNTL_GPIO_PIN3_FUN_SEL : R/W ;bitpos:[19:16] ;default: 4'd0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_PIN3_FUN_SEL 0x0000000F +#define RTC_CNTL_GPIO_PIN3_FUN_SEL_M ((RTC_CNTL_GPIO_PIN3_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN3_FUN_SEL_S)) +#define RTC_CNTL_GPIO_PIN3_FUN_SEL_V 0xF +#define RTC_CNTL_GPIO_PIN3_FUN_SEL_S 16 +/* RTC_CNTL_GPIO_PIN4_FUN_SEL : R/W ;bitpos:[15:12] ;default: 4'd0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_PIN4_FUN_SEL 0x0000000F +#define RTC_CNTL_GPIO_PIN4_FUN_SEL_M ((RTC_CNTL_GPIO_PIN4_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN4_FUN_SEL_S)) +#define RTC_CNTL_GPIO_PIN4_FUN_SEL_V 0xF +#define RTC_CNTL_GPIO_PIN4_FUN_SEL_S 12 +/* RTC_CNTL_GPIO_PIN5_FUN_SEL : R/W ;bitpos:[11:8] ;default: 4'd0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_PIN5_FUN_SEL 0x0000000F +#define RTC_CNTL_GPIO_PIN5_FUN_SEL_M ((RTC_CNTL_GPIO_PIN5_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN5_FUN_SEL_S)) +#define RTC_CNTL_GPIO_PIN5_FUN_SEL_V 0xF +#define RTC_CNTL_GPIO_PIN5_FUN_SEL_S 8 +/* RTC_CNTL_GPIO_PIN0_MUX_SEL : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_PIN0_MUX_SEL (BIT(7)) +#define RTC_CNTL_GPIO_PIN0_MUX_SEL_M (BIT(7)) +#define RTC_CNTL_GPIO_PIN0_MUX_SEL_V 0x1 +#define RTC_CNTL_GPIO_PIN0_MUX_SEL_S 7 +/* RTC_CNTL_GPIO_PIN1_MUX_SEL : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_PIN1_MUX_SEL (BIT(6)) +#define RTC_CNTL_GPIO_PIN1_MUX_SEL_M (BIT(6)) +#define RTC_CNTL_GPIO_PIN1_MUX_SEL_V 0x1 +#define RTC_CNTL_GPIO_PIN1_MUX_SEL_S 6 +/* RTC_CNTL_GPIO_PIN2_MUX_SEL : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_PIN2_MUX_SEL (BIT(5)) +#define RTC_CNTL_GPIO_PIN2_MUX_SEL_M (BIT(5)) +#define RTC_CNTL_GPIO_PIN2_MUX_SEL_V 0x1 +#define RTC_CNTL_GPIO_PIN2_MUX_SEL_S 5 +/* RTC_CNTL_GPIO_PIN3_MUX_SEL : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_PIN3_MUX_SEL (BIT(4)) +#define RTC_CNTL_GPIO_PIN3_MUX_SEL_M (BIT(4)) +#define RTC_CNTL_GPIO_PIN3_MUX_SEL_V 0x1 +#define RTC_CNTL_GPIO_PIN3_MUX_SEL_S 4 +/* RTC_CNTL_GPIO_PIN4_MUX_SEL : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_PIN4_MUX_SEL (BIT(3)) +#define RTC_CNTL_GPIO_PIN4_MUX_SEL_M (BIT(3)) +#define RTC_CNTL_GPIO_PIN4_MUX_SEL_V 0x1 +#define RTC_CNTL_GPIO_PIN4_MUX_SEL_S 3 +/* RTC_CNTL_GPIO_PIN5_MUX_SEL : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_GPIO_PIN5_MUX_SEL (BIT(2)) +#define RTC_CNTL_GPIO_PIN5_MUX_SEL_M (BIT(2)) +#define RTC_CNTL_GPIO_PIN5_MUX_SEL_V 0x1 +#define RTC_CNTL_GPIO_PIN5_MUX_SEL_S 2 + +#define RTC_CNTL_SENSOR_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x011C) +/* RTC_CNTL_FORCE_XPD_SAR : R/W ;bitpos:[31:30] ;default: 2'b0 ; */ +/*description: */ +#define RTC_CNTL_FORCE_XPD_SAR 0x00000003 +#define RTC_CNTL_FORCE_XPD_SAR_M ((RTC_CNTL_FORCE_XPD_SAR_V)<<(RTC_CNTL_FORCE_XPD_SAR_S)) +#define RTC_CNTL_FORCE_XPD_SAR_V 0x3 +#define RTC_CNTL_FORCE_XPD_SAR_S 30 +/* RTC_CNTL_SAR2_PWDET_CCT : R/W ;bitpos:[29:27] ;default: 3'd0 ; */ +/*description: */ +#define RTC_CNTL_SAR2_PWDET_CCT 0x00000007 +#define RTC_CNTL_SAR2_PWDET_CCT_M ((RTC_CNTL_SAR2_PWDET_CCT_V)<<(RTC_CNTL_SAR2_PWDET_CCT_S)) +#define RTC_CNTL_SAR2_PWDET_CCT_V 0x7 +#define RTC_CNTL_SAR2_PWDET_CCT_S 27 + +#define RTC_CNTL_DBG_SAR_SEL_REG (DR_REG_RTCCNTL_BASE + 0x0120) +/* RTC_CNTL_SAR_DEBUG_SEL : R/W ;bitpos:[31:27] ;default: 5'd0 ; */ +/*description: */ +#define RTC_CNTL_SAR_DEBUG_SEL 0x0000001F +#define RTC_CNTL_SAR_DEBUG_SEL_M ((RTC_CNTL_SAR_DEBUG_SEL_V)<<(RTC_CNTL_SAR_DEBUG_SEL_S)) +#define RTC_CNTL_SAR_DEBUG_SEL_V 0x1F +#define RTC_CNTL_SAR_DEBUG_SEL_S 27 + +#define RTC_CNTL_PG_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x0124) +/* RTC_CNTL_POWER_GLITCH_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_POWER_GLITCH_EN (BIT(31)) +#define RTC_CNTL_POWER_GLITCH_EN_M (BIT(31)) +#define RTC_CNTL_POWER_GLITCH_EN_V 0x1 +#define RTC_CNTL_POWER_GLITCH_EN_S 31 +/* RTC_CNTL_POWER_GLITCH_EFUSE_SEL : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL (BIT(30)) +#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL_M (BIT(30)) +#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL_V 0x1 +#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL_S 30 +/* RTC_CNTL_POWER_GLITCH_FORCE_PU : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_POWER_GLITCH_FORCE_PU (BIT(29)) +#define RTC_CNTL_POWER_GLITCH_FORCE_PU_M (BIT(29)) +#define RTC_CNTL_POWER_GLITCH_FORCE_PU_V 0x1 +#define RTC_CNTL_POWER_GLITCH_FORCE_PU_S 29 +/* RTC_CNTL_POWER_GLITCH_FORCE_PD : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_POWER_GLITCH_FORCE_PD (BIT(28)) +#define RTC_CNTL_POWER_GLITCH_FORCE_PD_M (BIT(28)) +#define RTC_CNTL_POWER_GLITCH_FORCE_PD_V 0x1 +#define RTC_CNTL_POWER_GLITCH_FORCE_PD_S 28 +/* RTC_CNTL_POWER_GLITCH_DSENSE : R/W ;bitpos:[27:26] ;default: 2'b0 ; */ +/*description: */ +#define RTC_CNTL_POWER_GLITCH_DSENSE 0x00000003 +#define RTC_CNTL_POWER_GLITCH_DSENSE_M ((RTC_CNTL_POWER_GLITCH_DSENSE_V)<<(RTC_CNTL_POWER_GLITCH_DSENSE_S)) +#define RTC_CNTL_POWER_GLITCH_DSENSE_V 0x3 +#define RTC_CNTL_POWER_GLITCH_DSENSE_S 26 + +#define RTC_CNTL_DATE_REG (DR_REG_RTCCNTL_BASE + 0x01fc) +/* RTC_CNTL_CNTL_DATE : R/W ;bitpos:[27:0] ;default: 28'h2007270 ; */ +/*description: */ +#define RTC_CNTL_CNTL_DATE 0x0FFFFFFF +#define RTC_CNTL_CNTL_DATE_M ((RTC_CNTL_CNTL_DATE_V)<<(RTC_CNTL_CNTL_DATE_S)) +#define RTC_CNTL_CNTL_DATE_V 0xFFFFFFF +#define RTC_CNTL_CNTL_DATE_S 0 + +#ifdef __cplusplus +} +#endif + +#endif /*_SOC_RTC_CNTL_REG_H_ */ diff --git a/src/target/esp32c3/include/soc/system_reg.h b/src/target/esp32c3/include/soc/system_reg.h new file mode 100644 index 0000000..fe391d6 --- /dev/null +++ b/src/target/esp32c3/include/soc/system_reg.h @@ -0,0 +1,1017 @@ +/* + * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 OR MIT + */ +#ifndef _SOC_SYSTEM_REG_H_ +#define _SOC_SYSTEM_REG_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define SYSTEM_CPU_PERI_CLK_EN_REG (DR_REG_SYSTEM_BASE + 0x000) +/* SYSTEM_CLK_EN_DEDICATED_GPIO : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_CLK_EN_DEDICATED_GPIO (BIT(7)) +#define SYSTEM_CLK_EN_DEDICATED_GPIO_M (BIT(7)) +#define SYSTEM_CLK_EN_DEDICATED_GPIO_V 0x1 +#define SYSTEM_CLK_EN_DEDICATED_GPIO_S 7 +/* SYSTEM_CLK_EN_ASSIST_DEBUG : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_CLK_EN_ASSIST_DEBUG (BIT(6)) +#define SYSTEM_CLK_EN_ASSIST_DEBUG_M (BIT(6)) +#define SYSTEM_CLK_EN_ASSIST_DEBUG_V 0x1 +#define SYSTEM_CLK_EN_ASSIST_DEBUG_S 6 + +#define SYSTEM_CPU_PERI_RST_EN_REG (DR_REG_SYSTEM_BASE + 0x004) +/* SYSTEM_RST_EN_DEDICATED_GPIO : R/W ;bitpos:[7] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_RST_EN_DEDICATED_GPIO (BIT(7)) +#define SYSTEM_RST_EN_DEDICATED_GPIO_M (BIT(7)) +#define SYSTEM_RST_EN_DEDICATED_GPIO_V 0x1 +#define SYSTEM_RST_EN_DEDICATED_GPIO_S 7 +/* SYSTEM_RST_EN_ASSIST_DEBUG : R/W ;bitpos:[6] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_RST_EN_ASSIST_DEBUG (BIT(6)) +#define SYSTEM_RST_EN_ASSIST_DEBUG_M (BIT(6)) +#define SYSTEM_RST_EN_ASSIST_DEBUG_V 0x1 +#define SYSTEM_RST_EN_ASSIST_DEBUG_S 6 + +#define SYSTEM_CPU_PER_CONF_REG (DR_REG_SYSTEM_BASE + 0x008) +/* SYSTEM_CPU_WAITI_DELAY_NUM : R/W ;bitpos:[7:4] ;default: 4'h0 ; */ +/*description: */ +#define SYSTEM_CPU_WAITI_DELAY_NUM 0x0000000F +#define SYSTEM_CPU_WAITI_DELAY_NUM_M ((SYSTEM_CPU_WAITI_DELAY_NUM_V)<<(SYSTEM_CPU_WAITI_DELAY_NUM_S)) +#define SYSTEM_CPU_WAITI_DELAY_NUM_V 0xF +#define SYSTEM_CPU_WAITI_DELAY_NUM_S 4 +/* SYSTEM_CPU_WAIT_MODE_FORCE_ON : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_CPU_WAIT_MODE_FORCE_ON (BIT(3)) +#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_M (BIT(3)) +#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_V 0x1 +#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_S 3 +/* SYSTEM_PLL_FREQ_SEL : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_PLL_FREQ_SEL (BIT(2)) +#define SYSTEM_PLL_FREQ_SEL_M (BIT(2)) +#define SYSTEM_PLL_FREQ_SEL_V 0x1 +#define SYSTEM_PLL_FREQ_SEL_S 2 +/* SYSTEM_CPUPERIOD_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: */ +#define SYSTEM_CPUPERIOD_SEL 0x00000003 +#define SYSTEM_CPUPERIOD_SEL_M ((SYSTEM_CPUPERIOD_SEL_V)<<(SYSTEM_CPUPERIOD_SEL_S)) +#define SYSTEM_CPUPERIOD_SEL_V 0x3 +#define SYSTEM_CPUPERIOD_SEL_S 0 + +#define SYSTEM_MEM_PD_MASK_REG (DR_REG_SYSTEM_BASE + 0x00C) +/* SYSTEM_LSLP_MEM_PD_MASK : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_LSLP_MEM_PD_MASK (BIT(0)) +#define SYSTEM_LSLP_MEM_PD_MASK_M (BIT(0)) +#define SYSTEM_LSLP_MEM_PD_MASK_V 0x1 +#define SYSTEM_LSLP_MEM_PD_MASK_S 0 + +#define SYSTEM_PERIP_CLK_EN0_REG (DR_REG_SYSTEM_BASE + 0x010) +/* SYSTEM_SPI4_CLK_EN : R/W ;bitpos:[31] ;default: 1'h1 ; */ +/*description: */ +#define SYSTEM_SPI4_CLK_EN (BIT(31)) +#define SYSTEM_SPI4_CLK_EN_M (BIT(31)) +#define SYSTEM_SPI4_CLK_EN_V 0x1 +#define SYSTEM_SPI4_CLK_EN_S 31 +/* SYSTEM_ADC2_ARB_CLK_EN : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_ADC2_ARB_CLK_EN (BIT(30)) +#define SYSTEM_ADC2_ARB_CLK_EN_M (BIT(30)) +#define SYSTEM_ADC2_ARB_CLK_EN_V 0x1 +#define SYSTEM_ADC2_ARB_CLK_EN_S 30 +/* SYSTEM_SYSTIMER_CLK_EN : R/W ;bitpos:[29] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_SYSTIMER_CLK_EN (BIT(29)) +#define SYSTEM_SYSTIMER_CLK_EN_M (BIT(29)) +#define SYSTEM_SYSTIMER_CLK_EN_V 0x1 +#define SYSTEM_SYSTIMER_CLK_EN_S 29 +/* SYSTEM_APB_SARADC_CLK_EN : R/W ;bitpos:[28] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_APB_SARADC_CLK_EN (BIT(28)) +#define SYSTEM_APB_SARADC_CLK_EN_M (BIT(28)) +#define SYSTEM_APB_SARADC_CLK_EN_V 0x1 +#define SYSTEM_APB_SARADC_CLK_EN_S 28 +/* SYSTEM_SPI3_DMA_CLK_EN : R/W ;bitpos:[27] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_SPI3_DMA_CLK_EN (BIT(27)) +#define SYSTEM_SPI3_DMA_CLK_EN_M (BIT(27)) +#define SYSTEM_SPI3_DMA_CLK_EN_V 0x1 +#define SYSTEM_SPI3_DMA_CLK_EN_S 27 +/* SYSTEM_PWM3_CLK_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_PWM3_CLK_EN (BIT(26)) +#define SYSTEM_PWM3_CLK_EN_M (BIT(26)) +#define SYSTEM_PWM3_CLK_EN_V 0x1 +#define SYSTEM_PWM3_CLK_EN_S 26 +/* SYSTEM_PWM2_CLK_EN : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_PWM2_CLK_EN (BIT(25)) +#define SYSTEM_PWM2_CLK_EN_M (BIT(25)) +#define SYSTEM_PWM2_CLK_EN_V 0x1 +#define SYSTEM_PWM2_CLK_EN_S 25 +/* SYSTEM_UART_MEM_CLK_EN : R/W ;bitpos:[24] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_UART_MEM_CLK_EN (BIT(24)) +#define SYSTEM_UART_MEM_CLK_EN_M (BIT(24)) +#define SYSTEM_UART_MEM_CLK_EN_V 0x1 +#define SYSTEM_UART_MEM_CLK_EN_S 24 +/* SYSTEM_USB_DEVICE_CLK_EN : R/W ;bitpos:[23] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_USB_DEVICE_CLK_EN (BIT(23)) +#define SYSTEM_USB_DEVICE_CLK_EN_M (BIT(23)) +#define SYSTEM_USB_DEVICE_CLK_EN_V 0x1 +#define SYSTEM_USB_DEVICE_CLK_EN_S 23 +/* SYSTEM_SPI2_DMA_CLK_EN : R/W ;bitpos:[22] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_SPI2_DMA_CLK_EN (BIT(22)) +#define SYSTEM_SPI2_DMA_CLK_EN_M (BIT(22)) +#define SYSTEM_SPI2_DMA_CLK_EN_V 0x1 +#define SYSTEM_SPI2_DMA_CLK_EN_S 22 +/* SYSTEM_I2S0_CLK_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_I2S0_CLK_EN (BIT(21)) +#define SYSTEM_I2S0_CLK_EN_M (BIT(21)) +#define SYSTEM_I2S0_CLK_EN_V 0x1 +#define SYSTEM_I2S0_CLK_EN_S 21 +/* SYSTEM_PWM1_CLK_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_PWM1_CLK_EN (BIT(20)) +#define SYSTEM_PWM1_CLK_EN_M (BIT(20)) +#define SYSTEM_PWM1_CLK_EN_V 0x1 +#define SYSTEM_PWM1_CLK_EN_S 20 +/* SYSTEM_TWAI_CLK_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_TWAI_CLK_EN (BIT(19)) +#define SYSTEM_TWAI_CLK_EN_M (BIT(19)) +#define SYSTEM_TWAI_CLK_EN_V 0x1 +#define SYSTEM_TWAI_CLK_EN_S 19 +/* SYSTEM_I2C_EXT1_CLK_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_I2C_EXT1_CLK_EN (BIT(18)) +#define SYSTEM_I2C_EXT1_CLK_EN_M (BIT(18)) +#define SYSTEM_I2C_EXT1_CLK_EN_V 0x1 +#define SYSTEM_I2C_EXT1_CLK_EN_S 18 +/* SYSTEM_PWM0_CLK_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_PWM0_CLK_EN (BIT(17)) +#define SYSTEM_PWM0_CLK_EN_M (BIT(17)) +#define SYSTEM_PWM0_CLK_EN_V 0x1 +#define SYSTEM_PWM0_CLK_EN_S 17 +/* SYSTEM_SPI3_CLK_EN : R/W ;bitpos:[16] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_SPI3_CLK_EN (BIT(16)) +#define SYSTEM_SPI3_CLK_EN_M (BIT(16)) +#define SYSTEM_SPI3_CLK_EN_V 0x1 +#define SYSTEM_SPI3_CLK_EN_S 16 +/* SYSTEM_TIMERGROUP1_CLK_EN : R/W ;bitpos:[15] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_TIMERGROUP1_CLK_EN (BIT(15)) +#define SYSTEM_TIMERGROUP1_CLK_EN_M (BIT(15)) +#define SYSTEM_TIMERGROUP1_CLK_EN_V 0x1 +#define SYSTEM_TIMERGROUP1_CLK_EN_S 15 +/* SYSTEM_EFUSE_CLK_EN : R/W ;bitpos:[14] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_EFUSE_CLK_EN (BIT(14)) +#define SYSTEM_EFUSE_CLK_EN_M (BIT(14)) +#define SYSTEM_EFUSE_CLK_EN_V 0x1 +#define SYSTEM_EFUSE_CLK_EN_S 14 +/* SYSTEM_TIMERGROUP_CLK_EN : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_TIMERGROUP_CLK_EN (BIT(13)) +#define SYSTEM_TIMERGROUP_CLK_EN_M (BIT(13)) +#define SYSTEM_TIMERGROUP_CLK_EN_V 0x1 +#define SYSTEM_TIMERGROUP_CLK_EN_S 13 +/* SYSTEM_UHCI1_CLK_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_UHCI1_CLK_EN (BIT(12)) +#define SYSTEM_UHCI1_CLK_EN_M (BIT(12)) +#define SYSTEM_UHCI1_CLK_EN_V 0x1 +#define SYSTEM_UHCI1_CLK_EN_S 12 +/* SYSTEM_LEDC_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_LEDC_CLK_EN (BIT(11)) +#define SYSTEM_LEDC_CLK_EN_M (BIT(11)) +#define SYSTEM_LEDC_CLK_EN_V 0x1 +#define SYSTEM_LEDC_CLK_EN_S 11 +/* SYSTEM_PCNT_CLK_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_PCNT_CLK_EN (BIT(10)) +#define SYSTEM_PCNT_CLK_EN_M (BIT(10)) +#define SYSTEM_PCNT_CLK_EN_V 0x1 +#define SYSTEM_PCNT_CLK_EN_S 10 +/* SYSTEM_RMT_CLK_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_RMT_CLK_EN (BIT(9)) +#define SYSTEM_RMT_CLK_EN_M (BIT(9)) +#define SYSTEM_RMT_CLK_EN_V 0x1 +#define SYSTEM_RMT_CLK_EN_S 9 +/* SYSTEM_UHCI0_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_UHCI0_CLK_EN (BIT(8)) +#define SYSTEM_UHCI0_CLK_EN_M (BIT(8)) +#define SYSTEM_UHCI0_CLK_EN_V 0x1 +#define SYSTEM_UHCI0_CLK_EN_S 8 +/* SYSTEM_I2C_EXT0_CLK_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_I2C_EXT0_CLK_EN (BIT(7)) +#define SYSTEM_I2C_EXT0_CLK_EN_M (BIT(7)) +#define SYSTEM_I2C_EXT0_CLK_EN_V 0x1 +#define SYSTEM_I2C_EXT0_CLK_EN_S 7 +/* SYSTEM_SPI2_CLK_EN : R/W ;bitpos:[6] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_SPI2_CLK_EN (BIT(6)) +#define SYSTEM_SPI2_CLK_EN_M (BIT(6)) +#define SYSTEM_SPI2_CLK_EN_V 0x1 +#define SYSTEM_SPI2_CLK_EN_S 6 +/* SYSTEM_UART1_CLK_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_UART1_CLK_EN (BIT(5)) +#define SYSTEM_UART1_CLK_EN_M (BIT(5)) +#define SYSTEM_UART1_CLK_EN_V 0x1 +#define SYSTEM_UART1_CLK_EN_S 5 +/* SYSTEM_WDG_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_WDG_CLK_EN (BIT(3)) +#define SYSTEM_WDG_CLK_EN_M (BIT(3)) +#define SYSTEM_WDG_CLK_EN_V 0x1 +#define SYSTEM_WDG_CLK_EN_S 3 +/* SYSTEM_UART_CLK_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_UART_CLK_EN (BIT(2)) +#define SYSTEM_UART_CLK_EN_M (BIT(2)) +#define SYSTEM_UART_CLK_EN_V 0x1 +#define SYSTEM_UART_CLK_EN_S 2 +/* SYSTEM_SPI01_CLK_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_SPI01_CLK_EN (BIT(1)) +#define SYSTEM_SPI01_CLK_EN_M (BIT(1)) +#define SYSTEM_SPI01_CLK_EN_V 0x1 +#define SYSTEM_SPI01_CLK_EN_S 1 +/* SYSTEM_TIMERS_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_TIMERS_CLK_EN (BIT(0)) +#define SYSTEM_TIMERS_CLK_EN_M (BIT(0)) +#define SYSTEM_TIMERS_CLK_EN_V 0x1 +#define SYSTEM_TIMERS_CLK_EN_S 0 + +#define SYSTEM_PERIP_CLK_EN1_REG (DR_REG_SYSTEM_BASE + 0x014) +/* SYSTEM_TSENS_CLK_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_TSENS_CLK_EN (BIT(10)) +#define SYSTEM_TSENS_CLK_EN_M (BIT(10)) +#define SYSTEM_TSENS_CLK_EN_V 0x1 +#define SYSTEM_TSENS_CLK_EN_S 10 +/* SYSTEM_LCD_CAM_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_LCD_CAM_CLK_EN (BIT(8)) +#define SYSTEM_LCD_CAM_CLK_EN_M (BIT(8)) +#define SYSTEM_LCD_CAM_CLK_EN_V 0x1 +#define SYSTEM_LCD_CAM_CLK_EN_S 8 +/* SYSTEM_SDIO_HOST_CLK_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_SDIO_HOST_CLK_EN (BIT(7)) +#define SYSTEM_SDIO_HOST_CLK_EN_M (BIT(7)) +#define SYSTEM_SDIO_HOST_CLK_EN_V 0x1 +#define SYSTEM_SDIO_HOST_CLK_EN_S 7 +/* SYSTEM_DMA_CLK_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_DMA_CLK_EN (BIT(6)) +#define SYSTEM_DMA_CLK_EN_M (BIT(6)) +#define SYSTEM_DMA_CLK_EN_V 0x1 +#define SYSTEM_DMA_CLK_EN_S 6 +/* SYSTEM_CRYPTO_HMAC_CLK_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_CRYPTO_HMAC_CLK_EN (BIT(5)) +#define SYSTEM_CRYPTO_HMAC_CLK_EN_M (BIT(5)) +#define SYSTEM_CRYPTO_HMAC_CLK_EN_V 0x1 +#define SYSTEM_CRYPTO_HMAC_CLK_EN_S 5 +/* SYSTEM_CRYPTO_DS_CLK_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_CRYPTO_DS_CLK_EN (BIT(4)) +#define SYSTEM_CRYPTO_DS_CLK_EN_M (BIT(4)) +#define SYSTEM_CRYPTO_DS_CLK_EN_V 0x1 +#define SYSTEM_CRYPTO_DS_CLK_EN_S 4 +/* SYSTEM_CRYPTO_RSA_CLK_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_CRYPTO_RSA_CLK_EN (BIT(3)) +#define SYSTEM_CRYPTO_RSA_CLK_EN_M (BIT(3)) +#define SYSTEM_CRYPTO_RSA_CLK_EN_V 0x1 +#define SYSTEM_CRYPTO_RSA_CLK_EN_S 3 +/* SYSTEM_CRYPTO_SHA_CLK_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_CRYPTO_SHA_CLK_EN (BIT(2)) +#define SYSTEM_CRYPTO_SHA_CLK_EN_M (BIT(2)) +#define SYSTEM_CRYPTO_SHA_CLK_EN_V 0x1 +#define SYSTEM_CRYPTO_SHA_CLK_EN_S 2 +/* SYSTEM_CRYPTO_AES_CLK_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_CRYPTO_AES_CLK_EN (BIT(1)) +#define SYSTEM_CRYPTO_AES_CLK_EN_M (BIT(1)) +#define SYSTEM_CRYPTO_AES_CLK_EN_V 0x1 +#define SYSTEM_CRYPTO_AES_CLK_EN_S 1 + +#define SYSTEM_PERIP_RST_EN0_REG (DR_REG_SYSTEM_BASE + 0x018) +/* SYSTEM_SPI4_RST : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: */ +#define SYSTEM_SPI4_RST (BIT(31)) +#define SYSTEM_SPI4_RST_M (BIT(31)) +#define SYSTEM_SPI4_RST_V 0x1 +#define SYSTEM_SPI4_RST_S 31 +/* SYSTEM_ADC2_ARB_RST : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_ADC2_ARB_RST (BIT(30)) +#define SYSTEM_ADC2_ARB_RST_M (BIT(30)) +#define SYSTEM_ADC2_ARB_RST_V 0x1 +#define SYSTEM_ADC2_ARB_RST_S 30 +/* SYSTEM_SYSTIMER_RST : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_SYSTIMER_RST (BIT(29)) +#define SYSTEM_SYSTIMER_RST_M (BIT(29)) +#define SYSTEM_SYSTIMER_RST_V 0x1 +#define SYSTEM_SYSTIMER_RST_S 29 +/* SYSTEM_APB_SARADC_RST : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_APB_SARADC_RST (BIT(28)) +#define SYSTEM_APB_SARADC_RST_M (BIT(28)) +#define SYSTEM_APB_SARADC_RST_V 0x1 +#define SYSTEM_APB_SARADC_RST_S 28 +/* SYSTEM_SPI3_DMA_RST : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_SPI3_DMA_RST (BIT(27)) +#define SYSTEM_SPI3_DMA_RST_M (BIT(27)) +#define SYSTEM_SPI3_DMA_RST_V 0x1 +#define SYSTEM_SPI3_DMA_RST_S 27 +/* SYSTEM_PWM3_RST : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_PWM3_RST (BIT(26)) +#define SYSTEM_PWM3_RST_M (BIT(26)) +#define SYSTEM_PWM3_RST_V 0x1 +#define SYSTEM_PWM3_RST_S 26 +/* SYSTEM_PWM2_RST : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_PWM2_RST (BIT(25)) +#define SYSTEM_PWM2_RST_M (BIT(25)) +#define SYSTEM_PWM2_RST_V 0x1 +#define SYSTEM_PWM2_RST_S 25 +/* SYSTEM_UART_MEM_RST : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_UART_MEM_RST (BIT(24)) +#define SYSTEM_UART_MEM_RST_M (BIT(24)) +#define SYSTEM_UART_MEM_RST_V 0x1 +#define SYSTEM_UART_MEM_RST_S 24 +/* SYSTEM_USB_DEVICE_RST : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_USB_DEVICE_RST (BIT(23)) +#define SYSTEM_USB_DEVICE_RST_M (BIT(23)) +#define SYSTEM_USB_DEVICE_RST_V 0x1 +#define SYSTEM_USB_DEVICE_RST_S 23 +/* SYSTEM_SPI2_DMA_RST : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_SPI2_DMA_RST (BIT(22)) +#define SYSTEM_SPI2_DMA_RST_M (BIT(22)) +#define SYSTEM_SPI2_DMA_RST_V 0x1 +#define SYSTEM_SPI2_DMA_RST_S 22 +/* SYSTEM_I2S0_RST : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_I2S0_RST (BIT(21)) +#define SYSTEM_I2S0_RST_M (BIT(21)) +#define SYSTEM_I2S0_RST_V 0x1 +#define SYSTEM_I2S0_RST_S 21 +/* SYSTEM_PWM1_RST : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_PWM1_RST (BIT(20)) +#define SYSTEM_PWM1_RST_M (BIT(20)) +#define SYSTEM_PWM1_RST_V 0x1 +#define SYSTEM_PWM1_RST_S 20 +/* SYSTEM_TWAI_RST : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_TWAI_RST (BIT(19)) +#define SYSTEM_TWAI_RST_M (BIT(19)) +#define SYSTEM_TWAI_RST_V 0x1 +#define SYSTEM_TWAI_RST_S 19 +/* SYSTEM_I2C_EXT1_RST : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_I2C_EXT1_RST (BIT(18)) +#define SYSTEM_I2C_EXT1_RST_M (BIT(18)) +#define SYSTEM_I2C_EXT1_RST_V 0x1 +#define SYSTEM_I2C_EXT1_RST_S 18 +/* SYSTEM_PWM0_RST : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_PWM0_RST (BIT(17)) +#define SYSTEM_PWM0_RST_M (BIT(17)) +#define SYSTEM_PWM0_RST_V 0x1 +#define SYSTEM_PWM0_RST_S 17 +/* SYSTEM_SPI3_RST : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_SPI3_RST (BIT(16)) +#define SYSTEM_SPI3_RST_M (BIT(16)) +#define SYSTEM_SPI3_RST_V 0x1 +#define SYSTEM_SPI3_RST_S 16 +/* SYSTEM_TIMERGROUP1_RST : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_TIMERGROUP1_RST (BIT(15)) +#define SYSTEM_TIMERGROUP1_RST_M (BIT(15)) +#define SYSTEM_TIMERGROUP1_RST_V 0x1 +#define SYSTEM_TIMERGROUP1_RST_S 15 +/* SYSTEM_EFUSE_RST : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_EFUSE_RST (BIT(14)) +#define SYSTEM_EFUSE_RST_M (BIT(14)) +#define SYSTEM_EFUSE_RST_V 0x1 +#define SYSTEM_EFUSE_RST_S 14 +/* SYSTEM_TIMERGROUP_RST : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_TIMERGROUP_RST (BIT(13)) +#define SYSTEM_TIMERGROUP_RST_M (BIT(13)) +#define SYSTEM_TIMERGROUP_RST_V 0x1 +#define SYSTEM_TIMERGROUP_RST_S 13 +/* SYSTEM_UHCI1_RST : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_UHCI1_RST (BIT(12)) +#define SYSTEM_UHCI1_RST_M (BIT(12)) +#define SYSTEM_UHCI1_RST_V 0x1 +#define SYSTEM_UHCI1_RST_S 12 +/* SYSTEM_LEDC_RST : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_LEDC_RST (BIT(11)) +#define SYSTEM_LEDC_RST_M (BIT(11)) +#define SYSTEM_LEDC_RST_V 0x1 +#define SYSTEM_LEDC_RST_S 11 +/* SYSTEM_PCNT_RST : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_PCNT_RST (BIT(10)) +#define SYSTEM_PCNT_RST_M (BIT(10)) +#define SYSTEM_PCNT_RST_V 0x1 +#define SYSTEM_PCNT_RST_S 10 +/* SYSTEM_RMT_RST : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_RMT_RST (BIT(9)) +#define SYSTEM_RMT_RST_M (BIT(9)) +#define SYSTEM_RMT_RST_V 0x1 +#define SYSTEM_RMT_RST_S 9 +/* SYSTEM_UHCI0_RST : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_UHCI0_RST (BIT(8)) +#define SYSTEM_UHCI0_RST_M (BIT(8)) +#define SYSTEM_UHCI0_RST_V 0x1 +#define SYSTEM_UHCI0_RST_S 8 +/* SYSTEM_I2C_EXT0_RST : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_I2C_EXT0_RST (BIT(7)) +#define SYSTEM_I2C_EXT0_RST_M (BIT(7)) +#define SYSTEM_I2C_EXT0_RST_V 0x1 +#define SYSTEM_I2C_EXT0_RST_S 7 +/* SYSTEM_SPI2_RST : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_SPI2_RST (BIT(6)) +#define SYSTEM_SPI2_RST_M (BIT(6)) +#define SYSTEM_SPI2_RST_V 0x1 +#define SYSTEM_SPI2_RST_S 6 +/* SYSTEM_UART1_RST : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_UART1_RST (BIT(5)) +#define SYSTEM_UART1_RST_M (BIT(5)) +#define SYSTEM_UART1_RST_V 0x1 +#define SYSTEM_UART1_RST_S 5 +/* SYSTEM_WDG_RST : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_WDG_RST (BIT(3)) +#define SYSTEM_WDG_RST_M (BIT(3)) +#define SYSTEM_WDG_RST_V 0x1 +#define SYSTEM_WDG_RST_S 3 +/* SYSTEM_UART_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_UART_RST (BIT(2)) +#define SYSTEM_UART_RST_M (BIT(2)) +#define SYSTEM_UART_RST_V 0x1 +#define SYSTEM_UART_RST_S 2 +/* SYSTEM_SPI01_RST : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_SPI01_RST (BIT(1)) +#define SYSTEM_SPI01_RST_M (BIT(1)) +#define SYSTEM_SPI01_RST_V 0x1 +#define SYSTEM_SPI01_RST_S 1 +/* SYSTEM_TIMERS_RST : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_TIMERS_RST (BIT(0)) +#define SYSTEM_TIMERS_RST_M (BIT(0)) +#define SYSTEM_TIMERS_RST_V 0x1 +#define SYSTEM_TIMERS_RST_S 0 + +#define SYSTEM_PERIP_RST_EN1_REG (DR_REG_SYSTEM_BASE + 0x01C) +/* SYSTEM_TSENS_RST : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_TSENS_RST (BIT(10)) +#define SYSTEM_TSENS_RST_M (BIT(10)) +#define SYSTEM_TSENS_RST_V 0x1 +#define SYSTEM_TSENS_RST_S 10 +/* SYSTEM_LCD_CAM_RST : R/W ;bitpos:[8] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_LCD_CAM_RST (BIT(8)) +#define SYSTEM_LCD_CAM_RST_M (BIT(8)) +#define SYSTEM_LCD_CAM_RST_V 0x1 +#define SYSTEM_LCD_CAM_RST_S 8 +/* SYSTEM_SDIO_HOST_RST : R/W ;bitpos:[7] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_SDIO_HOST_RST (BIT(7)) +#define SYSTEM_SDIO_HOST_RST_M (BIT(7)) +#define SYSTEM_SDIO_HOST_RST_V 0x1 +#define SYSTEM_SDIO_HOST_RST_S 7 +/* SYSTEM_DMA_RST : R/W ;bitpos:[6] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_DMA_RST (BIT(6)) +#define SYSTEM_DMA_RST_M (BIT(6)) +#define SYSTEM_DMA_RST_V 0x1 +#define SYSTEM_DMA_RST_S 6 +/* SYSTEM_CRYPTO_HMAC_RST : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_CRYPTO_HMAC_RST (BIT(5)) +#define SYSTEM_CRYPTO_HMAC_RST_M (BIT(5)) +#define SYSTEM_CRYPTO_HMAC_RST_V 0x1 +#define SYSTEM_CRYPTO_HMAC_RST_S 5 +/* SYSTEM_CRYPTO_DS_RST : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_CRYPTO_DS_RST (BIT(4)) +#define SYSTEM_CRYPTO_DS_RST_M (BIT(4)) +#define SYSTEM_CRYPTO_DS_RST_V 0x1 +#define SYSTEM_CRYPTO_DS_RST_S 4 +/* SYSTEM_CRYPTO_RSA_RST : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_CRYPTO_RSA_RST (BIT(3)) +#define SYSTEM_CRYPTO_RSA_RST_M (BIT(3)) +#define SYSTEM_CRYPTO_RSA_RST_V 0x1 +#define SYSTEM_CRYPTO_RSA_RST_S 3 +/* SYSTEM_CRYPTO_SHA_RST : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_CRYPTO_SHA_RST (BIT(2)) +#define SYSTEM_CRYPTO_SHA_RST_M (BIT(2)) +#define SYSTEM_CRYPTO_SHA_RST_V 0x1 +#define SYSTEM_CRYPTO_SHA_RST_S 2 +/* SYSTEM_CRYPTO_AES_RST : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_CRYPTO_AES_RST (BIT(1)) +#define SYSTEM_CRYPTO_AES_RST_M (BIT(1)) +#define SYSTEM_CRYPTO_AES_RST_V 0x1 +#define SYSTEM_CRYPTO_AES_RST_S 1 + +#define SYSTEM_BT_LPCK_DIV_INT_REG (DR_REG_SYSTEM_BASE + 0x020) +/* SYSTEM_BT_LPCK_DIV_NUM : R/W ;bitpos:[11:0] ;default: 12'd255 ; */ +/*description: */ +#define SYSTEM_BT_LPCK_DIV_NUM 0x00000FFF +#define SYSTEM_BT_LPCK_DIV_NUM_M ((SYSTEM_BT_LPCK_DIV_NUM_V)<<(SYSTEM_BT_LPCK_DIV_NUM_S)) +#define SYSTEM_BT_LPCK_DIV_NUM_V 0xFFF +#define SYSTEM_BT_LPCK_DIV_NUM_S 0 + +#define SYSTEM_BT_LPCK_DIV_FRAC_REG (DR_REG_SYSTEM_BASE + 0x024) +/* SYSTEM_LPCLK_RTC_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_LPCLK_RTC_EN (BIT(28)) +#define SYSTEM_LPCLK_RTC_EN_M (BIT(28)) +#define SYSTEM_LPCLK_RTC_EN_V 0x1 +#define SYSTEM_LPCLK_RTC_EN_S 28 +/* SYSTEM_LPCLK_SEL_XTAL32K : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_LPCLK_SEL_XTAL32K (BIT(27)) +#define SYSTEM_LPCLK_SEL_XTAL32K_M (BIT(27)) +#define SYSTEM_LPCLK_SEL_XTAL32K_V 0x1 +#define SYSTEM_LPCLK_SEL_XTAL32K_S 27 +/* SYSTEM_LPCLK_SEL_XTAL : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_LPCLK_SEL_XTAL (BIT(26)) +#define SYSTEM_LPCLK_SEL_XTAL_M (BIT(26)) +#define SYSTEM_LPCLK_SEL_XTAL_V 0x1 +#define SYSTEM_LPCLK_SEL_XTAL_S 26 +/* SYSTEM_LPCLK_SEL_8M : R/W ;bitpos:[25] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_LPCLK_SEL_8M (BIT(25)) +#define SYSTEM_LPCLK_SEL_8M_M (BIT(25)) +#define SYSTEM_LPCLK_SEL_8M_V 0x1 +#define SYSTEM_LPCLK_SEL_8M_S 25 +/* SYSTEM_LPCLK_SEL_RTC_SLOW : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_LPCLK_SEL_RTC_SLOW (BIT(24)) +#define SYSTEM_LPCLK_SEL_RTC_SLOW_M (BIT(24)) +#define SYSTEM_LPCLK_SEL_RTC_SLOW_V 0x1 +#define SYSTEM_LPCLK_SEL_RTC_SLOW_S 24 +/* SYSTEM_BT_LPCK_DIV_A : R/W ;bitpos:[23:12] ;default: 12'd1 ; */ +/*description: */ +#define SYSTEM_BT_LPCK_DIV_A 0x00000FFF +#define SYSTEM_BT_LPCK_DIV_A_M ((SYSTEM_BT_LPCK_DIV_A_V)<<(SYSTEM_BT_LPCK_DIV_A_S)) +#define SYSTEM_BT_LPCK_DIV_A_V 0xFFF +#define SYSTEM_BT_LPCK_DIV_A_S 12 +/* SYSTEM_BT_LPCK_DIV_B : R/W ;bitpos:[11:0] ;default: 12'd1 ; */ +/*description: */ +#define SYSTEM_BT_LPCK_DIV_B 0x00000FFF +#define SYSTEM_BT_LPCK_DIV_B_M ((SYSTEM_BT_LPCK_DIV_B_V)<<(SYSTEM_BT_LPCK_DIV_B_S)) +#define SYSTEM_BT_LPCK_DIV_B_V 0xFFF +#define SYSTEM_BT_LPCK_DIV_B_S 0 + +#define SYSTEM_CPU_INTR_FROM_CPU_0_REG (DR_REG_SYSTEM_BASE + 0x028) +/* SYSTEM_CPU_INTR_FROM_CPU_0 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_CPU_INTR_FROM_CPU_0 (BIT(0)) +#define SYSTEM_CPU_INTR_FROM_CPU_0_M (BIT(0)) +#define SYSTEM_CPU_INTR_FROM_CPU_0_V 0x1 +#define SYSTEM_CPU_INTR_FROM_CPU_0_S 0 + +#define SYSTEM_CPU_INTR_FROM_CPU_1_REG (DR_REG_SYSTEM_BASE + 0x02C) +/* SYSTEM_CPU_INTR_FROM_CPU_1 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_CPU_INTR_FROM_CPU_1 (BIT(0)) +#define SYSTEM_CPU_INTR_FROM_CPU_1_M (BIT(0)) +#define SYSTEM_CPU_INTR_FROM_CPU_1_V 0x1 +#define SYSTEM_CPU_INTR_FROM_CPU_1_S 0 + +#define SYSTEM_CPU_INTR_FROM_CPU_2_REG (DR_REG_SYSTEM_BASE + 0x030) +/* SYSTEM_CPU_INTR_FROM_CPU_2 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_CPU_INTR_FROM_CPU_2 (BIT(0)) +#define SYSTEM_CPU_INTR_FROM_CPU_2_M (BIT(0)) +#define SYSTEM_CPU_INTR_FROM_CPU_2_V 0x1 +#define SYSTEM_CPU_INTR_FROM_CPU_2_S 0 + +#define SYSTEM_CPU_INTR_FROM_CPU_3_REG (DR_REG_SYSTEM_BASE + 0x034) +/* SYSTEM_CPU_INTR_FROM_CPU_3 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_CPU_INTR_FROM_CPU_3 (BIT(0)) +#define SYSTEM_CPU_INTR_FROM_CPU_3_M (BIT(0)) +#define SYSTEM_CPU_INTR_FROM_CPU_3_V 0x1 +#define SYSTEM_CPU_INTR_FROM_CPU_3_S 0 + +#define SYSTEM_RSA_PD_CTRL_REG (DR_REG_SYSTEM_BASE + 0x038) +/* SYSTEM_RSA_MEM_FORCE_PD : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_RSA_MEM_FORCE_PD (BIT(2)) +#define SYSTEM_RSA_MEM_FORCE_PD_M (BIT(2)) +#define SYSTEM_RSA_MEM_FORCE_PD_V 0x1 +#define SYSTEM_RSA_MEM_FORCE_PD_S 2 +/* SYSTEM_RSA_MEM_FORCE_PU : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_RSA_MEM_FORCE_PU (BIT(1)) +#define SYSTEM_RSA_MEM_FORCE_PU_M (BIT(1)) +#define SYSTEM_RSA_MEM_FORCE_PU_V 0x1 +#define SYSTEM_RSA_MEM_FORCE_PU_S 1 +/* SYSTEM_RSA_MEM_PD : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_RSA_MEM_PD (BIT(0)) +#define SYSTEM_RSA_MEM_PD_M (BIT(0)) +#define SYSTEM_RSA_MEM_PD_V 0x1 +#define SYSTEM_RSA_MEM_PD_S 0 + +#define SYSTEM_EDMA_CTRL_REG (DR_REG_SYSTEM_BASE + 0x03C) +/* SYSTEM_EDMA_RESET : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_EDMA_RESET (BIT(1)) +#define SYSTEM_EDMA_RESET_M (BIT(1)) +#define SYSTEM_EDMA_RESET_V 0x1 +#define SYSTEM_EDMA_RESET_S 1 +/* SYSTEM_EDMA_CLK_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_EDMA_CLK_ON (BIT(0)) +#define SYSTEM_EDMA_CLK_ON_M (BIT(0)) +#define SYSTEM_EDMA_CLK_ON_V 0x1 +#define SYSTEM_EDMA_CLK_ON_S 0 + +#define SYSTEM_CACHE_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x040) +/* SYSTEM_DCACHE_RESET : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_DCACHE_RESET (BIT(3)) +#define SYSTEM_DCACHE_RESET_M (BIT(3)) +#define SYSTEM_DCACHE_RESET_V 0x1 +#define SYSTEM_DCACHE_RESET_S 3 +/* SYSTEM_DCACHE_CLK_ON : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_DCACHE_CLK_ON (BIT(2)) +#define SYSTEM_DCACHE_CLK_ON_M (BIT(2)) +#define SYSTEM_DCACHE_CLK_ON_V 0x1 +#define SYSTEM_DCACHE_CLK_ON_S 2 +/* SYSTEM_ICACHE_RESET : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_ICACHE_RESET (BIT(1)) +#define SYSTEM_ICACHE_RESET_M (BIT(1)) +#define SYSTEM_ICACHE_RESET_V 0x1 +#define SYSTEM_ICACHE_RESET_S 1 +/* SYSTEM_ICACHE_CLK_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_ICACHE_CLK_ON (BIT(0)) +#define SYSTEM_ICACHE_CLK_ON_M (BIT(0)) +#define SYSTEM_ICACHE_CLK_ON_V 0x1 +#define SYSTEM_ICACHE_CLK_ON_S 0 + +#define SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x044) +/* SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT (BIT(3)) +#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_M (BIT(3)) +#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V 0x1 +#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S 3 +/* SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT (BIT(2)) +#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_M (BIT(2)) +#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V 0x1 +#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S 2 +/* SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT (BIT(1)) +#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_M (BIT(1)) +#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V 0x1 +#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S 1 +/* SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT (BIT(0)) +#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_M (BIT(0)) +#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V 0x1 +#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S 0 + +#define SYSTEM_RTC_FASTMEM_CONFIG_REG (DR_REG_SYSTEM_BASE + 0x048) +/* SYSTEM_RTC_MEM_CRC_FINISH : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_RTC_MEM_CRC_FINISH (BIT(31)) +#define SYSTEM_RTC_MEM_CRC_FINISH_M (BIT(31)) +#define SYSTEM_RTC_MEM_CRC_FINISH_V 0x1 +#define SYSTEM_RTC_MEM_CRC_FINISH_S 31 +/* SYSTEM_RTC_MEM_CRC_LEN : R/W ;bitpos:[30:20] ;default: 11'h7ff ; */ +/*description: */ +#define SYSTEM_RTC_MEM_CRC_LEN 0x000007FF +#define SYSTEM_RTC_MEM_CRC_LEN_M ((SYSTEM_RTC_MEM_CRC_LEN_V)<<(SYSTEM_RTC_MEM_CRC_LEN_S)) +#define SYSTEM_RTC_MEM_CRC_LEN_V 0x7FF +#define SYSTEM_RTC_MEM_CRC_LEN_S 20 +/* SYSTEM_RTC_MEM_CRC_ADDR : R/W ;bitpos:[19:9] ;default: 11'h0 ; */ +/*description: */ +#define SYSTEM_RTC_MEM_CRC_ADDR 0x000007FF +#define SYSTEM_RTC_MEM_CRC_ADDR_M ((SYSTEM_RTC_MEM_CRC_ADDR_V)<<(SYSTEM_RTC_MEM_CRC_ADDR_S)) +#define SYSTEM_RTC_MEM_CRC_ADDR_V 0x7FF +#define SYSTEM_RTC_MEM_CRC_ADDR_S 9 +/* SYSTEM_RTC_MEM_CRC_START : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_RTC_MEM_CRC_START (BIT(8)) +#define SYSTEM_RTC_MEM_CRC_START_M (BIT(8)) +#define SYSTEM_RTC_MEM_CRC_START_V 0x1 +#define SYSTEM_RTC_MEM_CRC_START_S 8 + +#define SYSTEM_RTC_FASTMEM_CRC_REG (DR_REG_SYSTEM_BASE + 0x04C) +/* SYSTEM_RTC_MEM_CRC_RES : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define SYSTEM_RTC_MEM_CRC_RES 0xFFFFFFFF +#define SYSTEM_RTC_MEM_CRC_RES_M ((SYSTEM_RTC_MEM_CRC_RES_V)<<(SYSTEM_RTC_MEM_CRC_RES_S)) +#define SYSTEM_RTC_MEM_CRC_RES_V 0xFFFFFFFF +#define SYSTEM_RTC_MEM_CRC_RES_S 0 + +#define SYSTEM_REDUNDANT_ECO_CTRL_REG (DR_REG_SYSTEM_BASE + 0x050) +/* SYSTEM_REDUNDANT_ECO_RESULT : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_REDUNDANT_ECO_RESULT (BIT(1)) +#define SYSTEM_REDUNDANT_ECO_RESULT_M (BIT(1)) +#define SYSTEM_REDUNDANT_ECO_RESULT_V 0x1 +#define SYSTEM_REDUNDANT_ECO_RESULT_S 1 +/* SYSTEM_REDUNDANT_ECO_DRIVE : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_REDUNDANT_ECO_DRIVE (BIT(0)) +#define SYSTEM_REDUNDANT_ECO_DRIVE_M (BIT(0)) +#define SYSTEM_REDUNDANT_ECO_DRIVE_V 0x1 +#define SYSTEM_REDUNDANT_ECO_DRIVE_S 0 + +#define SYSTEM_CLOCK_GATE_REG (DR_REG_SYSTEM_BASE + 0x054) +/* SYSTEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_CLK_EN (BIT(0)) +#define SYSTEM_CLK_EN_M (BIT(0)) +#define SYSTEM_CLK_EN_V 0x1 +#define SYSTEM_CLK_EN_S 0 + +#define SYSTEM_SYSCLK_CONF_REG (DR_REG_SYSTEM_BASE + 0x058) +/* SYSTEM_CLK_DIV_EN : RO ;bitpos:[19] ;default: 1'd0 ; */ +/*description: */ +#define SYSTEM_CLK_DIV_EN (BIT(19)) +#define SYSTEM_CLK_DIV_EN_M (BIT(19)) +#define SYSTEM_CLK_DIV_EN_V 0x1 +#define SYSTEM_CLK_DIV_EN_S 19 +/* SYSTEM_CLK_XTAL_FREQ : RO ;bitpos:[18:12] ;default: 7'd0 ; */ +/*description: */ +#define SYSTEM_CLK_XTAL_FREQ 0x0000007F +#define SYSTEM_CLK_XTAL_FREQ_M ((SYSTEM_CLK_XTAL_FREQ_V)<<(SYSTEM_CLK_XTAL_FREQ_S)) +#define SYSTEM_CLK_XTAL_FREQ_V 0x7F +#define SYSTEM_CLK_XTAL_FREQ_S 12 +/* SYSTEM_SOC_CLK_SEL : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ +/*description: */ +#define SYSTEM_SOC_CLK_SEL 0x00000003 +#define SYSTEM_SOC_CLK_SEL_M ((SYSTEM_SOC_CLK_SEL_V)<<(SYSTEM_SOC_CLK_SEL_S)) +#define SYSTEM_SOC_CLK_SEL_V 0x3 +#define SYSTEM_SOC_CLK_SEL_S 10 +/* SYSTEM_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */ +/*description: */ +#define SYSTEM_PRE_DIV_CNT 0x000003FF +#define SYSTEM_PRE_DIV_CNT_M ((SYSTEM_PRE_DIV_CNT_V)<<(SYSTEM_PRE_DIV_CNT_S)) +#define SYSTEM_PRE_DIV_CNT_V 0x3FF +#define SYSTEM_PRE_DIV_CNT_S 0 + +#define SYSTEM_MEM_PVT_REG (DR_REG_SYSTEM_BASE + 0x05C) +/* SYSTEM_MEM_VT_SEL : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: */ +#define SYSTEM_MEM_VT_SEL 0x00000003 +#define SYSTEM_MEM_VT_SEL_M ((SYSTEM_MEM_VT_SEL_V)<<(SYSTEM_MEM_VT_SEL_S)) +#define SYSTEM_MEM_VT_SEL_V 0x3 +#define SYSTEM_MEM_VT_SEL_S 22 +/* SYSTEM_MEM_TIMING_ERR_CNT : RO ;bitpos:[21:6] ;default: 16'h0 ; */ +/*description: */ +#define SYSTEM_MEM_TIMING_ERR_CNT 0x0000FFFF +#define SYSTEM_MEM_TIMING_ERR_CNT_M ((SYSTEM_MEM_TIMING_ERR_CNT_V)<<(SYSTEM_MEM_TIMING_ERR_CNT_S)) +#define SYSTEM_MEM_TIMING_ERR_CNT_V 0xFFFF +#define SYSTEM_MEM_TIMING_ERR_CNT_S 6 +/* SYSTEM_MEM_PVT_MONITOR_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_MEM_PVT_MONITOR_EN (BIT(5)) +#define SYSTEM_MEM_PVT_MONITOR_EN_M (BIT(5)) +#define SYSTEM_MEM_PVT_MONITOR_EN_V 0x1 +#define SYSTEM_MEM_PVT_MONITOR_EN_S 5 +/* SYSTEM_MEM_ERR_CNT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_MEM_ERR_CNT_CLR (BIT(4)) +#define SYSTEM_MEM_ERR_CNT_CLR_M (BIT(4)) +#define SYSTEM_MEM_ERR_CNT_CLR_V 0x1 +#define SYSTEM_MEM_ERR_CNT_CLR_S 4 +/* SYSTEM_MEM_PATH_LEN : R/W ;bitpos:[3:0] ;default: 4'h3 ; */ +/*description: */ +#define SYSTEM_MEM_PATH_LEN 0x0000000F +#define SYSTEM_MEM_PATH_LEN_M ((SYSTEM_MEM_PATH_LEN_V)<<(SYSTEM_MEM_PATH_LEN_S)) +#define SYSTEM_MEM_PATH_LEN_V 0xF +#define SYSTEM_MEM_PATH_LEN_S 0 + +#define SYSTEM_COMB_PVT_LVT_CONF_REG (DR_REG_SYSTEM_BASE + 0x060) +/* SYSTEM_COMB_PVT_MONITOR_EN_LVT : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_COMB_PVT_MONITOR_EN_LVT (BIT(6)) +#define SYSTEM_COMB_PVT_MONITOR_EN_LVT_M (BIT(6)) +#define SYSTEM_COMB_PVT_MONITOR_EN_LVT_V 0x1 +#define SYSTEM_COMB_PVT_MONITOR_EN_LVT_S 6 +/* SYSTEM_COMB_ERR_CNT_CLR_LVT : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_COMB_ERR_CNT_CLR_LVT (BIT(5)) +#define SYSTEM_COMB_ERR_CNT_CLR_LVT_M (BIT(5)) +#define SYSTEM_COMB_ERR_CNT_CLR_LVT_V 0x1 +#define SYSTEM_COMB_ERR_CNT_CLR_LVT_S 5 +/* SYSTEM_COMB_PATH_LEN_LVT : R/W ;bitpos:[4:0] ;default: 5'h3 ; */ +/*description: */ +#define SYSTEM_COMB_PATH_LEN_LVT 0x0000001F +#define SYSTEM_COMB_PATH_LEN_LVT_M ((SYSTEM_COMB_PATH_LEN_LVT_V)<<(SYSTEM_COMB_PATH_LEN_LVT_S)) +#define SYSTEM_COMB_PATH_LEN_LVT_V 0x1F +#define SYSTEM_COMB_PATH_LEN_LVT_S 0 + +#define SYSTEM_COMB_PVT_NVT_CONF_REG (DR_REG_SYSTEM_BASE + 0x064) +/* SYSTEM_COMB_PVT_MONITOR_EN_NVT : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_COMB_PVT_MONITOR_EN_NVT (BIT(6)) +#define SYSTEM_COMB_PVT_MONITOR_EN_NVT_M (BIT(6)) +#define SYSTEM_COMB_PVT_MONITOR_EN_NVT_V 0x1 +#define SYSTEM_COMB_PVT_MONITOR_EN_NVT_S 6 +/* SYSTEM_COMB_ERR_CNT_CLR_NVT : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_COMB_ERR_CNT_CLR_NVT (BIT(5)) +#define SYSTEM_COMB_ERR_CNT_CLR_NVT_M (BIT(5)) +#define SYSTEM_COMB_ERR_CNT_CLR_NVT_V 0x1 +#define SYSTEM_COMB_ERR_CNT_CLR_NVT_S 5 +/* SYSTEM_COMB_PATH_LEN_NVT : R/W ;bitpos:[4:0] ;default: 5'h3 ; */ +/*description: */ +#define SYSTEM_COMB_PATH_LEN_NVT 0x0000001F +#define SYSTEM_COMB_PATH_LEN_NVT_M ((SYSTEM_COMB_PATH_LEN_NVT_V)<<(SYSTEM_COMB_PATH_LEN_NVT_S)) +#define SYSTEM_COMB_PATH_LEN_NVT_V 0x1F +#define SYSTEM_COMB_PATH_LEN_NVT_S 0 + +#define SYSTEM_COMB_PVT_HVT_CONF_REG (DR_REG_SYSTEM_BASE + 0x068) +/* SYSTEM_COMB_PVT_MONITOR_EN_HVT : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_COMB_PVT_MONITOR_EN_HVT (BIT(6)) +#define SYSTEM_COMB_PVT_MONITOR_EN_HVT_M (BIT(6)) +#define SYSTEM_COMB_PVT_MONITOR_EN_HVT_V 0x1 +#define SYSTEM_COMB_PVT_MONITOR_EN_HVT_S 6 +/* SYSTEM_COMB_ERR_CNT_CLR_HVT : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_COMB_ERR_CNT_CLR_HVT (BIT(5)) +#define SYSTEM_COMB_ERR_CNT_CLR_HVT_M (BIT(5)) +#define SYSTEM_COMB_ERR_CNT_CLR_HVT_V 0x1 +#define SYSTEM_COMB_ERR_CNT_CLR_HVT_S 5 +/* SYSTEM_COMB_PATH_LEN_HVT : R/W ;bitpos:[4:0] ;default: 5'h3 ; */ +/*description: */ +#define SYSTEM_COMB_PATH_LEN_HVT 0x0000001F +#define SYSTEM_COMB_PATH_LEN_HVT_M ((SYSTEM_COMB_PATH_LEN_HVT_V)<<(SYSTEM_COMB_PATH_LEN_HVT_S)) +#define SYSTEM_COMB_PATH_LEN_HVT_V 0x1F +#define SYSTEM_COMB_PATH_LEN_HVT_S 0 + +#define SYSTEM_COMB_PVT_ERR_LVT_SITE0_REG (DR_REG_SYSTEM_BASE + 0x06C) +/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: */ +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0 0x0000FFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_M ((SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_S)) +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_V 0xFFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_S 0 + +#define SYSTEM_COMB_PVT_ERR_NVT_SITE0_REG (DR_REG_SYSTEM_BASE + 0x070) +/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: */ +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0 0x0000FFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_M ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_S)) +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_V 0xFFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_S 0 + +#define SYSTEM_COMB_PVT_ERR_HVT_SITE0_REG (DR_REG_SYSTEM_BASE + 0x074) +/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: */ +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0 0x0000FFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_M ((SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_S)) +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_V 0xFFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_S 0 + +#define SYSTEM_COMB_PVT_ERR_LVT_SITE1_REG (DR_REG_SYSTEM_BASE + 0x078) +/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: */ +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1 0x0000FFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_M ((SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_S)) +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_V 0xFFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_S 0 + +#define SYSTEM_COMB_PVT_ERR_NVT_SITE1_REG (DR_REG_SYSTEM_BASE + 0x07C) +/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: */ +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1 0x0000FFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_M ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_S)) +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_V 0xFFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_S 0 + +#define SYSTEM_COMB_PVT_ERR_HVT_SITE1_REG (DR_REG_SYSTEM_BASE + 0x080) +/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: */ +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1 0x0000FFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_M ((SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_S)) +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_V 0xFFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_S 0 + +#define SYSTEM_COMB_PVT_ERR_LVT_SITE2_REG (DR_REG_SYSTEM_BASE + 0x084) +/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: */ +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2 0x0000FFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_M ((SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_S)) +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_V 0xFFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_S 0 + +#define SYSTEM_COMB_PVT_ERR_NVT_SITE2_REG (DR_REG_SYSTEM_BASE + 0x088) +/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: */ +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2 0x0000FFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_M ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_S)) +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_V 0xFFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_S 0 + +#define SYSTEM_COMB_PVT_ERR_HVT_SITE2_REG (DR_REG_SYSTEM_BASE + 0x08C) +/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: */ +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2 0x0000FFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_M ((SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_S)) +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_V 0xFFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_S 0 + +#define SYSTEM_COMB_PVT_ERR_LVT_SITE3_REG (DR_REG_SYSTEM_BASE + 0x090) +/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: */ +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3 0x0000FFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_M ((SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_S)) +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_V 0xFFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_S 0 + +#define SYSTEM_COMB_PVT_ERR_NVT_SITE3_REG (DR_REG_SYSTEM_BASE + 0x094) +/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: */ +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3 0x0000FFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_M ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_S)) +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_V 0xFFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_S 0 + +#define SYSTEM_COMB_PVT_ERR_HVT_SITE3_REG (DR_REG_SYSTEM_BASE + 0x098) +/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: */ +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3 0x0000FFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_M ((SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_S)) +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_V 0xFFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_S 0 + +#define SYSTEM_DATE_REG (DR_REG_SYSTEM_BASE + 0xFFC) +/* SYSTEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2007150 ; */ +/*description: */ +#define SYSTEM_DATE 0x0FFFFFFF +#define SYSTEM_DATE_M ((SYSTEM_DATE_V)<<(SYSTEM_DATE_S)) +#define SYSTEM_DATE_V 0xFFFFFFF +#define SYSTEM_DATE_S 0 + +#ifdef __cplusplus +} +#endif + +#endif /*_SOC_SYSTEM_REG_H_ */ diff --git a/src/target/esp32c3/ld/esp32c3.rom.api.ld b/src/target/esp32c3/ld/esp32c3.rom.api.ld index cefdef3..1ba3f97 100644 --- a/src/target/esp32c3/ld/esp32c3.rom.api.ld +++ b/src/target/esp32c3/ld/esp32c3.rom.api.ld @@ -52,6 +52,7 @@ PROVIDE ( esp_rom_isr_attach = ets_isr_attach ); PROVIDE ( esp_rom_isr_unmask = ets_isr_unmask ); PROVIDE ( esp_rom_get_cpu_ticks_per_us = ets_get_cpu_frequency ); PROVIDE ( esp_rom_set_cpu_ticks_per_us = ets_update_cpu_frequency ); +PROVIDE ( esp_rom_get_apb_freq = ets_get_apb_freq ); PROVIDE ( esp_rom_spiflash_clear_bp = esp_rom_spiflash_unlock ); PROVIDE ( esp_rom_spiflash_write_enable = SPI_write_enable ); diff --git a/src/target/esp32c3/src/clock.c b/src/target/esp32c3/src/clock.c new file mode 100644 index 0000000..847c1ab --- /dev/null +++ b/src/target/esp32c3/src/clock.c @@ -0,0 +1,43 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 OR MIT + */ + +#include +#include +#include +#include +#include +#include +#include + +#define MHZ 1000000 + +extern uint32_t esp_rom_get_xtal_freq(void); +extern void esp_rom_set_cpu_ticks_per_us(uint32_t ticks_per_us); +extern uint32_t esp_rom_get_apb_freq(void); + +static uint32_t s_cpu_freq = 0; + +void stub_target_clock_init(void) +{ + REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL, 1); + REG_SET_FIELD(SYSTEM_CPU_PER_CONF_REG, SYSTEM_PLL_FREQ_SEL, 1); + REG_SET_FIELD(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPUPERIOD_SEL, 1); + s_cpu_freq = 160 * MHZ; + esp_rom_set_cpu_ticks_per_us(s_cpu_freq / MHZ); +} + +uint32_t stub_target_get_cpu_freq(void) +{ + if (s_cpu_freq == 0) { + return esp_rom_get_xtal_freq(); + } + return s_cpu_freq; +} + +uint32_t stub_target_get_apb_freq(void) +{ + return esp_rom_get_apb_freq(); +} diff --git a/src/target/esp32c3/src/uart.c b/src/target/esp32c3/src/uart.c index 506ad5f..5156cdb 100644 --- a/src/target/esp32c3/src/uart.c +++ b/src/target/esp32c3/src/uart.c @@ -8,6 +8,8 @@ #include #include #include +#include +#include #include #include @@ -15,14 +17,11 @@ extern void esp_rom_uart_attach(void *rxBuffer); extern void esp_rom_uart_init(uint8_t uart_no, uint32_t clock); extern uint32_t esp_rom_get_apb_freq(void); -extern void esp_rom_set_cpu_ticks_per_us(uint32_t ticks_per_us); extern void esp_rom_uart_div_modify(uint8_t uart_no, uint32_t divisor); extern void esp_rom_isr_attach(int int_num, void *handler, void *arg); extern void esp_rom_isr_unmask(int int_num); extern uint32_t esp_rom_get_xtal_freq(void); -#define UART_CLK_FREQ_ROM (40 * 1000000) - void stub_target_rom_uart_attach(void *rxBuffer) { esp_rom_uart_attach(rxBuffer); @@ -37,15 +36,23 @@ void stub_target_uart_init(uint8_t uart_num) { extern bool g_uart_print; stub_target_rom_uart_attach(NULL); - esp_rom_set_cpu_ticks_per_us(esp_rom_get_xtal_freq() / 1000000); - stub_target_rom_uart_init(uart_num, UART_CLK_FREQ_ROM); + uint32_t clock = stub_target_get_apb_freq(); + stub_target_rom_uart_init(uart_num, clock); + + // Set UART clock source to APB, after this, baudrate needs to be set again to recalculate the clock divider + SET_PERI_REG_BITS(UART_CLK_CONF_REG(0), UART_SCLK_SEL_V, 1, UART_SCLK_SEL_S); + stub_target_uart_rominit_set_baudrate(0, 115200); + g_uart_print = true; } void stub_target_uart_rominit_set_baudrate(uint8_t uart_num, uint32_t baudrate) { - uint32_t clock = esp_rom_get_xtal_freq() << 4; - uint32_t divisor = clock / baudrate; - esp_rom_uart_div_modify(uart_num, divisor); - // TODO: Consider decimal part + stub_lib_delay_us(5 * 1000); + + uint32_t clk_div = (stub_target_get_apb_freq() << 4) / baudrate; + stub_target_uart_wait_idle(uart_num); + esp_rom_uart_div_modify(uart_num, clk_div); + + stub_lib_delay_us(5 * 1000); } diff --git a/src/target/esp32c5/CMakeLists.txt b/src/target/esp32c5/CMakeLists.txt index 1d1d1e8..12ef7f7 100644 --- a/src/target/esp32c5/CMakeLists.txt +++ b/src/target/esp32c5/CMakeLists.txt @@ -1,6 +1,7 @@ set(srcs src/uart.c src/usb_serial_jtag.c + src/clock.c ) add_library(${ESP_TARGET_LIB} STATIC ${srcs}) diff --git a/src/target/esp32c5/include/soc/pcr_reg.h b/src/target/esp32c5/include/soc/pcr_reg.h new file mode 100644 index 0000000..bf2cffa --- /dev/null +++ b/src/target/esp32c5/include/soc/pcr_reg.h @@ -0,0 +1,2638 @@ +/** + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 OR MIT + */ +#pragma once + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** PCR_UART0_CONF_REG register + * UART0 configuration register + */ +#define PCR_UART0_CONF_REG (DR_REG_PCR_BASE + 0x0) +/** PCR_UART0_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable uart0 apb clock + */ +#define PCR_UART0_CLK_EN (BIT(0)) +#define PCR_UART0_CLK_EN_M (PCR_UART0_CLK_EN_V << PCR_UART0_CLK_EN_S) +#define PCR_UART0_CLK_EN_V 0x00000001U +#define PCR_UART0_CLK_EN_S 0 +/** PCR_UART0_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset uart0 module + */ +#define PCR_UART0_RST_EN (BIT(1)) +#define PCR_UART0_RST_EN_M (PCR_UART0_RST_EN_V << PCR_UART0_RST_EN_S) +#define PCR_UART0_RST_EN_V 0x00000001U +#define PCR_UART0_RST_EN_S 1 +/** PCR_UART0_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset uart0 module + */ +#define PCR_UART0_READY (BIT(2)) +#define PCR_UART0_READY_M (PCR_UART0_READY_V << PCR_UART0_READY_S) +#define PCR_UART0_READY_V 0x00000001U +#define PCR_UART0_READY_S 2 + +/** PCR_UART0_SCLK_CONF_REG register + * UART0_SCLK configuration register + */ +#define PCR_UART0_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x4) +/** PCR_UART0_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the uart0 function clock. + */ +#define PCR_UART0_SCLK_DIV_A 0x0000003FU +#define PCR_UART0_SCLK_DIV_A_M (PCR_UART0_SCLK_DIV_A_V << PCR_UART0_SCLK_DIV_A_S) +#define PCR_UART0_SCLK_DIV_A_V 0x0000003FU +#define PCR_UART0_SCLK_DIV_A_S 0 +/** PCR_UART0_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the uart0 function clock. + */ +#define PCR_UART0_SCLK_DIV_B 0x0000003FU +#define PCR_UART0_SCLK_DIV_B_M (PCR_UART0_SCLK_DIV_B_V << PCR_UART0_SCLK_DIV_B_S) +#define PCR_UART0_SCLK_DIV_B_V 0x0000003FU +#define PCR_UART0_SCLK_DIV_B_S 6 +/** PCR_UART0_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the uart0 function clock. + */ +#define PCR_UART0_SCLK_DIV_NUM 0x000000FFU +#define PCR_UART0_SCLK_DIV_NUM_M (PCR_UART0_SCLK_DIV_NUM_V << PCR_UART0_SCLK_DIV_NUM_S) +#define PCR_UART0_SCLK_DIV_NUM_V 0x000000FFU +#define PCR_UART0_SCLK_DIV_NUM_S 12 +/** PCR_UART0_SCLK_SEL : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of UART0. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK + */ +#define PCR_UART0_SCLK_SEL 0x00000003U +#define PCR_UART0_SCLK_SEL_M (PCR_UART0_SCLK_SEL_V << PCR_UART0_SCLK_SEL_S) +#define PCR_UART0_SCLK_SEL_V 0x00000003U +#define PCR_UART0_SCLK_SEL_S 20 +/** PCR_UART0_SCLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable uart0 function clock + */ +#define PCR_UART0_SCLK_EN (BIT(22)) +#define PCR_UART0_SCLK_EN_M (PCR_UART0_SCLK_EN_V << PCR_UART0_SCLK_EN_S) +#define PCR_UART0_SCLK_EN_V 0x00000001U +#define PCR_UART0_SCLK_EN_S 22 + +/** PCR_UART0_PD_CTRL_REG register + * UART0 power control register + */ +#define PCR_UART0_PD_CTRL_REG (DR_REG_PCR_BASE + 0x8) +/** PCR_UART0_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1; + * Set this bit to force power up UART0 memory. + */ +#define PCR_UART0_MEM_FORCE_PU (BIT(1)) +#define PCR_UART0_MEM_FORCE_PU_M (PCR_UART0_MEM_FORCE_PU_V << PCR_UART0_MEM_FORCE_PU_S) +#define PCR_UART0_MEM_FORCE_PU_V 0x00000001U +#define PCR_UART0_MEM_FORCE_PU_S 1 +/** PCR_UART0_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; + * Set this bit to force power down UART0 memory. + */ +#define PCR_UART0_MEM_FORCE_PD (BIT(2)) +#define PCR_UART0_MEM_FORCE_PD_M (PCR_UART0_MEM_FORCE_PD_V << PCR_UART0_MEM_FORCE_PD_S) +#define PCR_UART0_MEM_FORCE_PD_V 0x00000001U +#define PCR_UART0_MEM_FORCE_PD_S 2 + +/** PCR_UART1_CONF_REG register + * UART1 configuration register + */ +#define PCR_UART1_CONF_REG (DR_REG_PCR_BASE + 0xc) +/** PCR_UART1_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable uart1 apb clock + */ +#define PCR_UART1_CLK_EN (BIT(0)) +#define PCR_UART1_CLK_EN_M (PCR_UART1_CLK_EN_V << PCR_UART1_CLK_EN_S) +#define PCR_UART1_CLK_EN_V 0x00000001U +#define PCR_UART1_CLK_EN_S 0 +/** PCR_UART1_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset uart1 module + */ +#define PCR_UART1_RST_EN (BIT(1)) +#define PCR_UART1_RST_EN_M (PCR_UART1_RST_EN_V << PCR_UART1_RST_EN_S) +#define PCR_UART1_RST_EN_V 0x00000001U +#define PCR_UART1_RST_EN_S 1 +/** PCR_UART1_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset uart1 module + */ +#define PCR_UART1_READY (BIT(2)) +#define PCR_UART1_READY_M (PCR_UART1_READY_V << PCR_UART1_READY_S) +#define PCR_UART1_READY_V 0x00000001U +#define PCR_UART1_READY_S 2 + +/** PCR_UART1_SCLK_CONF_REG register + * UART1_SCLK configuration register + */ +#define PCR_UART1_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x10) +/** PCR_UART1_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the uart1 function clock. + */ +#define PCR_UART1_SCLK_DIV_A 0x0000003FU +#define PCR_UART1_SCLK_DIV_A_M (PCR_UART1_SCLK_DIV_A_V << PCR_UART1_SCLK_DIV_A_S) +#define PCR_UART1_SCLK_DIV_A_V 0x0000003FU +#define PCR_UART1_SCLK_DIV_A_S 0 +/** PCR_UART1_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the uart1 function clock. + */ +#define PCR_UART1_SCLK_DIV_B 0x0000003FU +#define PCR_UART1_SCLK_DIV_B_M (PCR_UART1_SCLK_DIV_B_V << PCR_UART1_SCLK_DIV_B_S) +#define PCR_UART1_SCLK_DIV_B_V 0x0000003FU +#define PCR_UART1_SCLK_DIV_B_S 6 +/** PCR_UART1_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the uart1 function clock. + */ +#define PCR_UART1_SCLK_DIV_NUM 0x000000FFU +#define PCR_UART1_SCLK_DIV_NUM_M (PCR_UART1_SCLK_DIV_NUM_V << PCR_UART1_SCLK_DIV_NUM_S) +#define PCR_UART1_SCLK_DIV_NUM_V 0x000000FFU +#define PCR_UART1_SCLK_DIV_NUM_S 12 +/** PCR_UART1_SCLK_SEL : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of UART1. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK + */ +#define PCR_UART1_SCLK_SEL 0x00000003U +#define PCR_UART1_SCLK_SEL_M (PCR_UART1_SCLK_SEL_V << PCR_UART1_SCLK_SEL_S) +#define PCR_UART1_SCLK_SEL_V 0x00000003U +#define PCR_UART1_SCLK_SEL_S 20 +/** PCR_UART1_SCLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable uart0 function clock + */ +#define PCR_UART1_SCLK_EN (BIT(22)) +#define PCR_UART1_SCLK_EN_M (PCR_UART1_SCLK_EN_V << PCR_UART1_SCLK_EN_S) +#define PCR_UART1_SCLK_EN_V 0x00000001U +#define PCR_UART1_SCLK_EN_S 22 + +/** PCR_UART1_PD_CTRL_REG register + * UART1 power control register + */ +#define PCR_UART1_PD_CTRL_REG (DR_REG_PCR_BASE + 0x14) +/** PCR_UART1_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1; + * Set this bit to force power up UART1 memory. + */ +#define PCR_UART1_MEM_FORCE_PU (BIT(1)) +#define PCR_UART1_MEM_FORCE_PU_M (PCR_UART1_MEM_FORCE_PU_V << PCR_UART1_MEM_FORCE_PU_S) +#define PCR_UART1_MEM_FORCE_PU_V 0x00000001U +#define PCR_UART1_MEM_FORCE_PU_S 1 +/** PCR_UART1_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; + * Set this bit to force power down UART1 memory. + */ +#define PCR_UART1_MEM_FORCE_PD (BIT(2)) +#define PCR_UART1_MEM_FORCE_PD_M (PCR_UART1_MEM_FORCE_PD_V << PCR_UART1_MEM_FORCE_PD_S) +#define PCR_UART1_MEM_FORCE_PD_V 0x00000001U +#define PCR_UART1_MEM_FORCE_PD_S 2 + +/** PCR_MSPI_CONF_REG register + * MSPI configuration register + */ +#define PCR_MSPI_CONF_REG (DR_REG_PCR_BASE + 0x18) +/** PCR_MSPI_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable mspi apb clock and mspi pll clock + */ +#define PCR_MSPI_CLK_EN (BIT(0)) +#define PCR_MSPI_CLK_EN_M (PCR_MSPI_CLK_EN_V << PCR_MSPI_CLK_EN_S) +#define PCR_MSPI_CLK_EN_V 0x00000001U +#define PCR_MSPI_CLK_EN_S 0 +/** PCR_MSPI_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset mspi module + */ +#define PCR_MSPI_RST_EN (BIT(1)) +#define PCR_MSPI_RST_EN_M (PCR_MSPI_RST_EN_V << PCR_MSPI_RST_EN_S) +#define PCR_MSPI_RST_EN_V 0x00000001U +#define PCR_MSPI_RST_EN_S 1 +/** PCR_MSPI_PLL_CLK_EN : R/W; bitpos: [2]; default: 1; + * Set 1 to enable mspi pll clock + */ +#define PCR_MSPI_PLL_CLK_EN (BIT(2)) +#define PCR_MSPI_PLL_CLK_EN_M (PCR_MSPI_PLL_CLK_EN_V << PCR_MSPI_PLL_CLK_EN_S) +#define PCR_MSPI_PLL_CLK_EN_V 0x00000001U +#define PCR_MSPI_PLL_CLK_EN_S 2 +/** PCR_MSPI_READY : RO; bitpos: [3]; default: 1; + * Query this field after reset mspi module + */ +#define PCR_MSPI_READY (BIT(3)) +#define PCR_MSPI_READY_M (PCR_MSPI_READY_V << PCR_MSPI_READY_S) +#define PCR_MSPI_READY_V 0x00000001U +#define PCR_MSPI_READY_S 3 + +/** PCR_MSPI_CLK_CONF_REG register + * MSPI_CLK configuration register + */ +#define PCR_MSPI_CLK_CONF_REG (DR_REG_PCR_BASE + 0x1c) +/** PCR_MSPI_FAST_DIV_NUM : R/W; bitpos: [7:0]; default: 0; + * Set as one within (0,1,2) to generate div1(default)/div2/div4 of low-speed + * clock-source to drive clk_mspi_fast. Only available when the clck-source is a + * low-speed clock-source such as XTAL/FOSC. + */ +#define PCR_MSPI_FAST_DIV_NUM 0x000000FFU +#define PCR_MSPI_FAST_DIV_NUM_M (PCR_MSPI_FAST_DIV_NUM_V << PCR_MSPI_FAST_DIV_NUM_S) +#define PCR_MSPI_FAST_DIV_NUM_V 0x000000FFU +#define PCR_MSPI_FAST_DIV_NUM_S 0 +/** PCR_MSPI_FUNC_CLK_SEL : R/W; bitpos: [9:8]; default: 0; + * Configures the clock source for MSPI. + * 0(default): XTAL_CLK + * 1 RC_FAST_CLK + * 2: PLL_F480M_CLK + */ +#define PCR_MSPI_FUNC_CLK_SEL 0x00000003U +#define PCR_MSPI_FUNC_CLK_SEL_M (PCR_MSPI_FUNC_CLK_SEL_V << PCR_MSPI_FUNC_CLK_SEL_S) +#define PCR_MSPI_FUNC_CLK_SEL_V 0x00000003U +#define PCR_MSPI_FUNC_CLK_SEL_S 8 +/** PCR_MSPI_FUNC_CLK_EN : R/W; bitpos: [10]; default: 1; + * Set 1 to enable mspi func clock + */ +#define PCR_MSPI_FUNC_CLK_EN (BIT(10)) +#define PCR_MSPI_FUNC_CLK_EN_M (PCR_MSPI_FUNC_CLK_EN_V << PCR_MSPI_FUNC_CLK_EN_S) +#define PCR_MSPI_FUNC_CLK_EN_V 0x00000001U +#define PCR_MSPI_FUNC_CLK_EN_S 10 +/** PCR_MSPI_AXI_RST_EN : R/W; bitpos: [11]; default: 0; + * Set 1 to reset axi_clock domain of mspi module + */ +#define PCR_MSPI_AXI_RST_EN (BIT(11)) +#define PCR_MSPI_AXI_RST_EN_M (PCR_MSPI_AXI_RST_EN_V << PCR_MSPI_AXI_RST_EN_S) +#define PCR_MSPI_AXI_RST_EN_V 0x00000001U +#define PCR_MSPI_AXI_RST_EN_S 11 + +/** PCR_I2C_CONF_REG register + * I2C configuration register + */ +#define PCR_I2C_CONF_REG (DR_REG_PCR_BASE + 0x20) +/** PCR_I2C_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable i2c apb clock + */ +#define PCR_I2C_CLK_EN (BIT(0)) +#define PCR_I2C_CLK_EN_M (PCR_I2C_CLK_EN_V << PCR_I2C_CLK_EN_S) +#define PCR_I2C_CLK_EN_V 0x00000001U +#define PCR_I2C_CLK_EN_S 0 +/** PCR_I2C_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset i2c module + */ +#define PCR_I2C_RST_EN (BIT(1)) +#define PCR_I2C_RST_EN_M (PCR_I2C_RST_EN_V << PCR_I2C_RST_EN_S) +#define PCR_I2C_RST_EN_V 0x00000001U +#define PCR_I2C_RST_EN_S 1 + +/** PCR_I2C_SCLK_CONF_REG register + * I2C_SCLK configuration register + */ +#define PCR_I2C_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x24) +/** PCR_I2C_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the i2c function clock. + */ +#define PCR_I2C_SCLK_DIV_A 0x0000003FU +#define PCR_I2C_SCLK_DIV_A_M (PCR_I2C_SCLK_DIV_A_V << PCR_I2C_SCLK_DIV_A_S) +#define PCR_I2C_SCLK_DIV_A_V 0x0000003FU +#define PCR_I2C_SCLK_DIV_A_S 0 +/** PCR_I2C_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the i2c function clock. + */ +#define PCR_I2C_SCLK_DIV_B 0x0000003FU +#define PCR_I2C_SCLK_DIV_B_M (PCR_I2C_SCLK_DIV_B_V << PCR_I2C_SCLK_DIV_B_S) +#define PCR_I2C_SCLK_DIV_B_V 0x0000003FU +#define PCR_I2C_SCLK_DIV_B_S 6 +/** PCR_I2C_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the i2c function clock. + */ +#define PCR_I2C_SCLK_DIV_NUM 0x000000FFU +#define PCR_I2C_SCLK_DIV_NUM_M (PCR_I2C_SCLK_DIV_NUM_V << PCR_I2C_SCLK_DIV_NUM_S) +#define PCR_I2C_SCLK_DIV_NUM_V 0x000000FFU +#define PCR_I2C_SCLK_DIV_NUM_S 12 +/** PCR_I2C_SCLK_SEL : R/W; bitpos: [20]; default: 0; + * Configures the clock source of I2C. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + */ +#define PCR_I2C_SCLK_SEL (BIT(20)) +#define PCR_I2C_SCLK_SEL_M (PCR_I2C_SCLK_SEL_V << PCR_I2C_SCLK_SEL_S) +#define PCR_I2C_SCLK_SEL_V 0x00000001U +#define PCR_I2C_SCLK_SEL_S 20 +/** PCR_I2C_SCLK_EN : R/W; bitpos: [22]; default: 0; + * Set 1 to enable i2c function clock + */ +#define PCR_I2C_SCLK_EN (BIT(22)) +#define PCR_I2C_SCLK_EN_M (PCR_I2C_SCLK_EN_V << PCR_I2C_SCLK_EN_S) +#define PCR_I2C_SCLK_EN_V 0x00000001U +#define PCR_I2C_SCLK_EN_S 22 + +/** PCR_TWAI0_CONF_REG register + * TWAI0 configuration register + */ +#define PCR_TWAI0_CONF_REG (DR_REG_PCR_BASE + 0x28) +/** PCR_TWAI0_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable twai0 apb clock + */ +#define PCR_TWAI0_CLK_EN (BIT(0)) +#define PCR_TWAI0_CLK_EN_M (PCR_TWAI0_CLK_EN_V << PCR_TWAI0_CLK_EN_S) +#define PCR_TWAI0_CLK_EN_V 0x00000001U +#define PCR_TWAI0_CLK_EN_S 0 +/** PCR_TWAI0_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset twai0 module + */ +#define PCR_TWAI0_RST_EN (BIT(1)) +#define PCR_TWAI0_RST_EN_M (PCR_TWAI0_RST_EN_V << PCR_TWAI0_RST_EN_S) +#define PCR_TWAI0_RST_EN_V 0x00000001U +#define PCR_TWAI0_RST_EN_S 1 +/** PCR_TWAI0_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset twai0 module + */ +#define PCR_TWAI0_READY (BIT(2)) +#define PCR_TWAI0_READY_M (PCR_TWAI0_READY_V << PCR_TWAI0_READY_S) +#define PCR_TWAI0_READY_V 0x00000001U +#define PCR_TWAI0_READY_S 2 + +/** PCR_TWAI0_FUNC_CLK_CONF_REG register + * TWAI0_FUNC_CLK configuration register + */ +#define PCR_TWAI0_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x2c) +/** PCR_TWAI0_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0; + * Configures the clock source of TWAI0. + * 0 (default): XTAL_CLK + * 1: PLL_F80M_CLK + */ +#define PCR_TWAI0_FUNC_CLK_SEL (BIT(20)) +#define PCR_TWAI0_FUNC_CLK_SEL_M (PCR_TWAI0_FUNC_CLK_SEL_V << PCR_TWAI0_FUNC_CLK_SEL_S) +#define PCR_TWAI0_FUNC_CLK_SEL_V 0x00000001U +#define PCR_TWAI0_FUNC_CLK_SEL_S 20 +/** PCR_TWAI0_FUNC_CLK_EN : R/W; bitpos: [22]; default: 0; + * Set 1 to enable twai0 function clock + */ +#define PCR_TWAI0_FUNC_CLK_EN (BIT(22)) +#define PCR_TWAI0_FUNC_CLK_EN_M (PCR_TWAI0_FUNC_CLK_EN_V << PCR_TWAI0_FUNC_CLK_EN_S) +#define PCR_TWAI0_FUNC_CLK_EN_V 0x00000001U +#define PCR_TWAI0_FUNC_CLK_EN_S 22 + +/** PCR_TWAI1_CONF_REG register + * TWAI1 configuration register + */ +#define PCR_TWAI1_CONF_REG (DR_REG_PCR_BASE + 0x30) +/** PCR_TWAI1_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable twai1 apb clock + */ +#define PCR_TWAI1_CLK_EN (BIT(0)) +#define PCR_TWAI1_CLK_EN_M (PCR_TWAI1_CLK_EN_V << PCR_TWAI1_CLK_EN_S) +#define PCR_TWAI1_CLK_EN_V 0x00000001U +#define PCR_TWAI1_CLK_EN_S 0 +/** PCR_TWAI1_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset twai1 module + */ +#define PCR_TWAI1_RST_EN (BIT(1)) +#define PCR_TWAI1_RST_EN_M (PCR_TWAI1_RST_EN_V << PCR_TWAI1_RST_EN_S) +#define PCR_TWAI1_RST_EN_V 0x00000001U +#define PCR_TWAI1_RST_EN_S 1 +/** PCR_TWAI1_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset twai1 module + */ +#define PCR_TWAI1_READY (BIT(2)) +#define PCR_TWAI1_READY_M (PCR_TWAI1_READY_V << PCR_TWAI1_READY_S) +#define PCR_TWAI1_READY_V 0x00000001U +#define PCR_TWAI1_READY_S 2 + +/** PCR_TWAI1_FUNC_CLK_CONF_REG register + * TWAI1_FUNC_CLK configuration register + */ +#define PCR_TWAI1_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x34) +/** PCR_TWAI1_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0; + * Configures the clock source of TWAI1. + * 0 (default): XTAL_CLK + * 1: PLL_F80M_CLK + */ +#define PCR_TWAI1_FUNC_CLK_SEL (BIT(20)) +#define PCR_TWAI1_FUNC_CLK_SEL_M (PCR_TWAI1_FUNC_CLK_SEL_V << PCR_TWAI1_FUNC_CLK_SEL_S) +#define PCR_TWAI1_FUNC_CLK_SEL_V 0x00000001U +#define PCR_TWAI1_FUNC_CLK_SEL_S 20 +/** PCR_TWAI1_FUNC_CLK_EN : R/W; bitpos: [22]; default: 0; + * Set 1 to enable twai1 function clock + */ +#define PCR_TWAI1_FUNC_CLK_EN (BIT(22)) +#define PCR_TWAI1_FUNC_CLK_EN_M (PCR_TWAI1_FUNC_CLK_EN_V << PCR_TWAI1_FUNC_CLK_EN_S) +#define PCR_TWAI1_FUNC_CLK_EN_V 0x00000001U +#define PCR_TWAI1_FUNC_CLK_EN_S 22 + +/** PCR_UHCI_CONF_REG register + * UHCI configuration register + */ +#define PCR_UHCI_CONF_REG (DR_REG_PCR_BASE + 0x38) +/** PCR_UHCI_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable uhci clock + */ +#define PCR_UHCI_CLK_EN (BIT(0)) +#define PCR_UHCI_CLK_EN_M (PCR_UHCI_CLK_EN_V << PCR_UHCI_CLK_EN_S) +#define PCR_UHCI_CLK_EN_V 0x00000001U +#define PCR_UHCI_CLK_EN_S 0 +/** PCR_UHCI_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset uhci module + */ +#define PCR_UHCI_RST_EN (BIT(1)) +#define PCR_UHCI_RST_EN_M (PCR_UHCI_RST_EN_V << PCR_UHCI_RST_EN_S) +#define PCR_UHCI_RST_EN_V 0x00000001U +#define PCR_UHCI_RST_EN_S 1 +/** PCR_UHCI_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset uhci module + */ +#define PCR_UHCI_READY (BIT(2)) +#define PCR_UHCI_READY_M (PCR_UHCI_READY_V << PCR_UHCI_READY_S) +#define PCR_UHCI_READY_V 0x00000001U +#define PCR_UHCI_READY_S 2 + +/** PCR_RMT_CONF_REG register + * RMT configuration register + */ +#define PCR_RMT_CONF_REG (DR_REG_PCR_BASE + 0x3c) +/** PCR_RMT_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable rmt apb clock + */ +#define PCR_RMT_CLK_EN (BIT(0)) +#define PCR_RMT_CLK_EN_M (PCR_RMT_CLK_EN_V << PCR_RMT_CLK_EN_S) +#define PCR_RMT_CLK_EN_V 0x00000001U +#define PCR_RMT_CLK_EN_S 0 +/** PCR_RMT_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset rmt module + */ +#define PCR_RMT_RST_EN (BIT(1)) +#define PCR_RMT_RST_EN_M (PCR_RMT_RST_EN_V << PCR_RMT_RST_EN_S) +#define PCR_RMT_RST_EN_V 0x00000001U +#define PCR_RMT_RST_EN_S 1 + +/** PCR_RMT_SCLK_CONF_REG register + * RMT_SCLK configuration register + */ +#define PCR_RMT_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x40) +/** PCR_RMT_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the rmt function clock. + */ +#define PCR_RMT_SCLK_DIV_A 0x0000003FU +#define PCR_RMT_SCLK_DIV_A_M (PCR_RMT_SCLK_DIV_A_V << PCR_RMT_SCLK_DIV_A_S) +#define PCR_RMT_SCLK_DIV_A_V 0x0000003FU +#define PCR_RMT_SCLK_DIV_A_S 0 +/** PCR_RMT_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the rmt function clock. + */ +#define PCR_RMT_SCLK_DIV_B 0x0000003FU +#define PCR_RMT_SCLK_DIV_B_M (PCR_RMT_SCLK_DIV_B_V << PCR_RMT_SCLK_DIV_B_S) +#define PCR_RMT_SCLK_DIV_B_V 0x0000003FU +#define PCR_RMT_SCLK_DIV_B_S 6 +/** PCR_RMT_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 1; + * The integral part of the frequency divider factor of the rmt function clock. + */ +#define PCR_RMT_SCLK_DIV_NUM 0x000000FFU +#define PCR_RMT_SCLK_DIV_NUM_M (PCR_RMT_SCLK_DIV_NUM_V << PCR_RMT_SCLK_DIV_NUM_S) +#define PCR_RMT_SCLK_DIV_NUM_V 0x000000FFU +#define PCR_RMT_SCLK_DIV_NUM_S 12 +/** PCR_RMT_SCLK_SEL : R/W; bitpos: [21:20]; default: 1; + * Configures the clock source of RMT. + * 0: XTAL_CLK + * 1 (default): RC_FAST_CLK + * 2: PLL_F80M_CLK + */ +#define PCR_RMT_SCLK_SEL 0x00000003U +#define PCR_RMT_SCLK_SEL_M (PCR_RMT_SCLK_SEL_V << PCR_RMT_SCLK_SEL_S) +#define PCR_RMT_SCLK_SEL_V 0x00000003U +#define PCR_RMT_SCLK_SEL_S 20 +/** PCR_RMT_SCLK_EN : R/W; bitpos: [22]; default: 0; + * Set 1 to enable rmt function clock + */ +#define PCR_RMT_SCLK_EN (BIT(22)) +#define PCR_RMT_SCLK_EN_M (PCR_RMT_SCLK_EN_V << PCR_RMT_SCLK_EN_S) +#define PCR_RMT_SCLK_EN_V 0x00000001U +#define PCR_RMT_SCLK_EN_S 22 + +/** PCR_RMT_PD_CTRL_REG register + * RMT power control register + */ +#define PCR_RMT_PD_CTRL_REG (DR_REG_PCR_BASE + 0x44) +/** PCR_RMT_MEM_FORCE_PU : R/W; bitpos: [1]; default: 0; + * Set this bit to force power up RMT memory. + */ +#define PCR_RMT_MEM_FORCE_PU (BIT(1)) +#define PCR_RMT_MEM_FORCE_PU_M (PCR_RMT_MEM_FORCE_PU_V << PCR_RMT_MEM_FORCE_PU_S) +#define PCR_RMT_MEM_FORCE_PU_V 0x00000001U +#define PCR_RMT_MEM_FORCE_PU_S 1 +/** PCR_RMT_MEM_FORCE_PD : R/W; bitpos: [2]; default: 1; + * Set this bit to force power down RMT memory. + */ +#define PCR_RMT_MEM_FORCE_PD (BIT(2)) +#define PCR_RMT_MEM_FORCE_PD_M (PCR_RMT_MEM_FORCE_PD_V << PCR_RMT_MEM_FORCE_PD_S) +#define PCR_RMT_MEM_FORCE_PD_V 0x00000001U +#define PCR_RMT_MEM_FORCE_PD_S 2 + +/** PCR_LEDC_CONF_REG register + * LEDC configuration register + */ +#define PCR_LEDC_CONF_REG (DR_REG_PCR_BASE + 0x48) +/** PCR_LEDC_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable ledc apb clock + */ +#define PCR_LEDC_CLK_EN (BIT(0)) +#define PCR_LEDC_CLK_EN_M (PCR_LEDC_CLK_EN_V << PCR_LEDC_CLK_EN_S) +#define PCR_LEDC_CLK_EN_V 0x00000001U +#define PCR_LEDC_CLK_EN_S 0 +/** PCR_LEDC_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset ledc module + */ +#define PCR_LEDC_RST_EN (BIT(1)) +#define PCR_LEDC_RST_EN_M (PCR_LEDC_RST_EN_V << PCR_LEDC_RST_EN_S) +#define PCR_LEDC_RST_EN_V 0x00000001U +#define PCR_LEDC_RST_EN_S 1 +/** PCR_LEDC_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset ledc module + */ +#define PCR_LEDC_READY (BIT(2)) +#define PCR_LEDC_READY_M (PCR_LEDC_READY_V << PCR_LEDC_READY_S) +#define PCR_LEDC_READY_V 0x00000001U +#define PCR_LEDC_READY_S 2 + +/** PCR_LEDC_SCLK_CONF_REG register + * LEDC_SCLK configuration register + */ +#define PCR_LEDC_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x4c) +/** PCR_LEDC_SCLK_SEL : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of LEDC. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK + */ +#define PCR_LEDC_SCLK_SEL 0x00000003U +#define PCR_LEDC_SCLK_SEL_M (PCR_LEDC_SCLK_SEL_V << PCR_LEDC_SCLK_SEL_S) +#define PCR_LEDC_SCLK_SEL_V 0x00000003U +#define PCR_LEDC_SCLK_SEL_S 20 +/** PCR_LEDC_SCLK_EN : R/W; bitpos: [22]; default: 0; + * Set 1 to enable ledc function clock + */ +#define PCR_LEDC_SCLK_EN (BIT(22)) +#define PCR_LEDC_SCLK_EN_M (PCR_LEDC_SCLK_EN_V << PCR_LEDC_SCLK_EN_S) +#define PCR_LEDC_SCLK_EN_V 0x00000001U +#define PCR_LEDC_SCLK_EN_S 22 + +/** PCR_LEDC_PD_CTRL_REG register + * LEDC power control register + */ +#define PCR_LEDC_PD_CTRL_REG (DR_REG_PCR_BASE + 0x50) +/** PCR_LEDC_MEM_FORCE_PU : R/W; bitpos: [1]; default: 0; + * Set this bit to force power up LEDC memory. + */ +#define PCR_LEDC_MEM_FORCE_PU (BIT(1)) +#define PCR_LEDC_MEM_FORCE_PU_M (PCR_LEDC_MEM_FORCE_PU_V << PCR_LEDC_MEM_FORCE_PU_S) +#define PCR_LEDC_MEM_FORCE_PU_V 0x00000001U +#define PCR_LEDC_MEM_FORCE_PU_S 1 +/** PCR_LEDC_MEM_FORCE_PD : R/W; bitpos: [2]; default: 1; + * Set this bit to force power down LEDC memory. + */ +#define PCR_LEDC_MEM_FORCE_PD (BIT(2)) +#define PCR_LEDC_MEM_FORCE_PD_M (PCR_LEDC_MEM_FORCE_PD_V << PCR_LEDC_MEM_FORCE_PD_S) +#define PCR_LEDC_MEM_FORCE_PD_V 0x00000001U +#define PCR_LEDC_MEM_FORCE_PD_S 2 + +/** PCR_TIMERGROUP0_CONF_REG register + * TIMERGROUP0 configuration register + */ +#define PCR_TIMERGROUP0_CONF_REG (DR_REG_PCR_BASE + 0x54) +/** PCR_TG0_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable timer_group0 apb clock + */ +#define PCR_TG0_CLK_EN (BIT(0)) +#define PCR_TG0_CLK_EN_M (PCR_TG0_CLK_EN_V << PCR_TG0_CLK_EN_S) +#define PCR_TG0_CLK_EN_V 0x00000001U +#define PCR_TG0_CLK_EN_S 0 +/** PCR_TG0_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset timer_group0 module + */ +#define PCR_TG0_RST_EN (BIT(1)) +#define PCR_TG0_RST_EN_M (PCR_TG0_RST_EN_V << PCR_TG0_RST_EN_S) +#define PCR_TG0_RST_EN_V 0x00000001U +#define PCR_TG0_RST_EN_S 1 +/** PCR_TG0_WDT_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset timer_group0 wdt module + */ +#define PCR_TG0_WDT_READY (BIT(2)) +#define PCR_TG0_WDT_READY_M (PCR_TG0_WDT_READY_V << PCR_TG0_WDT_READY_S) +#define PCR_TG0_WDT_READY_V 0x00000001U +#define PCR_TG0_WDT_READY_S 2 +/** PCR_TG0_TIMER0_READY : RO; bitpos: [3]; default: 1; + * Query this field after reset timer_group0 timer0 module + */ +#define PCR_TG0_TIMER0_READY (BIT(3)) +#define PCR_TG0_TIMER0_READY_M (PCR_TG0_TIMER0_READY_V << PCR_TG0_TIMER0_READY_S) +#define PCR_TG0_TIMER0_READY_V 0x00000001U +#define PCR_TG0_TIMER0_READY_S 3 +/** PCR_TG0_TIMER1_READY : RO; bitpos: [4]; default: 1; + * Query this field after reset timer_group0 timer1 module + */ +#define PCR_TG0_TIMER1_READY (BIT(4)) +#define PCR_TG0_TIMER1_READY_M (PCR_TG0_TIMER1_READY_V << PCR_TG0_TIMER1_READY_S) +#define PCR_TG0_TIMER1_READY_V 0x00000001U +#define PCR_TG0_TIMER1_READY_S 4 + +/** PCR_TIMERGROUP0_TIMER_CLK_CONF_REG register + * TIMERGROUP0_TIMER_CLK configuration register + */ +#define PCR_TIMERGROUP0_TIMER_CLK_CONF_REG (DR_REG_PCR_BASE + 0x58) +/** PCR_TG0_TIMER_CLK_SEL : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of general-purpose timers in Timer Group 0. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK + */ +#define PCR_TG0_TIMER_CLK_SEL 0x00000003U +#define PCR_TG0_TIMER_CLK_SEL_M (PCR_TG0_TIMER_CLK_SEL_V << PCR_TG0_TIMER_CLK_SEL_S) +#define PCR_TG0_TIMER_CLK_SEL_V 0x00000003U +#define PCR_TG0_TIMER_CLK_SEL_S 20 +/** PCR_TG0_TIMER_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group0 timer clock + */ +#define PCR_TG0_TIMER_CLK_EN (BIT(22)) +#define PCR_TG0_TIMER_CLK_EN_M (PCR_TG0_TIMER_CLK_EN_V << PCR_TG0_TIMER_CLK_EN_S) +#define PCR_TG0_TIMER_CLK_EN_V 0x00000001U +#define PCR_TG0_TIMER_CLK_EN_S 22 + +/** PCR_TIMERGROUP0_WDT_CLK_CONF_REG register + * TIMERGROUP0_WDT_CLK configuration register + */ +#define PCR_TIMERGROUP0_WDT_CLK_CONF_REG (DR_REG_PCR_BASE + 0x5c) +/** PCR_TG0_WDT_CLK_SEL : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of WDT in Timer Group 0. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK + */ +#define PCR_TG0_WDT_CLK_SEL 0x00000003U +#define PCR_TG0_WDT_CLK_SEL_M (PCR_TG0_WDT_CLK_SEL_V << PCR_TG0_WDT_CLK_SEL_S) +#define PCR_TG0_WDT_CLK_SEL_V 0x00000003U +#define PCR_TG0_WDT_CLK_SEL_S 20 +/** PCR_TG0_WDT_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group0 wdt clock + */ +#define PCR_TG0_WDT_CLK_EN (BIT(22)) +#define PCR_TG0_WDT_CLK_EN_M (PCR_TG0_WDT_CLK_EN_V << PCR_TG0_WDT_CLK_EN_S) +#define PCR_TG0_WDT_CLK_EN_V 0x00000001U +#define PCR_TG0_WDT_CLK_EN_S 22 + +/** PCR_TIMERGROUP1_CONF_REG register + * TIMERGROUP1 configuration register + */ +#define PCR_TIMERGROUP1_CONF_REG (DR_REG_PCR_BASE + 0x60) +/** PCR_TG1_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable timer_group1 apb clock + */ +#define PCR_TG1_CLK_EN (BIT(0)) +#define PCR_TG1_CLK_EN_M (PCR_TG1_CLK_EN_V << PCR_TG1_CLK_EN_S) +#define PCR_TG1_CLK_EN_V 0x00000001U +#define PCR_TG1_CLK_EN_S 0 +/** PCR_TG1_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset timer_group1 module + */ +#define PCR_TG1_RST_EN (BIT(1)) +#define PCR_TG1_RST_EN_M (PCR_TG1_RST_EN_V << PCR_TG1_RST_EN_S) +#define PCR_TG1_RST_EN_V 0x00000001U +#define PCR_TG1_RST_EN_S 1 +/** PCR_TG1_WDT_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset timer_group1 wdt module + */ +#define PCR_TG1_WDT_READY (BIT(2)) +#define PCR_TG1_WDT_READY_M (PCR_TG1_WDT_READY_V << PCR_TG1_WDT_READY_S) +#define PCR_TG1_WDT_READY_V 0x00000001U +#define PCR_TG1_WDT_READY_S 2 +/** PCR_TG1_TIMER0_READY : RO; bitpos: [3]; default: 1; + * Query this field after reset timer_group1 timer0 module + */ +#define PCR_TG1_TIMER0_READY (BIT(3)) +#define PCR_TG1_TIMER0_READY_M (PCR_TG1_TIMER0_READY_V << PCR_TG1_TIMER0_READY_S) +#define PCR_TG1_TIMER0_READY_V 0x00000001U +#define PCR_TG1_TIMER0_READY_S 3 +/** PCR_TG1_TIMER1_READY : RO; bitpos: [4]; default: 1; + * Query this field after reset timer_group1 timer1 module + */ +#define PCR_TG1_TIMER1_READY (BIT(4)) +#define PCR_TG1_TIMER1_READY_M (PCR_TG1_TIMER1_READY_V << PCR_TG1_TIMER1_READY_S) +#define PCR_TG1_TIMER1_READY_V 0x00000001U +#define PCR_TG1_TIMER1_READY_S 4 + +/** PCR_TIMERGROUP1_TIMER_CLK_CONF_REG register + * TIMERGROUP1_TIMER_CLK configuration register + */ +#define PCR_TIMERGROUP1_TIMER_CLK_CONF_REG (DR_REG_PCR_BASE + 0x64) +/** PCR_TG1_TIMER_CLK_SEL : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of general-purpose timers in Timer Group 1. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK + */ +#define PCR_TG1_TIMER_CLK_SEL 0x00000003U +#define PCR_TG1_TIMER_CLK_SEL_M (PCR_TG1_TIMER_CLK_SEL_V << PCR_TG1_TIMER_CLK_SEL_S) +#define PCR_TG1_TIMER_CLK_SEL_V 0x00000003U +#define PCR_TG1_TIMER_CLK_SEL_S 20 +/** PCR_TG1_TIMER_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group1 timer clock + */ +#define PCR_TG1_TIMER_CLK_EN (BIT(22)) +#define PCR_TG1_TIMER_CLK_EN_M (PCR_TG1_TIMER_CLK_EN_V << PCR_TG1_TIMER_CLK_EN_S) +#define PCR_TG1_TIMER_CLK_EN_V 0x00000001U +#define PCR_TG1_TIMER_CLK_EN_S 22 + +/** PCR_TIMERGROUP1_WDT_CLK_CONF_REG register + * TIMERGROUP1_WDT_CLK configuration register + */ +#define PCR_TIMERGROUP1_WDT_CLK_CONF_REG (DR_REG_PCR_BASE + 0x68) +/** PCR_TG1_WDT_CLK_SEL : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of WDT in Timer Group 1. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK + */ +#define PCR_TG1_WDT_CLK_SEL 0x00000003U +#define PCR_TG1_WDT_CLK_SEL_M (PCR_TG1_WDT_CLK_SEL_V << PCR_TG1_WDT_CLK_SEL_S) +#define PCR_TG1_WDT_CLK_SEL_V 0x00000003U +#define PCR_TG1_WDT_CLK_SEL_S 20 +/** PCR_TG1_WDT_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group0 wdt clock + */ +#define PCR_TG1_WDT_CLK_EN (BIT(22)) +#define PCR_TG1_WDT_CLK_EN_M (PCR_TG1_WDT_CLK_EN_V << PCR_TG1_WDT_CLK_EN_S) +#define PCR_TG1_WDT_CLK_EN_V 0x00000001U +#define PCR_TG1_WDT_CLK_EN_S 22 + +/** PCR_SYSTIMER_CONF_REG register + * SYSTIMER configuration register + */ +#define PCR_SYSTIMER_CONF_REG (DR_REG_PCR_BASE + 0x6c) +/** PCR_SYSTIMER_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable systimer apb clock + */ +#define PCR_SYSTIMER_CLK_EN (BIT(0)) +#define PCR_SYSTIMER_CLK_EN_M (PCR_SYSTIMER_CLK_EN_V << PCR_SYSTIMER_CLK_EN_S) +#define PCR_SYSTIMER_CLK_EN_V 0x00000001U +#define PCR_SYSTIMER_CLK_EN_S 0 +/** PCR_SYSTIMER_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset systimer module + */ +#define PCR_SYSTIMER_RST_EN (BIT(1)) +#define PCR_SYSTIMER_RST_EN_M (PCR_SYSTIMER_RST_EN_V << PCR_SYSTIMER_RST_EN_S) +#define PCR_SYSTIMER_RST_EN_V 0x00000001U +#define PCR_SYSTIMER_RST_EN_S 1 +/** PCR_SYSTIMER_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset systimer module + */ +#define PCR_SYSTIMER_READY (BIT(2)) +#define PCR_SYSTIMER_READY_M (PCR_SYSTIMER_READY_V << PCR_SYSTIMER_READY_S) +#define PCR_SYSTIMER_READY_V 0x00000001U +#define PCR_SYSTIMER_READY_S 2 + +/** PCR_SYSTIMER_FUNC_CLK_CONF_REG register + * SYSTIMER_FUNC_CLK configuration register + */ +#define PCR_SYSTIMER_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x70) +/** PCR_SYSTIMER_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0; + * Configures the clock source of System Timer. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + */ +#define PCR_SYSTIMER_FUNC_CLK_SEL (BIT(20)) +#define PCR_SYSTIMER_FUNC_CLK_SEL_M (PCR_SYSTIMER_FUNC_CLK_SEL_V << PCR_SYSTIMER_FUNC_CLK_SEL_S) +#define PCR_SYSTIMER_FUNC_CLK_SEL_V 0x00000001U +#define PCR_SYSTIMER_FUNC_CLK_SEL_S 20 +/** PCR_SYSTIMER_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable systimer function clock + */ +#define PCR_SYSTIMER_FUNC_CLK_EN (BIT(22)) +#define PCR_SYSTIMER_FUNC_CLK_EN_M (PCR_SYSTIMER_FUNC_CLK_EN_V << PCR_SYSTIMER_FUNC_CLK_EN_S) +#define PCR_SYSTIMER_FUNC_CLK_EN_V 0x00000001U +#define PCR_SYSTIMER_FUNC_CLK_EN_S 22 + +/** PCR_I2S_CONF_REG register + * I2S configuration register + */ +#define PCR_I2S_CONF_REG (DR_REG_PCR_BASE + 0x74) +/** PCR_I2S_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable i2s apb clock + */ +#define PCR_I2S_CLK_EN (BIT(0)) +#define PCR_I2S_CLK_EN_M (PCR_I2S_CLK_EN_V << PCR_I2S_CLK_EN_S) +#define PCR_I2S_CLK_EN_V 0x00000001U +#define PCR_I2S_CLK_EN_S 0 +/** PCR_I2S_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset i2s module + */ +#define PCR_I2S_RST_EN (BIT(1)) +#define PCR_I2S_RST_EN_M (PCR_I2S_RST_EN_V << PCR_I2S_RST_EN_S) +#define PCR_I2S_RST_EN_V 0x00000001U +#define PCR_I2S_RST_EN_S 1 +/** PCR_I2S_RX_READY : RO; bitpos: [2]; default: 1; + * Query this field before using i2s rx function, after reset i2s module + */ +#define PCR_I2S_RX_READY (BIT(2)) +#define PCR_I2S_RX_READY_M (PCR_I2S_RX_READY_V << PCR_I2S_RX_READY_S) +#define PCR_I2S_RX_READY_V 0x00000001U +#define PCR_I2S_RX_READY_S 2 +/** PCR_I2S_TX_READY : RO; bitpos: [3]; default: 1; + * Query this field before using i2s tx function, after reset i2s module + */ +#define PCR_I2S_TX_READY (BIT(3)) +#define PCR_I2S_TX_READY_M (PCR_I2S_TX_READY_V << PCR_I2S_TX_READY_S) +#define PCR_I2S_TX_READY_V 0x00000001U +#define PCR_I2S_TX_READY_S 3 + +/** PCR_I2S_TX_CLKM_CONF_REG register + * I2S_TX_CLKM configuration register + */ +#define PCR_I2S_TX_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x78) +/** PCR_I2S_TX_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 2; + * Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be + * (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= + * a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * + * (n+1)-div] + y * (n+1)-div. + */ +#define PCR_I2S_TX_CLKM_DIV_NUM 0x000000FFU +#define PCR_I2S_TX_CLKM_DIV_NUM_M (PCR_I2S_TX_CLKM_DIV_NUM_V << PCR_I2S_TX_CLKM_DIV_NUM_S) +#define PCR_I2S_TX_CLKM_DIV_NUM_V 0x000000FFU +#define PCR_I2S_TX_CLKM_DIV_NUM_S 12 +/** PCR_I2S_TX_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of I2S TX. + * 0 (default): XTAL_CLK + * 1: PLL_F240M_CLK + * 2: PLL_F160M_CLK + * 3: I2S_MCLK_in + */ +#define PCR_I2S_TX_CLKM_SEL 0x00000003U +#define PCR_I2S_TX_CLKM_SEL_M (PCR_I2S_TX_CLKM_SEL_V << PCR_I2S_TX_CLKM_SEL_S) +#define PCR_I2S_TX_CLKM_SEL_V 0x00000003U +#define PCR_I2S_TX_CLKM_SEL_S 20 +/** PCR_I2S_TX_CLKM_EN : R/W; bitpos: [22]; default: 0; + * Set 1 to enable i2s_tx function clock + */ +#define PCR_I2S_TX_CLKM_EN (BIT(22)) +#define PCR_I2S_TX_CLKM_EN_M (PCR_I2S_TX_CLKM_EN_V << PCR_I2S_TX_CLKM_EN_S) +#define PCR_I2S_TX_CLKM_EN_V 0x00000001U +#define PCR_I2S_TX_CLKM_EN_S 22 + +/** PCR_I2S_TX_CLKM_DIV_CONF_REG register + * I2S_TX_CLKM_DIV configuration register + */ +#define PCR_I2S_TX_CLKM_DIV_CONF_REG (DR_REG_PCR_BASE + 0x7c) +/** PCR_I2S_TX_CLKM_DIV_Z : R/W; bitpos: [8:0]; default: 0; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of + * I2S_TX_CLKM_DIV_Z is (a-b). + */ +#define PCR_I2S_TX_CLKM_DIV_Z 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_Z_M (PCR_I2S_TX_CLKM_DIV_Z_V << PCR_I2S_TX_CLKM_DIV_Z_S) +#define PCR_I2S_TX_CLKM_DIV_Z_V 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_Z_S 0 +/** PCR_I2S_TX_CLKM_DIV_Y : R/W; bitpos: [17:9]; default: 1; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of + * I2S_TX_CLKM_DIV_Y is (a%(a-b)). + */ +#define PCR_I2S_TX_CLKM_DIV_Y 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_Y_M (PCR_I2S_TX_CLKM_DIV_Y_V << PCR_I2S_TX_CLKM_DIV_Y_S) +#define PCR_I2S_TX_CLKM_DIV_Y_V 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_Y_S 9 +/** PCR_I2S_TX_CLKM_DIV_X : R/W; bitpos: [26:18]; default: 0; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value + * of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1. + */ +#define PCR_I2S_TX_CLKM_DIV_X 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_X_M (PCR_I2S_TX_CLKM_DIV_X_V << PCR_I2S_TX_CLKM_DIV_X_S) +#define PCR_I2S_TX_CLKM_DIV_X_V 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_X_S 18 +/** PCR_I2S_TX_CLKM_DIV_YN1 : R/W; bitpos: [27]; default: 0; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of + * I2S_TX_CLKM_DIV_YN1 is 1. + */ +#define PCR_I2S_TX_CLKM_DIV_YN1 (BIT(27)) +#define PCR_I2S_TX_CLKM_DIV_YN1_M (PCR_I2S_TX_CLKM_DIV_YN1_V << PCR_I2S_TX_CLKM_DIV_YN1_S) +#define PCR_I2S_TX_CLKM_DIV_YN1_V 0x00000001U +#define PCR_I2S_TX_CLKM_DIV_YN1_S 27 + +/** PCR_I2S_RX_CLKM_CONF_REG register + * I2S_RX_CLKM configuration register + */ +#define PCR_I2S_RX_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x80) +/** PCR_I2S_RX_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 2; + * Integral I2S clock divider value + */ +#define PCR_I2S_RX_CLKM_DIV_NUM 0x000000FFU +#define PCR_I2S_RX_CLKM_DIV_NUM_M (PCR_I2S_RX_CLKM_DIV_NUM_V << PCR_I2S_RX_CLKM_DIV_NUM_S) +#define PCR_I2S_RX_CLKM_DIV_NUM_V 0x000000FFU +#define PCR_I2S_RX_CLKM_DIV_NUM_S 12 +/** PCR_I2S_RX_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of I2S RX. + * 0 (default): XTAL_CLK + * 1: PLL_F240M_CLK + * 2: PLL_F160M_CLK + * 3: I2S_MCLK_in + */ +#define PCR_I2S_RX_CLKM_SEL 0x00000003U +#define PCR_I2S_RX_CLKM_SEL_M (PCR_I2S_RX_CLKM_SEL_V << PCR_I2S_RX_CLKM_SEL_S) +#define PCR_I2S_RX_CLKM_SEL_V 0x00000003U +#define PCR_I2S_RX_CLKM_SEL_S 20 +/** PCR_I2S_RX_CLKM_EN : R/W; bitpos: [22]; default: 0; + * Set 1 to enable i2s_rx function clock + */ +#define PCR_I2S_RX_CLKM_EN (BIT(22)) +#define PCR_I2S_RX_CLKM_EN_M (PCR_I2S_RX_CLKM_EN_V << PCR_I2S_RX_CLKM_EN_S) +#define PCR_I2S_RX_CLKM_EN_V 0x00000001U +#define PCR_I2S_RX_CLKM_EN_S 22 +/** PCR_I2S_MCLK_SEL : R/W; bitpos: [23]; default: 0; + * Configures to select master clock. + * 0 (default): I2S_TX_CLK + * 1: I2S_RX_CLK + */ +#define PCR_I2S_MCLK_SEL (BIT(23)) +#define PCR_I2S_MCLK_SEL_M (PCR_I2S_MCLK_SEL_V << PCR_I2S_MCLK_SEL_S) +#define PCR_I2S_MCLK_SEL_V 0x00000001U +#define PCR_I2S_MCLK_SEL_S 23 + +/** PCR_I2S_RX_CLKM_DIV_CONF_REG register + * I2S_RX_CLKM_DIV configuration register + */ +#define PCR_I2S_RX_CLKM_DIV_CONF_REG (DR_REG_PCR_BASE + 0x84) +/** PCR_I2S_RX_CLKM_DIV_Z : R/W; bitpos: [8:0]; default: 0; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of + * I2S_RX_CLKM_DIV_Z is (a-b). + */ +#define PCR_I2S_RX_CLKM_DIV_Z 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_Z_M (PCR_I2S_RX_CLKM_DIV_Z_V << PCR_I2S_RX_CLKM_DIV_Z_S) +#define PCR_I2S_RX_CLKM_DIV_Z_V 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_Z_S 0 +/** PCR_I2S_RX_CLKM_DIV_Y : R/W; bitpos: [17:9]; default: 1; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of + * I2S_RX_CLKM_DIV_Y is (a%(a-b)). + */ +#define PCR_I2S_RX_CLKM_DIV_Y 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_Y_M (PCR_I2S_RX_CLKM_DIV_Y_V << PCR_I2S_RX_CLKM_DIV_Y_S) +#define PCR_I2S_RX_CLKM_DIV_Y_V 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_Y_S 9 +/** PCR_I2S_RX_CLKM_DIV_X : R/W; bitpos: [26:18]; default: 0; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value + * of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1. + */ +#define PCR_I2S_RX_CLKM_DIV_X 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_X_M (PCR_I2S_RX_CLKM_DIV_X_V << PCR_I2S_RX_CLKM_DIV_X_S) +#define PCR_I2S_RX_CLKM_DIV_X_V 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_X_S 18 +/** PCR_I2S_RX_CLKM_DIV_YN1 : R/W; bitpos: [27]; default: 0; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of + * I2S_RX_CLKM_DIV_YN1 is 1. + */ +#define PCR_I2S_RX_CLKM_DIV_YN1 (BIT(27)) +#define PCR_I2S_RX_CLKM_DIV_YN1_M (PCR_I2S_RX_CLKM_DIV_YN1_V << PCR_I2S_RX_CLKM_DIV_YN1_S) +#define PCR_I2S_RX_CLKM_DIV_YN1_V 0x00000001U +#define PCR_I2S_RX_CLKM_DIV_YN1_S 27 + +/** PCR_SARADC_CONF_REG register + * SARADC configuration register + */ +#define PCR_SARADC_CONF_REG (DR_REG_PCR_BASE + 0x88) +/** PCR_SARADC_CLK_EN : R/W; bitpos: [0]; default: 1; + * no use + */ +#define PCR_SARADC_CLK_EN (BIT(0)) +#define PCR_SARADC_CLK_EN_M (PCR_SARADC_CLK_EN_V << PCR_SARADC_CLK_EN_S) +#define PCR_SARADC_CLK_EN_V 0x00000001U +#define PCR_SARADC_CLK_EN_S 0 +/** PCR_SARADC_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset function_register of saradc module + */ +#define PCR_SARADC_RST_EN (BIT(1)) +#define PCR_SARADC_RST_EN_M (PCR_SARADC_RST_EN_V << PCR_SARADC_RST_EN_S) +#define PCR_SARADC_RST_EN_V 0x00000001U +#define PCR_SARADC_RST_EN_S 1 +/** PCR_SARADC_REG_CLK_EN : R/W; bitpos: [2]; default: 0; + * Set 1 to enable saradc apb clock + */ +#define PCR_SARADC_REG_CLK_EN (BIT(2)) +#define PCR_SARADC_REG_CLK_EN_M (PCR_SARADC_REG_CLK_EN_V << PCR_SARADC_REG_CLK_EN_S) +#define PCR_SARADC_REG_CLK_EN_V 0x00000001U +#define PCR_SARADC_REG_CLK_EN_S 2 +/** PCR_SARADC_REG_RST_EN : R/W; bitpos: [3]; default: 0; + * Set 1 to reset apb_register of saradc module + */ +#define PCR_SARADC_REG_RST_EN (BIT(3)) +#define PCR_SARADC_REG_RST_EN_M (PCR_SARADC_REG_RST_EN_V << PCR_SARADC_REG_RST_EN_S) +#define PCR_SARADC_REG_RST_EN_V 0x00000001U +#define PCR_SARADC_REG_RST_EN_S 3 + +/** PCR_SARADC_CLKM_CONF_REG register + * SARADC_CLKM configuration register + */ +#define PCR_SARADC_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x8c) +/** PCR_SARADC_CLKM_DIV_A : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the saradc function clock. + */ +#define PCR_SARADC_CLKM_DIV_A 0x0000003FU +#define PCR_SARADC_CLKM_DIV_A_M (PCR_SARADC_CLKM_DIV_A_V << PCR_SARADC_CLKM_DIV_A_S) +#define PCR_SARADC_CLKM_DIV_A_V 0x0000003FU +#define PCR_SARADC_CLKM_DIV_A_S 0 +/** PCR_SARADC_CLKM_DIV_B : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the saradc function clock. + */ +#define PCR_SARADC_CLKM_DIV_B 0x0000003FU +#define PCR_SARADC_CLKM_DIV_B_M (PCR_SARADC_CLKM_DIV_B_V << PCR_SARADC_CLKM_DIV_B_S) +#define PCR_SARADC_CLKM_DIV_B_V 0x0000003FU +#define PCR_SARADC_CLKM_DIV_B_S 6 +/** PCR_SARADC_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 4; + * The integral part of the frequency divider factor of the saradc function clock. + */ +#define PCR_SARADC_CLKM_DIV_NUM 0x000000FFU +#define PCR_SARADC_CLKM_DIV_NUM_M (PCR_SARADC_CLKM_DIV_NUM_V << PCR_SARADC_CLKM_DIV_NUM_S) +#define PCR_SARADC_CLKM_DIV_NUM_V 0x000000FFU +#define PCR_SARADC_CLKM_DIV_NUM_S 12 +/** PCR_SARADC_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of SAR ADC. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK + */ +#define PCR_SARADC_CLKM_SEL 0x00000003U +#define PCR_SARADC_CLKM_SEL_M (PCR_SARADC_CLKM_SEL_V << PCR_SARADC_CLKM_SEL_S) +#define PCR_SARADC_CLKM_SEL_V 0x00000003U +#define PCR_SARADC_CLKM_SEL_S 20 +/** PCR_SARADC_CLKM_EN : R/W; bitpos: [22]; default: 0; + * Set 1 to enable saradc function clock + */ +#define PCR_SARADC_CLKM_EN (BIT(22)) +#define PCR_SARADC_CLKM_EN_M (PCR_SARADC_CLKM_EN_V << PCR_SARADC_CLKM_EN_S) +#define PCR_SARADC_CLKM_EN_V 0x00000001U +#define PCR_SARADC_CLKM_EN_S 22 + +/** PCR_TSENS_CLK_CONF_REG register + * TSENS_CLK configuration register + */ +#define PCR_TSENS_CLK_CONF_REG (DR_REG_PCR_BASE + 0x90) +/** PCR_TSENS_CLK_SEL : R/W; bitpos: [20]; default: 0; + * Configures the clock source of the temperature sensor. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + */ +#define PCR_TSENS_CLK_SEL (BIT(20)) +#define PCR_TSENS_CLK_SEL_M (PCR_TSENS_CLK_SEL_V << PCR_TSENS_CLK_SEL_S) +#define PCR_TSENS_CLK_SEL_V 0x00000001U +#define PCR_TSENS_CLK_SEL_S 20 +/** PCR_TSENS_CLK_EN : R/W; bitpos: [22]; default: 0; + * Set 1 to enable tsens clock + */ +#define PCR_TSENS_CLK_EN (BIT(22)) +#define PCR_TSENS_CLK_EN_M (PCR_TSENS_CLK_EN_V << PCR_TSENS_CLK_EN_S) +#define PCR_TSENS_CLK_EN_V 0x00000001U +#define PCR_TSENS_CLK_EN_S 22 +/** PCR_TSENS_RST_EN : R/W; bitpos: [23]; default: 0; + * Set 1 to reset tsens module + */ +#define PCR_TSENS_RST_EN (BIT(23)) +#define PCR_TSENS_RST_EN_M (PCR_TSENS_RST_EN_V << PCR_TSENS_RST_EN_S) +#define PCR_TSENS_RST_EN_V 0x00000001U +#define PCR_TSENS_RST_EN_S 23 + +/** PCR_USB_DEVICE_CONF_REG register + * USB_DEVICE configuration register + */ +#define PCR_USB_DEVICE_CONF_REG (DR_REG_PCR_BASE + 0x94) +/** PCR_USB_DEVICE_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable usb_device clock + */ +#define PCR_USB_DEVICE_CLK_EN (BIT(0)) +#define PCR_USB_DEVICE_CLK_EN_M (PCR_USB_DEVICE_CLK_EN_V << PCR_USB_DEVICE_CLK_EN_S) +#define PCR_USB_DEVICE_CLK_EN_V 0x00000001U +#define PCR_USB_DEVICE_CLK_EN_S 0 +/** PCR_USB_DEVICE_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset usb_device module + */ +#define PCR_USB_DEVICE_RST_EN (BIT(1)) +#define PCR_USB_DEVICE_RST_EN_M (PCR_USB_DEVICE_RST_EN_V << PCR_USB_DEVICE_RST_EN_S) +#define PCR_USB_DEVICE_RST_EN_V 0x00000001U +#define PCR_USB_DEVICE_RST_EN_S 1 +/** PCR_USB_DEVICE_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset usb_device module + */ +#define PCR_USB_DEVICE_READY (BIT(2)) +#define PCR_USB_DEVICE_READY_M (PCR_USB_DEVICE_READY_V << PCR_USB_DEVICE_READY_S) +#define PCR_USB_DEVICE_READY_V 0x00000001U +#define PCR_USB_DEVICE_READY_S 2 + +/** PCR_INTMTX_CONF_REG register + * INTMTX configuration register + */ +#define PCR_INTMTX_CONF_REG (DR_REG_PCR_BASE + 0x98) +/** PCR_INTMTX_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable intmtx clock + */ +#define PCR_INTMTX_CLK_EN (BIT(0)) +#define PCR_INTMTX_CLK_EN_M (PCR_INTMTX_CLK_EN_V << PCR_INTMTX_CLK_EN_S) +#define PCR_INTMTX_CLK_EN_V 0x00000001U +#define PCR_INTMTX_CLK_EN_S 0 +/** PCR_INTMTX_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset intmtx module + */ +#define PCR_INTMTX_RST_EN (BIT(1)) +#define PCR_INTMTX_RST_EN_M (PCR_INTMTX_RST_EN_V << PCR_INTMTX_RST_EN_S) +#define PCR_INTMTX_RST_EN_V 0x00000001U +#define PCR_INTMTX_RST_EN_S 1 +/** PCR_INTMTX_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset intmtx module + */ +#define PCR_INTMTX_READY (BIT(2)) +#define PCR_INTMTX_READY_M (PCR_INTMTX_READY_V << PCR_INTMTX_READY_S) +#define PCR_INTMTX_READY_V 0x00000001U +#define PCR_INTMTX_READY_S 2 + +/** PCR_PCNT_CONF_REG register + * PCNT configuration register + */ +#define PCR_PCNT_CONF_REG (DR_REG_PCR_BASE + 0x9c) +/** PCR_PCNT_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable pcnt clock + */ +#define PCR_PCNT_CLK_EN (BIT(0)) +#define PCR_PCNT_CLK_EN_M (PCR_PCNT_CLK_EN_V << PCR_PCNT_CLK_EN_S) +#define PCR_PCNT_CLK_EN_V 0x00000001U +#define PCR_PCNT_CLK_EN_S 0 +/** PCR_PCNT_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset pcnt module + */ +#define PCR_PCNT_RST_EN (BIT(1)) +#define PCR_PCNT_RST_EN_M (PCR_PCNT_RST_EN_V << PCR_PCNT_RST_EN_S) +#define PCR_PCNT_RST_EN_V 0x00000001U +#define PCR_PCNT_RST_EN_S 1 +/** PCR_PCNT_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset pcnt module + */ +#define PCR_PCNT_READY (BIT(2)) +#define PCR_PCNT_READY_M (PCR_PCNT_READY_V << PCR_PCNT_READY_S) +#define PCR_PCNT_READY_V 0x00000001U +#define PCR_PCNT_READY_S 2 + +/** PCR_ETM_CONF_REG register + * ETM configuration register + */ +#define PCR_ETM_CONF_REG (DR_REG_PCR_BASE + 0xa0) +/** PCR_ETM_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable etm clock + */ +#define PCR_ETM_CLK_EN (BIT(0)) +#define PCR_ETM_CLK_EN_M (PCR_ETM_CLK_EN_V << PCR_ETM_CLK_EN_S) +#define PCR_ETM_CLK_EN_V 0x00000001U +#define PCR_ETM_CLK_EN_S 0 +/** PCR_ETM_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset etm module + */ +#define PCR_ETM_RST_EN (BIT(1)) +#define PCR_ETM_RST_EN_M (PCR_ETM_RST_EN_V << PCR_ETM_RST_EN_S) +#define PCR_ETM_RST_EN_V 0x00000001U +#define PCR_ETM_RST_EN_S 1 +/** PCR_ETM_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset etm module + */ +#define PCR_ETM_READY (BIT(2)) +#define PCR_ETM_READY_M (PCR_ETM_READY_V << PCR_ETM_READY_S) +#define PCR_ETM_READY_V 0x00000001U +#define PCR_ETM_READY_S 2 + +/** PCR_PWM_CONF_REG register + * PWM configuration register + */ +#define PCR_PWM_CONF_REG (DR_REG_PCR_BASE + 0xa4) +/** PCR_PWM_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable pwm clock + */ +#define PCR_PWM_CLK_EN (BIT(0)) +#define PCR_PWM_CLK_EN_M (PCR_PWM_CLK_EN_V << PCR_PWM_CLK_EN_S) +#define PCR_PWM_CLK_EN_V 0x00000001U +#define PCR_PWM_CLK_EN_S 0 +/** PCR_PWM_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset pwm module + */ +#define PCR_PWM_RST_EN (BIT(1)) +#define PCR_PWM_RST_EN_M (PCR_PWM_RST_EN_V << PCR_PWM_RST_EN_S) +#define PCR_PWM_RST_EN_V 0x00000001U +#define PCR_PWM_RST_EN_S 1 +/** PCR_PWM_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset pwm module + */ +#define PCR_PWM_READY (BIT(2)) +#define PCR_PWM_READY_M (PCR_PWM_READY_V << PCR_PWM_READY_S) +#define PCR_PWM_READY_V 0x00000001U +#define PCR_PWM_READY_S 2 + +/** PCR_PWM_CLK_CONF_REG register + * PWM_CLK configuration register + */ +#define PCR_PWM_CLK_CONF_REG (DR_REG_PCR_BASE + 0xa8) +/** PCR_PWM_DIV_NUM : R/W; bitpos: [19:12]; default: 4; + * The integral part of the frequency divider factor of the pwm function clock. + */ +#define PCR_PWM_DIV_NUM 0x000000FFU +#define PCR_PWM_DIV_NUM_M (PCR_PWM_DIV_NUM_V << PCR_PWM_DIV_NUM_S) +#define PCR_PWM_DIV_NUM_V 0x000000FFU +#define PCR_PWM_DIV_NUM_S 12 +/** PCR_PWM_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of MCPWM. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F160M_CLK + */ +#define PCR_PWM_CLKM_SEL 0x00000003U +#define PCR_PWM_CLKM_SEL_M (PCR_PWM_CLKM_SEL_V << PCR_PWM_CLKM_SEL_S) +#define PCR_PWM_CLKM_SEL_V 0x00000003U +#define PCR_PWM_CLKM_SEL_S 20 +/** PCR_PWM_CLKM_EN : R/W; bitpos: [22]; default: 0; + * set this field as 1 to activate pwm clkm. + */ +#define PCR_PWM_CLKM_EN (BIT(22)) +#define PCR_PWM_CLKM_EN_M (PCR_PWM_CLKM_EN_V << PCR_PWM_CLKM_EN_S) +#define PCR_PWM_CLKM_EN_V 0x00000001U +#define PCR_PWM_CLKM_EN_S 22 + +/** PCR_PARL_IO_CONF_REG register + * PARL_IO configuration register + */ +#define PCR_PARL_IO_CONF_REG (DR_REG_PCR_BASE + 0xac) +/** PCR_PARL_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable parl apb clock + */ +#define PCR_PARL_CLK_EN (BIT(0)) +#define PCR_PARL_CLK_EN_M (PCR_PARL_CLK_EN_V << PCR_PARL_CLK_EN_S) +#define PCR_PARL_CLK_EN_V 0x00000001U +#define PCR_PARL_CLK_EN_S 0 +/** PCR_PARL_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset parl apb reg + */ +#define PCR_PARL_RST_EN (BIT(1)) +#define PCR_PARL_RST_EN_M (PCR_PARL_RST_EN_V << PCR_PARL_RST_EN_S) +#define PCR_PARL_RST_EN_V 0x00000001U +#define PCR_PARL_RST_EN_S 1 +/** PCR_PARL_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset parl module + */ +#define PCR_PARL_READY (BIT(2)) +#define PCR_PARL_READY_M (PCR_PARL_READY_V << PCR_PARL_READY_S) +#define PCR_PARL_READY_V 0x00000001U +#define PCR_PARL_READY_S 2 + +/** PCR_PARL_CLK_RX_CONF_REG register + * PARL_CLK_RX configuration register + */ +#define PCR_PARL_CLK_RX_CONF_REG (DR_REG_PCR_BASE + 0xb0) +/** PCR_PARL_CLK_RX_DIV_NUM : R/W; bitpos: [15:0]; default: 0; + * The integral part of the frequency divider factor of the parl rx clock. + */ +#define PCR_PARL_CLK_RX_DIV_NUM 0x0000FFFFU +#define PCR_PARL_CLK_RX_DIV_NUM_M (PCR_PARL_CLK_RX_DIV_NUM_V << PCR_PARL_CLK_RX_DIV_NUM_S) +#define PCR_PARL_CLK_RX_DIV_NUM_V 0x0000FFFFU +#define PCR_PARL_CLK_RX_DIV_NUM_S 0 +/** PCR_PARL_CLK_RX_SEL : R/W; bitpos: [17:16]; default: 0; + * Configures the clock source of Paraller IO RX + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F240M_CLK + * 3: Use the clock from chip pin + */ +#define PCR_PARL_CLK_RX_SEL 0x00000003U +#define PCR_PARL_CLK_RX_SEL_M (PCR_PARL_CLK_RX_SEL_V << PCR_PARL_CLK_RX_SEL_S) +#define PCR_PARL_CLK_RX_SEL_V 0x00000003U +#define PCR_PARL_CLK_RX_SEL_S 16 +/** PCR_PARL_CLK_RX_EN : R/W; bitpos: [18]; default: 0; + * Set 1 to enable parl rx clock + */ +#define PCR_PARL_CLK_RX_EN (BIT(18)) +#define PCR_PARL_CLK_RX_EN_M (PCR_PARL_CLK_RX_EN_V << PCR_PARL_CLK_RX_EN_S) +#define PCR_PARL_CLK_RX_EN_V 0x00000001U +#define PCR_PARL_CLK_RX_EN_S 18 +/** PCR_PARL_RX_RST_EN : R/W; bitpos: [19]; default: 0; + * Set 1 to reset parl rx module + */ +#define PCR_PARL_RX_RST_EN (BIT(19)) +#define PCR_PARL_RX_RST_EN_M (PCR_PARL_RX_RST_EN_V << PCR_PARL_RX_RST_EN_S) +#define PCR_PARL_RX_RST_EN_V 0x00000001U +#define PCR_PARL_RX_RST_EN_S 19 + +/** PCR_PARL_CLK_TX_CONF_REG register + * PARL_CLK_TX configuration register + */ +#define PCR_PARL_CLK_TX_CONF_REG (DR_REG_PCR_BASE + 0xb4) +/** PCR_PARL_CLK_TX_DIV_NUM : R/W; bitpos: [15:0]; default: 0; + * The integral part of the frequency divider factor of the parl tx clock. + */ +#define PCR_PARL_CLK_TX_DIV_NUM 0x0000FFFFU +#define PCR_PARL_CLK_TX_DIV_NUM_M (PCR_PARL_CLK_TX_DIV_NUM_V << PCR_PARL_CLK_TX_DIV_NUM_S) +#define PCR_PARL_CLK_TX_DIV_NUM_V 0x0000FFFFU +#define PCR_PARL_CLK_TX_DIV_NUM_S 0 +/** PCR_PARL_CLK_TX_SEL : R/W; bitpos: [17:16]; default: 0; + * Configures the clock source of Paraller IO RX + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F240M_CLK + * 3: Use the clock from chip pin + */ +#define PCR_PARL_CLK_TX_SEL 0x00000003U +#define PCR_PARL_CLK_TX_SEL_M (PCR_PARL_CLK_TX_SEL_V << PCR_PARL_CLK_TX_SEL_S) +#define PCR_PARL_CLK_TX_SEL_V 0x00000003U +#define PCR_PARL_CLK_TX_SEL_S 16 +/** PCR_PARL_CLK_TX_EN : R/W; bitpos: [18]; default: 0; + * Set 1 to enable parl tx clock + */ +#define PCR_PARL_CLK_TX_EN (BIT(18)) +#define PCR_PARL_CLK_TX_EN_M (PCR_PARL_CLK_TX_EN_V << PCR_PARL_CLK_TX_EN_S) +#define PCR_PARL_CLK_TX_EN_V 0x00000001U +#define PCR_PARL_CLK_TX_EN_S 18 +/** PCR_PARL_TX_RST_EN : R/W; bitpos: [19]; default: 0; + * Set 1 to reset parl tx module + */ +#define PCR_PARL_TX_RST_EN (BIT(19)) +#define PCR_PARL_TX_RST_EN_M (PCR_PARL_TX_RST_EN_V << PCR_PARL_TX_RST_EN_S) +#define PCR_PARL_TX_RST_EN_V 0x00000001U +#define PCR_PARL_TX_RST_EN_S 19 + +/** PCR_PVT_MONITOR_CONF_REG register + * PVT_MONITOR configuration register + */ +#define PCR_PVT_MONITOR_CONF_REG (DR_REG_PCR_BASE + 0xb8) +/** PCR_PVT_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable apb clock of pvt module + */ +#define PCR_PVT_MONITOR_CLK_EN (BIT(0)) +#define PCR_PVT_MONITOR_CLK_EN_M (PCR_PVT_MONITOR_CLK_EN_V << PCR_PVT_MONITOR_CLK_EN_S) +#define PCR_PVT_MONITOR_CLK_EN_V 0x00000001U +#define PCR_PVT_MONITOR_CLK_EN_S 0 +/** PCR_PVT_MONITOR_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset all pvt monitor module + */ +#define PCR_PVT_MONITOR_RST_EN (BIT(1)) +#define PCR_PVT_MONITOR_RST_EN_M (PCR_PVT_MONITOR_RST_EN_V << PCR_PVT_MONITOR_RST_EN_S) +#define PCR_PVT_MONITOR_RST_EN_V 0x00000001U +#define PCR_PVT_MONITOR_RST_EN_S 1 +/** PCR_PVT_MONITOR_SITE1_CLK_EN : R/W; bitpos: [2]; default: 1; + * Set 1 to enable function clock of modem pvt module + */ +#define PCR_PVT_MONITOR_SITE1_CLK_EN (BIT(2)) +#define PCR_PVT_MONITOR_SITE1_CLK_EN_M (PCR_PVT_MONITOR_SITE1_CLK_EN_V << PCR_PVT_MONITOR_SITE1_CLK_EN_S) +#define PCR_PVT_MONITOR_SITE1_CLK_EN_V 0x00000001U +#define PCR_PVT_MONITOR_SITE1_CLK_EN_S 2 +/** PCR_PVT_MONITOR_SITE2_CLK_EN : R/W; bitpos: [3]; default: 1; + * Set 1 to enable function clock of cpu pvt module + */ +#define PCR_PVT_MONITOR_SITE2_CLK_EN (BIT(3)) +#define PCR_PVT_MONITOR_SITE2_CLK_EN_M (PCR_PVT_MONITOR_SITE2_CLK_EN_V << PCR_PVT_MONITOR_SITE2_CLK_EN_S) +#define PCR_PVT_MONITOR_SITE2_CLK_EN_V 0x00000001U +#define PCR_PVT_MONITOR_SITE2_CLK_EN_S 3 +/** PCR_PVT_MONITOR_SITE3_CLK_EN : R/W; bitpos: [4]; default: 1; + * Set 1 to enable function clock of hp_peri pvt module + */ +#define PCR_PVT_MONITOR_SITE3_CLK_EN (BIT(4)) +#define PCR_PVT_MONITOR_SITE3_CLK_EN_M (PCR_PVT_MONITOR_SITE3_CLK_EN_V << PCR_PVT_MONITOR_SITE3_CLK_EN_S) +#define PCR_PVT_MONITOR_SITE3_CLK_EN_V 0x00000001U +#define PCR_PVT_MONITOR_SITE3_CLK_EN_S 4 + +/** PCR_PVT_MONITOR_FUNC_CLK_CONF_REG register + * PVT_MONITOR function clock configuration register + */ +#define PCR_PVT_MONITOR_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0xbc) +/** PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM : R/W; bitpos: [3:0]; default: 0; + * The integral part of the frequency divider factor of the pvt_monitor function clock. + */ +#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM 0x0000000FU +#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_M (PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_V << PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_S) +#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_V 0x0000000FU +#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_S 0 +/** PCR_PVT_MONITOR_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0; + * Configures the clock source of PVT MONITOR. + * 0 (default): XTAL_CLK + * 1: PLL_F160M_CLK + */ +#define PCR_PVT_MONITOR_FUNC_CLK_SEL (BIT(20)) +#define PCR_PVT_MONITOR_FUNC_CLK_SEL_M (PCR_PVT_MONITOR_FUNC_CLK_SEL_V << PCR_PVT_MONITOR_FUNC_CLK_SEL_S) +#define PCR_PVT_MONITOR_FUNC_CLK_SEL_V 0x00000001U +#define PCR_PVT_MONITOR_FUNC_CLK_SEL_S 20 +/** PCR_PVT_MONITOR_FUNC_CLK_EN : R/W; bitpos: [22]; default: 0; + * Set 1 to enable source clock of pvt sitex + */ +#define PCR_PVT_MONITOR_FUNC_CLK_EN (BIT(22)) +#define PCR_PVT_MONITOR_FUNC_CLK_EN_M (PCR_PVT_MONITOR_FUNC_CLK_EN_V << PCR_PVT_MONITOR_FUNC_CLK_EN_S) +#define PCR_PVT_MONITOR_FUNC_CLK_EN_V 0x00000001U +#define PCR_PVT_MONITOR_FUNC_CLK_EN_S 22 + +/** PCR_GDMA_CONF_REG register + * GDMA configuration register + */ +#define PCR_GDMA_CONF_REG (DR_REG_PCR_BASE + 0xc0) +/** PCR_GDMA_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable gdma clock + */ +#define PCR_GDMA_CLK_EN (BIT(0)) +#define PCR_GDMA_CLK_EN_M (PCR_GDMA_CLK_EN_V << PCR_GDMA_CLK_EN_S) +#define PCR_GDMA_CLK_EN_V 0x00000001U +#define PCR_GDMA_CLK_EN_S 0 +/** PCR_GDMA_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset gdma module + */ +#define PCR_GDMA_RST_EN (BIT(1)) +#define PCR_GDMA_RST_EN_M (PCR_GDMA_RST_EN_V << PCR_GDMA_RST_EN_S) +#define PCR_GDMA_RST_EN_V 0x00000001U +#define PCR_GDMA_RST_EN_S 1 + +/** PCR_SPI2_CONF_REG register + * SPI2 configuration register + */ +#define PCR_SPI2_CONF_REG (DR_REG_PCR_BASE + 0xc4) +/** PCR_SPI2_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable spi2 apb clock + */ +#define PCR_SPI2_CLK_EN (BIT(0)) +#define PCR_SPI2_CLK_EN_M (PCR_SPI2_CLK_EN_V << PCR_SPI2_CLK_EN_S) +#define PCR_SPI2_CLK_EN_V 0x00000001U +#define PCR_SPI2_CLK_EN_S 0 +/** PCR_SPI2_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset spi2 module + */ +#define PCR_SPI2_RST_EN (BIT(1)) +#define PCR_SPI2_RST_EN_M (PCR_SPI2_RST_EN_V << PCR_SPI2_RST_EN_S) +#define PCR_SPI2_RST_EN_V 0x00000001U +#define PCR_SPI2_RST_EN_S 1 +/** PCR_SPI2_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset spi2 module + */ +#define PCR_SPI2_READY (BIT(2)) +#define PCR_SPI2_READY_M (PCR_SPI2_READY_V << PCR_SPI2_READY_S) +#define PCR_SPI2_READY_V 0x00000001U +#define PCR_SPI2_READY_S 2 + +/** PCR_SPI2_CLKM_CONF_REG register + * SPI2_CLKM configuration register + */ +#define PCR_SPI2_CLKM_CONF_REG (DR_REG_PCR_BASE + 0xc8) +/** PCR_SPI2_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the spi2_mst clock. + */ +#define PCR_SPI2_CLKM_DIV_NUM 0x000000FFU +#define PCR_SPI2_CLKM_DIV_NUM_M (PCR_SPI2_CLKM_DIV_NUM_V << PCR_SPI2_CLKM_DIV_NUM_S) +#define PCR_SPI2_CLKM_DIV_NUM_V 0x000000FFU +#define PCR_SPI2_CLKM_DIV_NUM_S 12 +/** PCR_SPI2_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of SPI2. + * 0 (default): XTAL_CLK + * 1: PLL_F160M_CLK + * 2: RC_FAST_CLK + * 3: PLL_F120M_CLK + */ +#define PCR_SPI2_CLKM_SEL 0x00000003U +#define PCR_SPI2_CLKM_SEL_M (PCR_SPI2_CLKM_SEL_V << PCR_SPI2_CLKM_SEL_S) +#define PCR_SPI2_CLKM_SEL_V 0x00000003U +#define PCR_SPI2_CLKM_SEL_S 20 +/** PCR_SPI2_CLKM_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable spi2 function clock + */ +#define PCR_SPI2_CLKM_EN (BIT(22)) +#define PCR_SPI2_CLKM_EN_M (PCR_SPI2_CLKM_EN_V << PCR_SPI2_CLKM_EN_S) +#define PCR_SPI2_CLKM_EN_V 0x00000001U +#define PCR_SPI2_CLKM_EN_S 22 + +/** PCR_AES_CONF_REG register + * AES configuration register + */ +#define PCR_AES_CONF_REG (DR_REG_PCR_BASE + 0xcc) +/** PCR_AES_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable aes clock + */ +#define PCR_AES_CLK_EN (BIT(0)) +#define PCR_AES_CLK_EN_M (PCR_AES_CLK_EN_V << PCR_AES_CLK_EN_S) +#define PCR_AES_CLK_EN_V 0x00000001U +#define PCR_AES_CLK_EN_S 0 +/** PCR_AES_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset aes module + */ +#define PCR_AES_RST_EN (BIT(1)) +#define PCR_AES_RST_EN_M (PCR_AES_RST_EN_V << PCR_AES_RST_EN_S) +#define PCR_AES_RST_EN_V 0x00000001U +#define PCR_AES_RST_EN_S 1 +/** PCR_AES_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset aes module + */ +#define PCR_AES_READY (BIT(2)) +#define PCR_AES_READY_M (PCR_AES_READY_V << PCR_AES_READY_S) +#define PCR_AES_READY_V 0x00000001U +#define PCR_AES_READY_S 2 + +/** PCR_SHA_CONF_REG register + * SHA configuration register + */ +#define PCR_SHA_CONF_REG (DR_REG_PCR_BASE + 0xd0) +/** PCR_SHA_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable sha clock + */ +#define PCR_SHA_CLK_EN (BIT(0)) +#define PCR_SHA_CLK_EN_M (PCR_SHA_CLK_EN_V << PCR_SHA_CLK_EN_S) +#define PCR_SHA_CLK_EN_V 0x00000001U +#define PCR_SHA_CLK_EN_S 0 +/** PCR_SHA_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset sha module + */ +#define PCR_SHA_RST_EN (BIT(1)) +#define PCR_SHA_RST_EN_M (PCR_SHA_RST_EN_V << PCR_SHA_RST_EN_S) +#define PCR_SHA_RST_EN_V 0x00000001U +#define PCR_SHA_RST_EN_S 1 +/** PCR_SHA_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset sha module + */ +#define PCR_SHA_READY (BIT(2)) +#define PCR_SHA_READY_M (PCR_SHA_READY_V << PCR_SHA_READY_S) +#define PCR_SHA_READY_V 0x00000001U +#define PCR_SHA_READY_S 2 + +/** PCR_RSA_CONF_REG register + * RSA configuration register + */ +#define PCR_RSA_CONF_REG (DR_REG_PCR_BASE + 0xd4) +/** PCR_RSA_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable rsa clock + */ +#define PCR_RSA_CLK_EN (BIT(0)) +#define PCR_RSA_CLK_EN_M (PCR_RSA_CLK_EN_V << PCR_RSA_CLK_EN_S) +#define PCR_RSA_CLK_EN_V 0x00000001U +#define PCR_RSA_CLK_EN_S 0 +/** PCR_RSA_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset rsa module + */ +#define PCR_RSA_RST_EN (BIT(1)) +#define PCR_RSA_RST_EN_M (PCR_RSA_RST_EN_V << PCR_RSA_RST_EN_S) +#define PCR_RSA_RST_EN_V 0x00000001U +#define PCR_RSA_RST_EN_S 1 +/** PCR_RSA_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset rsa module + */ +#define PCR_RSA_READY (BIT(2)) +#define PCR_RSA_READY_M (PCR_RSA_READY_V << PCR_RSA_READY_S) +#define PCR_RSA_READY_V 0x00000001U +#define PCR_RSA_READY_S 2 + +/** PCR_RSA_PD_CTRL_REG register + * RSA power control register + */ +#define PCR_RSA_PD_CTRL_REG (DR_REG_PCR_BASE + 0xd8) +/** PCR_RSA_MEM_PD : R/W; bitpos: [0]; default: 1; + * Set this bit to power down rsa internal memory. + */ +#define PCR_RSA_MEM_PD (BIT(0)) +#define PCR_RSA_MEM_PD_M (PCR_RSA_MEM_PD_V << PCR_RSA_MEM_PD_S) +#define PCR_RSA_MEM_PD_V 0x00000001U +#define PCR_RSA_MEM_PD_S 0 +/** PCR_RSA_MEM_FORCE_PU : R/W; bitpos: [1]; default: 0; + * Set this bit to force power up rsa internal memory + */ +#define PCR_RSA_MEM_FORCE_PU (BIT(1)) +#define PCR_RSA_MEM_FORCE_PU_M (PCR_RSA_MEM_FORCE_PU_V << PCR_RSA_MEM_FORCE_PU_S) +#define PCR_RSA_MEM_FORCE_PU_V 0x00000001U +#define PCR_RSA_MEM_FORCE_PU_S 1 +/** PCR_RSA_MEM_FORCE_PD : R/W; bitpos: [2]; default: 1; + * Set this bit to force power down rsa internal memory. + */ +#define PCR_RSA_MEM_FORCE_PD (BIT(2)) +#define PCR_RSA_MEM_FORCE_PD_M (PCR_RSA_MEM_FORCE_PD_V << PCR_RSA_MEM_FORCE_PD_S) +#define PCR_RSA_MEM_FORCE_PD_V 0x00000001U +#define PCR_RSA_MEM_FORCE_PD_S 2 + +/** PCR_ECC_CONF_REG register + * ECC configuration register + */ +#define PCR_ECC_CONF_REG (DR_REG_PCR_BASE + 0xdc) +/** PCR_ECC_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable ecc clock + */ +#define PCR_ECC_CLK_EN (BIT(0)) +#define PCR_ECC_CLK_EN_M (PCR_ECC_CLK_EN_V << PCR_ECC_CLK_EN_S) +#define PCR_ECC_CLK_EN_V 0x00000001U +#define PCR_ECC_CLK_EN_S 0 +/** PCR_ECC_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset ecc module + */ +#define PCR_ECC_RST_EN (BIT(1)) +#define PCR_ECC_RST_EN_M (PCR_ECC_RST_EN_V << PCR_ECC_RST_EN_S) +#define PCR_ECC_RST_EN_V 0x00000001U +#define PCR_ECC_RST_EN_S 1 +/** PCR_ECC_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset ecc module + */ +#define PCR_ECC_READY (BIT(2)) +#define PCR_ECC_READY_M (PCR_ECC_READY_V << PCR_ECC_READY_S) +#define PCR_ECC_READY_V 0x00000001U +#define PCR_ECC_READY_S 2 + +/** PCR_ECC_PD_CTRL_REG register + * ECC power control register + */ +#define PCR_ECC_PD_CTRL_REG (DR_REG_PCR_BASE + 0xe0) +/** PCR_ECC_MEM_PD : R/W; bitpos: [0]; default: 1; + * Set this bit to power down ecc internal memory. + */ +#define PCR_ECC_MEM_PD (BIT(0)) +#define PCR_ECC_MEM_PD_M (PCR_ECC_MEM_PD_V << PCR_ECC_MEM_PD_S) +#define PCR_ECC_MEM_PD_V 0x00000001U +#define PCR_ECC_MEM_PD_S 0 +/** PCR_ECC_MEM_FORCE_PU : R/W; bitpos: [1]; default: 0; + * Set this bit to force power up ecc internal memory + */ +#define PCR_ECC_MEM_FORCE_PU (BIT(1)) +#define PCR_ECC_MEM_FORCE_PU_M (PCR_ECC_MEM_FORCE_PU_V << PCR_ECC_MEM_FORCE_PU_S) +#define PCR_ECC_MEM_FORCE_PU_V 0x00000001U +#define PCR_ECC_MEM_FORCE_PU_S 1 +/** PCR_ECC_MEM_FORCE_PD : R/W; bitpos: [2]; default: 1; + * Set this bit to force power down ecc internal memory. + */ +#define PCR_ECC_MEM_FORCE_PD (BIT(2)) +#define PCR_ECC_MEM_FORCE_PD_M (PCR_ECC_MEM_FORCE_PD_V << PCR_ECC_MEM_FORCE_PD_S) +#define PCR_ECC_MEM_FORCE_PD_V 0x00000001U +#define PCR_ECC_MEM_FORCE_PD_S 2 + +/** PCR_DS_CONF_REG register + * DS configuration register + */ +#define PCR_DS_CONF_REG (DR_REG_PCR_BASE + 0xe4) +/** PCR_DS_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable ds clock + */ +#define PCR_DS_CLK_EN (BIT(0)) +#define PCR_DS_CLK_EN_M (PCR_DS_CLK_EN_V << PCR_DS_CLK_EN_S) +#define PCR_DS_CLK_EN_V 0x00000001U +#define PCR_DS_CLK_EN_S 0 +/** PCR_DS_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset ds module + */ +#define PCR_DS_RST_EN (BIT(1)) +#define PCR_DS_RST_EN_M (PCR_DS_RST_EN_V << PCR_DS_RST_EN_S) +#define PCR_DS_RST_EN_V 0x00000001U +#define PCR_DS_RST_EN_S 1 +/** PCR_DS_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset ds module + */ +#define PCR_DS_READY (BIT(2)) +#define PCR_DS_READY_M (PCR_DS_READY_V << PCR_DS_READY_S) +#define PCR_DS_READY_V 0x00000001U +#define PCR_DS_READY_S 2 + +/** PCR_HMAC_CONF_REG register + * HMAC configuration register + */ +#define PCR_HMAC_CONF_REG (DR_REG_PCR_BASE + 0xe8) +/** PCR_HMAC_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable hmac clock + */ +#define PCR_HMAC_CLK_EN (BIT(0)) +#define PCR_HMAC_CLK_EN_M (PCR_HMAC_CLK_EN_V << PCR_HMAC_CLK_EN_S) +#define PCR_HMAC_CLK_EN_V 0x00000001U +#define PCR_HMAC_CLK_EN_S 0 +/** PCR_HMAC_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset hmac module + */ +#define PCR_HMAC_RST_EN (BIT(1)) +#define PCR_HMAC_RST_EN_M (PCR_HMAC_RST_EN_V << PCR_HMAC_RST_EN_S) +#define PCR_HMAC_RST_EN_V 0x00000001U +#define PCR_HMAC_RST_EN_S 1 +/** PCR_HMAC_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset hmac module + */ +#define PCR_HMAC_READY (BIT(2)) +#define PCR_HMAC_READY_M (PCR_HMAC_READY_V << PCR_HMAC_READY_S) +#define PCR_HMAC_READY_V 0x00000001U +#define PCR_HMAC_READY_S 2 + +/** PCR_ECDSA_CONF_REG register + * ECDSA configuration register + */ +#define PCR_ECDSA_CONF_REG (DR_REG_PCR_BASE + 0xec) +/** PCR_ECDSA_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable ecdsa clock + */ +#define PCR_ECDSA_CLK_EN (BIT(0)) +#define PCR_ECDSA_CLK_EN_M (PCR_ECDSA_CLK_EN_V << PCR_ECDSA_CLK_EN_S) +#define PCR_ECDSA_CLK_EN_V 0x00000001U +#define PCR_ECDSA_CLK_EN_S 0 +/** PCR_ECDSA_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset ecdsa module + */ +#define PCR_ECDSA_RST_EN (BIT(1)) +#define PCR_ECDSA_RST_EN_M (PCR_ECDSA_RST_EN_V << PCR_ECDSA_RST_EN_S) +#define PCR_ECDSA_RST_EN_V 0x00000001U +#define PCR_ECDSA_RST_EN_S 1 +/** PCR_ECDSA_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset ecdsa module + */ +#define PCR_ECDSA_READY (BIT(2)) +#define PCR_ECDSA_READY_M (PCR_ECDSA_READY_V << PCR_ECDSA_READY_S) +#define PCR_ECDSA_READY_V 0x00000001U +#define PCR_ECDSA_READY_S 2 + +/** PCR_IOMUX_CONF_REG register + * IOMUX configuration register + */ +#define PCR_IOMUX_CONF_REG (DR_REG_PCR_BASE + 0xf0) +/** PCR_IOMUX_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable iomux apb clock + */ +#define PCR_IOMUX_CLK_EN (BIT(0)) +#define PCR_IOMUX_CLK_EN_M (PCR_IOMUX_CLK_EN_V << PCR_IOMUX_CLK_EN_S) +#define PCR_IOMUX_CLK_EN_V 0x00000001U +#define PCR_IOMUX_CLK_EN_S 0 +/** PCR_IOMUX_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset iomux module + */ +#define PCR_IOMUX_RST_EN (BIT(1)) +#define PCR_IOMUX_RST_EN_M (PCR_IOMUX_RST_EN_V << PCR_IOMUX_RST_EN_S) +#define PCR_IOMUX_RST_EN_V 0x00000001U +#define PCR_IOMUX_RST_EN_S 1 + +/** PCR_IOMUX_CLK_CONF_REG register + * IOMUX_CLK configuration register + */ +#define PCR_IOMUX_CLK_CONF_REG (DR_REG_PCR_BASE + 0xf4) +/** PCR_IOMUX_FUNC_CLK_SEL : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of IO MUX. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK + */ +#define PCR_IOMUX_FUNC_CLK_SEL 0x00000003U +#define PCR_IOMUX_FUNC_CLK_SEL_M (PCR_IOMUX_FUNC_CLK_SEL_V << PCR_IOMUX_FUNC_CLK_SEL_S) +#define PCR_IOMUX_FUNC_CLK_SEL_V 0x00000003U +#define PCR_IOMUX_FUNC_CLK_SEL_S 20 +/** PCR_IOMUX_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable iomux function clock + */ +#define PCR_IOMUX_FUNC_CLK_EN (BIT(22)) +#define PCR_IOMUX_FUNC_CLK_EN_M (PCR_IOMUX_FUNC_CLK_EN_V << PCR_IOMUX_FUNC_CLK_EN_S) +#define PCR_IOMUX_FUNC_CLK_EN_V 0x00000001U +#define PCR_IOMUX_FUNC_CLK_EN_S 22 + +/** PCR_REGDMA_CONF_REG register + * REGDMA configuration register + */ +#define PCR_REGDMA_CONF_REG (DR_REG_PCR_BASE + 0xf8) +/** PCR_REGDMA_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable regdma clock + */ +#define PCR_REGDMA_CLK_EN (BIT(0)) +#define PCR_REGDMA_CLK_EN_M (PCR_REGDMA_CLK_EN_V << PCR_REGDMA_CLK_EN_S) +#define PCR_REGDMA_CLK_EN_V 0x00000001U +#define PCR_REGDMA_CLK_EN_S 0 +/** PCR_REGDMA_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset regdma module + */ +#define PCR_REGDMA_RST_EN (BIT(1)) +#define PCR_REGDMA_RST_EN_M (PCR_REGDMA_RST_EN_V << PCR_REGDMA_RST_EN_S) +#define PCR_REGDMA_RST_EN_V 0x00000001U +#define PCR_REGDMA_RST_EN_S 1 + +/** PCR_TRACE_CONF_REG register + * TRACE configuration register + */ +#define PCR_TRACE_CONF_REG (DR_REG_PCR_BASE + 0xfc) +/** PCR_TRACE_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable trace clock + */ +#define PCR_TRACE_CLK_EN (BIT(0)) +#define PCR_TRACE_CLK_EN_M (PCR_TRACE_CLK_EN_V << PCR_TRACE_CLK_EN_S) +#define PCR_TRACE_CLK_EN_V 0x00000001U +#define PCR_TRACE_CLK_EN_S 0 +/** PCR_TRACE_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset trace module + */ +#define PCR_TRACE_RST_EN (BIT(1)) +#define PCR_TRACE_RST_EN_M (PCR_TRACE_RST_EN_V << PCR_TRACE_RST_EN_S) +#define PCR_TRACE_RST_EN_V 0x00000001U +#define PCR_TRACE_RST_EN_S 1 + +/** PCR_ASSIST_CONF_REG register + * ASSIST configuration register + */ +#define PCR_ASSIST_CONF_REG (DR_REG_PCR_BASE + 0x100) +/** PCR_ASSIST_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable assist clock + */ +#define PCR_ASSIST_CLK_EN (BIT(0)) +#define PCR_ASSIST_CLK_EN_M (PCR_ASSIST_CLK_EN_V << PCR_ASSIST_CLK_EN_S) +#define PCR_ASSIST_CLK_EN_V 0x00000001U +#define PCR_ASSIST_CLK_EN_S 0 +/** PCR_ASSIST_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset assist module + */ +#define PCR_ASSIST_RST_EN (BIT(1)) +#define PCR_ASSIST_RST_EN_M (PCR_ASSIST_RST_EN_V << PCR_ASSIST_RST_EN_S) +#define PCR_ASSIST_RST_EN_V 0x00000001U +#define PCR_ASSIST_RST_EN_S 1 + +/** PCR_CACHE_CONF_REG register + * CACHE configuration register + */ +#define PCR_CACHE_CONF_REG (DR_REG_PCR_BASE + 0x104) +/** PCR_CACHE_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable cache clock + */ +#define PCR_CACHE_CLK_EN (BIT(0)) +#define PCR_CACHE_CLK_EN_M (PCR_CACHE_CLK_EN_V << PCR_CACHE_CLK_EN_S) +#define PCR_CACHE_CLK_EN_V 0x00000001U +#define PCR_CACHE_CLK_EN_S 0 +/** PCR_CACHE_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset cache module + */ +#define PCR_CACHE_RST_EN (BIT(1)) +#define PCR_CACHE_RST_EN_M (PCR_CACHE_RST_EN_V << PCR_CACHE_RST_EN_S) +#define PCR_CACHE_RST_EN_V 0x00000001U +#define PCR_CACHE_RST_EN_S 1 +/** PCR_CACHE_PU_EN : R/W; bitpos: [2]; default: 1; + * Set 0 to power up cache mem + */ +#define PCR_CACHE_PU_EN (BIT(2)) +#define PCR_CACHE_PU_EN_M (PCR_CACHE_PU_EN_V << PCR_CACHE_PU_EN_S) +#define PCR_CACHE_PU_EN_V 0x00000001U +#define PCR_CACHE_PU_EN_S 2 +/** PCR_CACHE_PD_EN : R/W; bitpos: [3]; default: 0; + * Set 0 to power down cache mem + */ +#define PCR_CACHE_PD_EN (BIT(3)) +#define PCR_CACHE_PD_EN_M (PCR_CACHE_PD_EN_V << PCR_CACHE_PD_EN_S) +#define PCR_CACHE_PD_EN_V 0x00000001U +#define PCR_CACHE_PD_EN_S 3 + +/** PCR_MODEM_CONF_REG register + * MODEM_APB configuration register + */ +#define PCR_MODEM_CONF_REG (DR_REG_PCR_BASE + 0x108) +/** PCR_MODEM_APB_CLK_EN : R/W; bitpos: [0]; default: 1; + * This field indicates if modem_apb clock is enable. 0: disable, 1: enable(default). + */ +#define PCR_MODEM_APB_CLK_EN (BIT(0)) +#define PCR_MODEM_APB_CLK_EN_M (PCR_MODEM_APB_CLK_EN_V << PCR_MODEM_APB_CLK_EN_S) +#define PCR_MODEM_APB_CLK_EN_V 0x00000001U +#define PCR_MODEM_APB_CLK_EN_S 0 +/** PCR_MODEM_RST_EN : R/W; bitpos: [1]; default: 0; + * Set this file as 1 to reset modem-subsystem. + */ +#define PCR_MODEM_RST_EN (BIT(1)) +#define PCR_MODEM_RST_EN_M (PCR_MODEM_RST_EN_V << PCR_MODEM_RST_EN_S) +#define PCR_MODEM_RST_EN_V 0x00000001U +#define PCR_MODEM_RST_EN_S 1 +/** PCR_MODEM_CLK_EN : R/W; bitpos: [2]; default: 1; + * This field indicates if modem source clock is enable. 0: disable, 1: + * enable(default). + */ +#define PCR_MODEM_CLK_EN (BIT(2)) +#define PCR_MODEM_CLK_EN_M (PCR_MODEM_CLK_EN_V << PCR_MODEM_CLK_EN_S) +#define PCR_MODEM_CLK_EN_V 0x00000001U +#define PCR_MODEM_CLK_EN_S 2 + +/** PCR_TIMEOUT_CONF_REG register + * TIMEOUT configuration register + */ +#define PCR_TIMEOUT_CONF_REG (DR_REG_PCR_BASE + 0x10c) +/** PCR_CPU_TIMEOUT_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset cpu_peri timeout module + */ +#define PCR_CPU_TIMEOUT_RST_EN (BIT(1)) +#define PCR_CPU_TIMEOUT_RST_EN_M (PCR_CPU_TIMEOUT_RST_EN_V << PCR_CPU_TIMEOUT_RST_EN_S) +#define PCR_CPU_TIMEOUT_RST_EN_V 0x00000001U +#define PCR_CPU_TIMEOUT_RST_EN_S 1 +/** PCR_HP_TIMEOUT_RST_EN : R/W; bitpos: [2]; default: 0; + * Set 1 to reset hp_peri timeout module and hp_modem timeout module + */ +#define PCR_HP_TIMEOUT_RST_EN (BIT(2)) +#define PCR_HP_TIMEOUT_RST_EN_M (PCR_HP_TIMEOUT_RST_EN_V << PCR_HP_TIMEOUT_RST_EN_S) +#define PCR_HP_TIMEOUT_RST_EN_V 0x00000001U +#define PCR_HP_TIMEOUT_RST_EN_S 2 + +/** PCR_SYSCLK_CONF_REG register + * SYSCLK configuration register + */ +#define PCR_SYSCLK_CONF_REG (DR_REG_PCR_BASE + 0x110) +/** PCR_LS_DIV_NUM : HRO; bitpos: [7:0]; default: 0; + * clk_hproot is div1 of low-speed clock-source if clck-source is a low-speed + * clock-source such as XTAL/FOSC. + */ +#define PCR_LS_DIV_NUM 0x000000FFU +#define PCR_LS_DIV_NUM_M (PCR_LS_DIV_NUM_V << PCR_LS_DIV_NUM_S) +#define PCR_LS_DIV_NUM_V 0x000000FFU +#define PCR_LS_DIV_NUM_S 0 +/** PCR_HS_DIV_NUM : HRO; bitpos: [15:8]; default: 2; + * clk_hproot is div3 of SPLL if the clock-source is high-speed clock SPLL. + */ +#define PCR_HS_DIV_NUM 0x000000FFU +#define PCR_HS_DIV_NUM_M (PCR_HS_DIV_NUM_V << PCR_HS_DIV_NUM_S) +#define PCR_HS_DIV_NUM_V 0x000000FFU +#define PCR_HS_DIV_NUM_S 8 +/** PCR_SOC_CLK_SEL : R/W; bitpos: [17:16]; default: 0; + * Configures to select the clock source of HP_ROOT_CLK. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F160M_CLK + * 2: PLL_F240M_CLK + */ +#define PCR_SOC_CLK_SEL 0x00000003U +#define PCR_SOC_CLK_SEL_M (PCR_SOC_CLK_SEL_V << PCR_SOC_CLK_SEL_S) +#define PCR_SOC_CLK_SEL_V 0x00000003U +#define PCR_SOC_CLK_SEL_S 16 +/** PCR_CLK_XTAL_FREQ : RO; bitpos: [30:24]; default: 40; + * This field indicates the frequency(MHz) of XTAL. + */ +#define PCR_CLK_XTAL_FREQ 0x0000007FU +#define PCR_CLK_XTAL_FREQ_M (PCR_CLK_XTAL_FREQ_V << PCR_CLK_XTAL_FREQ_S) +#define PCR_CLK_XTAL_FREQ_V 0x0000007FU +#define PCR_CLK_XTAL_FREQ_S 24 +/** PCR_CPU_DBGMD_CLK_EN : R/W; bitpos: [31]; default: 1; + * This field indicates if cpu debug mode clock is enable. 0: disable, 1: + * enable(default). + */ +#define PCR_CPU_DBGMD_CLK_EN (BIT(31)) +#define PCR_CPU_DBGMD_CLK_EN_M (PCR_CPU_DBGMD_CLK_EN_V << PCR_CPU_DBGMD_CLK_EN_S) +#define PCR_CPU_DBGMD_CLK_EN_V 0x00000001U +#define PCR_CPU_DBGMD_CLK_EN_S 31 + +/** PCR_CPU_WAITI_CONF_REG register + * CPU_WAITI configuration register + */ +#define PCR_CPU_WAITI_CONF_REG (DR_REG_PCR_BASE + 0x114) +/** PCR_CPU_WAIT_MODE_FORCE_ON : R/W; bitpos: [3]; default: 1; + * Set 1 to force cpu_waiti_clk enable. + */ +#define PCR_CPU_WAIT_MODE_FORCE_ON (BIT(3)) +#define PCR_CPU_WAIT_MODE_FORCE_ON_M (PCR_CPU_WAIT_MODE_FORCE_ON_V << PCR_CPU_WAIT_MODE_FORCE_ON_S) +#define PCR_CPU_WAIT_MODE_FORCE_ON_V 0x00000001U +#define PCR_CPU_WAIT_MODE_FORCE_ON_S 3 +/** PCR_CPU_WAITI_DELAY_NUM : R/W; bitpos: [7:4]; default: 0; + * This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk + * will close + */ +#define PCR_CPU_WAITI_DELAY_NUM 0x0000000FU +#define PCR_CPU_WAITI_DELAY_NUM_M (PCR_CPU_WAITI_DELAY_NUM_V << PCR_CPU_WAITI_DELAY_NUM_S) +#define PCR_CPU_WAITI_DELAY_NUM_V 0x0000000FU +#define PCR_CPU_WAITI_DELAY_NUM_S 4 + +/** PCR_CPU_FREQ_CONF_REG register + * CPU_FREQ configuration register + */ +#define PCR_CPU_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x118) +/** PCR_CPU_DIV_NUM : R/W; bitpos: [7:0]; default: 0; + * Set this field to generate clk_cpu derived by clk_hproot. The clk_cpu is + * div1(default)/div2/div4 of clk_hproot. This field is only available for low-speed + * clock-source such as XTAL/FOSC, and should be used together with PCR_AHB_DIV_NUM. + */ +#define PCR_CPU_DIV_NUM 0x000000FFU +#define PCR_CPU_DIV_NUM_M (PCR_CPU_DIV_NUM_V << PCR_CPU_DIV_NUM_S) +#define PCR_CPU_DIV_NUM_V 0x000000FFU +#define PCR_CPU_DIV_NUM_S 0 + +/** PCR_AHB_FREQ_CONF_REG register + * AHB_FREQ configuration register + */ +#define PCR_AHB_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x11c) +/** PCR_AHB_DIV_NUM : R/W; bitpos: [7:0]; default: 0; + * Set this field to generate clk_ahb derived by clk_hproot. The clk_ahb is + * div1(default)/div2/div4/div8 of clk_hproot. This field is only available for + * low-speed clock-source such as XTAL/FOSC, and should be used together with + * PCR_CPU_DIV_NUM. + */ +#define PCR_AHB_DIV_NUM 0x000000FFU +#define PCR_AHB_DIV_NUM_M (PCR_AHB_DIV_NUM_V << PCR_AHB_DIV_NUM_S) +#define PCR_AHB_DIV_NUM_V 0x000000FFU +#define PCR_AHB_DIV_NUM_S 0 + +/** PCR_APB_FREQ_CONF_REG register + * APB_FREQ configuration register + */ +#define PCR_APB_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x120) +/** PCR_APB_DECREASE_DIV_NUM : R/W; bitpos: [7:0]; default: 0; + * If this field's value is grater than PCR_APB_DIV_NUM, the clk_apb will be + * automatically down to clk_apb_decrease only when no access is on apb-bus, and will + * recover to the previous frequency when a new access appears on apb-bus. Set as one + * within (0,1,3) to set clk_apb_decrease as div1/div2/div4(default) of clk_ahb. Note + * that enable this function will reduce performance. Users can set this field as zero + * to disable the auto-decrease-apb-freq function. By default, this function is + * disable. + */ +#define PCR_APB_DECREASE_DIV_NUM 0x000000FFU +#define PCR_APB_DECREASE_DIV_NUM_M (PCR_APB_DECREASE_DIV_NUM_V << PCR_APB_DECREASE_DIV_NUM_S) +#define PCR_APB_DECREASE_DIV_NUM_V 0x000000FFU +#define PCR_APB_DECREASE_DIV_NUM_S 0 +/** PCR_APB_DIV_NUM : R/W; bitpos: [15:8]; default: 0; + * Set as one within (0,1,3) to generate clk_apb derived by clk_ahb. The clk_apb is + * div1(default)/div2/div4 of clk_ahb. + */ +#define PCR_APB_DIV_NUM 0x000000FFU +#define PCR_APB_DIV_NUM_M (PCR_APB_DIV_NUM_V << PCR_APB_DIV_NUM_S) +#define PCR_APB_DIV_NUM_V 0x000000FFU +#define PCR_APB_DIV_NUM_S 8 + +/** PCR_SYSCLK_FREQ_QUERY_0_REG register + * SYSCLK frequency query 0 register + */ +#define PCR_SYSCLK_FREQ_QUERY_0_REG (DR_REG_PCR_BASE + 0x124) +/** PCR_FOSC_FREQ : HRO; bitpos: [7:0]; default: 8; + * This field indicates the frequency(MHz) of FOSC. + */ +#define PCR_FOSC_FREQ 0x000000FFU +#define PCR_FOSC_FREQ_M (PCR_FOSC_FREQ_V << PCR_FOSC_FREQ_S) +#define PCR_FOSC_FREQ_V 0x000000FFU +#define PCR_FOSC_FREQ_S 0 +/** PCR_PLL_FREQ : HRO; bitpos: [17:8]; default: 96; + * This field indicates the frequency(MHz) of SPLL. + */ +#define PCR_PLL_FREQ 0x000003FFU +#define PCR_PLL_FREQ_M (PCR_PLL_FREQ_V << PCR_PLL_FREQ_S) +#define PCR_PLL_FREQ_V 0x000003FFU +#define PCR_PLL_FREQ_S 8 + +/** PCR_PLL_DIV_CLK_EN_REG register + * SPLL DIV clock-gating configuration register + */ +#define PCR_PLL_DIV_CLK_EN_REG (DR_REG_PCR_BASE + 0x128) +/** PCR_PLL_240M_CLK_EN : R/W; bitpos: [0]; default: 1; + * This field is used to open 240 MHz clock (div2 of SPLL) derived from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_240M_CLK_EN (BIT(0)) +#define PCR_PLL_240M_CLK_EN_M (PCR_PLL_240M_CLK_EN_V << PCR_PLL_240M_CLK_EN_S) +#define PCR_PLL_240M_CLK_EN_V 0x00000001U +#define PCR_PLL_240M_CLK_EN_S 0 +/** PCR_PLL_160M_CLK_EN : R/W; bitpos: [1]; default: 1; + * This field is used to open 160 MHz clock (div3 of SPLL) derived from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_160M_CLK_EN (BIT(1)) +#define PCR_PLL_160M_CLK_EN_M (PCR_PLL_160M_CLK_EN_V << PCR_PLL_160M_CLK_EN_S) +#define PCR_PLL_160M_CLK_EN_V 0x00000001U +#define PCR_PLL_160M_CLK_EN_S 1 +/** PCR_PLL_120M_CLK_EN : R/W; bitpos: [2]; default: 1; + * This field is used to open 120 MHz clock (div4 of SPLL) derived from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_120M_CLK_EN (BIT(2)) +#define PCR_PLL_120M_CLK_EN_M (PCR_PLL_120M_CLK_EN_V << PCR_PLL_120M_CLK_EN_S) +#define PCR_PLL_120M_CLK_EN_V 0x00000001U +#define PCR_PLL_120M_CLK_EN_S 2 +/** PCR_PLL_80M_CLK_EN : R/W; bitpos: [3]; default: 1; + * This field is used to open 80 MHz clock (div6 of SPLL) derived from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_80M_CLK_EN (BIT(3)) +#define PCR_PLL_80M_CLK_EN_M (PCR_PLL_80M_CLK_EN_V << PCR_PLL_80M_CLK_EN_S) +#define PCR_PLL_80M_CLK_EN_V 0x00000001U +#define PCR_PLL_80M_CLK_EN_S 3 +/** PCR_PLL_60M_CLK_EN : R/W; bitpos: [4]; default: 1; + * This field is used to open 60 MHz clock (div8 of SPLL) derived from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_60M_CLK_EN (BIT(4)) +#define PCR_PLL_60M_CLK_EN_M (PCR_PLL_60M_CLK_EN_V << PCR_PLL_60M_CLK_EN_S) +#define PCR_PLL_60M_CLK_EN_V 0x00000001U +#define PCR_PLL_60M_CLK_EN_S 4 +/** PCR_PLL_48M_CLK_EN : R/W; bitpos: [5]; default: 1; + * This field is used to open 48 MHz clock (div10 of SPLL) derived from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_48M_CLK_EN (BIT(5)) +#define PCR_PLL_48M_CLK_EN_M (PCR_PLL_48M_CLK_EN_V << PCR_PLL_48M_CLK_EN_S) +#define PCR_PLL_48M_CLK_EN_V 0x00000001U +#define PCR_PLL_48M_CLK_EN_S 5 +/** PCR_PLL_40M_CLK_EN : R/W; bitpos: [6]; default: 1; + * This field is used to open 40 MHz clock (div12 of SPLL) derived from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_40M_CLK_EN (BIT(6)) +#define PCR_PLL_40M_CLK_EN_M (PCR_PLL_40M_CLK_EN_V << PCR_PLL_40M_CLK_EN_S) +#define PCR_PLL_40M_CLK_EN_V 0x00000001U +#define PCR_PLL_40M_CLK_EN_S 6 +/** PCR_PLL_20M_CLK_EN : R/W; bitpos: [7]; default: 1; + * This field is used to open 20 MHz clock (div24 of SPLL) derived from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_20M_CLK_EN (BIT(7)) +#define PCR_PLL_20M_CLK_EN_M (PCR_PLL_20M_CLK_EN_V << PCR_PLL_20M_CLK_EN_S) +#define PCR_PLL_20M_CLK_EN_V 0x00000001U +#define PCR_PLL_20M_CLK_EN_S 7 +/** PCR_PLL_12M_CLK_EN : R/W; bitpos: [8]; default: 1; + * This field is used to open 12 MHz clock (div40 of SPLL) derived from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_12M_CLK_EN (BIT(8)) +#define PCR_PLL_12M_CLK_EN_M (PCR_PLL_12M_CLK_EN_V << PCR_PLL_12M_CLK_EN_S) +#define PCR_PLL_12M_CLK_EN_V 0x00000001U +#define PCR_PLL_12M_CLK_EN_S 8 + +/** PCR_CTRL_CLK_OUT_EN_REG register + * CLK_OUT_EN configuration register + */ +#define PCR_CTRL_CLK_OUT_EN_REG (DR_REG_PCR_BASE + 0x12c) +/** PCR_CLK20_OEN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable 20m clock + */ +#define PCR_CLK20_OEN (BIT(0)) +#define PCR_CLK20_OEN_M (PCR_CLK20_OEN_V << PCR_CLK20_OEN_S) +#define PCR_CLK20_OEN_V 0x00000001U +#define PCR_CLK20_OEN_S 0 +/** PCR_CLK22_OEN : R/W; bitpos: [1]; default: 1; + * Set 1 to enable 22m clock + */ +#define PCR_CLK22_OEN (BIT(1)) +#define PCR_CLK22_OEN_M (PCR_CLK22_OEN_V << PCR_CLK22_OEN_S) +#define PCR_CLK22_OEN_V 0x00000001U +#define PCR_CLK22_OEN_S 1 +/** PCR_CLK44_OEN : R/W; bitpos: [2]; default: 1; + * Set 1 to enable 44m clock + */ +#define PCR_CLK44_OEN (BIT(2)) +#define PCR_CLK44_OEN_M (PCR_CLK44_OEN_V << PCR_CLK44_OEN_S) +#define PCR_CLK44_OEN_V 0x00000001U +#define PCR_CLK44_OEN_S 2 +/** PCR_CLK_BB_OEN : R/W; bitpos: [3]; default: 1; + * Set 1 to enable bb clock + */ +#define PCR_CLK_BB_OEN (BIT(3)) +#define PCR_CLK_BB_OEN_M (PCR_CLK_BB_OEN_V << PCR_CLK_BB_OEN_S) +#define PCR_CLK_BB_OEN_V 0x00000001U +#define PCR_CLK_BB_OEN_S 3 +/** PCR_CLK80_OEN : R/W; bitpos: [4]; default: 1; + * Set 1 to enable 80m clock + */ +#define PCR_CLK80_OEN (BIT(4)) +#define PCR_CLK80_OEN_M (PCR_CLK80_OEN_V << PCR_CLK80_OEN_S) +#define PCR_CLK80_OEN_V 0x00000001U +#define PCR_CLK80_OEN_S 4 +/** PCR_CLK160_OEN : R/W; bitpos: [5]; default: 1; + * Set 1 to enable 160m clock + */ +#define PCR_CLK160_OEN (BIT(5)) +#define PCR_CLK160_OEN_M (PCR_CLK160_OEN_V << PCR_CLK160_OEN_S) +#define PCR_CLK160_OEN_V 0x00000001U +#define PCR_CLK160_OEN_S 5 +/** PCR_CLK_480M_OEN : R/W; bitpos: [6]; default: 1; + * Set 1 to enable 480m clock + */ +#define PCR_CLK_480M_OEN (BIT(6)) +#define PCR_CLK_480M_OEN_M (PCR_CLK_480M_OEN_V << PCR_CLK_480M_OEN_S) +#define PCR_CLK_480M_OEN_V 0x00000001U +#define PCR_CLK_480M_OEN_S 6 +/** PCR_CLK_ADC_INF_OEN : R/W; bitpos: [7]; default: 1; + * Reserved + */ +#define PCR_CLK_ADC_INF_OEN (BIT(7)) +#define PCR_CLK_ADC_INF_OEN_M (PCR_CLK_ADC_INF_OEN_V << PCR_CLK_ADC_INF_OEN_S) +#define PCR_CLK_ADC_INF_OEN_V 0x00000001U +#define PCR_CLK_ADC_INF_OEN_S 7 +/** PCR_CLK_DAC_CPU_OEN : R/W; bitpos: [8]; default: 1; + * Reserved + */ +#define PCR_CLK_DAC_CPU_OEN (BIT(8)) +#define PCR_CLK_DAC_CPU_OEN_M (PCR_CLK_DAC_CPU_OEN_V << PCR_CLK_DAC_CPU_OEN_S) +#define PCR_CLK_DAC_CPU_OEN_V 0x00000001U +#define PCR_CLK_DAC_CPU_OEN_S 8 +/** PCR_CLK40X_BB_OEN : R/W; bitpos: [9]; default: 1; + * Reserved + */ +#define PCR_CLK40X_BB_OEN (BIT(9)) +#define PCR_CLK40X_BB_OEN_M (PCR_CLK40X_BB_OEN_V << PCR_CLK40X_BB_OEN_S) +#define PCR_CLK40X_BB_OEN_V 0x00000001U +#define PCR_CLK40X_BB_OEN_S 9 +/** PCR_CLK_XTAL_OEN : R/W; bitpos: [10]; default: 1; + * Set 1 to enable xtal clock + */ +#define PCR_CLK_XTAL_OEN (BIT(10)) +#define PCR_CLK_XTAL_OEN_M (PCR_CLK_XTAL_OEN_V << PCR_CLK_XTAL_OEN_S) +#define PCR_CLK_XTAL_OEN_V 0x00000001U +#define PCR_CLK_XTAL_OEN_S 10 + +/** PCR_CTRL_32K_CONF_REG register + * 32KHz clock configuration register + */ +#define PCR_CTRL_32K_CONF_REG (DR_REG_PCR_BASE + 0x130) +/** PCR_32K_SEL : R/W; bitpos: [2:0]; default: 0; + * Configures the 32KHz clock for TIMER_GROUP. + * 0 (default): RC32K_CLK + * 1: XTAL32K_CLK + * 2: OSC_SLOW_CLK + * 3: RC_SLOW_CLK + * 4: RC_FAST_CLK + */ +#define PCR_32K_SEL 0x00000007U +#define PCR_32K_SEL_M (PCR_32K_SEL_V << PCR_32K_SEL_S) +#define PCR_32K_SEL_V 0x00000007U +#define PCR_32K_SEL_S 0 +/** PCR_FOSC_TICK_NUM : R/W; bitpos: [15:8]; default: 7; + * When PCR_32K_SEL set as 4, This field PCR_FOSC_TICK_NUM is used to set the divider + * number of fosc. + */ +#define PCR_FOSC_TICK_NUM 0x000000FFU +#define PCR_FOSC_TICK_NUM_M (PCR_FOSC_TICK_NUM_V << PCR_FOSC_TICK_NUM_S) +#define PCR_FOSC_TICK_NUM_V 0x000000FFU +#define PCR_FOSC_TICK_NUM_S 8 + +/** PCR_SRAM_POWER_CONF_0_REG register + * HP SRAM/ROM configuration register + */ +#define PCR_SRAM_POWER_CONF_0_REG (DR_REG_PCR_BASE + 0x134) +/** PCR_ROM_FORCE_PU : R/W; bitpos: [2:0]; default: 7; + * Set this bit to force power up ROM + */ +#define PCR_ROM_FORCE_PU 0x00000007U +#define PCR_ROM_FORCE_PU_M (PCR_ROM_FORCE_PU_V << PCR_ROM_FORCE_PU_S) +#define PCR_ROM_FORCE_PU_V 0x00000007U +#define PCR_ROM_FORCE_PU_S 0 +/** PCR_ROM_FORCE_PD : R/W; bitpos: [5:3]; default: 0; + * Set this bit to force power down ROM. + */ +#define PCR_ROM_FORCE_PD 0x00000007U +#define PCR_ROM_FORCE_PD_M (PCR_ROM_FORCE_PD_V << PCR_ROM_FORCE_PD_S) +#define PCR_ROM_FORCE_PD_V 0x00000007U +#define PCR_ROM_FORCE_PD_S 3 +/** PCR_ROM_CLKGATE_FORCE_ON : R/W; bitpos: [8:6]; default: 0; + * 1: Force to open the clock and bypass the gate-clock when accessing the ROM. 0: A + * gate-clock will be used when accessing the ROM. + */ +#define PCR_ROM_CLKGATE_FORCE_ON 0x00000007U +#define PCR_ROM_CLKGATE_FORCE_ON_M (PCR_ROM_CLKGATE_FORCE_ON_V << PCR_ROM_CLKGATE_FORCE_ON_S) +#define PCR_ROM_CLKGATE_FORCE_ON_V 0x00000007U +#define PCR_ROM_CLKGATE_FORCE_ON_S 6 + +/** PCR_SRAM_POWER_CONF_1_REG register + * HP SRAM/ROM configuration register + */ +#define PCR_SRAM_POWER_CONF_1_REG (DR_REG_PCR_BASE + 0x138) +/** PCR_SRAM_FORCE_PU : R/W; bitpos: [3:0]; default: 15; + * Set this bit to force power up SRAM + */ +#define PCR_SRAM_FORCE_PU 0x0000000FU +#define PCR_SRAM_FORCE_PU_M (PCR_SRAM_FORCE_PU_V << PCR_SRAM_FORCE_PU_S) +#define PCR_SRAM_FORCE_PU_V 0x0000000FU +#define PCR_SRAM_FORCE_PU_S 0 +/** PCR_SRAM_FORCE_PD : R/W; bitpos: [13:10]; default: 0; + * Set this bit to force power down SRAM. + */ +#define PCR_SRAM_FORCE_PD 0x0000000FU +#define PCR_SRAM_FORCE_PD_M (PCR_SRAM_FORCE_PD_V << PCR_SRAM_FORCE_PD_S) +#define PCR_SRAM_FORCE_PD_V 0x0000000FU +#define PCR_SRAM_FORCE_PD_S 10 +/** PCR_SRAM_CLKGATE_FORCE_ON : R/W; bitpos: [23:20]; default: 0; + * 1: Force to open the clock and bypass the gate-clock when accessing the SRAM. 0: A + * gate-clock will be used when accessing the SRAM. + */ +#define PCR_SRAM_CLKGATE_FORCE_ON 0x0000000FU +#define PCR_SRAM_CLKGATE_FORCE_ON_M (PCR_SRAM_CLKGATE_FORCE_ON_V << PCR_SRAM_CLKGATE_FORCE_ON_S) +#define PCR_SRAM_CLKGATE_FORCE_ON_V 0x0000000FU +#define PCR_SRAM_CLKGATE_FORCE_ON_S 20 + +/** PCR_SEC_CONF_REG register + * Clock source configuration register for External Memory Encryption and Decryption + */ +#define PCR_SEC_CONF_REG (DR_REG_PCR_BASE + 0x13c) +/** PCR_SEC_CLK_SEL : R/W; bitpos: [1:0]; default: 0; + * Configures the clock source for the External Memory Encryption and Decryption + * module. + * 0(default): XTAL_CLK + * 1 RC_FAST_CLK + * 2: PLL_F480M_CLK + */ +#define PCR_SEC_CLK_SEL 0x00000003U +#define PCR_SEC_CLK_SEL_M (PCR_SEC_CLK_SEL_V << PCR_SEC_CLK_SEL_S) +#define PCR_SEC_CLK_SEL_V 0x00000003U +#define PCR_SEC_CLK_SEL_S 0 +/** PCR_SEC_RST_EN : R/W; bitpos: [2]; default: 0; + * Set 1 to reset sec module + */ +#define PCR_SEC_RST_EN (BIT(2)) +#define PCR_SEC_RST_EN_M (PCR_SEC_RST_EN_V << PCR_SEC_RST_EN_S) +#define PCR_SEC_RST_EN_V 0x00000001U +#define PCR_SEC_RST_EN_S 2 + +/** PCR_BUS_CLK_UPDATE_REG register + * Configuration register for applying updated high-performance system clock sources + */ +#define PCR_BUS_CLK_UPDATE_REG (DR_REG_PCR_BASE + 0x144) +/** PCR_BUS_CLOCK_UPDATE : R/W/WTC; bitpos: [0]; default: 0; + * Configures whether or not to update configurations for CPU_CLK division, AHB_CLK + * division and HP_ROOT_CLK clock source selection. + * 0: Not update configurations + * 1: Update configurations + * This bit is automatically cleared when configurations have been updated. + */ +#define PCR_BUS_CLOCK_UPDATE (BIT(0)) +#define PCR_BUS_CLOCK_UPDATE_M (PCR_BUS_CLOCK_UPDATE_V << PCR_BUS_CLOCK_UPDATE_S) +#define PCR_BUS_CLOCK_UPDATE_V 0x00000001U +#define PCR_BUS_CLOCK_UPDATE_S 0 + +/** PCR_SAR_CLK_DIV_REG register + * SAR ADC clock divisor configuration register + */ +#define PCR_SAR_CLK_DIV_REG (DR_REG_PCR_BASE + 0x148) +/** PCR_SAR2_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 4; + * Configures the divisor for SAR ADC 2 clock to generate ADC analog control signals. + */ +#define PCR_SAR2_CLK_DIV_NUM 0x000000FFU +#define PCR_SAR2_CLK_DIV_NUM_M (PCR_SAR2_CLK_DIV_NUM_V << PCR_SAR2_CLK_DIV_NUM_S) +#define PCR_SAR2_CLK_DIV_NUM_V 0x000000FFU +#define PCR_SAR2_CLK_DIV_NUM_S 0 +/** PCR_SAR1_CLK_DIV_NUM : R/W; bitpos: [15:8]; default: 4; + * Configures the divisor for SAR ADC 1 clock to generate ADC analog control signals. + */ +#define PCR_SAR1_CLK_DIV_NUM 0x000000FFU +#define PCR_SAR1_CLK_DIV_NUM_M (PCR_SAR1_CLK_DIV_NUM_V << PCR_SAR1_CLK_DIV_NUM_S) +#define PCR_SAR1_CLK_DIV_NUM_V 0x000000FFU +#define PCR_SAR1_CLK_DIV_NUM_S 8 + +/** PCR_BS_CONF_REG register + * BS configuration register + */ +#define PCR_BS_CONF_REG (DR_REG_PCR_BASE + 0x150) +/** PCR_BS_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable bs clock + */ +#define PCR_BS_CLK_EN (BIT(0)) +#define PCR_BS_CLK_EN_M (PCR_BS_CLK_EN_V << PCR_BS_CLK_EN_S) +#define PCR_BS_CLK_EN_V 0x00000001U +#define PCR_BS_CLK_EN_S 0 +/** PCR_BS_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset bs module + */ +#define PCR_BS_RST_EN (BIT(1)) +#define PCR_BS_RST_EN_M (PCR_BS_RST_EN_V << PCR_BS_RST_EN_S) +#define PCR_BS_RST_EN_V 0x00000001U +#define PCR_BS_RST_EN_S 1 + +/** PCR_BS_FUNC_CONF_REG register + * BS_FUNC_CLK configuration register + */ +#define PCR_BS_FUNC_CONF_REG (DR_REG_PCR_BASE + 0x154) +/** PCR_BS_TX_RST_EN : R/W; bitpos: [23]; default: 0; + * Set 1 to reset bs tx module + */ +#define PCR_BS_TX_RST_EN (BIT(23)) +#define PCR_BS_TX_RST_EN_M (PCR_BS_TX_RST_EN_V << PCR_BS_TX_RST_EN_S) +#define PCR_BS_TX_RST_EN_V 0x00000001U +#define PCR_BS_TX_RST_EN_S 23 +/** PCR_BS_RX_RST_EN : R/W; bitpos: [24]; default: 0; + * Set 1 to reset bs rx module + */ +#define PCR_BS_RX_RST_EN (BIT(24)) +#define PCR_BS_RX_RST_EN_M (PCR_BS_RX_RST_EN_V << PCR_BS_RX_RST_EN_S) +#define PCR_BS_RX_RST_EN_V 0x00000001U +#define PCR_BS_RX_RST_EN_S 24 + +/** PCR_BS_PD_CTRL_REG register + * BS power control register + */ +#define PCR_BS_PD_CTRL_REG (DR_REG_PCR_BASE + 0x158) +/** PCR_BS_MEM_FORCE_PU : R/W; bitpos: [1]; default: 0; + * Set this bit to force power up bs memory. + */ +#define PCR_BS_MEM_FORCE_PU (BIT(1)) +#define PCR_BS_MEM_FORCE_PU_M (PCR_BS_MEM_FORCE_PU_V << PCR_BS_MEM_FORCE_PU_S) +#define PCR_BS_MEM_FORCE_PU_V 0x00000001U +#define PCR_BS_MEM_FORCE_PU_S 1 +/** PCR_BS_MEM_FORCE_PD : R/W; bitpos: [2]; default: 1; + * Set this bit to force power down bs memory. + */ +#define PCR_BS_MEM_FORCE_PD (BIT(2)) +#define PCR_BS_MEM_FORCE_PD_M (PCR_BS_MEM_FORCE_PD_V << PCR_BS_MEM_FORCE_PD_S) +#define PCR_BS_MEM_FORCE_PD_V 0x00000001U +#define PCR_BS_MEM_FORCE_PD_S 2 + +/** PCR_TIMERGROUP_WDT_CONF_REG register + * TIMERGROUP_WDT configuration register + */ +#define PCR_TIMERGROUP_WDT_CONF_REG (DR_REG_PCR_BASE + 0x15c) +/** PCR_TG0_WDT_RST_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to reset timer_group0 wdt module + */ +#define PCR_TG0_WDT_RST_EN (BIT(0)) +#define PCR_TG0_WDT_RST_EN_M (PCR_TG0_WDT_RST_EN_V << PCR_TG0_WDT_RST_EN_S) +#define PCR_TG0_WDT_RST_EN_V 0x00000001U +#define PCR_TG0_WDT_RST_EN_S 0 +/** PCR_TG1_WDT_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset timer_group1 wdt module + */ +#define PCR_TG1_WDT_RST_EN (BIT(1)) +#define PCR_TG1_WDT_RST_EN_M (PCR_TG1_WDT_RST_EN_V << PCR_TG1_WDT_RST_EN_S) +#define PCR_TG1_WDT_RST_EN_V 0x00000001U +#define PCR_TG1_WDT_RST_EN_S 1 + +/** PCR_TIMERGROUP_XTAL_CONF_REG register + * TIMERGROUP1 configuration register + */ +#define PCR_TIMERGROUP_XTAL_CONF_REG (DR_REG_PCR_BASE + 0x160) +/** PCR_TG0_XTAL_RST_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to reset timer_group0 xtal clock domain + */ +#define PCR_TG0_XTAL_RST_EN (BIT(0)) +#define PCR_TG0_XTAL_RST_EN_M (PCR_TG0_XTAL_RST_EN_V << PCR_TG0_XTAL_RST_EN_S) +#define PCR_TG0_XTAL_RST_EN_V 0x00000001U +#define PCR_TG0_XTAL_RST_EN_S 0 +/** PCR_TG1_XTAL_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset timer_group1 xtal clock domain + */ +#define PCR_TG1_XTAL_RST_EN (BIT(1)) +#define PCR_TG1_XTAL_RST_EN_M (PCR_TG1_XTAL_RST_EN_V << PCR_TG1_XTAL_RST_EN_S) +#define PCR_TG1_XTAL_RST_EN_V 0x00000001U +#define PCR_TG1_XTAL_RST_EN_S 1 +/** PCR_TG0_XTAL_CLK_EN : R/W; bitpos: [2]; default: 1; + * Set 1 to enable tg0 xtal clock + */ +#define PCR_TG0_XTAL_CLK_EN (BIT(2)) +#define PCR_TG0_XTAL_CLK_EN_M (PCR_TG0_XTAL_CLK_EN_V << PCR_TG0_XTAL_CLK_EN_S) +#define PCR_TG0_XTAL_CLK_EN_V 0x00000001U +#define PCR_TG0_XTAL_CLK_EN_S 2 + +/** PCR_KM_CONF_REG register + * Key Manager configuration register + */ +#define PCR_KM_CONF_REG (DR_REG_PCR_BASE + 0x164) +/** PCR_KM_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable km clock + */ +#define PCR_KM_CLK_EN (BIT(0)) +#define PCR_KM_CLK_EN_M (PCR_KM_CLK_EN_V << PCR_KM_CLK_EN_S) +#define PCR_KM_CLK_EN_V 0x00000001U +#define PCR_KM_CLK_EN_S 0 +/** PCR_KM_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset km module + */ +#define PCR_KM_RST_EN (BIT(1)) +#define PCR_KM_RST_EN_M (PCR_KM_RST_EN_V << PCR_KM_RST_EN_S) +#define PCR_KM_RST_EN_V 0x00000001U +#define PCR_KM_RST_EN_S 1 +/** PCR_KM_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset km module + */ +#define PCR_KM_READY (BIT(2)) +#define PCR_KM_READY_M (PCR_KM_READY_V << PCR_KM_READY_S) +#define PCR_KM_READY_V 0x00000001U +#define PCR_KM_READY_S 2 + +/** PCR_KM_PD_CTRL_REG register + * Key Manager power control register + */ +#define PCR_KM_PD_CTRL_REG (DR_REG_PCR_BASE + 0x168) +/** PCR_KM_MEM_FORCE_PU : R/W; bitpos: [1]; default: 0; + * Set this bit to force power up KM memory. + */ +#define PCR_KM_MEM_FORCE_PU (BIT(1)) +#define PCR_KM_MEM_FORCE_PU_M (PCR_KM_MEM_FORCE_PU_V << PCR_KM_MEM_FORCE_PU_S) +#define PCR_KM_MEM_FORCE_PU_V 0x00000001U +#define PCR_KM_MEM_FORCE_PU_S 1 +/** PCR_KM_MEM_FORCE_PD : R/W; bitpos: [2]; default: 1; + * Set this bit to force power down KM memory. + */ +#define PCR_KM_MEM_FORCE_PD (BIT(2)) +#define PCR_KM_MEM_FORCE_PD_M (PCR_KM_MEM_FORCE_PD_V << PCR_KM_MEM_FORCE_PD_S) +#define PCR_KM_MEM_FORCE_PD_V 0x00000001U +#define PCR_KM_MEM_FORCE_PD_S 2 + +/** PCR_TCM_MEM_MONITOR_CONF_REG register + * TCM_MEM_MONITOR configuration register + */ +#define PCR_TCM_MEM_MONITOR_CONF_REG (DR_REG_PCR_BASE + 0x16c) +/** PCR_TCM_MEM_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable tcm_mem_monitor clock + */ +#define PCR_TCM_MEM_MONITOR_CLK_EN (BIT(0)) +#define PCR_TCM_MEM_MONITOR_CLK_EN_M (PCR_TCM_MEM_MONITOR_CLK_EN_V << PCR_TCM_MEM_MONITOR_CLK_EN_S) +#define PCR_TCM_MEM_MONITOR_CLK_EN_V 0x00000001U +#define PCR_TCM_MEM_MONITOR_CLK_EN_S 0 +/** PCR_TCM_MEM_MONITOR_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset tcm_mem_monitor module + */ +#define PCR_TCM_MEM_MONITOR_RST_EN (BIT(1)) +#define PCR_TCM_MEM_MONITOR_RST_EN_M (PCR_TCM_MEM_MONITOR_RST_EN_V << PCR_TCM_MEM_MONITOR_RST_EN_S) +#define PCR_TCM_MEM_MONITOR_RST_EN_V 0x00000001U +#define PCR_TCM_MEM_MONITOR_RST_EN_S 1 +/** PCR_TCM_MEM_MONITOR_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset tcm_mem_monitor module + */ +#define PCR_TCM_MEM_MONITOR_READY (BIT(2)) +#define PCR_TCM_MEM_MONITOR_READY_M (PCR_TCM_MEM_MONITOR_READY_V << PCR_TCM_MEM_MONITOR_READY_S) +#define PCR_TCM_MEM_MONITOR_READY_V 0x00000001U +#define PCR_TCM_MEM_MONITOR_READY_S 2 + +/** PCR_PSRAM_MEM_MONITOR_CONF_REG register + * PSRAM_MEM_MONITOR configuration register + */ +#define PCR_PSRAM_MEM_MONITOR_CONF_REG (DR_REG_PCR_BASE + 0x170) +/** PCR_PSRAM_MEM_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable psram_mem_monitor clock + */ +#define PCR_PSRAM_MEM_MONITOR_CLK_EN (BIT(0)) +#define PCR_PSRAM_MEM_MONITOR_CLK_EN_M (PCR_PSRAM_MEM_MONITOR_CLK_EN_V << PCR_PSRAM_MEM_MONITOR_CLK_EN_S) +#define PCR_PSRAM_MEM_MONITOR_CLK_EN_V 0x00000001U +#define PCR_PSRAM_MEM_MONITOR_CLK_EN_S 0 +/** PCR_PSRAM_MEM_MONITOR_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset psram_mem_monitor module + */ +#define PCR_PSRAM_MEM_MONITOR_RST_EN (BIT(1)) +#define PCR_PSRAM_MEM_MONITOR_RST_EN_M (PCR_PSRAM_MEM_MONITOR_RST_EN_V << PCR_PSRAM_MEM_MONITOR_RST_EN_S) +#define PCR_PSRAM_MEM_MONITOR_RST_EN_V 0x00000001U +#define PCR_PSRAM_MEM_MONITOR_RST_EN_S 1 +/** PCR_PSRAM_MEM_MONITOR_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset psram_mem_monitor module + */ +#define PCR_PSRAM_MEM_MONITOR_READY (BIT(2)) +#define PCR_PSRAM_MEM_MONITOR_READY_M (PCR_PSRAM_MEM_MONITOR_READY_V << PCR_PSRAM_MEM_MONITOR_READY_S) +#define PCR_PSRAM_MEM_MONITOR_READY_V 0x00000001U +#define PCR_PSRAM_MEM_MONITOR_READY_S 2 + +/** PCR_RESET_EVENT_BYPASS_REG register + * reset event bypass backdoor configuration register + */ +#define PCR_RESET_EVENT_BYPASS_REG (DR_REG_PCR_BASE + 0x174) +/** PCR_RESET_EVENT_BYPASS_APM : R/W; bitpos: [0]; default: 0; + * This field is used to control reset event relationship for + * tee_reg/apm_reg/hp_system_reg. 1: tee_reg/apm_reg/hp_system_reg will only be reset + * by power-reset. some reset event will be bypass. 0: tee_reg/apm_reg/hp_system_reg + * will not only be reset by power-reset, but also some reset event. + */ +#define PCR_RESET_EVENT_BYPASS_APM (BIT(0)) +#define PCR_RESET_EVENT_BYPASS_APM_M (PCR_RESET_EVENT_BYPASS_APM_V << PCR_RESET_EVENT_BYPASS_APM_S) +#define PCR_RESET_EVENT_BYPASS_APM_V 0x00000001U +#define PCR_RESET_EVENT_BYPASS_APM_S 0 +/** PCR_RESET_EVENT_BYPASS : R/W; bitpos: [1]; default: 1; + * This field is used to control reset event relationship for system-bus. 1: system + * bus (including arbiter/router) will only be reset by power-reset. some reset event + * will be bypass. 0: system bus (including arbiter/router) will not only be reset by + * power-reset, but also some reset event. + */ +#define PCR_RESET_EVENT_BYPASS (BIT(1)) +#define PCR_RESET_EVENT_BYPASS_M (PCR_RESET_EVENT_BYPASS_V << PCR_RESET_EVENT_BYPASS_S) +#define PCR_RESET_EVENT_BYPASS_V 0x00000001U +#define PCR_RESET_EVENT_BYPASS_S 1 + +/** PCR_HPCORE_0_PD_CTRL_REG register + * HP CORE0 power control register + */ +#define PCR_HPCORE_0_PD_CTRL_REG (DR_REG_PCR_BASE + 0x178) +/** PCR_HPCORE_0_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1; + * Set this bit to force power up HP CORE0 memory. + */ +#define PCR_HPCORE_0_MEM_FORCE_PU (BIT(1)) +#define PCR_HPCORE_0_MEM_FORCE_PU_M (PCR_HPCORE_0_MEM_FORCE_PU_V << PCR_HPCORE_0_MEM_FORCE_PU_S) +#define PCR_HPCORE_0_MEM_FORCE_PU_V 0x00000001U +#define PCR_HPCORE_0_MEM_FORCE_PU_S 1 +/** PCR_HPCORE_0_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; + * Set this bit to force power down HP CORE0 memory. + */ +#define PCR_HPCORE_0_MEM_FORCE_PD (BIT(2)) +#define PCR_HPCORE_0_MEM_FORCE_PD_M (PCR_HPCORE_0_MEM_FORCE_PD_V << PCR_HPCORE_0_MEM_FORCE_PD_S) +#define PCR_HPCORE_0_MEM_FORCE_PD_V 0x00000001U +#define PCR_HPCORE_0_MEM_FORCE_PD_S 2 + +/** PCR_SDIO_SLAVE_CONF_REG register + * SDIO_SLAVE configuration register + */ +#define PCR_SDIO_SLAVE_CONF_REG (DR_REG_PCR_BASE + 0x17c) +/** PCR_SDIO_SLAVE_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable sdio_slave clock + */ +#define PCR_SDIO_SLAVE_CLK_EN (BIT(0)) +#define PCR_SDIO_SLAVE_CLK_EN_M (PCR_SDIO_SLAVE_CLK_EN_V << PCR_SDIO_SLAVE_CLK_EN_S) +#define PCR_SDIO_SLAVE_CLK_EN_V 0x00000001U +#define PCR_SDIO_SLAVE_CLK_EN_S 0 +/** PCR_SDIO_SLAVE_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset sdio_slave module + */ +#define PCR_SDIO_SLAVE_RST_EN (BIT(1)) +#define PCR_SDIO_SLAVE_RST_EN_M (PCR_SDIO_SLAVE_RST_EN_V << PCR_SDIO_SLAVE_RST_EN_S) +#define PCR_SDIO_SLAVE_RST_EN_V 0x00000001U +#define PCR_SDIO_SLAVE_RST_EN_S 1 + +/** PCR_FPGA_DEBUG_REG register + * fpga debug register + */ +#define PCR_FPGA_DEBUG_REG (DR_REG_PCR_BASE + 0xff4) +/** PCR_FPGA_DEBUG : R/W; bitpos: [31:0]; default: 4294967295; + * Only used in fpga debug. + */ +#define PCR_FPGA_DEBUG 0xFFFFFFFFU +#define PCR_FPGA_DEBUG_M (PCR_FPGA_DEBUG_V << PCR_FPGA_DEBUG_S) +#define PCR_FPGA_DEBUG_V 0xFFFFFFFFU +#define PCR_FPGA_DEBUG_S 0 + +/** PCR_CLOCK_GATE_REG register + * PCR clock gating configure register + */ +#define PCR_CLOCK_GATE_REG (DR_REG_PCR_BASE + 0xff8) +/** PCR_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set this bit as 1 to force on clock gating. + */ +#define PCR_CLK_EN (BIT(0)) +#define PCR_CLK_EN_M (PCR_CLK_EN_V << PCR_CLK_EN_S) +#define PCR_CLK_EN_V 0x00000001U +#define PCR_CLK_EN_S 0 + +/** PCR_DATE_REG register + * Date register. + */ +#define PCR_DATE_REG (DR_REG_PCR_BASE + 0xffc) +/** PCR_DATE : R/W; bitpos: [27:0]; default: 2363425; + * PCR version information. + */ +#define PCR_DATE 0x0FFFFFFFU +#define PCR_DATE_M (PCR_DATE_V << PCR_DATE_S) +#define PCR_DATE_V 0x0FFFFFFFU +#define PCR_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/src/target/esp32c5/ld/esp32c5.rom.api.ld b/src/target/esp32c5/ld/esp32c5.rom.api.ld index dcb922d..8b530f2 100644 --- a/src/target/esp32c5/ld/esp32c5.rom.api.ld +++ b/src/target/esp32c5/ld/esp32c5.rom.api.ld @@ -28,7 +28,6 @@ PROVIDE ( esp_rom_uart_putc = ets_write_char_uart ); PROVIDE ( esp_rom_uart_attach = uartAttach ); PROVIDE ( esp_rom_uart_init = Uart_Init ); PROVIDE ( esp_rom_uart_div_modify = uart_div_modify ); -PROVIDE ( esp_rom_get_apb_freq = ets_get_apb_freq ); PROVIDE ( esp_rom_get_cpu_freq = ets_clk_get_cpu_freq ); PROVIDE ( esp_rom_get_uart_device = GetUartDevice ); @@ -58,6 +57,7 @@ PROVIDE ( esp_rom_isr_attach = ets_isr_attach ); PROVIDE ( esp_rom_isr_unmask = ets_isr_unmask ); PROVIDE ( esp_rom_get_cpu_ticks_per_us = ets_get_cpu_frequency ); PROVIDE ( esp_rom_set_cpu_ticks_per_us = ets_update_cpu_frequency ); +PROVIDE ( esp_rom_get_xtal_freq = ets_clk_get_xtal_freq ); PROVIDE ( esp_rom_spiflash_attach = spi_flash_attach ); PROVIDE ( esp_rom_spiflash_clear_bp = esp_rom_spiflash_unlock ); diff --git a/src/target/esp32c5/src/clock.c b/src/target/esp32c5/src/clock.c new file mode 100644 index 0000000..fa72842 --- /dev/null +++ b/src/target/esp32c5/src/clock.c @@ -0,0 +1,38 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 OR MIT + */ + +#include +#include +#include +#include +#include +#include + +#define MHZ 1000000 + +extern uint32_t esp_rom_get_cpu_freq(void); +extern void esp_rom_set_cpu_ticks_per_us(uint32_t ticks_per_us); + +static uint32_t s_cpu_freq = 0; + +void stub_target_clock_init(void) +{ + REG_SET_FIELD(PCR_SYSCLK_CONF_REG, PCR_SOC_CLK_SEL, 2); + REG_SET_FIELD(PCR_BUS_CLK_UPDATE_REG, PCR_BUS_CLOCK_UPDATE, 1); + + // TODO: Investigate why 192 MHz instead of 160 MHz + // Also regarding 240 MHz, there might be some HW bug with switching to it, check ESP-IDF. + s_cpu_freq = 192 * MHZ; + esp_rom_set_cpu_ticks_per_us(s_cpu_freq / MHZ); +} + +uint32_t stub_target_get_cpu_freq(void) +{ + if (s_cpu_freq == 0) { + return esp_rom_get_cpu_freq(); + } + return s_cpu_freq; +} diff --git a/src/target/esp32c6/CMakeLists.txt b/src/target/esp32c6/CMakeLists.txt index 353fb79..56f7a76 100644 --- a/src/target/esp32c6/CMakeLists.txt +++ b/src/target/esp32c6/CMakeLists.txt @@ -1,6 +1,7 @@ set(srcs src/uart.c src/usb_serial_jtag.c + src/clock.c ) add_library(${ESP_TARGET_LIB} STATIC ${srcs}) diff --git a/src/target/esp32c6/include/soc/pcr_reg.h b/src/target/esp32c6/include/soc/pcr_reg.h new file mode 100644 index 0000000..df43e14 --- /dev/null +++ b/src/target/esp32c6/include/soc/pcr_reg.h @@ -0,0 +1,2066 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 OR MIT + */ +#pragma once + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** PCR_UART0_CONF_REG register + * UART0 configuration register + */ +#define PCR_UART0_CONF_REG (DR_REG_PCR_BASE + 0x0) +/** PCR_UART0_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable uart0 apb clock + */ +#define PCR_UART0_CLK_EN (BIT(0)) +#define PCR_UART0_CLK_EN_M (PCR_UART0_CLK_EN_V << PCR_UART0_CLK_EN_S) +#define PCR_UART0_CLK_EN_V 0x00000001U +#define PCR_UART0_CLK_EN_S 0 +/** PCR_UART0_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset uart0 module + */ +#define PCR_UART0_RST_EN (BIT(1)) +#define PCR_UART0_RST_EN_M (PCR_UART0_RST_EN_V << PCR_UART0_RST_EN_S) +#define PCR_UART0_RST_EN_V 0x00000001U +#define PCR_UART0_RST_EN_S 1 + +/** PCR_UART0_SCLK_CONF_REG register + * UART0_SCLK configuration register + */ +#define PCR_UART0_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x4) +/** PCR_UART0_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the uart0 function clock. + */ +#define PCR_UART0_SCLK_DIV_A 0x0000003FU +#define PCR_UART0_SCLK_DIV_A_M (PCR_UART0_SCLK_DIV_A_V << PCR_UART0_SCLK_DIV_A_S) +#define PCR_UART0_SCLK_DIV_A_V 0x0000003FU +#define PCR_UART0_SCLK_DIV_A_S 0 +/** PCR_UART0_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the uart0 function clock. + */ +#define PCR_UART0_SCLK_DIV_B 0x0000003FU +#define PCR_UART0_SCLK_DIV_B_M (PCR_UART0_SCLK_DIV_B_V << PCR_UART0_SCLK_DIV_B_S) +#define PCR_UART0_SCLK_DIV_B_V 0x0000003FU +#define PCR_UART0_SCLK_DIV_B_S 6 +/** PCR_UART0_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the uart0 function clock. + */ +#define PCR_UART0_SCLK_DIV_NUM 0x000000FFU +#define PCR_UART0_SCLK_DIV_NUM_M (PCR_UART0_SCLK_DIV_NUM_V << PCR_UART0_SCLK_DIV_NUM_S) +#define PCR_UART0_SCLK_DIV_NUM_V 0x000000FFU +#define PCR_UART0_SCLK_DIV_NUM_S 12 +/** PCR_UART0_SCLK_SEL : R/W; bitpos: [21:20]; default: 3; + * set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: + * FOSC, 3(default): XTAL. + */ +#define PCR_UART0_SCLK_SEL 0x00000003U +#define PCR_UART0_SCLK_SEL_M (PCR_UART0_SCLK_SEL_V << PCR_UART0_SCLK_SEL_S) +#define PCR_UART0_SCLK_SEL_V 0x00000003U +#define PCR_UART0_SCLK_SEL_S 20 +/** PCR_UART0_SCLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable uart0 function clock + */ +#define PCR_UART0_SCLK_EN (BIT(22)) +#define PCR_UART0_SCLK_EN_M (PCR_UART0_SCLK_EN_V << PCR_UART0_SCLK_EN_S) +#define PCR_UART0_SCLK_EN_V 0x00000001U +#define PCR_UART0_SCLK_EN_S 22 + +/** PCR_UART0_PD_CTRL_REG register + * UART0 power control register + */ +#define PCR_UART0_PD_CTRL_REG (DR_REG_PCR_BASE + 0x8) +/** PCR_UART0_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1; + * Set this bit to force power down UART0 memory. + */ +#define PCR_UART0_MEM_FORCE_PU (BIT(1)) +#define PCR_UART0_MEM_FORCE_PU_M (PCR_UART0_MEM_FORCE_PU_V << PCR_UART0_MEM_FORCE_PU_S) +#define PCR_UART0_MEM_FORCE_PU_V 0x00000001U +#define PCR_UART0_MEM_FORCE_PU_S 1 +/** PCR_UART0_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; + * Set this bit to force power up UART0 memory. + */ +#define PCR_UART0_MEM_FORCE_PD (BIT(2)) +#define PCR_UART0_MEM_FORCE_PD_M (PCR_UART0_MEM_FORCE_PD_V << PCR_UART0_MEM_FORCE_PD_S) +#define PCR_UART0_MEM_FORCE_PD_V 0x00000001U +#define PCR_UART0_MEM_FORCE_PD_S 2 + +/** PCR_UART1_CONF_REG register + * UART1 configuration register + */ +#define PCR_UART1_CONF_REG (DR_REG_PCR_BASE + 0xc) +/** PCR_UART1_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable uart1 apb clock + */ +#define PCR_UART1_CLK_EN (BIT(0)) +#define PCR_UART1_CLK_EN_M (PCR_UART1_CLK_EN_V << PCR_UART1_CLK_EN_S) +#define PCR_UART1_CLK_EN_V 0x00000001U +#define PCR_UART1_CLK_EN_S 0 +/** PCR_UART1_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset uart1 module + */ +#define PCR_UART1_RST_EN (BIT(1)) +#define PCR_UART1_RST_EN_M (PCR_UART1_RST_EN_V << PCR_UART1_RST_EN_S) +#define PCR_UART1_RST_EN_V 0x00000001U +#define PCR_UART1_RST_EN_S 1 + +/** PCR_UART1_SCLK_CONF_REG register + * UART1_SCLK configuration register + */ +#define PCR_UART1_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x10) +/** PCR_UART1_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the uart1 function clock. + */ +#define PCR_UART1_SCLK_DIV_A 0x0000003FU +#define PCR_UART1_SCLK_DIV_A_M (PCR_UART1_SCLK_DIV_A_V << PCR_UART1_SCLK_DIV_A_S) +#define PCR_UART1_SCLK_DIV_A_V 0x0000003FU +#define PCR_UART1_SCLK_DIV_A_S 0 +/** PCR_UART1_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the uart1 function clock. + */ +#define PCR_UART1_SCLK_DIV_B 0x0000003FU +#define PCR_UART1_SCLK_DIV_B_M (PCR_UART1_SCLK_DIV_B_V << PCR_UART1_SCLK_DIV_B_S) +#define PCR_UART1_SCLK_DIV_B_V 0x0000003FU +#define PCR_UART1_SCLK_DIV_B_S 6 +/** PCR_UART1_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the uart1 function clock. + */ +#define PCR_UART1_SCLK_DIV_NUM 0x000000FFU +#define PCR_UART1_SCLK_DIV_NUM_M (PCR_UART1_SCLK_DIV_NUM_V << PCR_UART1_SCLK_DIV_NUM_S) +#define PCR_UART1_SCLK_DIV_NUM_V 0x000000FFU +#define PCR_UART1_SCLK_DIV_NUM_S 12 +/** PCR_UART1_SCLK_SEL : R/W; bitpos: [21:20]; default: 3; + * set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: + * FOSC, 3(default): XTAL. + */ +#define PCR_UART1_SCLK_SEL 0x00000003U +#define PCR_UART1_SCLK_SEL_M (PCR_UART1_SCLK_SEL_V << PCR_UART1_SCLK_SEL_S) +#define PCR_UART1_SCLK_SEL_V 0x00000003U +#define PCR_UART1_SCLK_SEL_S 20 +/** PCR_UART1_SCLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable uart0 function clock + */ +#define PCR_UART1_SCLK_EN (BIT(22)) +#define PCR_UART1_SCLK_EN_M (PCR_UART1_SCLK_EN_V << PCR_UART1_SCLK_EN_S) +#define PCR_UART1_SCLK_EN_V 0x00000001U +#define PCR_UART1_SCLK_EN_S 22 + +/** PCR_UART1_PD_CTRL_REG register + * UART1 power control register + */ +#define PCR_UART1_PD_CTRL_REG (DR_REG_PCR_BASE + 0x14) +/** PCR_UART1_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1; + * Set this bit to force power down UART1 memory. + */ +#define PCR_UART1_MEM_FORCE_PU (BIT(1)) +#define PCR_UART1_MEM_FORCE_PU_M (PCR_UART1_MEM_FORCE_PU_V << PCR_UART1_MEM_FORCE_PU_S) +#define PCR_UART1_MEM_FORCE_PU_V 0x00000001U +#define PCR_UART1_MEM_FORCE_PU_S 1 +/** PCR_UART1_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; + * Set this bit to force power up UART1 memory. + */ +#define PCR_UART1_MEM_FORCE_PD (BIT(2)) +#define PCR_UART1_MEM_FORCE_PD_M (PCR_UART1_MEM_FORCE_PD_V << PCR_UART1_MEM_FORCE_PD_S) +#define PCR_UART1_MEM_FORCE_PD_V 0x00000001U +#define PCR_UART1_MEM_FORCE_PD_S 2 + +/** PCR_MSPI_CONF_REG register + * MSPI configuration register + */ +#define PCR_MSPI_CONF_REG (DR_REG_PCR_BASE + 0x18) +/** PCR_MSPI_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable mspi clock, include mspi pll clock + */ +#define PCR_MSPI_CLK_EN (BIT(0)) +#define PCR_MSPI_CLK_EN_M (PCR_MSPI_CLK_EN_V << PCR_MSPI_CLK_EN_S) +#define PCR_MSPI_CLK_EN_V 0x00000001U +#define PCR_MSPI_CLK_EN_S 0 +/** PCR_MSPI_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset mspi module + */ +#define PCR_MSPI_RST_EN (BIT(1)) +#define PCR_MSPI_RST_EN_M (PCR_MSPI_RST_EN_V << PCR_MSPI_RST_EN_S) +#define PCR_MSPI_RST_EN_V 0x00000001U +#define PCR_MSPI_RST_EN_S 1 +/** PCR_MSPI_PLL_CLK_EN : R/W; bitpos: [2]; default: 1; + * Set 1 to enable mspi pll clock + */ +#define PCR_MSPI_PLL_CLK_EN (BIT(2)) +#define PCR_MSPI_PLL_CLK_EN_M (PCR_MSPI_PLL_CLK_EN_V << PCR_MSPI_PLL_CLK_EN_S) +#define PCR_MSPI_PLL_CLK_EN_V 0x00000001U +#define PCR_MSPI_PLL_CLK_EN_S 2 + +/** PCR_MSPI_CLK_CONF_REG register + * MSPI_CLK configuration register + */ +#define PCR_MSPI_CLK_CONF_REG (DR_REG_PCR_BASE + 0x1c) +/** PCR_MSPI_FAST_LS_DIV_NUM : R/W; bitpos: [7:0]; default: 0; + * Set as one within (0,1,2) to generate div1(default)/div2/div4 of low-speed + * clock-source to drive clk_mspi_fast. Only available when the clck-source is a + * low-speed clock-source such as XTAL/FOSC. + */ +#define PCR_MSPI_FAST_LS_DIV_NUM 0x000000FFU +#define PCR_MSPI_FAST_LS_DIV_NUM_M (PCR_MSPI_FAST_LS_DIV_NUM_V << PCR_MSPI_FAST_LS_DIV_NUM_S) +#define PCR_MSPI_FAST_LS_DIV_NUM_V 0x000000FFU +#define PCR_MSPI_FAST_LS_DIV_NUM_S 0 +/** PCR_MSPI_FAST_HS_DIV_NUM : R/W; bitpos: [15:8]; default: 3; + * Set as one within (3,4,5) to generate div4(default)/div5/div6 of high-speed + * clock-source to drive clk_mspi_fast. Only available when the clck-source is a + * high-speed clock-source such as SPLL. + */ +#define PCR_MSPI_FAST_HS_DIV_NUM 0x000000FFU +#define PCR_MSPI_FAST_HS_DIV_NUM_M (PCR_MSPI_FAST_HS_DIV_NUM_V << PCR_MSPI_FAST_HS_DIV_NUM_S) +#define PCR_MSPI_FAST_HS_DIV_NUM_V 0x000000FFU +#define PCR_MSPI_FAST_HS_DIV_NUM_S 8 + +/** PCR_I2C_CONF_REG register + * I2C configuration register + */ +#define PCR_I2C_CONF_REG (DR_REG_PCR_BASE + 0x20) +/** PCR_I2C_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable i2c apb clock + */ +#define PCR_I2C_CLK_EN (BIT(0)) +#define PCR_I2C_CLK_EN_M (PCR_I2C_CLK_EN_V << PCR_I2C_CLK_EN_S) +#define PCR_I2C_CLK_EN_V 0x00000001U +#define PCR_I2C_CLK_EN_S 0 +/** PCR_I2C_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset i2c module + */ +#define PCR_I2C_RST_EN (BIT(1)) +#define PCR_I2C_RST_EN_M (PCR_I2C_RST_EN_V << PCR_I2C_RST_EN_S) +#define PCR_I2C_RST_EN_V 0x00000001U +#define PCR_I2C_RST_EN_S 1 + +/** PCR_I2C_SCLK_CONF_REG register + * I2C_SCLK configuration register + */ +#define PCR_I2C_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x24) +/** PCR_I2C_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the i2c function clock. + */ +#define PCR_I2C_SCLK_DIV_A 0x0000003FU +#define PCR_I2C_SCLK_DIV_A_M (PCR_I2C_SCLK_DIV_A_V << PCR_I2C_SCLK_DIV_A_S) +#define PCR_I2C_SCLK_DIV_A_V 0x0000003FU +#define PCR_I2C_SCLK_DIV_A_S 0 +/** PCR_I2C_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the i2c function clock. + */ +#define PCR_I2C_SCLK_DIV_B 0x0000003FU +#define PCR_I2C_SCLK_DIV_B_M (PCR_I2C_SCLK_DIV_B_V << PCR_I2C_SCLK_DIV_B_S) +#define PCR_I2C_SCLK_DIV_B_V 0x0000003FU +#define PCR_I2C_SCLK_DIV_B_S 6 +/** PCR_I2C_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the i2c function clock. + */ +#define PCR_I2C_SCLK_DIV_NUM 0x000000FFU +#define PCR_I2C_SCLK_DIV_NUM_M (PCR_I2C_SCLK_DIV_NUM_V << PCR_I2C_SCLK_DIV_NUM_S) +#define PCR_I2C_SCLK_DIV_NUM_V 0x000000FFU +#define PCR_I2C_SCLK_DIV_NUM_S 12 +/** PCR_I2C_SCLK_SEL : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: FOSC. + */ +#define PCR_I2C_SCLK_SEL (BIT(20)) +#define PCR_I2C_SCLK_SEL_M (PCR_I2C_SCLK_SEL_V << PCR_I2C_SCLK_SEL_S) +#define PCR_I2C_SCLK_SEL_V 0x00000001U +#define PCR_I2C_SCLK_SEL_S 20 +/** PCR_I2C_SCLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable i2c function clock + */ +#define PCR_I2C_SCLK_EN (BIT(22)) +#define PCR_I2C_SCLK_EN_M (PCR_I2C_SCLK_EN_V << PCR_I2C_SCLK_EN_S) +#define PCR_I2C_SCLK_EN_V 0x00000001U +#define PCR_I2C_SCLK_EN_S 22 + +/** PCR_UHCI_CONF_REG register + * UHCI configuration register + */ +#define PCR_UHCI_CONF_REG (DR_REG_PCR_BASE + 0x28) +/** PCR_UHCI_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable uhci clock + */ +#define PCR_UHCI_CLK_EN (BIT(0)) +#define PCR_UHCI_CLK_EN_M (PCR_UHCI_CLK_EN_V << PCR_UHCI_CLK_EN_S) +#define PCR_UHCI_CLK_EN_V 0x00000001U +#define PCR_UHCI_CLK_EN_S 0 +/** PCR_UHCI_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset uhci module + */ +#define PCR_UHCI_RST_EN (BIT(1)) +#define PCR_UHCI_RST_EN_M (PCR_UHCI_RST_EN_V << PCR_UHCI_RST_EN_S) +#define PCR_UHCI_RST_EN_V 0x00000001U +#define PCR_UHCI_RST_EN_S 1 + +/** PCR_RMT_CONF_REG register + * RMT configuration register + */ +#define PCR_RMT_CONF_REG (DR_REG_PCR_BASE + 0x2c) +/** PCR_RMT_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable rmt apb clock + */ +#define PCR_RMT_CLK_EN (BIT(0)) +#define PCR_RMT_CLK_EN_M (PCR_RMT_CLK_EN_V << PCR_RMT_CLK_EN_S) +#define PCR_RMT_CLK_EN_V 0x00000001U +#define PCR_RMT_CLK_EN_S 0 +/** PCR_RMT_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset rmt module + */ +#define PCR_RMT_RST_EN (BIT(1)) +#define PCR_RMT_RST_EN_M (PCR_RMT_RST_EN_V << PCR_RMT_RST_EN_S) +#define PCR_RMT_RST_EN_V 0x00000001U +#define PCR_RMT_RST_EN_S 1 + +/** PCR_RMT_SCLK_CONF_REG register + * RMT_SCLK configuration register + */ +#define PCR_RMT_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x30) +/** PCR_RMT_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the rmt function clock. + */ +#define PCR_RMT_SCLK_DIV_A 0x0000003FU +#define PCR_RMT_SCLK_DIV_A_M (PCR_RMT_SCLK_DIV_A_V << PCR_RMT_SCLK_DIV_A_S) +#define PCR_RMT_SCLK_DIV_A_V 0x0000003FU +#define PCR_RMT_SCLK_DIV_A_S 0 +/** PCR_RMT_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the rmt function clock. + */ +#define PCR_RMT_SCLK_DIV_B 0x0000003FU +#define PCR_RMT_SCLK_DIV_B_M (PCR_RMT_SCLK_DIV_B_V << PCR_RMT_SCLK_DIV_B_S) +#define PCR_RMT_SCLK_DIV_B_V 0x0000003FU +#define PCR_RMT_SCLK_DIV_B_S 6 +/** PCR_RMT_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 1; + * The integral part of the frequency divider factor of the rmt function clock. + */ +#define PCR_RMT_SCLK_DIV_NUM 0x000000FFU +#define PCR_RMT_SCLK_DIV_NUM_M (PCR_RMT_SCLK_DIV_NUM_V << PCR_RMT_SCLK_DIV_NUM_S) +#define PCR_RMT_SCLK_DIV_NUM_V 0x000000FFU +#define PCR_RMT_SCLK_DIV_NUM_S 12 +/** PCR_RMT_SCLK_SEL : R/W; bitpos: [21:20]; default: 1; + * set this field to select clock-source. 0: do not select anyone clock, 1(default): + * 80MHz, 2: FOSC, 3: XTAL. + */ +#define PCR_RMT_SCLK_SEL 0x00000003U +#define PCR_RMT_SCLK_SEL_M (PCR_RMT_SCLK_SEL_V << PCR_RMT_SCLK_SEL_S) +#define PCR_RMT_SCLK_SEL_V 0x00000003U +#define PCR_RMT_SCLK_SEL_S 20 +/** PCR_RMT_SCLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable rmt function clock + */ +#define PCR_RMT_SCLK_EN (BIT(22)) +#define PCR_RMT_SCLK_EN_M (PCR_RMT_SCLK_EN_V << PCR_RMT_SCLK_EN_S) +#define PCR_RMT_SCLK_EN_V 0x00000001U +#define PCR_RMT_SCLK_EN_S 22 + +/** PCR_LEDC_CONF_REG register + * LEDC configuration register + */ +#define PCR_LEDC_CONF_REG (DR_REG_PCR_BASE + 0x34) +/** PCR_LEDC_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable ledc apb clock + */ +#define PCR_LEDC_CLK_EN (BIT(0)) +#define PCR_LEDC_CLK_EN_M (PCR_LEDC_CLK_EN_V << PCR_LEDC_CLK_EN_S) +#define PCR_LEDC_CLK_EN_V 0x00000001U +#define PCR_LEDC_CLK_EN_S 0 +/** PCR_LEDC_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset ledc module + */ +#define PCR_LEDC_RST_EN (BIT(1)) +#define PCR_LEDC_RST_EN_M (PCR_LEDC_RST_EN_V << PCR_LEDC_RST_EN_S) +#define PCR_LEDC_RST_EN_V 0x00000001U +#define PCR_LEDC_RST_EN_S 1 + +/** PCR_LEDC_SCLK_CONF_REG register + * LEDC_SCLK configuration register + */ +#define PCR_LEDC_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x38) +/** PCR_LEDC_SCLK_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): do not select anyone clock, 1: + * 80MHz, 2: FOSC, 3: XTAL. + */ +#define PCR_LEDC_SCLK_SEL 0x00000003U +#define PCR_LEDC_SCLK_SEL_M (PCR_LEDC_SCLK_SEL_V << PCR_LEDC_SCLK_SEL_S) +#define PCR_LEDC_SCLK_SEL_V 0x00000003U +#define PCR_LEDC_SCLK_SEL_S 20 +/** PCR_LEDC_SCLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable ledc function clock + */ +#define PCR_LEDC_SCLK_EN (BIT(22)) +#define PCR_LEDC_SCLK_EN_M (PCR_LEDC_SCLK_EN_V << PCR_LEDC_SCLK_EN_S) +#define PCR_LEDC_SCLK_EN_V 0x00000001U +#define PCR_LEDC_SCLK_EN_S 22 + +/** PCR_TIMERGROUP0_CONF_REG register + * TIMERGROUP0 configuration register + */ +#define PCR_TIMERGROUP0_CONF_REG (DR_REG_PCR_BASE + 0x3c) +/** PCR_TG0_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable timer_group0 apb clock + */ +#define PCR_TG0_CLK_EN (BIT(0)) +#define PCR_TG0_CLK_EN_M (PCR_TG0_CLK_EN_V << PCR_TG0_CLK_EN_S) +#define PCR_TG0_CLK_EN_V 0x00000001U +#define PCR_TG0_CLK_EN_S 0 +/** PCR_TG0_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset timer_group0 module + */ +#define PCR_TG0_RST_EN (BIT(1)) +#define PCR_TG0_RST_EN_M (PCR_TG0_RST_EN_V << PCR_TG0_RST_EN_S) +#define PCR_TG0_RST_EN_V 0x00000001U +#define PCR_TG0_RST_EN_S 1 + +/** PCR_TIMERGROUP0_TIMER_CLK_CONF_REG register + * TIMERGROUP0_TIMER_CLK configuration register + */ +#define PCR_TIMERGROUP0_TIMER_CLK_CONF_REG (DR_REG_PCR_BASE + 0x40) +/** PCR_TG0_TIMER_CLK_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: + * reserved. + */ +#define PCR_TG0_TIMER_CLK_SEL 0x00000003U +#define PCR_TG0_TIMER_CLK_SEL_M (PCR_TG0_TIMER_CLK_SEL_V << PCR_TG0_TIMER_CLK_SEL_S) +#define PCR_TG0_TIMER_CLK_SEL_V 0x00000003U +#define PCR_TG0_TIMER_CLK_SEL_S 20 +/** PCR_TG0_TIMER_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group0 timer clock + */ +#define PCR_TG0_TIMER_CLK_EN (BIT(22)) +#define PCR_TG0_TIMER_CLK_EN_M (PCR_TG0_TIMER_CLK_EN_V << PCR_TG0_TIMER_CLK_EN_S) +#define PCR_TG0_TIMER_CLK_EN_V 0x00000001U +#define PCR_TG0_TIMER_CLK_EN_S 22 + +/** PCR_TIMERGROUP0_WDT_CLK_CONF_REG register + * TIMERGROUP0_WDT_CLK configuration register + */ +#define PCR_TIMERGROUP0_WDT_CLK_CONF_REG (DR_REG_PCR_BASE + 0x44) +/** PCR_TG0_WDT_CLK_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: + * reserved. + */ +#define PCR_TG0_WDT_CLK_SEL 0x00000003U +#define PCR_TG0_WDT_CLK_SEL_M (PCR_TG0_WDT_CLK_SEL_V << PCR_TG0_WDT_CLK_SEL_S) +#define PCR_TG0_WDT_CLK_SEL_V 0x00000003U +#define PCR_TG0_WDT_CLK_SEL_S 20 +/** PCR_TG0_WDT_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group0 wdt clock + */ +#define PCR_TG0_WDT_CLK_EN (BIT(22)) +#define PCR_TG0_WDT_CLK_EN_M (PCR_TG0_WDT_CLK_EN_V << PCR_TG0_WDT_CLK_EN_S) +#define PCR_TG0_WDT_CLK_EN_V 0x00000001U +#define PCR_TG0_WDT_CLK_EN_S 22 + +/** PCR_TIMERGROUP1_CONF_REG register + * TIMERGROUP1 configuration register + */ +#define PCR_TIMERGROUP1_CONF_REG (DR_REG_PCR_BASE + 0x48) +/** PCR_TG1_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable timer_group1 apb clock + */ +#define PCR_TG1_CLK_EN (BIT(0)) +#define PCR_TG1_CLK_EN_M (PCR_TG1_CLK_EN_V << PCR_TG1_CLK_EN_S) +#define PCR_TG1_CLK_EN_V 0x00000001U +#define PCR_TG1_CLK_EN_S 0 +/** PCR_TG1_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset timer_group1 module + */ +#define PCR_TG1_RST_EN (BIT(1)) +#define PCR_TG1_RST_EN_M (PCR_TG1_RST_EN_V << PCR_TG1_RST_EN_S) +#define PCR_TG1_RST_EN_V 0x00000001U +#define PCR_TG1_RST_EN_S 1 + +/** PCR_TIMERGROUP1_TIMER_CLK_CONF_REG register + * TIMERGROUP1_TIMER_CLK configuration register + */ +#define PCR_TIMERGROUP1_TIMER_CLK_CONF_REG (DR_REG_PCR_BASE + 0x4c) +/** PCR_TG1_TIMER_CLK_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: + * reserved. + */ +#define PCR_TG1_TIMER_CLK_SEL 0x00000003U +#define PCR_TG1_TIMER_CLK_SEL_M (PCR_TG1_TIMER_CLK_SEL_V << PCR_TG1_TIMER_CLK_SEL_S) +#define PCR_TG1_TIMER_CLK_SEL_V 0x00000003U +#define PCR_TG1_TIMER_CLK_SEL_S 20 +/** PCR_TG1_TIMER_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group1 timer clock + */ +#define PCR_TG1_TIMER_CLK_EN (BIT(22)) +#define PCR_TG1_TIMER_CLK_EN_M (PCR_TG1_TIMER_CLK_EN_V << PCR_TG1_TIMER_CLK_EN_S) +#define PCR_TG1_TIMER_CLK_EN_V 0x00000001U +#define PCR_TG1_TIMER_CLK_EN_S 22 + +/** PCR_TIMERGROUP1_WDT_CLK_CONF_REG register + * TIMERGROUP1_WDT_CLK configuration register + */ +#define PCR_TIMERGROUP1_WDT_CLK_CONF_REG (DR_REG_PCR_BASE + 0x50) +/** PCR_TG1_WDT_CLK_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: + * reserved. + */ +#define PCR_TG1_WDT_CLK_SEL 0x00000003U +#define PCR_TG1_WDT_CLK_SEL_M (PCR_TG1_WDT_CLK_SEL_V << PCR_TG1_WDT_CLK_SEL_S) +#define PCR_TG1_WDT_CLK_SEL_V 0x00000003U +#define PCR_TG1_WDT_CLK_SEL_S 20 +/** PCR_TG1_WDT_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group0 wdt clock + */ +#define PCR_TG1_WDT_CLK_EN (BIT(22)) +#define PCR_TG1_WDT_CLK_EN_M (PCR_TG1_WDT_CLK_EN_V << PCR_TG1_WDT_CLK_EN_S) +#define PCR_TG1_WDT_CLK_EN_V 0x00000001U +#define PCR_TG1_WDT_CLK_EN_S 22 + +/** PCR_SYSTIMER_CONF_REG register + * SYSTIMER configuration register + */ +#define PCR_SYSTIMER_CONF_REG (DR_REG_PCR_BASE + 0x54) +/** PCR_SYSTIMER_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable systimer apb clock + */ +#define PCR_SYSTIMER_CLK_EN (BIT(0)) +#define PCR_SYSTIMER_CLK_EN_M (PCR_SYSTIMER_CLK_EN_V << PCR_SYSTIMER_CLK_EN_S) +#define PCR_SYSTIMER_CLK_EN_V 0x00000001U +#define PCR_SYSTIMER_CLK_EN_S 0 +/** PCR_SYSTIMER_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset systimer module + */ +#define PCR_SYSTIMER_RST_EN (BIT(1)) +#define PCR_SYSTIMER_RST_EN_M (PCR_SYSTIMER_RST_EN_V << PCR_SYSTIMER_RST_EN_S) +#define PCR_SYSTIMER_RST_EN_V 0x00000001U +#define PCR_SYSTIMER_RST_EN_S 1 + +/** PCR_SYSTIMER_FUNC_CLK_CONF_REG register + * SYSTIMER_FUNC_CLK configuration register + */ +#define PCR_SYSTIMER_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x58) +/** PCR_SYSTIMER_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: FOSC. + */ +#define PCR_SYSTIMER_FUNC_CLK_SEL (BIT(20)) +#define PCR_SYSTIMER_FUNC_CLK_SEL_M (PCR_SYSTIMER_FUNC_CLK_SEL_V << PCR_SYSTIMER_FUNC_CLK_SEL_S) +#define PCR_SYSTIMER_FUNC_CLK_SEL_V 0x00000001U +#define PCR_SYSTIMER_FUNC_CLK_SEL_S 20 +/** PCR_SYSTIMER_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable systimer function clock + */ +#define PCR_SYSTIMER_FUNC_CLK_EN (BIT(22)) +#define PCR_SYSTIMER_FUNC_CLK_EN_M (PCR_SYSTIMER_FUNC_CLK_EN_V << PCR_SYSTIMER_FUNC_CLK_EN_S) +#define PCR_SYSTIMER_FUNC_CLK_EN_V 0x00000001U +#define PCR_SYSTIMER_FUNC_CLK_EN_S 22 + +/** PCR_TWAI0_CONF_REG register + * TWAI0 configuration register + */ +#define PCR_TWAI0_CONF_REG (DR_REG_PCR_BASE + 0x5c) +/** PCR_TWAI0_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable twai0 apb clock + */ +#define PCR_TWAI0_CLK_EN (BIT(0)) +#define PCR_TWAI0_CLK_EN_M (PCR_TWAI0_CLK_EN_V << PCR_TWAI0_CLK_EN_S) +#define PCR_TWAI0_CLK_EN_V 0x00000001U +#define PCR_TWAI0_CLK_EN_S 0 +/** PCR_TWAI0_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset twai0 module + */ +#define PCR_TWAI0_RST_EN (BIT(1)) +#define PCR_TWAI0_RST_EN_M (PCR_TWAI0_RST_EN_V << PCR_TWAI0_RST_EN_S) +#define PCR_TWAI0_RST_EN_V 0x00000001U +#define PCR_TWAI0_RST_EN_S 1 + +/** PCR_TWAI0_FUNC_CLK_CONF_REG register + * TWAI0_FUNC_CLK configuration register + */ +#define PCR_TWAI0_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x60) +/** PCR_TWAI0_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: FOSC. + */ +#define PCR_TWAI0_FUNC_CLK_SEL (BIT(20)) +#define PCR_TWAI0_FUNC_CLK_SEL_M (PCR_TWAI0_FUNC_CLK_SEL_V << PCR_TWAI0_FUNC_CLK_SEL_S) +#define PCR_TWAI0_FUNC_CLK_SEL_V 0x00000001U +#define PCR_TWAI0_FUNC_CLK_SEL_S 20 +/** PCR_TWAI0_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable twai0 function clock + */ +#define PCR_TWAI0_FUNC_CLK_EN (BIT(22)) +#define PCR_TWAI0_FUNC_CLK_EN_M (PCR_TWAI0_FUNC_CLK_EN_V << PCR_TWAI0_FUNC_CLK_EN_S) +#define PCR_TWAI0_FUNC_CLK_EN_V 0x00000001U +#define PCR_TWAI0_FUNC_CLK_EN_S 22 + +/** PCR_TWAI1_CONF_REG register + * TWAI1 configuration register + */ +#define PCR_TWAI1_CONF_REG (DR_REG_PCR_BASE + 0x64) +/** PCR_TWAI1_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable twai1 apb clock + */ +#define PCR_TWAI1_CLK_EN (BIT(0)) +#define PCR_TWAI1_CLK_EN_M (PCR_TWAI1_CLK_EN_V << PCR_TWAI1_CLK_EN_S) +#define PCR_TWAI1_CLK_EN_V 0x00000001U +#define PCR_TWAI1_CLK_EN_S 0 +/** PCR_TWAI1_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset twai1 module + */ +#define PCR_TWAI1_RST_EN (BIT(1)) +#define PCR_TWAI1_RST_EN_M (PCR_TWAI1_RST_EN_V << PCR_TWAI1_RST_EN_S) +#define PCR_TWAI1_RST_EN_V 0x00000001U +#define PCR_TWAI1_RST_EN_S 1 + +/** PCR_TWAI1_FUNC_CLK_CONF_REG register + * TWAI1_FUNC_CLK configuration register + */ +#define PCR_TWAI1_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x68) +/** PCR_TWAI1_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: FOSC. + */ +#define PCR_TWAI1_FUNC_CLK_SEL (BIT(20)) +#define PCR_TWAI1_FUNC_CLK_SEL_M (PCR_TWAI1_FUNC_CLK_SEL_V << PCR_TWAI1_FUNC_CLK_SEL_S) +#define PCR_TWAI1_FUNC_CLK_SEL_V 0x00000001U +#define PCR_TWAI1_FUNC_CLK_SEL_S 20 +/** PCR_TWAI1_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable twai1 function clock + */ +#define PCR_TWAI1_FUNC_CLK_EN (BIT(22)) +#define PCR_TWAI1_FUNC_CLK_EN_M (PCR_TWAI1_FUNC_CLK_EN_V << PCR_TWAI1_FUNC_CLK_EN_S) +#define PCR_TWAI1_FUNC_CLK_EN_V 0x00000001U +#define PCR_TWAI1_FUNC_CLK_EN_S 22 + +/** PCR_I2S_CONF_REG register + * I2S configuration register + */ +#define PCR_I2S_CONF_REG (DR_REG_PCR_BASE + 0x6c) +/** PCR_I2S_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable i2s apb clock + */ +#define PCR_I2S_CLK_EN (BIT(0)) +#define PCR_I2S_CLK_EN_M (PCR_I2S_CLK_EN_V << PCR_I2S_CLK_EN_S) +#define PCR_I2S_CLK_EN_V 0x00000001U +#define PCR_I2S_CLK_EN_S 0 +/** PCR_I2S_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset i2s module + */ +#define PCR_I2S_RST_EN (BIT(1)) +#define PCR_I2S_RST_EN_M (PCR_I2S_RST_EN_V << PCR_I2S_RST_EN_S) +#define PCR_I2S_RST_EN_V 0x00000001U +#define PCR_I2S_RST_EN_S 1 + +/** PCR_I2S_TX_CLKM_CONF_REG register + * I2S_TX_CLKM configuration register + */ +#define PCR_I2S_TX_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x70) +/** PCR_I2S_TX_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 2; + * Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be + * (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= + * a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * + * (n+1)-div] + y * (n+1)-div. + */ +#define PCR_I2S_TX_CLKM_DIV_NUM 0x000000FFU +#define PCR_I2S_TX_CLKM_DIV_NUM_M (PCR_I2S_TX_CLKM_DIV_NUM_V << PCR_I2S_TX_CLKM_DIV_NUM_S) +#define PCR_I2S_TX_CLKM_DIV_NUM_V 0x000000FFU +#define PCR_I2S_TX_CLKM_DIV_NUM_S 12 +/** PCR_I2S_TX_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; + * Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: + * I2S_MCLK_in. + */ +#define PCR_I2S_TX_CLKM_SEL 0x00000003U +#define PCR_I2S_TX_CLKM_SEL_M (PCR_I2S_TX_CLKM_SEL_V << PCR_I2S_TX_CLKM_SEL_S) +#define PCR_I2S_TX_CLKM_SEL_V 0x00000003U +#define PCR_I2S_TX_CLKM_SEL_S 20 +/** PCR_I2S_TX_CLKM_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable i2s_tx function clock + */ +#define PCR_I2S_TX_CLKM_EN (BIT(22)) +#define PCR_I2S_TX_CLKM_EN_M (PCR_I2S_TX_CLKM_EN_V << PCR_I2S_TX_CLKM_EN_S) +#define PCR_I2S_TX_CLKM_EN_V 0x00000001U +#define PCR_I2S_TX_CLKM_EN_S 22 + +/** PCR_I2S_TX_CLKM_DIV_CONF_REG register + * I2S_TX_CLKM_DIV configuration register + */ +#define PCR_I2S_TX_CLKM_DIV_CONF_REG (DR_REG_PCR_BASE + 0x74) +/** PCR_I2S_TX_CLKM_DIV_Z : R/W; bitpos: [8:0]; default: 0; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of + * I2S_TX_CLKM_DIV_Z is (a-b). + */ +#define PCR_I2S_TX_CLKM_DIV_Z 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_Z_M (PCR_I2S_TX_CLKM_DIV_Z_V << PCR_I2S_TX_CLKM_DIV_Z_S) +#define PCR_I2S_TX_CLKM_DIV_Z_V 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_Z_S 0 +/** PCR_I2S_TX_CLKM_DIV_Y : R/W; bitpos: [17:9]; default: 1; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of + * I2S_TX_CLKM_DIV_Y is (a%(a-b)). + */ +#define PCR_I2S_TX_CLKM_DIV_Y 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_Y_M (PCR_I2S_TX_CLKM_DIV_Y_V << PCR_I2S_TX_CLKM_DIV_Y_S) +#define PCR_I2S_TX_CLKM_DIV_Y_V 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_Y_S 9 +/** PCR_I2S_TX_CLKM_DIV_X : R/W; bitpos: [26:18]; default: 0; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value + * of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1. + */ +#define PCR_I2S_TX_CLKM_DIV_X 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_X_M (PCR_I2S_TX_CLKM_DIV_X_V << PCR_I2S_TX_CLKM_DIV_X_S) +#define PCR_I2S_TX_CLKM_DIV_X_V 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_X_S 18 +/** PCR_I2S_TX_CLKM_DIV_YN1 : R/W; bitpos: [27]; default: 0; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of + * I2S_TX_CLKM_DIV_YN1 is 1. + */ +#define PCR_I2S_TX_CLKM_DIV_YN1 (BIT(27)) +#define PCR_I2S_TX_CLKM_DIV_YN1_M (PCR_I2S_TX_CLKM_DIV_YN1_V << PCR_I2S_TX_CLKM_DIV_YN1_S) +#define PCR_I2S_TX_CLKM_DIV_YN1_V 0x00000001U +#define PCR_I2S_TX_CLKM_DIV_YN1_S 27 + +/** PCR_I2S_RX_CLKM_CONF_REG register + * I2S_RX_CLKM configuration register + */ +#define PCR_I2S_RX_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x78) +/** PCR_I2S_RX_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 2; + * Integral I2S clock divider value + */ +#define PCR_I2S_RX_CLKM_DIV_NUM 0x000000FFU +#define PCR_I2S_RX_CLKM_DIV_NUM_M (PCR_I2S_RX_CLKM_DIV_NUM_V << PCR_I2S_RX_CLKM_DIV_NUM_S) +#define PCR_I2S_RX_CLKM_DIV_NUM_V 0x000000FFU +#define PCR_I2S_RX_CLKM_DIV_NUM_S 12 +/** PCR_I2S_RX_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; + * Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in. + */ +#define PCR_I2S_RX_CLKM_SEL 0x00000003U +#define PCR_I2S_RX_CLKM_SEL_M (PCR_I2S_RX_CLKM_SEL_V << PCR_I2S_RX_CLKM_SEL_S) +#define PCR_I2S_RX_CLKM_SEL_V 0x00000003U +#define PCR_I2S_RX_CLKM_SEL_S 20 +/** PCR_I2S_RX_CLKM_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable i2s_rx function clock + */ +#define PCR_I2S_RX_CLKM_EN (BIT(22)) +#define PCR_I2S_RX_CLKM_EN_M (PCR_I2S_RX_CLKM_EN_V << PCR_I2S_RX_CLKM_EN_S) +#define PCR_I2S_RX_CLKM_EN_V 0x00000001U +#define PCR_I2S_RX_CLKM_EN_S 22 +/** PCR_I2S_MCLK_SEL : R/W; bitpos: [23]; default: 0; + * This field is used to select master-clock. 0(default): clk_i2s_rx, 1: clk_i2s_tx + */ +#define PCR_I2S_MCLK_SEL (BIT(23)) +#define PCR_I2S_MCLK_SEL_M (PCR_I2S_MCLK_SEL_V << PCR_I2S_MCLK_SEL_S) +#define PCR_I2S_MCLK_SEL_V 0x00000001U +#define PCR_I2S_MCLK_SEL_S 23 + +/** PCR_I2S_RX_CLKM_DIV_CONF_REG register + * I2S_RX_CLKM_DIV configuration register + */ +#define PCR_I2S_RX_CLKM_DIV_CONF_REG (DR_REG_PCR_BASE + 0x7c) +/** PCR_I2S_RX_CLKM_DIV_Z : R/W; bitpos: [8:0]; default: 0; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of + * I2S_RX_CLKM_DIV_Z is (a-b). + */ +#define PCR_I2S_RX_CLKM_DIV_Z 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_Z_M (PCR_I2S_RX_CLKM_DIV_Z_V << PCR_I2S_RX_CLKM_DIV_Z_S) +#define PCR_I2S_RX_CLKM_DIV_Z_V 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_Z_S 0 +/** PCR_I2S_RX_CLKM_DIV_Y : R/W; bitpos: [17:9]; default: 1; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of + * I2S_RX_CLKM_DIV_Y is (a%(a-b)). + */ +#define PCR_I2S_RX_CLKM_DIV_Y 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_Y_M (PCR_I2S_RX_CLKM_DIV_Y_V << PCR_I2S_RX_CLKM_DIV_Y_S) +#define PCR_I2S_RX_CLKM_DIV_Y_V 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_Y_S 9 +/** PCR_I2S_RX_CLKM_DIV_X : R/W; bitpos: [26:18]; default: 0; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value + * of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1. + */ +#define PCR_I2S_RX_CLKM_DIV_X 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_X_M (PCR_I2S_RX_CLKM_DIV_X_V << PCR_I2S_RX_CLKM_DIV_X_S) +#define PCR_I2S_RX_CLKM_DIV_X_V 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_X_S 18 +/** PCR_I2S_RX_CLKM_DIV_YN1 : R/W; bitpos: [27]; default: 0; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of + * I2S_RX_CLKM_DIV_YN1 is 1. + */ +#define PCR_I2S_RX_CLKM_DIV_YN1 (BIT(27)) +#define PCR_I2S_RX_CLKM_DIV_YN1_M (PCR_I2S_RX_CLKM_DIV_YN1_V << PCR_I2S_RX_CLKM_DIV_YN1_S) +#define PCR_I2S_RX_CLKM_DIV_YN1_V 0x00000001U +#define PCR_I2S_RX_CLKM_DIV_YN1_S 27 + +/** PCR_SARADC_CONF_REG register + * SARADC configuration register + */ +#define PCR_SARADC_CONF_REG (DR_REG_PCR_BASE + 0x80) +/** PCR_SARADC_CLK_EN : R/W; bitpos: [0]; default: 1; + * no use + */ +#define PCR_SARADC_CLK_EN (BIT(0)) +#define PCR_SARADC_CLK_EN_M (PCR_SARADC_CLK_EN_V << PCR_SARADC_CLK_EN_S) +#define PCR_SARADC_CLK_EN_V 0x00000001U +#define PCR_SARADC_CLK_EN_S 0 +/** PCR_SARADC_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset function_register of saradc module + */ +#define PCR_SARADC_RST_EN (BIT(1)) +#define PCR_SARADC_RST_EN_M (PCR_SARADC_RST_EN_V << PCR_SARADC_RST_EN_S) +#define PCR_SARADC_RST_EN_V 0x00000001U +#define PCR_SARADC_RST_EN_S 1 +/** PCR_SARADC_REG_CLK_EN : R/W; bitpos: [2]; default: 1; + * Set 1 to enable saradc apb clock + */ +#define PCR_SARADC_REG_CLK_EN (BIT(2)) +#define PCR_SARADC_REG_CLK_EN_M (PCR_SARADC_REG_CLK_EN_V << PCR_SARADC_REG_CLK_EN_S) +#define PCR_SARADC_REG_CLK_EN_V 0x00000001U +#define PCR_SARADC_REG_CLK_EN_S 2 +/** PCR_SARADC_REG_RST_EN : R/W; bitpos: [3]; default: 0; + * Set 0 to reset apb_register of saradc module + */ +#define PCR_SARADC_REG_RST_EN (BIT(3)) +#define PCR_SARADC_REG_RST_EN_M (PCR_SARADC_REG_RST_EN_V << PCR_SARADC_REG_RST_EN_S) +#define PCR_SARADC_REG_RST_EN_V 0x00000001U +#define PCR_SARADC_REG_RST_EN_S 3 + +/** PCR_SARADC_CLKM_CONF_REG register + * SARADC_CLKM configuration register + */ +#define PCR_SARADC_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x84) +/** PCR_SARADC_CLKM_DIV_A : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the saradc function clock. + */ +#define PCR_SARADC_CLKM_DIV_A 0x0000003FU +#define PCR_SARADC_CLKM_DIV_A_M (PCR_SARADC_CLKM_DIV_A_V << PCR_SARADC_CLKM_DIV_A_S) +#define PCR_SARADC_CLKM_DIV_A_V 0x0000003FU +#define PCR_SARADC_CLKM_DIV_A_S 0 +/** PCR_SARADC_CLKM_DIV_B : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the saradc function clock. + */ +#define PCR_SARADC_CLKM_DIV_B 0x0000003FU +#define PCR_SARADC_CLKM_DIV_B_M (PCR_SARADC_CLKM_DIV_B_V << PCR_SARADC_CLKM_DIV_B_S) +#define PCR_SARADC_CLKM_DIV_B_V 0x0000003FU +#define PCR_SARADC_CLKM_DIV_B_S 6 +/** PCR_SARADC_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 4; + * The integral part of the frequency divider factor of the saradc function clock. + */ +#define PCR_SARADC_CLKM_DIV_NUM 0x000000FFU +#define PCR_SARADC_CLKM_DIV_NUM_M (PCR_SARADC_CLKM_DIV_NUM_V << PCR_SARADC_CLKM_DIV_NUM_S) +#define PCR_SARADC_CLKM_DIV_NUM_V 0x000000FFU +#define PCR_SARADC_CLKM_DIV_NUM_S 12 +/** PCR_SARADC_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3: + * reserved. + */ +#define PCR_SARADC_CLKM_SEL 0x00000003U +#define PCR_SARADC_CLKM_SEL_M (PCR_SARADC_CLKM_SEL_V << PCR_SARADC_CLKM_SEL_S) +#define PCR_SARADC_CLKM_SEL_V 0x00000003U +#define PCR_SARADC_CLKM_SEL_S 20 +/** PCR_SARADC_CLKM_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable saradc function clock + */ +#define PCR_SARADC_CLKM_EN (BIT(22)) +#define PCR_SARADC_CLKM_EN_M (PCR_SARADC_CLKM_EN_V << PCR_SARADC_CLKM_EN_S) +#define PCR_SARADC_CLKM_EN_V 0x00000001U +#define PCR_SARADC_CLKM_EN_S 22 + +/** PCR_TSENS_CLK_CONF_REG register + * TSENS_CLK configuration register + */ +#define PCR_TSENS_CLK_CONF_REG (DR_REG_PCR_BASE + 0x88) +/** PCR_TSENS_CLK_SEL : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0(default): FOSC, 1: XTAL. + */ +#define PCR_TSENS_CLK_SEL (BIT(20)) +#define PCR_TSENS_CLK_SEL_M (PCR_TSENS_CLK_SEL_V << PCR_TSENS_CLK_SEL_S) +#define PCR_TSENS_CLK_SEL_V 0x00000001U +#define PCR_TSENS_CLK_SEL_S 20 +/** PCR_TSENS_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable tsens clock + */ +#define PCR_TSENS_CLK_EN (BIT(22)) +#define PCR_TSENS_CLK_EN_M (PCR_TSENS_CLK_EN_V << PCR_TSENS_CLK_EN_S) +#define PCR_TSENS_CLK_EN_V 0x00000001U +#define PCR_TSENS_CLK_EN_S 22 +/** PCR_TSENS_RST_EN : R/W; bitpos: [23]; default: 0; + * Set 0 to reset tsens module + */ +#define PCR_TSENS_RST_EN (BIT(23)) +#define PCR_TSENS_RST_EN_M (PCR_TSENS_RST_EN_V << PCR_TSENS_RST_EN_S) +#define PCR_TSENS_RST_EN_V 0x00000001U +#define PCR_TSENS_RST_EN_S 23 + +/** PCR_USB_DEVICE_CONF_REG register + * USB_DEVICE configuration register + */ +#define PCR_USB_DEVICE_CONF_REG (DR_REG_PCR_BASE + 0x8c) +/** PCR_USB_DEVICE_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable usb_device clock + */ +#define PCR_USB_DEVICE_CLK_EN (BIT(0)) +#define PCR_USB_DEVICE_CLK_EN_M (PCR_USB_DEVICE_CLK_EN_V << PCR_USB_DEVICE_CLK_EN_S) +#define PCR_USB_DEVICE_CLK_EN_V 0x00000001U +#define PCR_USB_DEVICE_CLK_EN_S 0 +/** PCR_USB_DEVICE_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset usb_device module + */ +#define PCR_USB_DEVICE_RST_EN (BIT(1)) +#define PCR_USB_DEVICE_RST_EN_M (PCR_USB_DEVICE_RST_EN_V << PCR_USB_DEVICE_RST_EN_S) +#define PCR_USB_DEVICE_RST_EN_V 0x00000001U +#define PCR_USB_DEVICE_RST_EN_S 1 + +/** PCR_INTMTX_CONF_REG register + * INTMTX configuration register + */ +#define PCR_INTMTX_CONF_REG (DR_REG_PCR_BASE + 0x90) +/** PCR_INTMTX_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable intmtx clock + */ +#define PCR_INTMTX_CLK_EN (BIT(0)) +#define PCR_INTMTX_CLK_EN_M (PCR_INTMTX_CLK_EN_V << PCR_INTMTX_CLK_EN_S) +#define PCR_INTMTX_CLK_EN_V 0x00000001U +#define PCR_INTMTX_CLK_EN_S 0 +/** PCR_INTMTX_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset intmtx module + */ +#define PCR_INTMTX_RST_EN (BIT(1)) +#define PCR_INTMTX_RST_EN_M (PCR_INTMTX_RST_EN_V << PCR_INTMTX_RST_EN_S) +#define PCR_INTMTX_RST_EN_V 0x00000001U +#define PCR_INTMTX_RST_EN_S 1 + +/** PCR_PCNT_CONF_REG register + * PCNT configuration register + */ +#define PCR_PCNT_CONF_REG (DR_REG_PCR_BASE + 0x94) +/** PCR_PCNT_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable pcnt clock + */ +#define PCR_PCNT_CLK_EN (BIT(0)) +#define PCR_PCNT_CLK_EN_M (PCR_PCNT_CLK_EN_V << PCR_PCNT_CLK_EN_S) +#define PCR_PCNT_CLK_EN_V 0x00000001U +#define PCR_PCNT_CLK_EN_S 0 +/** PCR_PCNT_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset pcnt module + */ +#define PCR_PCNT_RST_EN (BIT(1)) +#define PCR_PCNT_RST_EN_M (PCR_PCNT_RST_EN_V << PCR_PCNT_RST_EN_S) +#define PCR_PCNT_RST_EN_V 0x00000001U +#define PCR_PCNT_RST_EN_S 1 + +/** PCR_ETM_CONF_REG register + * ETM configuration register + */ +#define PCR_ETM_CONF_REG (DR_REG_PCR_BASE + 0x98) +/** PCR_ETM_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable etm clock + */ +#define PCR_ETM_CLK_EN (BIT(0)) +#define PCR_ETM_CLK_EN_M (PCR_ETM_CLK_EN_V << PCR_ETM_CLK_EN_S) +#define PCR_ETM_CLK_EN_V 0x00000001U +#define PCR_ETM_CLK_EN_S 0 +/** PCR_ETM_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset etm module + */ +#define PCR_ETM_RST_EN (BIT(1)) +#define PCR_ETM_RST_EN_M (PCR_ETM_RST_EN_V << PCR_ETM_RST_EN_S) +#define PCR_ETM_RST_EN_V 0x00000001U +#define PCR_ETM_RST_EN_S 1 + +/** PCR_PWM_CONF_REG register + * PWM configuration register + */ +#define PCR_PWM_CONF_REG (DR_REG_PCR_BASE + 0x9c) +/** PCR_PWM_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable pwm clock + */ +#define PCR_PWM_CLK_EN (BIT(0)) +#define PCR_PWM_CLK_EN_M (PCR_PWM_CLK_EN_V << PCR_PWM_CLK_EN_S) +#define PCR_PWM_CLK_EN_V 0x00000001U +#define PCR_PWM_CLK_EN_S 0 +/** PCR_PWM_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset pwm module + */ +#define PCR_PWM_RST_EN (BIT(1)) +#define PCR_PWM_RST_EN_M (PCR_PWM_RST_EN_V << PCR_PWM_RST_EN_S) +#define PCR_PWM_RST_EN_V 0x00000001U +#define PCR_PWM_RST_EN_S 1 + +/** PCR_PWM_CLK_CONF_REG register + * PWM_CLK configuration register + */ +#define PCR_PWM_CLK_CONF_REG (DR_REG_PCR_BASE + 0xa0) +/** PCR_PWM_DIV_NUM : R/W; bitpos: [19:12]; default: 4; + * The integral part of the frequency divider factor of the pwm function clock. + */ +#define PCR_PWM_DIV_NUM 0x000000FFU +#define PCR_PWM_DIV_NUM_M (PCR_PWM_DIV_NUM_V << PCR_PWM_DIV_NUM_S) +#define PCR_PWM_DIV_NUM_V 0x000000FFU +#define PCR_PWM_DIV_NUM_S 12 +/** PCR_PWM_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): do not select anyone clock, 1: + * 160MHz, 2: XTAL, 3: FOSC. + */ +#define PCR_PWM_CLKM_SEL 0x00000003U +#define PCR_PWM_CLKM_SEL_M (PCR_PWM_CLKM_SEL_V << PCR_PWM_CLKM_SEL_S) +#define PCR_PWM_CLKM_SEL_V 0x00000003U +#define PCR_PWM_CLKM_SEL_S 20 +/** PCR_PWM_CLKM_EN : R/W; bitpos: [22]; default: 1; + * set this field as 1 to activate pwm clkm. + */ +#define PCR_PWM_CLKM_EN (BIT(22)) +#define PCR_PWM_CLKM_EN_M (PCR_PWM_CLKM_EN_V << PCR_PWM_CLKM_EN_S) +#define PCR_PWM_CLKM_EN_V 0x00000001U +#define PCR_PWM_CLKM_EN_S 22 + +/** PCR_PARL_IO_CONF_REG register + * PARL_IO configuration register + */ +#define PCR_PARL_IO_CONF_REG (DR_REG_PCR_BASE + 0xa4) +/** PCR_PARL_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable parl apb clock + */ +#define PCR_PARL_CLK_EN (BIT(0)) +#define PCR_PARL_CLK_EN_M (PCR_PARL_CLK_EN_V << PCR_PARL_CLK_EN_S) +#define PCR_PARL_CLK_EN_V 0x00000001U +#define PCR_PARL_CLK_EN_S 0 +/** PCR_PARL_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset parl apb reg + */ +#define PCR_PARL_RST_EN (BIT(1)) +#define PCR_PARL_RST_EN_M (PCR_PARL_RST_EN_V << PCR_PARL_RST_EN_S) +#define PCR_PARL_RST_EN_V 0x00000001U +#define PCR_PARL_RST_EN_S 1 + +/** PCR_PARL_CLK_RX_CONF_REG register + * PARL_CLK_RX configuration register + */ +#define PCR_PARL_CLK_RX_CONF_REG (DR_REG_PCR_BASE + 0xa8) +/** PCR_PARL_CLK_RX_DIV_NUM : R/W; bitpos: [15:0]; default: 0; + * The integral part of the frequency divider factor of the parl rx clock. + */ +#define PCR_PARL_CLK_RX_DIV_NUM 0x0000FFFFU +#define PCR_PARL_CLK_RX_DIV_NUM_M (PCR_PARL_CLK_RX_DIV_NUM_V << PCR_PARL_CLK_RX_DIV_NUM_S) +#define PCR_PARL_CLK_RX_DIV_NUM_V 0x0000FFFFU +#define PCR_PARL_CLK_RX_DIV_NUM_S 0 +/** PCR_PARL_CLK_RX_SEL : R/W; bitpos: [17:16]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3: + * user clock from pad. + */ +#define PCR_PARL_CLK_RX_SEL 0x00000003U +#define PCR_PARL_CLK_RX_SEL_M (PCR_PARL_CLK_RX_SEL_V << PCR_PARL_CLK_RX_SEL_S) +#define PCR_PARL_CLK_RX_SEL_V 0x00000003U +#define PCR_PARL_CLK_RX_SEL_S 16 +/** PCR_PARL_CLK_RX_EN : R/W; bitpos: [18]; default: 1; + * Set 1 to enable parl rx clock + */ +#define PCR_PARL_CLK_RX_EN (BIT(18)) +#define PCR_PARL_CLK_RX_EN_M (PCR_PARL_CLK_RX_EN_V << PCR_PARL_CLK_RX_EN_S) +#define PCR_PARL_CLK_RX_EN_V 0x00000001U +#define PCR_PARL_CLK_RX_EN_S 18 +/** PCR_PARL_RX_RST_EN : R/W; bitpos: [19]; default: 0; + * Set 0 to reset parl rx module + */ +#define PCR_PARL_RX_RST_EN (BIT(19)) +#define PCR_PARL_RX_RST_EN_M (PCR_PARL_RX_RST_EN_V << PCR_PARL_RX_RST_EN_S) +#define PCR_PARL_RX_RST_EN_V 0x00000001U +#define PCR_PARL_RX_RST_EN_S 19 + +/** PCR_PARL_CLK_TX_CONF_REG register + * PARL_CLK_TX configuration register + */ +#define PCR_PARL_CLK_TX_CONF_REG (DR_REG_PCR_BASE + 0xac) +/** PCR_PARL_CLK_TX_DIV_NUM : R/W; bitpos: [15:0]; default: 0; + * The integral part of the frequency divider factor of the parl tx clock. + */ +#define PCR_PARL_CLK_TX_DIV_NUM 0x0000FFFFU +#define PCR_PARL_CLK_TX_DIV_NUM_M (PCR_PARL_CLK_TX_DIV_NUM_V << PCR_PARL_CLK_TX_DIV_NUM_S) +#define PCR_PARL_CLK_TX_DIV_NUM_V 0x0000FFFFU +#define PCR_PARL_CLK_TX_DIV_NUM_S 0 +/** PCR_PARL_CLK_TX_SEL : R/W; bitpos: [17:16]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3: + * user clock from pad. + */ +#define PCR_PARL_CLK_TX_SEL 0x00000003U +#define PCR_PARL_CLK_TX_SEL_M (PCR_PARL_CLK_TX_SEL_V << PCR_PARL_CLK_TX_SEL_S) +#define PCR_PARL_CLK_TX_SEL_V 0x00000003U +#define PCR_PARL_CLK_TX_SEL_S 16 +/** PCR_PARL_CLK_TX_EN : R/W; bitpos: [18]; default: 1; + * Set 1 to enable parl tx clock + */ +#define PCR_PARL_CLK_TX_EN (BIT(18)) +#define PCR_PARL_CLK_TX_EN_M (PCR_PARL_CLK_TX_EN_V << PCR_PARL_CLK_TX_EN_S) +#define PCR_PARL_CLK_TX_EN_V 0x00000001U +#define PCR_PARL_CLK_TX_EN_S 18 +/** PCR_PARL_TX_RST_EN : R/W; bitpos: [19]; default: 0; + * Set 0 to reset parl tx module + */ +#define PCR_PARL_TX_RST_EN (BIT(19)) +#define PCR_PARL_TX_RST_EN_M (PCR_PARL_TX_RST_EN_V << PCR_PARL_TX_RST_EN_S) +#define PCR_PARL_TX_RST_EN_V 0x00000001U +#define PCR_PARL_TX_RST_EN_S 19 + +/** PCR_SDIO_SLAVE_CONF_REG register + * SDIO_SLAVE configuration register + */ +#define PCR_SDIO_SLAVE_CONF_REG (DR_REG_PCR_BASE + 0xb0) +/** PCR_SDIO_SLAVE_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable sdio_slave clock + */ +#define PCR_SDIO_SLAVE_CLK_EN (BIT(0)) +#define PCR_SDIO_SLAVE_CLK_EN_M (PCR_SDIO_SLAVE_CLK_EN_V << PCR_SDIO_SLAVE_CLK_EN_S) +#define PCR_SDIO_SLAVE_CLK_EN_V 0x00000001U +#define PCR_SDIO_SLAVE_CLK_EN_S 0 +/** PCR_SDIO_SLAVE_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset sdio_slave module + */ +#define PCR_SDIO_SLAVE_RST_EN (BIT(1)) +#define PCR_SDIO_SLAVE_RST_EN_M (PCR_SDIO_SLAVE_RST_EN_V << PCR_SDIO_SLAVE_RST_EN_S) +#define PCR_SDIO_SLAVE_RST_EN_V 0x00000001U +#define PCR_SDIO_SLAVE_RST_EN_S 1 + +/** PCR_PVT_MONITOR_CONF_REG register + * PVT_MONITOR configuration register + */ +#define PCR_PVT_MONITOR_CONF_REG (DR_REG_PCR_BASE + 0xb4) +/** PCR_PVT_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable apb clock of pvt module + */ +#define PCR_PVT_MONITOR_CLK_EN (BIT(0)) +#define PCR_PVT_MONITOR_CLK_EN_M (PCR_PVT_MONITOR_CLK_EN_V << PCR_PVT_MONITOR_CLK_EN_S) +#define PCR_PVT_MONITOR_CLK_EN_V 0x00000001U +#define PCR_PVT_MONITOR_CLK_EN_S 0 +/** PCR_PVT_MONITOR_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset all pvt monitor module + */ +#define PCR_PVT_MONITOR_RST_EN (BIT(1)) +#define PCR_PVT_MONITOR_RST_EN_M (PCR_PVT_MONITOR_RST_EN_V << PCR_PVT_MONITOR_RST_EN_S) +#define PCR_PVT_MONITOR_RST_EN_V 0x00000001U +#define PCR_PVT_MONITOR_RST_EN_S 1 +/** PCR_PVT_MONITOR_SITE1_CLK_EN : R/W; bitpos: [2]; default: 1; + * Set 1 to enable function clock of modem pvt module + */ +#define PCR_PVT_MONITOR_SITE1_CLK_EN (BIT(2)) +#define PCR_PVT_MONITOR_SITE1_CLK_EN_M (PCR_PVT_MONITOR_SITE1_CLK_EN_V << PCR_PVT_MONITOR_SITE1_CLK_EN_S) +#define PCR_PVT_MONITOR_SITE1_CLK_EN_V 0x00000001U +#define PCR_PVT_MONITOR_SITE1_CLK_EN_S 2 +/** PCR_PVT_MONITOR_SITE2_CLK_EN : R/W; bitpos: [3]; default: 1; + * Set 1 to enable function clock of cpu pvt module + */ +#define PCR_PVT_MONITOR_SITE2_CLK_EN (BIT(3)) +#define PCR_PVT_MONITOR_SITE2_CLK_EN_M (PCR_PVT_MONITOR_SITE2_CLK_EN_V << PCR_PVT_MONITOR_SITE2_CLK_EN_S) +#define PCR_PVT_MONITOR_SITE2_CLK_EN_V 0x00000001U +#define PCR_PVT_MONITOR_SITE2_CLK_EN_S 3 +/** PCR_PVT_MONITOR_SITE3_CLK_EN : R/W; bitpos: [4]; default: 1; + * Set 1 to enable function clock of hp_peri pvt module + */ +#define PCR_PVT_MONITOR_SITE3_CLK_EN (BIT(4)) +#define PCR_PVT_MONITOR_SITE3_CLK_EN_M (PCR_PVT_MONITOR_SITE3_CLK_EN_V << PCR_PVT_MONITOR_SITE3_CLK_EN_S) +#define PCR_PVT_MONITOR_SITE3_CLK_EN_V 0x00000001U +#define PCR_PVT_MONITOR_SITE3_CLK_EN_S 4 + +/** PCR_PVT_MONITOR_FUNC_CLK_CONF_REG register + * PVT_MONITOR function clock configuration register + */ +#define PCR_PVT_MONITOR_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0xb8) +/** PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM : R/W; bitpos: [3:0]; default: 0; + * The integral part of the frequency divider factor of the pvt_monitor function clock. + */ +#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM 0x0000000FU +#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_M (PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_V << PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_S) +#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_V 0x0000000FU +#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_S 0 +/** PCR_PVT_MONITOR_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0: XTAL, 1(default): 160MHz driven by SPLL + * divided by 3. + */ +#define PCR_PVT_MONITOR_FUNC_CLK_SEL (BIT(20)) +#define PCR_PVT_MONITOR_FUNC_CLK_SEL_M (PCR_PVT_MONITOR_FUNC_CLK_SEL_V << PCR_PVT_MONITOR_FUNC_CLK_SEL_S) +#define PCR_PVT_MONITOR_FUNC_CLK_SEL_V 0x00000001U +#define PCR_PVT_MONITOR_FUNC_CLK_SEL_S 20 +/** PCR_PVT_MONITOR_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable source clock of pvt sitex + */ +#define PCR_PVT_MONITOR_FUNC_CLK_EN (BIT(22)) +#define PCR_PVT_MONITOR_FUNC_CLK_EN_M (PCR_PVT_MONITOR_FUNC_CLK_EN_V << PCR_PVT_MONITOR_FUNC_CLK_EN_S) +#define PCR_PVT_MONITOR_FUNC_CLK_EN_V 0x00000001U +#define PCR_PVT_MONITOR_FUNC_CLK_EN_S 22 + +/** PCR_GDMA_CONF_REG register + * GDMA configuration register + */ +#define PCR_GDMA_CONF_REG (DR_REG_PCR_BASE + 0xbc) +/** PCR_GDMA_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable gdma clock + */ +#define PCR_GDMA_CLK_EN (BIT(0)) +#define PCR_GDMA_CLK_EN_M (PCR_GDMA_CLK_EN_V << PCR_GDMA_CLK_EN_S) +#define PCR_GDMA_CLK_EN_V 0x00000001U +#define PCR_GDMA_CLK_EN_S 0 +/** PCR_GDMA_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset gdma module + */ +#define PCR_GDMA_RST_EN (BIT(1)) +#define PCR_GDMA_RST_EN_M (PCR_GDMA_RST_EN_V << PCR_GDMA_RST_EN_S) +#define PCR_GDMA_RST_EN_V 0x00000001U +#define PCR_GDMA_RST_EN_S 1 + +/** PCR_SPI2_CONF_REG register + * SPI2 configuration register + */ +#define PCR_SPI2_CONF_REG (DR_REG_PCR_BASE + 0xc0) +/** PCR_SPI2_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable spi2 apb clock + */ +#define PCR_SPI2_CLK_EN (BIT(0)) +#define PCR_SPI2_CLK_EN_M (PCR_SPI2_CLK_EN_V << PCR_SPI2_CLK_EN_S) +#define PCR_SPI2_CLK_EN_V 0x00000001U +#define PCR_SPI2_CLK_EN_S 0 +/** PCR_SPI2_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset spi2 module + */ +#define PCR_SPI2_RST_EN (BIT(1)) +#define PCR_SPI2_RST_EN_M (PCR_SPI2_RST_EN_V << PCR_SPI2_RST_EN_S) +#define PCR_SPI2_RST_EN_V 0x00000001U +#define PCR_SPI2_RST_EN_S 1 + +/** PCR_SPI2_CLKM_CONF_REG register + * SPI2_CLKM configuration register + */ +#define PCR_SPI2_CLKM_CONF_REG (DR_REG_PCR_BASE + 0xc4) +/** PCR_SPI2_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: + * reserved. + */ +#define PCR_SPI2_CLKM_SEL 0x00000003U +#define PCR_SPI2_CLKM_SEL_M (PCR_SPI2_CLKM_SEL_V << PCR_SPI2_CLKM_SEL_S) +#define PCR_SPI2_CLKM_SEL_V 0x00000003U +#define PCR_SPI2_CLKM_SEL_S 20 +/** PCR_SPI2_CLKM_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable spi2 function clock + */ +#define PCR_SPI2_CLKM_EN (BIT(22)) +#define PCR_SPI2_CLKM_EN_M (PCR_SPI2_CLKM_EN_V << PCR_SPI2_CLKM_EN_S) +#define PCR_SPI2_CLKM_EN_V 0x00000001U +#define PCR_SPI2_CLKM_EN_S 22 + +/** PCR_AES_CONF_REG register + * AES configuration register + */ +#define PCR_AES_CONF_REG (DR_REG_PCR_BASE + 0xc8) +/** PCR_AES_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable aes clock + */ +#define PCR_AES_CLK_EN (BIT(0)) +#define PCR_AES_CLK_EN_M (PCR_AES_CLK_EN_V << PCR_AES_CLK_EN_S) +#define PCR_AES_CLK_EN_V 0x00000001U +#define PCR_AES_CLK_EN_S 0 +/** PCR_AES_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset aes module + */ +#define PCR_AES_RST_EN (BIT(1)) +#define PCR_AES_RST_EN_M (PCR_AES_RST_EN_V << PCR_AES_RST_EN_S) +#define PCR_AES_RST_EN_V 0x00000001U +#define PCR_AES_RST_EN_S 1 + +/** PCR_SHA_CONF_REG register + * SHA configuration register + */ +#define PCR_SHA_CONF_REG (DR_REG_PCR_BASE + 0xcc) +/** PCR_SHA_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable sha clock + */ +#define PCR_SHA_CLK_EN (BIT(0)) +#define PCR_SHA_CLK_EN_M (PCR_SHA_CLK_EN_V << PCR_SHA_CLK_EN_S) +#define PCR_SHA_CLK_EN_V 0x00000001U +#define PCR_SHA_CLK_EN_S 0 +/** PCR_SHA_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset sha module + */ +#define PCR_SHA_RST_EN (BIT(1)) +#define PCR_SHA_RST_EN_M (PCR_SHA_RST_EN_V << PCR_SHA_RST_EN_S) +#define PCR_SHA_RST_EN_V 0x00000001U +#define PCR_SHA_RST_EN_S 1 + +/** PCR_RSA_CONF_REG register + * RSA configuration register + */ +#define PCR_RSA_CONF_REG (DR_REG_PCR_BASE + 0xd0) +/** PCR_RSA_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable rsa clock + */ +#define PCR_RSA_CLK_EN (BIT(0)) +#define PCR_RSA_CLK_EN_M (PCR_RSA_CLK_EN_V << PCR_RSA_CLK_EN_S) +#define PCR_RSA_CLK_EN_V 0x00000001U +#define PCR_RSA_CLK_EN_S 0 +/** PCR_RSA_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset rsa module + */ +#define PCR_RSA_RST_EN (BIT(1)) +#define PCR_RSA_RST_EN_M (PCR_RSA_RST_EN_V << PCR_RSA_RST_EN_S) +#define PCR_RSA_RST_EN_V 0x00000001U +#define PCR_RSA_RST_EN_S 1 + +/** PCR_RSA_PD_CTRL_REG register + * RSA power control register + */ +#define PCR_RSA_PD_CTRL_REG (DR_REG_PCR_BASE + 0xd4) +/** PCR_RSA_MEM_PD : R/W; bitpos: [0]; default: 0; + * Set this bit to power down rsa internal memory. + */ +#define PCR_RSA_MEM_PD (BIT(0)) +#define PCR_RSA_MEM_PD_M (PCR_RSA_MEM_PD_V << PCR_RSA_MEM_PD_S) +#define PCR_RSA_MEM_PD_V 0x00000001U +#define PCR_RSA_MEM_PD_S 0 +/** PCR_RSA_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1; + * Set this bit to force power up rsa internal memory + */ +#define PCR_RSA_MEM_FORCE_PU (BIT(1)) +#define PCR_RSA_MEM_FORCE_PU_M (PCR_RSA_MEM_FORCE_PU_V << PCR_RSA_MEM_FORCE_PU_S) +#define PCR_RSA_MEM_FORCE_PU_V 0x00000001U +#define PCR_RSA_MEM_FORCE_PU_S 1 +/** PCR_RSA_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; + * Set this bit to force power down rsa internal memory. + */ +#define PCR_RSA_MEM_FORCE_PD (BIT(2)) +#define PCR_RSA_MEM_FORCE_PD_M (PCR_RSA_MEM_FORCE_PD_V << PCR_RSA_MEM_FORCE_PD_S) +#define PCR_RSA_MEM_FORCE_PD_V 0x00000001U +#define PCR_RSA_MEM_FORCE_PD_S 2 + +/** PCR_ECC_CONF_REG register + * ECC configuration register + */ +#define PCR_ECC_CONF_REG (DR_REG_PCR_BASE + 0xd8) +/** PCR_ECC_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable ecc clock + */ +#define PCR_ECC_CLK_EN (BIT(0)) +#define PCR_ECC_CLK_EN_M (PCR_ECC_CLK_EN_V << PCR_ECC_CLK_EN_S) +#define PCR_ECC_CLK_EN_V 0x00000001U +#define PCR_ECC_CLK_EN_S 0 +/** PCR_ECC_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset ecc module + */ +#define PCR_ECC_RST_EN (BIT(1)) +#define PCR_ECC_RST_EN_M (PCR_ECC_RST_EN_V << PCR_ECC_RST_EN_S) +#define PCR_ECC_RST_EN_V 0x00000001U +#define PCR_ECC_RST_EN_S 1 + +/** PCR_ECC_PD_CTRL_REG register + * ECC power control register + */ +#define PCR_ECC_PD_CTRL_REG (DR_REG_PCR_BASE + 0xdc) +/** PCR_ECC_MEM_PD : R/W; bitpos: [0]; default: 0; + * Set this bit to power down ecc internal memory. + */ +#define PCR_ECC_MEM_PD (BIT(0)) +#define PCR_ECC_MEM_PD_M (PCR_ECC_MEM_PD_V << PCR_ECC_MEM_PD_S) +#define PCR_ECC_MEM_PD_V 0x00000001U +#define PCR_ECC_MEM_PD_S 0 +/** PCR_ECC_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1; + * Set this bit to force power up ecc internal memory + */ +#define PCR_ECC_MEM_FORCE_PU (BIT(1)) +#define PCR_ECC_MEM_FORCE_PU_M (PCR_ECC_MEM_FORCE_PU_V << PCR_ECC_MEM_FORCE_PU_S) +#define PCR_ECC_MEM_FORCE_PU_V 0x00000001U +#define PCR_ECC_MEM_FORCE_PU_S 1 +/** PCR_ECC_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; + * Set this bit to force power down ecc internal memory. + */ +#define PCR_ECC_MEM_FORCE_PD (BIT(2)) +#define PCR_ECC_MEM_FORCE_PD_M (PCR_ECC_MEM_FORCE_PD_V << PCR_ECC_MEM_FORCE_PD_S) +#define PCR_ECC_MEM_FORCE_PD_V 0x00000001U +#define PCR_ECC_MEM_FORCE_PD_S 2 + +/** PCR_DS_CONF_REG register + * DS configuration register + */ +#define PCR_DS_CONF_REG (DR_REG_PCR_BASE + 0xe0) +/** PCR_DS_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable ds clock + */ +#define PCR_DS_CLK_EN (BIT(0)) +#define PCR_DS_CLK_EN_M (PCR_DS_CLK_EN_V << PCR_DS_CLK_EN_S) +#define PCR_DS_CLK_EN_V 0x00000001U +#define PCR_DS_CLK_EN_S 0 +/** PCR_DS_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset ds module + */ +#define PCR_DS_RST_EN (BIT(1)) +#define PCR_DS_RST_EN_M (PCR_DS_RST_EN_V << PCR_DS_RST_EN_S) +#define PCR_DS_RST_EN_V 0x00000001U +#define PCR_DS_RST_EN_S 1 + +/** PCR_HMAC_CONF_REG register + * HMAC configuration register + */ +#define PCR_HMAC_CONF_REG (DR_REG_PCR_BASE + 0xe4) +/** PCR_HMAC_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable hmac clock + */ +#define PCR_HMAC_CLK_EN (BIT(0)) +#define PCR_HMAC_CLK_EN_M (PCR_HMAC_CLK_EN_V << PCR_HMAC_CLK_EN_S) +#define PCR_HMAC_CLK_EN_V 0x00000001U +#define PCR_HMAC_CLK_EN_S 0 +/** PCR_HMAC_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset hmac module + */ +#define PCR_HMAC_RST_EN (BIT(1)) +#define PCR_HMAC_RST_EN_M (PCR_HMAC_RST_EN_V << PCR_HMAC_RST_EN_S) +#define PCR_HMAC_RST_EN_V 0x00000001U +#define PCR_HMAC_RST_EN_S 1 + +/** PCR_IOMUX_CONF_REG register + * IOMUX configuration register + */ +#define PCR_IOMUX_CONF_REG (DR_REG_PCR_BASE + 0xe8) +/** PCR_IOMUX_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable iomux apb clock + */ +#define PCR_IOMUX_CLK_EN (BIT(0)) +#define PCR_IOMUX_CLK_EN_M (PCR_IOMUX_CLK_EN_V << PCR_IOMUX_CLK_EN_S) +#define PCR_IOMUX_CLK_EN_V 0x00000001U +#define PCR_IOMUX_CLK_EN_S 0 +/** PCR_IOMUX_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset iomux module + */ +#define PCR_IOMUX_RST_EN (BIT(1)) +#define PCR_IOMUX_RST_EN_M (PCR_IOMUX_RST_EN_V << PCR_IOMUX_RST_EN_S) +#define PCR_IOMUX_RST_EN_V 0x00000001U +#define PCR_IOMUX_RST_EN_S 1 + +/** PCR_IOMUX_CLK_CONF_REG register + * IOMUX_CLK configuration register + */ +#define PCR_IOMUX_CLK_CONF_REG (DR_REG_PCR_BASE + 0xec) +/** PCR_IOMUX_FUNC_CLK_SEL : R/W; bitpos: [21:20]; default: 3; + * set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: + * FOSC, 3(default): XTAL. + */ +#define PCR_IOMUX_FUNC_CLK_SEL 0x00000003U +#define PCR_IOMUX_FUNC_CLK_SEL_M (PCR_IOMUX_FUNC_CLK_SEL_V << PCR_IOMUX_FUNC_CLK_SEL_S) +#define PCR_IOMUX_FUNC_CLK_SEL_V 0x00000003U +#define PCR_IOMUX_FUNC_CLK_SEL_S 20 +/** PCR_IOMUX_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable iomux function clock + */ +#define PCR_IOMUX_FUNC_CLK_EN (BIT(22)) +#define PCR_IOMUX_FUNC_CLK_EN_M (PCR_IOMUX_FUNC_CLK_EN_V << PCR_IOMUX_FUNC_CLK_EN_S) +#define PCR_IOMUX_FUNC_CLK_EN_V 0x00000001U +#define PCR_IOMUX_FUNC_CLK_EN_S 22 + +/** PCR_MEM_MONITOR_CONF_REG register + * MEM_MONITOR configuration register + */ +#define PCR_MEM_MONITOR_CONF_REG (DR_REG_PCR_BASE + 0xf0) +/** PCR_MEM_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable mem_monitor clock + */ +#define PCR_MEM_MONITOR_CLK_EN (BIT(0)) +#define PCR_MEM_MONITOR_CLK_EN_M (PCR_MEM_MONITOR_CLK_EN_V << PCR_MEM_MONITOR_CLK_EN_S) +#define PCR_MEM_MONITOR_CLK_EN_V 0x00000001U +#define PCR_MEM_MONITOR_CLK_EN_S 0 +/** PCR_MEM_MONITOR_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset mem_monitor module + */ +#define PCR_MEM_MONITOR_RST_EN (BIT(1)) +#define PCR_MEM_MONITOR_RST_EN_M (PCR_MEM_MONITOR_RST_EN_V << PCR_MEM_MONITOR_RST_EN_S) +#define PCR_MEM_MONITOR_RST_EN_V 0x00000001U +#define PCR_MEM_MONITOR_RST_EN_S 1 + +/** PCR_REGDMA_CONF_REG register + * REGDMA configuration register + */ +#define PCR_REGDMA_CONF_REG (DR_REG_PCR_BASE + 0xf4) +/** PCR_REGDMA_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable regdma clock + */ +#define PCR_REGDMA_CLK_EN (BIT(0)) +#define PCR_REGDMA_CLK_EN_M (PCR_REGDMA_CLK_EN_V << PCR_REGDMA_CLK_EN_S) +#define PCR_REGDMA_CLK_EN_V 0x00000001U +#define PCR_REGDMA_CLK_EN_S 0 +/** PCR_REGDMA_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset regdma module + */ +#define PCR_REGDMA_RST_EN (BIT(1)) +#define PCR_REGDMA_RST_EN_M (PCR_REGDMA_RST_EN_V << PCR_REGDMA_RST_EN_S) +#define PCR_REGDMA_RST_EN_V 0x00000001U +#define PCR_REGDMA_RST_EN_S 1 + +/** PCR_RETENTION_CONF_REG register + * retention configuration register + */ +#define PCR_RETENTION_CONF_REG (DR_REG_PCR_BASE + 0xf8) +/** PCR_RETENTION_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable retention clock + */ +#define PCR_RETENTION_CLK_EN (BIT(0)) +#define PCR_RETENTION_CLK_EN_M (PCR_RETENTION_CLK_EN_V << PCR_RETENTION_CLK_EN_S) +#define PCR_RETENTION_CLK_EN_V 0x00000001U +#define PCR_RETENTION_CLK_EN_S 0 +/** PCR_RETENTION_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset retention module + */ +#define PCR_RETENTION_RST_EN (BIT(1)) +#define PCR_RETENTION_RST_EN_M (PCR_RETENTION_RST_EN_V << PCR_RETENTION_RST_EN_S) +#define PCR_RETENTION_RST_EN_V 0x00000001U +#define PCR_RETENTION_RST_EN_S 1 + +/** PCR_TRACE_CONF_REG register + * TRACE configuration register + */ +#define PCR_TRACE_CONF_REG (DR_REG_PCR_BASE + 0xfc) +/** PCR_TRACE_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable trace clock + */ +#define PCR_TRACE_CLK_EN (BIT(0)) +#define PCR_TRACE_CLK_EN_M (PCR_TRACE_CLK_EN_V << PCR_TRACE_CLK_EN_S) +#define PCR_TRACE_CLK_EN_V 0x00000001U +#define PCR_TRACE_CLK_EN_S 0 +/** PCR_TRACE_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset trace module + */ +#define PCR_TRACE_RST_EN (BIT(1)) +#define PCR_TRACE_RST_EN_M (PCR_TRACE_RST_EN_V << PCR_TRACE_RST_EN_S) +#define PCR_TRACE_RST_EN_V 0x00000001U +#define PCR_TRACE_RST_EN_S 1 + +/** PCR_ASSIST_CONF_REG register + * ASSIST configuration register + */ +#define PCR_ASSIST_CONF_REG (DR_REG_PCR_BASE + 0x100) +/** PCR_ASSIST_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable assist clock + */ +#define PCR_ASSIST_CLK_EN (BIT(0)) +#define PCR_ASSIST_CLK_EN_M (PCR_ASSIST_CLK_EN_V << PCR_ASSIST_CLK_EN_S) +#define PCR_ASSIST_CLK_EN_V 0x00000001U +#define PCR_ASSIST_CLK_EN_S 0 +/** PCR_ASSIST_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset assist module + */ +#define PCR_ASSIST_RST_EN (BIT(1)) +#define PCR_ASSIST_RST_EN_M (PCR_ASSIST_RST_EN_V << PCR_ASSIST_RST_EN_S) +#define PCR_ASSIST_RST_EN_V 0x00000001U +#define PCR_ASSIST_RST_EN_S 1 + +/** PCR_CACHE_CONF_REG register + * CACHE configuration register + */ +#define PCR_CACHE_CONF_REG (DR_REG_PCR_BASE + 0x104) +/** PCR_CACHE_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable cache clock + */ +#define PCR_CACHE_CLK_EN (BIT(0)) +#define PCR_CACHE_CLK_EN_M (PCR_CACHE_CLK_EN_V << PCR_CACHE_CLK_EN_S) +#define PCR_CACHE_CLK_EN_V 0x00000001U +#define PCR_CACHE_CLK_EN_S 0 +/** PCR_CACHE_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset cache module + */ +#define PCR_CACHE_RST_EN (BIT(1)) +#define PCR_CACHE_RST_EN_M (PCR_CACHE_RST_EN_V << PCR_CACHE_RST_EN_S) +#define PCR_CACHE_RST_EN_V 0x00000001U +#define PCR_CACHE_RST_EN_S 1 + +/** PCR_MODEM_APB_CONF_REG register + * MODEM_APB configuration register + */ +#define PCR_MODEM_APB_CONF_REG (DR_REG_PCR_BASE + 0x108) +/** PCR_MODEM_APB_CLK_EN : R/W; bitpos: [0]; default: 1; + * This field indicates if modem_apb clock is enable. 0: disable, 1: enable(default). + */ +#define PCR_MODEM_APB_CLK_EN (BIT(0)) +#define PCR_MODEM_APB_CLK_EN_M (PCR_MODEM_APB_CLK_EN_V << PCR_MODEM_APB_CLK_EN_S) +#define PCR_MODEM_APB_CLK_EN_V 0x00000001U +#define PCR_MODEM_APB_CLK_EN_S 0 +/** PCR_MODEM_RST_EN : R/W; bitpos: [1]; default: 0; + * Set this file as 1 to reset modem-subsystem. + */ +#define PCR_MODEM_RST_EN (BIT(1)) +#define PCR_MODEM_RST_EN_M (PCR_MODEM_RST_EN_V << PCR_MODEM_RST_EN_S) +#define PCR_MODEM_RST_EN_V 0x00000001U +#define PCR_MODEM_RST_EN_S 1 + +/** PCR_TIMEOUT_CONF_REG register + * TIMEOUT configuration register + */ +#define PCR_TIMEOUT_CONF_REG (DR_REG_PCR_BASE + 0x10c) +/** PCR_CPU_TIMEOUT_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset cpu_peri timeout module + */ +#define PCR_CPU_TIMEOUT_RST_EN (BIT(1)) +#define PCR_CPU_TIMEOUT_RST_EN_M (PCR_CPU_TIMEOUT_RST_EN_V << PCR_CPU_TIMEOUT_RST_EN_S) +#define PCR_CPU_TIMEOUT_RST_EN_V 0x00000001U +#define PCR_CPU_TIMEOUT_RST_EN_S 1 +/** PCR_HP_TIMEOUT_RST_EN : R/W; bitpos: [2]; default: 0; + * Set 0 to reset hp_peri timeout module and hp_modem timeout module + */ +#define PCR_HP_TIMEOUT_RST_EN (BIT(2)) +#define PCR_HP_TIMEOUT_RST_EN_M (PCR_HP_TIMEOUT_RST_EN_V << PCR_HP_TIMEOUT_RST_EN_S) +#define PCR_HP_TIMEOUT_RST_EN_V 0x00000001U +#define PCR_HP_TIMEOUT_RST_EN_S 2 + +/** PCR_SYSCLK_CONF_REG register + * SYSCLK configuration register + */ +#define PCR_SYSCLK_CONF_REG (DR_REG_PCR_BASE + 0x110) +/** PCR_LS_DIV_NUM : HRO; bitpos: [7:0]; default: 0; + * clk_hproot is div1 of low-speed clock-source if clck-source is a low-speed + * clock-source such as XTAL/FOSC. + */ +#define PCR_LS_DIV_NUM 0x000000FFU +#define PCR_LS_DIV_NUM_M (PCR_LS_DIV_NUM_V << PCR_LS_DIV_NUM_S) +#define PCR_LS_DIV_NUM_V 0x000000FFU +#define PCR_LS_DIV_NUM_S 0 +/** PCR_HS_DIV_NUM : HRO; bitpos: [15:8]; default: 2; + * clk_hproot is div3 of SPLL if the clock-source is high-speed clock SPLL. + */ +#define PCR_HS_DIV_NUM 0x000000FFU +#define PCR_HS_DIV_NUM_M (PCR_HS_DIV_NUM_V << PCR_HS_DIV_NUM_S) +#define PCR_HS_DIV_NUM_V 0x000000FFU +#define PCR_HS_DIV_NUM_S 8 +/** PCR_SOC_CLK_SEL : R/W; bitpos: [17:16]; default: 0; + * This field is used to select clock source. 0: XTAL, 1: SPLL, 2: FOSC, 3: reserved. + */ +#define PCR_SOC_CLK_SEL 0x00000003U +#define PCR_SOC_CLK_SEL_M (PCR_SOC_CLK_SEL_V << PCR_SOC_CLK_SEL_S) +#define PCR_SOC_CLK_SEL_V 0x00000003U +#define PCR_SOC_CLK_SEL_S 16 +/** PCR_CLK_XTAL_FREQ : RO; bitpos: [30:24]; default: 40; + * This field indicates the frequency(MHz) of XTAL. + */ +#define PCR_CLK_XTAL_FREQ 0x0000007FU +#define PCR_CLK_XTAL_FREQ_M (PCR_CLK_XTAL_FREQ_V << PCR_CLK_XTAL_FREQ_S) +#define PCR_CLK_XTAL_FREQ_V 0x0000007FU +#define PCR_CLK_XTAL_FREQ_S 24 + +/** PCR_CPU_WAITI_CONF_REG register + * CPU_WAITI configuration register + */ +#define PCR_CPU_WAITI_CONF_REG (DR_REG_PCR_BASE + 0x114) +/** PCR_CPUPERIOD_SEL : HRO; bitpos: [1:0]; default: 1; + * Reserved. This filed has been replaced by PCR_CPU_HS_DIV_NUM and PCR_CPU_LS_DIV_NUM + */ +#define PCR_CPUPERIOD_SEL 0x00000003U +#define PCR_CPUPERIOD_SEL_M (PCR_CPUPERIOD_SEL_V << PCR_CPUPERIOD_SEL_S) +#define PCR_CPUPERIOD_SEL_V 0x00000003U +#define PCR_CPUPERIOD_SEL_S 0 +/** PCR_PLL_FREQ_SEL : HRO; bitpos: [2]; default: 1; + * Reserved. This filed has been replaced by PCR_CPU_HS_DIV_NUM and PCR_CPU_LS_DIV_NUM + */ +#define PCR_PLL_FREQ_SEL (BIT(2)) +#define PCR_PLL_FREQ_SEL_M (PCR_PLL_FREQ_SEL_V << PCR_PLL_FREQ_SEL_S) +#define PCR_PLL_FREQ_SEL_V 0x00000001U +#define PCR_PLL_FREQ_SEL_S 2 +/** PCR_CPU_WAIT_MODE_FORCE_ON : R/W; bitpos: [3]; default: 1; + * Set 1 to force cpu_waiti_clk enable. + */ +#define PCR_CPU_WAIT_MODE_FORCE_ON (BIT(3)) +#define PCR_CPU_WAIT_MODE_FORCE_ON_M (PCR_CPU_WAIT_MODE_FORCE_ON_V << PCR_CPU_WAIT_MODE_FORCE_ON_S) +#define PCR_CPU_WAIT_MODE_FORCE_ON_V 0x00000001U +#define PCR_CPU_WAIT_MODE_FORCE_ON_S 3 +/** PCR_CPU_WAITI_DELAY_NUM : R/W; bitpos: [7:4]; default: 0; + * This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk + * will close + */ +#define PCR_CPU_WAITI_DELAY_NUM 0x0000000FU +#define PCR_CPU_WAITI_DELAY_NUM_M (PCR_CPU_WAITI_DELAY_NUM_V << PCR_CPU_WAITI_DELAY_NUM_S) +#define PCR_CPU_WAITI_DELAY_NUM_V 0x0000000FU +#define PCR_CPU_WAITI_DELAY_NUM_S 4 + +/** PCR_CPU_FREQ_CONF_REG register + * CPU_FREQ configuration register + */ +#define PCR_CPU_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x118) +/** PCR_CPU_LS_DIV_NUM : R/W; bitpos: [7:0]; default: 0; + * Set as one within (0,1,3) to generate clk_cpu driven by clk_hproot. The clk_cpu is + * div1(default)/div2/div4 of clk_hproot. This field is only available for low-speed + * clock-source such as XTAL/FOSC, and should be used together with PCR_AHB_LS_DIV_NUM. + */ +#define PCR_CPU_LS_DIV_NUM 0x000000FFU +#define PCR_CPU_LS_DIV_NUM_M (PCR_CPU_LS_DIV_NUM_V << PCR_CPU_LS_DIV_NUM_S) +#define PCR_CPU_LS_DIV_NUM_V 0x000000FFU +#define PCR_CPU_LS_DIV_NUM_S 0 +/** PCR_CPU_HS_DIV_NUM : R/W; bitpos: [15:8]; default: 0; + * Set as one within (0,1,3) to generate clk_cpu driven by clk_hproot. The clk_cpu is + * div1(default)/div2/div4 of clk_hproot. This field is only available for high-speed + * clock-source such as SPLL, and should be used together with PCR_AHB_HS_DIV_NUM. + */ +#define PCR_CPU_HS_DIV_NUM 0x000000FFU +#define PCR_CPU_HS_DIV_NUM_M (PCR_CPU_HS_DIV_NUM_V << PCR_CPU_HS_DIV_NUM_S) +#define PCR_CPU_HS_DIV_NUM_V 0x000000FFU +#define PCR_CPU_HS_DIV_NUM_S 8 +/** PCR_CPU_HS_120M_FORCE : R/W; bitpos: [16]; default: 0; + * Given that PCR_CPU_HS_DIV_NUM is 0, set this field as 1 to force clk_cpu at 120MHz. + * Only available when PCR_CPU_HS_DIV_NUM is 0 and clk_cpu is driven by SPLL. + */ +#define PCR_CPU_HS_120M_FORCE (BIT(16)) +#define PCR_CPU_HS_120M_FORCE_M (PCR_CPU_HS_120M_FORCE_V << PCR_CPU_HS_120M_FORCE_S) +#define PCR_CPU_HS_120M_FORCE_V 0x00000001U +#define PCR_CPU_HS_120M_FORCE_S 16 + +/** PCR_AHB_FREQ_CONF_REG register + * AHB_FREQ configuration register + */ +#define PCR_AHB_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x11c) +/** PCR_AHB_LS_DIV_NUM : R/W; bitpos: [7:0]; default: 0; + * Set as one within (0,1,3,7) to generate clk_ahb driven by clk_hproot. The clk_ahb + * is div1(default)/div2/div4/div8 of clk_hproot. This field is only available for + * low-speed clock-source such as XTAL/FOSC, and should be used together with + * PCR_CPU_LS_DIV_NUM. + */ +#define PCR_AHB_LS_DIV_NUM 0x000000FFU +#define PCR_AHB_LS_DIV_NUM_M (PCR_AHB_LS_DIV_NUM_V << PCR_AHB_LS_DIV_NUM_S) +#define PCR_AHB_LS_DIV_NUM_V 0x000000FFU +#define PCR_AHB_LS_DIV_NUM_S 0 +/** PCR_AHB_HS_DIV_NUM : R/W; bitpos: [15:8]; default: 3; + * Set as one within (3,7,15) to generate clk_ahb driven by clk_hproot. The clk_ahb is + * div4(default)/div8/div16 of clk_hproot. This field is only available for high-speed + * clock-source such as SPLL, and should be used together with PCR_CPU_HS_DIV_NUM. + */ +#define PCR_AHB_HS_DIV_NUM 0x000000FFU +#define PCR_AHB_HS_DIV_NUM_M (PCR_AHB_HS_DIV_NUM_V << PCR_AHB_HS_DIV_NUM_S) +#define PCR_AHB_HS_DIV_NUM_V 0x000000FFU +#define PCR_AHB_HS_DIV_NUM_S 8 + +/** PCR_APB_FREQ_CONF_REG register + * APB_FREQ configuration register + */ +#define PCR_APB_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x120) +/** PCR_APB_DECREASE_DIV_NUM : R/W; bitpos: [7:0]; default: 0; + * If this field's value is grater than PCR_APB_DIV_NUM, the clk_apb will be + * automatically down to clk_apb_decrease only when no access is on apb-bus, and will + * recover to the previous frequency when a new access appears on apb-bus. Set as one + * within (0,1,3) to set clk_apb_decrease as div1/div2/div4(default) of clk_ahb. Note + * that enable this function will reduce performance. Users can set this field as zero + * to disable the auto-decrease-apb-freq function. By default, this function is + * disable. + */ +#define PCR_APB_DECREASE_DIV_NUM 0x000000FFU +#define PCR_APB_DECREASE_DIV_NUM_M (PCR_APB_DECREASE_DIV_NUM_V << PCR_APB_DECREASE_DIV_NUM_S) +#define PCR_APB_DECREASE_DIV_NUM_V 0x000000FFU +#define PCR_APB_DECREASE_DIV_NUM_S 0 +/** PCR_APB_DIV_NUM : R/W; bitpos: [15:8]; default: 0; + * Set as one within (0,1,3) to generate clk_apb driven by clk_ahb. The clk_apb is + * div1(default)/div2/div4 of clk_ahb. + */ +#define PCR_APB_DIV_NUM 0x000000FFU +#define PCR_APB_DIV_NUM_M (PCR_APB_DIV_NUM_V << PCR_APB_DIV_NUM_S) +#define PCR_APB_DIV_NUM_V 0x000000FFU +#define PCR_APB_DIV_NUM_S 8 + +/** PCR_SYSCLK_FREQ_QUERY_0_REG register + * SYSCLK frequency query 0 register + */ +#define PCR_SYSCLK_FREQ_QUERY_0_REG (DR_REG_PCR_BASE + 0x124) +/** PCR_FOSC_FREQ : HRO; bitpos: [7:0]; default: 20; + * This field indicates the frequency(MHz) of FOSC. + */ +#define PCR_FOSC_FREQ 0x000000FFU +#define PCR_FOSC_FREQ_M (PCR_FOSC_FREQ_V << PCR_FOSC_FREQ_S) +#define PCR_FOSC_FREQ_V 0x000000FFU +#define PCR_FOSC_FREQ_S 0 +/** PCR_PLL_FREQ : HRO; bitpos: [17:8]; default: 480; + * This field indicates the frequency(MHz) of SPLL. + */ +#define PCR_PLL_FREQ 0x000003FFU +#define PCR_PLL_FREQ_M (PCR_PLL_FREQ_V << PCR_PLL_FREQ_S) +#define PCR_PLL_FREQ_V 0x000003FFU +#define PCR_PLL_FREQ_S 8 + +/** PCR_PLL_DIV_CLK_EN_REG register + * SPLL DIV clock-gating configuration register + */ +#define PCR_PLL_DIV_CLK_EN_REG (DR_REG_PCR_BASE + 0x128) +/** PCR_PLL_240M_CLK_EN : R/W; bitpos: [0]; default: 1; + * This field is used to open 240 MHz clock (div2 of SPLL) driven from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_240M_CLK_EN (BIT(0)) +#define PCR_PLL_240M_CLK_EN_M (PCR_PLL_240M_CLK_EN_V << PCR_PLL_240M_CLK_EN_S) +#define PCR_PLL_240M_CLK_EN_V 0x00000001U +#define PCR_PLL_240M_CLK_EN_S 0 +/** PCR_PLL_160M_CLK_EN : R/W; bitpos: [1]; default: 1; + * This field is used to open 160 MHz clock (div3 of SPLL) driven from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_160M_CLK_EN (BIT(1)) +#define PCR_PLL_160M_CLK_EN_M (PCR_PLL_160M_CLK_EN_V << PCR_PLL_160M_CLK_EN_S) +#define PCR_PLL_160M_CLK_EN_V 0x00000001U +#define PCR_PLL_160M_CLK_EN_S 1 +/** PCR_PLL_120M_CLK_EN : R/W; bitpos: [2]; default: 1; + * This field is used to open 120 MHz clock (div4 of SPLL) driven from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_120M_CLK_EN (BIT(2)) +#define PCR_PLL_120M_CLK_EN_M (PCR_PLL_120M_CLK_EN_V << PCR_PLL_120M_CLK_EN_S) +#define PCR_PLL_120M_CLK_EN_V 0x00000001U +#define PCR_PLL_120M_CLK_EN_S 2 +/** PCR_PLL_80M_CLK_EN : R/W; bitpos: [3]; default: 1; + * This field is used to open 80 MHz clock (div6 of SPLL) driven from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_80M_CLK_EN (BIT(3)) +#define PCR_PLL_80M_CLK_EN_M (PCR_PLL_80M_CLK_EN_V << PCR_PLL_80M_CLK_EN_S) +#define PCR_PLL_80M_CLK_EN_V 0x00000001U +#define PCR_PLL_80M_CLK_EN_S 3 +/** PCR_PLL_48M_CLK_EN : R/W; bitpos: [4]; default: 1; + * This field is used to open 48 MHz clock (div10 of SPLL) driven from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_48M_CLK_EN (BIT(4)) +#define PCR_PLL_48M_CLK_EN_M (PCR_PLL_48M_CLK_EN_V << PCR_PLL_48M_CLK_EN_S) +#define PCR_PLL_48M_CLK_EN_V 0x00000001U +#define PCR_PLL_48M_CLK_EN_S 4 +/** PCR_PLL_40M_CLK_EN : R/W; bitpos: [5]; default: 1; + * This field is used to open 40 MHz clock (div12 of SPLL) driven from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_40M_CLK_EN (BIT(5)) +#define PCR_PLL_40M_CLK_EN_M (PCR_PLL_40M_CLK_EN_V << PCR_PLL_40M_CLK_EN_S) +#define PCR_PLL_40M_CLK_EN_V 0x00000001U +#define PCR_PLL_40M_CLK_EN_S 5 +/** PCR_PLL_20M_CLK_EN : R/W; bitpos: [6]; default: 1; + * This field is used to open 20 MHz clock (div24 of SPLL) driven from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_20M_CLK_EN (BIT(6)) +#define PCR_PLL_20M_CLK_EN_M (PCR_PLL_20M_CLK_EN_V << PCR_PLL_20M_CLK_EN_S) +#define PCR_PLL_20M_CLK_EN_V 0x00000001U +#define PCR_PLL_20M_CLK_EN_S 6 + +/** PCR_CTRL_CLK_OUT_EN_REG register + * CLK_OUT_EN configuration register + */ +#define PCR_CTRL_CLK_OUT_EN_REG (DR_REG_PCR_BASE + 0x12c) +/** PCR_CLK20_OEN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable 20m clock + */ +#define PCR_CLK20_OEN (BIT(0)) +#define PCR_CLK20_OEN_M (PCR_CLK20_OEN_V << PCR_CLK20_OEN_S) +#define PCR_CLK20_OEN_V 0x00000001U +#define PCR_CLK20_OEN_S 0 +/** PCR_CLK22_OEN : R/W; bitpos: [1]; default: 1; + * Set 1 to enable 22m clock + */ +#define PCR_CLK22_OEN (BIT(1)) +#define PCR_CLK22_OEN_M (PCR_CLK22_OEN_V << PCR_CLK22_OEN_S) +#define PCR_CLK22_OEN_V 0x00000001U +#define PCR_CLK22_OEN_S 1 +/** PCR_CLK44_OEN : R/W; bitpos: [2]; default: 1; + * Set 1 to enable 44m clock + */ +#define PCR_CLK44_OEN (BIT(2)) +#define PCR_CLK44_OEN_M (PCR_CLK44_OEN_V << PCR_CLK44_OEN_S) +#define PCR_CLK44_OEN_V 0x00000001U +#define PCR_CLK44_OEN_S 2 +/** PCR_CLK_BB_OEN : R/W; bitpos: [3]; default: 1; + * Set 1 to enable bb clock + */ +#define PCR_CLK_BB_OEN (BIT(3)) +#define PCR_CLK_BB_OEN_M (PCR_CLK_BB_OEN_V << PCR_CLK_BB_OEN_S) +#define PCR_CLK_BB_OEN_V 0x00000001U +#define PCR_CLK_BB_OEN_S 3 +/** PCR_CLK80_OEN : R/W; bitpos: [4]; default: 1; + * Set 1 to enable 80m clock + */ +#define PCR_CLK80_OEN (BIT(4)) +#define PCR_CLK80_OEN_M (PCR_CLK80_OEN_V << PCR_CLK80_OEN_S) +#define PCR_CLK80_OEN_V 0x00000001U +#define PCR_CLK80_OEN_S 4 +/** PCR_CLK160_OEN : R/W; bitpos: [5]; default: 1; + * Set 1 to enable 160m clock + */ +#define PCR_CLK160_OEN (BIT(5)) +#define PCR_CLK160_OEN_M (PCR_CLK160_OEN_V << PCR_CLK160_OEN_S) +#define PCR_CLK160_OEN_V 0x00000001U +#define PCR_CLK160_OEN_S 5 +/** PCR_CLK_320M_OEN : R/W; bitpos: [6]; default: 1; + * Set 1 to enable 320m clock + */ +#define PCR_CLK_320M_OEN (BIT(6)) +#define PCR_CLK_320M_OEN_M (PCR_CLK_320M_OEN_V << PCR_CLK_320M_OEN_S) +#define PCR_CLK_320M_OEN_V 0x00000001U +#define PCR_CLK_320M_OEN_S 6 +/** PCR_CLK_ADC_INF_OEN : R/W; bitpos: [7]; default: 1; + * Reserved + */ +#define PCR_CLK_ADC_INF_OEN (BIT(7)) +#define PCR_CLK_ADC_INF_OEN_M (PCR_CLK_ADC_INF_OEN_V << PCR_CLK_ADC_INF_OEN_S) +#define PCR_CLK_ADC_INF_OEN_V 0x00000001U +#define PCR_CLK_ADC_INF_OEN_S 7 +/** PCR_CLK_DAC_CPU_OEN : R/W; bitpos: [8]; default: 1; + * Reserved + */ +#define PCR_CLK_DAC_CPU_OEN (BIT(8)) +#define PCR_CLK_DAC_CPU_OEN_M (PCR_CLK_DAC_CPU_OEN_V << PCR_CLK_DAC_CPU_OEN_S) +#define PCR_CLK_DAC_CPU_OEN_V 0x00000001U +#define PCR_CLK_DAC_CPU_OEN_S 8 +/** PCR_CLK40X_BB_OEN : R/W; bitpos: [9]; default: 1; + * Set 1 to enable 40x_bb clock + */ +#define PCR_CLK40X_BB_OEN (BIT(9)) +#define PCR_CLK40X_BB_OEN_M (PCR_CLK40X_BB_OEN_V << PCR_CLK40X_BB_OEN_S) +#define PCR_CLK40X_BB_OEN_V 0x00000001U +#define PCR_CLK40X_BB_OEN_S 9 +/** PCR_CLK_XTAL_OEN : R/W; bitpos: [10]; default: 1; + * Set 1 to enable xtal clock + */ +#define PCR_CLK_XTAL_OEN (BIT(10)) +#define PCR_CLK_XTAL_OEN_M (PCR_CLK_XTAL_OEN_V << PCR_CLK_XTAL_OEN_S) +#define PCR_CLK_XTAL_OEN_V 0x00000001U +#define PCR_CLK_XTAL_OEN_S 10 + +/** PCR_CTRL_TICK_CONF_REG register + * TICK configuration register + */ +#define PCR_CTRL_TICK_CONF_REG (DR_REG_PCR_BASE + 0x130) +/** PCR_XTAL_TICK_NUM : R/W; bitpos: [7:0]; default: 39; + * ******* Description *********** + */ +#define PCR_XTAL_TICK_NUM 0x000000FFU +#define PCR_XTAL_TICK_NUM_M (PCR_XTAL_TICK_NUM_V << PCR_XTAL_TICK_NUM_S) +#define PCR_XTAL_TICK_NUM_V 0x000000FFU +#define PCR_XTAL_TICK_NUM_S 0 +/** PCR_FOSC_TICK_NUM : R/W; bitpos: [15:8]; default: 7; + * ******* Description *********** + */ +#define PCR_FOSC_TICK_NUM 0x000000FFU +#define PCR_FOSC_TICK_NUM_M (PCR_FOSC_TICK_NUM_V << PCR_FOSC_TICK_NUM_S) +#define PCR_FOSC_TICK_NUM_V 0x000000FFU +#define PCR_FOSC_TICK_NUM_S 8 +/** PCR_TICK_ENABLE : R/W; bitpos: [16]; default: 1; + * ******* Description *********** + */ +#define PCR_TICK_ENABLE (BIT(16)) +#define PCR_TICK_ENABLE_M (PCR_TICK_ENABLE_V << PCR_TICK_ENABLE_S) +#define PCR_TICK_ENABLE_V 0x00000001U +#define PCR_TICK_ENABLE_S 16 +/** PCR_RST_TICK_CNT : R/W; bitpos: [17]; default: 0; + * ******* Description *********** + */ +#define PCR_RST_TICK_CNT (BIT(17)) +#define PCR_RST_TICK_CNT_M (PCR_RST_TICK_CNT_V << PCR_RST_TICK_CNT_S) +#define PCR_RST_TICK_CNT_V 0x00000001U +#define PCR_RST_TICK_CNT_S 17 + +/** PCR_CTRL_32K_CONF_REG register + * 32KHz clock configuration register + */ +#define PCR_CTRL_32K_CONF_REG (DR_REG_PCR_BASE + 0x134) +/** PCR_32K_SEL : R/W; bitpos: [1:0]; default: 0; + * This field indicates which one 32KHz clock will be used by MODEM_SYSTEM and + * timergroup. 0: OSC32K(default), 1: XTAL32K, 2/3: 32KHz from pad GPIO0. + */ +#define PCR_32K_SEL 0x00000003U +#define PCR_32K_SEL_M (PCR_32K_SEL_V << PCR_32K_SEL_S) +#define PCR_32K_SEL_V 0x00000003U +#define PCR_32K_SEL_S 0 + +/** PCR_SRAM_POWER_CONF_REG register + * HP SRAM/ROM configuration register + */ +#define PCR_SRAM_POWER_CONF_REG (DR_REG_PCR_BASE + 0x138) +/** PCR_SRAM_FORCE_PU : R/W; bitpos: [3:0]; default: 15; + * Set this bit to force power up SRAM + */ +#define PCR_SRAM_FORCE_PU 0x0000000FU +#define PCR_SRAM_FORCE_PU_M (PCR_SRAM_FORCE_PU_V << PCR_SRAM_FORCE_PU_S) +#define PCR_SRAM_FORCE_PU_V 0x0000000FU +#define PCR_SRAM_FORCE_PU_S 0 +/** PCR_SRAM_FORCE_PD : R/W; bitpos: [7:4]; default: 0; + * Set this bit to force power down SRAM. + */ +#define PCR_SRAM_FORCE_PD 0x0000000FU +#define PCR_SRAM_FORCE_PD_M (PCR_SRAM_FORCE_PD_V << PCR_SRAM_FORCE_PD_S) +#define PCR_SRAM_FORCE_PD_V 0x0000000FU +#define PCR_SRAM_FORCE_PD_S 4 +/** PCR_SRAM_CLKGATE_FORCE_ON : R/W; bitpos: [11:8]; default: 0; + * 1: Force to open the clock and bypass the gate-clock when accessing the SRAM. 0: A + * gate-clock will be used when accessing the SRAM. + */ +#define PCR_SRAM_CLKGATE_FORCE_ON 0x0000000FU +#define PCR_SRAM_CLKGATE_FORCE_ON_M (PCR_SRAM_CLKGATE_FORCE_ON_V << PCR_SRAM_CLKGATE_FORCE_ON_S) +#define PCR_SRAM_CLKGATE_FORCE_ON_V 0x0000000FU +#define PCR_SRAM_CLKGATE_FORCE_ON_S 8 +/** PCR_ROM_FORCE_PU : R/W; bitpos: [14:12]; default: 7; + * Set this bit to force power up ROM + */ +#define PCR_ROM_FORCE_PU 0x00000007U +#define PCR_ROM_FORCE_PU_M (PCR_ROM_FORCE_PU_V << PCR_ROM_FORCE_PU_S) +#define PCR_ROM_FORCE_PU_V 0x00000007U +#define PCR_ROM_FORCE_PU_S 12 +/** PCR_ROM_FORCE_PD : R/W; bitpos: [17:15]; default: 0; + * Set this bit to force power down ROM. + */ +#define PCR_ROM_FORCE_PD 0x00000007U +#define PCR_ROM_FORCE_PD_M (PCR_ROM_FORCE_PD_V << PCR_ROM_FORCE_PD_S) +#define PCR_ROM_FORCE_PD_V 0x00000007U +#define PCR_ROM_FORCE_PD_S 15 +/** PCR_ROM_CLKGATE_FORCE_ON : R/W; bitpos: [20:18]; default: 0; + * 1: Force to open the clock and bypass the gate-clock when accessing the ROM. 0: A + * gate-clock will be used when accessing the ROM. + */ +#define PCR_ROM_CLKGATE_FORCE_ON 0x00000007U +#define PCR_ROM_CLKGATE_FORCE_ON_M (PCR_ROM_CLKGATE_FORCE_ON_V << PCR_ROM_CLKGATE_FORCE_ON_S) +#define PCR_ROM_CLKGATE_FORCE_ON_V 0x00000007U +#define PCR_ROM_CLKGATE_FORCE_ON_S 18 + +/** PCR_RESET_EVENT_BYPASS_REG register + * reset event bypass backdoor configuration register + */ +#define PCR_RESET_EVENT_BYPASS_REG (DR_REG_PCR_BASE + 0xff0) +/** PCR_RESET_EVENT_BYPASS_APM : R/W; bitpos: [0]; default: 0; + * This field is used to control reset event relationship for + * tee_reg/apm_reg/hp_system_reg. 1: tee_reg/apm_reg/hp_system_reg will only be reset + * by power-reset. some reset event will be bypass. 0: tee_reg/apm_reg/hp_system_reg + * will not only be reset by power-reset, but also some reset event. + */ +#define PCR_RESET_EVENT_BYPASS_APM (BIT(0)) +#define PCR_RESET_EVENT_BYPASS_APM_M (PCR_RESET_EVENT_BYPASS_APM_V << PCR_RESET_EVENT_BYPASS_APM_S) +#define PCR_RESET_EVENT_BYPASS_APM_V 0x00000001U +#define PCR_RESET_EVENT_BYPASS_APM_S 0 +/** PCR_RESET_EVENT_BYPASS : R/W; bitpos: [1]; default: 1; + * This field is used to control reset event relationship for system-bus. 1: system + * bus (including arbiter/router) will only be reset by power-reset. some reset event + * will be bypass. 0: system bus (including arbiter/router) will not only be reset by + * power-reset, but also some reset event. + */ +#define PCR_RESET_EVENT_BYPASS (BIT(1)) +#define PCR_RESET_EVENT_BYPASS_M (PCR_RESET_EVENT_BYPASS_V << PCR_RESET_EVENT_BYPASS_S) +#define PCR_RESET_EVENT_BYPASS_V 0x00000001U +#define PCR_RESET_EVENT_BYPASS_S 1 + +/** PCR_FPGA_DEBUG_REG register + * fpga debug register + */ +#define PCR_FPGA_DEBUG_REG (DR_REG_PCR_BASE + 0xff4) +/** PCR_FPGA_DEBUG : R/W; bitpos: [31:0]; default: 4294967295; + * Only used in fpga debug. + */ +#define PCR_FPGA_DEBUG 0xFFFFFFFFU +#define PCR_FPGA_DEBUG_M (PCR_FPGA_DEBUG_V << PCR_FPGA_DEBUG_S) +#define PCR_FPGA_DEBUG_V 0xFFFFFFFFU +#define PCR_FPGA_DEBUG_S 0 + +/** PCR_CLOCK_GATE_REG register + * PCR clock gating configure register + */ +#define PCR_CLOCK_GATE_REG (DR_REG_PCR_BASE + 0xff8) +/** PCR_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set this bit as 1 to force on clock gating. + */ +#define PCR_CLK_EN (BIT(0)) +#define PCR_CLK_EN_M (PCR_CLK_EN_V << PCR_CLK_EN_S) +#define PCR_CLK_EN_V 0x00000001U +#define PCR_CLK_EN_S 0 + +/** PCR_DATE_REG register + * Date register. + */ +#define PCR_DATE_REG (DR_REG_PCR_BASE + 0xffc) +/** PCR_DATE : R/W; bitpos: [27:0]; default: 35676496; + * PCR version information. + */ +#define PCR_DATE 0x0FFFFFFFU +#define PCR_DATE_M (PCR_DATE_V << PCR_DATE_S) +#define PCR_DATE_V 0x0FFFFFFFU +#define PCR_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/src/target/esp32c6/ld/esp32c6.rom.api.ld b/src/target/esp32c6/ld/esp32c6.rom.api.ld index 2cab47c..46a2061 100644 --- a/src/target/esp32c6/ld/esp32c6.rom.api.ld +++ b/src/target/esp32c6/ld/esp32c6.rom.api.ld @@ -28,9 +28,9 @@ PROVIDE ( esp_rom_uart_putc = ets_write_char_uart ); PROVIDE ( esp_rom_uart_attach = uartAttach ); PROVIDE ( esp_rom_uart_init = Uart_Init ); PROVIDE ( esp_rom_uart_div_modify = uart_div_modify ); -PROVIDE ( esp_rom_get_apb_freq = ets_get_apb_freq ); PROVIDE ( esp_rom_get_cpu_freq = ets_clk_get_cpu_freq ); PROVIDE ( esp_rom_get_uart_device = GetUartDevice ); +PROVIDE ( esp_rom_get_xtal_freq = ets_clk_get_xtal_freq ); PROVIDE ( esp_rom_output_flush_tx = uart_tx_flush ); PROVIDE ( esp_rom_output_tx_one_char = uart_tx_one_char ); diff --git a/src/target/esp32c6/src/clock.c b/src/target/esp32c6/src/clock.c new file mode 100644 index 0000000..72d26d1 --- /dev/null +++ b/src/target/esp32c6/src/clock.c @@ -0,0 +1,35 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 OR MIT + */ + +#include +#include +#include +#include +#include +#include + +#define MHZ 1000000 + +extern uint32_t esp_rom_get_cpu_freq(void); +extern void esp_rom_set_cpu_ticks_per_us(uint32_t ticks_per_us); + +static uint32_t s_cpu_freq = 0; + +void stub_target_clock_init(void) +{ + REG_SET_FIELD(PCR_SYSCLK_CONF_REG, PCR_SOC_CLK_SEL, 1); + + s_cpu_freq = 160 * MHZ; + esp_rom_set_cpu_ticks_per_us(s_cpu_freq / MHZ); +} + +uint32_t stub_target_get_cpu_freq(void) +{ + if (s_cpu_freq == 0) { + return esp_rom_get_cpu_freq(); + } + return s_cpu_freq; +} diff --git a/src/target/esp32c61/CMakeLists.txt b/src/target/esp32c61/CMakeLists.txt index 00af8a9..b9c651d 100644 --- a/src/target/esp32c61/CMakeLists.txt +++ b/src/target/esp32c61/CMakeLists.txt @@ -1,6 +1,7 @@ set(srcs src/uart.c src/usb_serial_jtag.c + src/clock.c ) add_library(${ESP_TARGET_LIB} STATIC ${srcs}) diff --git a/src/target/esp32c61/include/soc/pcr_reg.h b/src/target/esp32c61/include/soc/pcr_reg.h new file mode 100644 index 0000000..57fffba --- /dev/null +++ b/src/target/esp32c61/include/soc/pcr_reg.h @@ -0,0 +1,2198 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 OR MIT + */ +#pragma once + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** PCR_UART0_CONF_REG register + * UART0 configuration register + */ +#define PCR_UART0_CONF_REG (DR_REG_PCR_BASE + 0x0) +/** PCR_UART0_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable uart0 apb clock + */ +#define PCR_UART0_CLK_EN (BIT(0)) +#define PCR_UART0_CLK_EN_M (PCR_UART0_CLK_EN_V << PCR_UART0_CLK_EN_S) +#define PCR_UART0_CLK_EN_V 0x00000001U +#define PCR_UART0_CLK_EN_S 0 +/** PCR_UART0_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset uart0 module + */ +#define PCR_UART0_RST_EN (BIT(1)) +#define PCR_UART0_RST_EN_M (PCR_UART0_RST_EN_V << PCR_UART0_RST_EN_S) +#define PCR_UART0_RST_EN_V 0x00000001U +#define PCR_UART0_RST_EN_S 1 +/** PCR_UART0_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset uart0 module + */ +#define PCR_UART0_READY (BIT(2)) +#define PCR_UART0_READY_M (PCR_UART0_READY_V << PCR_UART0_READY_S) +#define PCR_UART0_READY_V 0x00000001U +#define PCR_UART0_READY_S 2 + +/** PCR_UART0_SCLK_CONF_REG register + * UART0_SCLK configuration register + */ +#define PCR_UART0_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x4) +/** PCR_UART0_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the uart0 function clock. + */ +#define PCR_UART0_SCLK_DIV_A 0x0000003FU +#define PCR_UART0_SCLK_DIV_A_M (PCR_UART0_SCLK_DIV_A_V << PCR_UART0_SCLK_DIV_A_S) +#define PCR_UART0_SCLK_DIV_A_V 0x0000003FU +#define PCR_UART0_SCLK_DIV_A_S 0 +/** PCR_UART0_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the uart0 function clock. + */ +#define PCR_UART0_SCLK_DIV_B 0x0000003FU +#define PCR_UART0_SCLK_DIV_B_M (PCR_UART0_SCLK_DIV_B_V << PCR_UART0_SCLK_DIV_B_S) +#define PCR_UART0_SCLK_DIV_B_V 0x0000003FU +#define PCR_UART0_SCLK_DIV_B_S 6 +/** PCR_UART0_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the uart0 function clock. + */ +#define PCR_UART0_SCLK_DIV_NUM 0x000000FFU +#define PCR_UART0_SCLK_DIV_NUM_M (PCR_UART0_SCLK_DIV_NUM_V << PCR_UART0_SCLK_DIV_NUM_S) +#define PCR_UART0_SCLK_DIV_NUM_V 0x000000FFU +#define PCR_UART0_SCLK_DIV_NUM_S 12 +/** PCR_UART0_SCLK_SEL : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of UART0. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK + */ +#define PCR_UART0_SCLK_SEL 0x00000003U +#define PCR_UART0_SCLK_SEL_M (PCR_UART0_SCLK_SEL_V << PCR_UART0_SCLK_SEL_S) +#define PCR_UART0_SCLK_SEL_V 0x00000003U +#define PCR_UART0_SCLK_SEL_S 20 +/** PCR_UART0_SCLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable uart0 function clock + */ +#define PCR_UART0_SCLK_EN (BIT(22)) +#define PCR_UART0_SCLK_EN_M (PCR_UART0_SCLK_EN_V << PCR_UART0_SCLK_EN_S) +#define PCR_UART0_SCLK_EN_V 0x00000001U +#define PCR_UART0_SCLK_EN_S 22 + +/** PCR_UART0_PD_CTRL_REG register + * UART0 power control register + */ +#define PCR_UART0_PD_CTRL_REG (DR_REG_PCR_BASE + 0x8) +/** PCR_UART0_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1; + * Set this bit to force power down UART0 memory. + */ +#define PCR_UART0_MEM_FORCE_PU (BIT(1)) +#define PCR_UART0_MEM_FORCE_PU_M (PCR_UART0_MEM_FORCE_PU_V << PCR_UART0_MEM_FORCE_PU_S) +#define PCR_UART0_MEM_FORCE_PU_V 0x00000001U +#define PCR_UART0_MEM_FORCE_PU_S 1 +/** PCR_UART0_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; + * Set this bit to force power up UART0 memory. + */ +#define PCR_UART0_MEM_FORCE_PD (BIT(2)) +#define PCR_UART0_MEM_FORCE_PD_M (PCR_UART0_MEM_FORCE_PD_V << PCR_UART0_MEM_FORCE_PD_S) +#define PCR_UART0_MEM_FORCE_PD_V 0x00000001U +#define PCR_UART0_MEM_FORCE_PD_S 2 + +/** PCR_UART1_CONF_REG register + * UART1 configuration register + */ +#define PCR_UART1_CONF_REG (DR_REG_PCR_BASE + 0xc) +/** PCR_UART1_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable uart1 apb clock + */ +#define PCR_UART1_CLK_EN (BIT(0)) +#define PCR_UART1_CLK_EN_M (PCR_UART1_CLK_EN_V << PCR_UART1_CLK_EN_S) +#define PCR_UART1_CLK_EN_V 0x00000001U +#define PCR_UART1_CLK_EN_S 0 +/** PCR_UART1_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset uart1 module + */ +#define PCR_UART1_RST_EN (BIT(1)) +#define PCR_UART1_RST_EN_M (PCR_UART1_RST_EN_V << PCR_UART1_RST_EN_S) +#define PCR_UART1_RST_EN_V 0x00000001U +#define PCR_UART1_RST_EN_S 1 +/** PCR_UART1_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset uart1 module + */ +#define PCR_UART1_READY (BIT(2)) +#define PCR_UART1_READY_M (PCR_UART1_READY_V << PCR_UART1_READY_S) +#define PCR_UART1_READY_V 0x00000001U +#define PCR_UART1_READY_S 2 + +/** PCR_UART1_SCLK_CONF_REG register + * UART1_SCLK configuration register + */ +#define PCR_UART1_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x10) +/** PCR_UART1_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the uart1 function clock. + */ +#define PCR_UART1_SCLK_DIV_A 0x0000003FU +#define PCR_UART1_SCLK_DIV_A_M (PCR_UART1_SCLK_DIV_A_V << PCR_UART1_SCLK_DIV_A_S) +#define PCR_UART1_SCLK_DIV_A_V 0x0000003FU +#define PCR_UART1_SCLK_DIV_A_S 0 +/** PCR_UART1_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the uart1 function clock. + */ +#define PCR_UART1_SCLK_DIV_B 0x0000003FU +#define PCR_UART1_SCLK_DIV_B_M (PCR_UART1_SCLK_DIV_B_V << PCR_UART1_SCLK_DIV_B_S) +#define PCR_UART1_SCLK_DIV_B_V 0x0000003FU +#define PCR_UART1_SCLK_DIV_B_S 6 +/** PCR_UART1_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the uart1 function clock. + */ +#define PCR_UART1_SCLK_DIV_NUM 0x000000FFU +#define PCR_UART1_SCLK_DIV_NUM_M (PCR_UART1_SCLK_DIV_NUM_V << PCR_UART1_SCLK_DIV_NUM_S) +#define PCR_UART1_SCLK_DIV_NUM_V 0x000000FFU +#define PCR_UART1_SCLK_DIV_NUM_S 12 +/** PCR_UART1_SCLK_SEL : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of UART1. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK + */ +#define PCR_UART1_SCLK_SEL 0x00000003U +#define PCR_UART1_SCLK_SEL_M (PCR_UART1_SCLK_SEL_V << PCR_UART1_SCLK_SEL_S) +#define PCR_UART1_SCLK_SEL_V 0x00000003U +#define PCR_UART1_SCLK_SEL_S 20 +/** PCR_UART1_SCLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable uart1 function clock + */ +#define PCR_UART1_SCLK_EN (BIT(22)) +#define PCR_UART1_SCLK_EN_M (PCR_UART1_SCLK_EN_V << PCR_UART1_SCLK_EN_S) +#define PCR_UART1_SCLK_EN_V 0x00000001U +#define PCR_UART1_SCLK_EN_S 22 + +/** PCR_UART1_PD_CTRL_REG register + * UART1 power control register + */ +#define PCR_UART1_PD_CTRL_REG (DR_REG_PCR_BASE + 0x14) +/** PCR_UART1_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1; + * Set this bit to force power down UART1 memory. + */ +#define PCR_UART1_MEM_FORCE_PU (BIT(1)) +#define PCR_UART1_MEM_FORCE_PU_M (PCR_UART1_MEM_FORCE_PU_V << PCR_UART1_MEM_FORCE_PU_S) +#define PCR_UART1_MEM_FORCE_PU_V 0x00000001U +#define PCR_UART1_MEM_FORCE_PU_S 1 +/** PCR_UART1_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; + * Set this bit to force power up UART1 memory. + */ +#define PCR_UART1_MEM_FORCE_PD (BIT(2)) +#define PCR_UART1_MEM_FORCE_PD_M (PCR_UART1_MEM_FORCE_PD_V << PCR_UART1_MEM_FORCE_PD_S) +#define PCR_UART1_MEM_FORCE_PD_V 0x00000001U +#define PCR_UART1_MEM_FORCE_PD_S 2 + +/** PCR_UART2_CONF_REG register + * UART2 configuration register + */ +#define PCR_UART2_CONF_REG (DR_REG_PCR_BASE + 0x18) +/** PCR_UART2_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable uart2 apb clock + */ +#define PCR_UART2_CLK_EN (BIT(0)) +#define PCR_UART2_CLK_EN_M (PCR_UART2_CLK_EN_V << PCR_UART2_CLK_EN_S) +#define PCR_UART2_CLK_EN_V 0x00000001U +#define PCR_UART2_CLK_EN_S 0 +/** PCR_UART2_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset uart2 module + */ +#define PCR_UART2_RST_EN (BIT(1)) +#define PCR_UART2_RST_EN_M (PCR_UART2_RST_EN_V << PCR_UART2_RST_EN_S) +#define PCR_UART2_RST_EN_V 0x00000001U +#define PCR_UART2_RST_EN_S 1 +/** PCR_UART2_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset uart2 module + */ +#define PCR_UART2_READY (BIT(2)) +#define PCR_UART2_READY_M (PCR_UART2_READY_V << PCR_UART2_READY_S) +#define PCR_UART2_READY_V 0x00000001U +#define PCR_UART2_READY_S 2 + +/** PCR_UART2_SCLK_CONF_REG register + * UART2_SCLK configuration register + */ +#define PCR_UART2_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x1c) +/** PCR_UART2_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the uart2 function clock. + */ +#define PCR_UART2_SCLK_DIV_A 0x0000003FU +#define PCR_UART2_SCLK_DIV_A_M (PCR_UART2_SCLK_DIV_A_V << PCR_UART2_SCLK_DIV_A_S) +#define PCR_UART2_SCLK_DIV_A_V 0x0000003FU +#define PCR_UART2_SCLK_DIV_A_S 0 +/** PCR_UART2_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the uart2 function clock. + */ +#define PCR_UART2_SCLK_DIV_B 0x0000003FU +#define PCR_UART2_SCLK_DIV_B_M (PCR_UART2_SCLK_DIV_B_V << PCR_UART2_SCLK_DIV_B_S) +#define PCR_UART2_SCLK_DIV_B_V 0x0000003FU +#define PCR_UART2_SCLK_DIV_B_S 6 +/** PCR_UART2_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the uart2 function clock. + */ +#define PCR_UART2_SCLK_DIV_NUM 0x000000FFU +#define PCR_UART2_SCLK_DIV_NUM_M (PCR_UART2_SCLK_DIV_NUM_V << PCR_UART2_SCLK_DIV_NUM_S) +#define PCR_UART2_SCLK_DIV_NUM_V 0x000000FFU +#define PCR_UART2_SCLK_DIV_NUM_S 12 +/** PCR_UART2_SCLK_SEL : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of UART2. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK + */ +#define PCR_UART2_SCLK_SEL 0x00000003U +#define PCR_UART2_SCLK_SEL_M (PCR_UART2_SCLK_SEL_V << PCR_UART2_SCLK_SEL_S) +#define PCR_UART2_SCLK_SEL_V 0x00000003U +#define PCR_UART2_SCLK_SEL_S 20 +/** PCR_UART2_SCLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable uart2 function clock + */ +#define PCR_UART2_SCLK_EN (BIT(22)) +#define PCR_UART2_SCLK_EN_M (PCR_UART2_SCLK_EN_V << PCR_UART2_SCLK_EN_S) +#define PCR_UART2_SCLK_EN_V 0x00000001U +#define PCR_UART2_SCLK_EN_S 22 + +/** PCR_UART2_PD_CTRL_REG register + * UART2 power control register + */ +#define PCR_UART2_PD_CTRL_REG (DR_REG_PCR_BASE + 0x20) +/** PCR_UART2_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1; + * Set this bit to force power down UART2 memory. + */ +#define PCR_UART2_MEM_FORCE_PU (BIT(1)) +#define PCR_UART2_MEM_FORCE_PU_M (PCR_UART2_MEM_FORCE_PU_V << PCR_UART2_MEM_FORCE_PU_S) +#define PCR_UART2_MEM_FORCE_PU_V 0x00000001U +#define PCR_UART2_MEM_FORCE_PU_S 1 +/** PCR_UART2_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; + * Set this bit to force power up UART2 memory. + */ +#define PCR_UART2_MEM_FORCE_PD (BIT(2)) +#define PCR_UART2_MEM_FORCE_PD_M (PCR_UART2_MEM_FORCE_PD_V << PCR_UART2_MEM_FORCE_PD_S) +#define PCR_UART2_MEM_FORCE_PD_V 0x00000001U +#define PCR_UART2_MEM_FORCE_PD_S 2 + +/** PCR_MSPI_CONF_REG register + * MSPI configuration register + */ +#define PCR_MSPI_CONF_REG (DR_REG_PCR_BASE + 0x24) +/** PCR_MSPI_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable mspi apb clock and mspi pll clock + */ +#define PCR_MSPI_CLK_EN (BIT(0)) +#define PCR_MSPI_CLK_EN_M (PCR_MSPI_CLK_EN_V << PCR_MSPI_CLK_EN_S) +#define PCR_MSPI_CLK_EN_V 0x00000001U +#define PCR_MSPI_CLK_EN_S 0 +/** PCR_MSPI_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset mspi module + */ +#define PCR_MSPI_RST_EN (BIT(1)) +#define PCR_MSPI_RST_EN_M (PCR_MSPI_RST_EN_V << PCR_MSPI_RST_EN_S) +#define PCR_MSPI_RST_EN_V 0x00000001U +#define PCR_MSPI_RST_EN_S 1 +/** PCR_MSPI_PLL_CLK_EN : R/W; bitpos: [2]; default: 1; + * Set 1 to enable mspi pll clock + */ +#define PCR_MSPI_PLL_CLK_EN (BIT(2)) +#define PCR_MSPI_PLL_CLK_EN_M (PCR_MSPI_PLL_CLK_EN_V << PCR_MSPI_PLL_CLK_EN_S) +#define PCR_MSPI_PLL_CLK_EN_V 0x00000001U +#define PCR_MSPI_PLL_CLK_EN_S 2 +/** PCR_MSPI_READY : RO; bitpos: [3]; default: 1; + * Query this field after reset mspi module + */ +#define PCR_MSPI_READY (BIT(3)) +#define PCR_MSPI_READY_M (PCR_MSPI_READY_V << PCR_MSPI_READY_S) +#define PCR_MSPI_READY_V 0x00000001U +#define PCR_MSPI_READY_S 3 + +/** PCR_MSPI_CLK_CONF_REG register + * MSPI_CLK configuration register + */ +#define PCR_MSPI_CLK_CONF_REG (DR_REG_PCR_BASE + 0x28) +/** PCR_MSPI_FAST_DIV_NUM : R/W; bitpos: [7:0]; default: 0; + * Set as one within (0,1,2) to generate div1(default)/div2/div4 of low-speed + * clock-source to drive clk_mspi_fast. Only available when the clck-source is a + * low-speed clock-source such as XTAL/FOSC. + */ +#define PCR_MSPI_FAST_DIV_NUM 0x000000FFU +#define PCR_MSPI_FAST_DIV_NUM_M (PCR_MSPI_FAST_DIV_NUM_V << PCR_MSPI_FAST_DIV_NUM_S) +#define PCR_MSPI_FAST_DIV_NUM_V 0x000000FFU +#define PCR_MSPI_FAST_DIV_NUM_S 0 +/** PCR_MSPI_FUNC_CLK_SEL : R/W; bitpos: [9:8]; default: 0; + * Configures the clock source for MSPI. + * 0(default): XTAL_CLK + * 1 RC_FAST_CLK + * 2: PLL_F480M_CLK + */ +#define PCR_MSPI_FUNC_CLK_SEL 0x00000003U +#define PCR_MSPI_FUNC_CLK_SEL_M (PCR_MSPI_FUNC_CLK_SEL_V << PCR_MSPI_FUNC_CLK_SEL_S) +#define PCR_MSPI_FUNC_CLK_SEL_V 0x00000003U +#define PCR_MSPI_FUNC_CLK_SEL_S 8 +/** PCR_MSPI_FUNC_CLK_EN : R/W; bitpos: [10]; default: 1; + * Set 1 to enable mspi func clock + */ +#define PCR_MSPI_FUNC_CLK_EN (BIT(10)) +#define PCR_MSPI_FUNC_CLK_EN_M (PCR_MSPI_FUNC_CLK_EN_V << PCR_MSPI_FUNC_CLK_EN_S) +#define PCR_MSPI_FUNC_CLK_EN_V 0x00000001U +#define PCR_MSPI_FUNC_CLK_EN_S 10 +/** PCR_MSPI_AXI_RST_EN : R/W; bitpos: [11]; default: 0; + * Set 1 to reset axi_clock domain of mspi module + */ +#define PCR_MSPI_AXI_RST_EN (BIT(11)) +#define PCR_MSPI_AXI_RST_EN_M (PCR_MSPI_AXI_RST_EN_V << PCR_MSPI_AXI_RST_EN_S) +#define PCR_MSPI_AXI_RST_EN_V 0x00000001U +#define PCR_MSPI_AXI_RST_EN_S 11 + +/** PCR_I2C_CONF_REG register + * I2C configuration register + */ +#define PCR_I2C_CONF_REG (DR_REG_PCR_BASE + 0x2c) +/** PCR_I2C_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable i2c apb clock + */ +#define PCR_I2C_CLK_EN (BIT(0)) +#define PCR_I2C_CLK_EN_M (PCR_I2C_CLK_EN_V << PCR_I2C_CLK_EN_S) +#define PCR_I2C_CLK_EN_V 0x00000001U +#define PCR_I2C_CLK_EN_S 0 +/** PCR_I2C_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset i2c module + */ +#define PCR_I2C_RST_EN (BIT(1)) +#define PCR_I2C_RST_EN_M (PCR_I2C_RST_EN_V << PCR_I2C_RST_EN_S) +#define PCR_I2C_RST_EN_V 0x00000001U +#define PCR_I2C_RST_EN_S 1 + +/** PCR_I2C_SCLK_CONF_REG register + * I2C_SCLK configuration register + */ +#define PCR_I2C_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x30) +/** PCR_I2C_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the i2c function clock. + */ +#define PCR_I2C_SCLK_DIV_A 0x0000003FU +#define PCR_I2C_SCLK_DIV_A_M (PCR_I2C_SCLK_DIV_A_V << PCR_I2C_SCLK_DIV_A_S) +#define PCR_I2C_SCLK_DIV_A_V 0x0000003FU +#define PCR_I2C_SCLK_DIV_A_S 0 +/** PCR_I2C_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the i2c function clock. + */ +#define PCR_I2C_SCLK_DIV_B 0x0000003FU +#define PCR_I2C_SCLK_DIV_B_M (PCR_I2C_SCLK_DIV_B_V << PCR_I2C_SCLK_DIV_B_S) +#define PCR_I2C_SCLK_DIV_B_V 0x0000003FU +#define PCR_I2C_SCLK_DIV_B_S 6 +/** PCR_I2C_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the i2c function clock. + */ +#define PCR_I2C_SCLK_DIV_NUM 0x000000FFU +#define PCR_I2C_SCLK_DIV_NUM_M (PCR_I2C_SCLK_DIV_NUM_V << PCR_I2C_SCLK_DIV_NUM_S) +#define PCR_I2C_SCLK_DIV_NUM_V 0x000000FFU +#define PCR_I2C_SCLK_DIV_NUM_S 12 +/** PCR_I2C_SCLK_SEL : R/W; bitpos: [20]; default: 0; + * Configures the clock source of I2C. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + */ +#define PCR_I2C_SCLK_SEL (BIT(20)) +#define PCR_I2C_SCLK_SEL_M (PCR_I2C_SCLK_SEL_V << PCR_I2C_SCLK_SEL_S) +#define PCR_I2C_SCLK_SEL_V 0x00000001U +#define PCR_I2C_SCLK_SEL_S 20 +/** PCR_I2C_SCLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable i2c function clock + */ +#define PCR_I2C_SCLK_EN (BIT(22)) +#define PCR_I2C_SCLK_EN_M (PCR_I2C_SCLK_EN_V << PCR_I2C_SCLK_EN_S) +#define PCR_I2C_SCLK_EN_V 0x00000001U +#define PCR_I2C_SCLK_EN_S 22 + +/** PCR_LEDC_CONF_REG register + * LEDC configuration register + */ +#define PCR_LEDC_CONF_REG (DR_REG_PCR_BASE + 0x34) +/** PCR_LEDC_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable ledc apb clock + */ +#define PCR_LEDC_CLK_EN (BIT(0)) +#define PCR_LEDC_CLK_EN_M (PCR_LEDC_CLK_EN_V << PCR_LEDC_CLK_EN_S) +#define PCR_LEDC_CLK_EN_V 0x00000001U +#define PCR_LEDC_CLK_EN_S 0 +/** PCR_LEDC_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset ledc module + */ +#define PCR_LEDC_RST_EN (BIT(1)) +#define PCR_LEDC_RST_EN_M (PCR_LEDC_RST_EN_V << PCR_LEDC_RST_EN_S) +#define PCR_LEDC_RST_EN_V 0x00000001U +#define PCR_LEDC_RST_EN_S 1 +/** PCR_LEDC_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset ledc module + */ +#define PCR_LEDC_READY (BIT(2)) +#define PCR_LEDC_READY_M (PCR_LEDC_READY_V << PCR_LEDC_READY_S) +#define PCR_LEDC_READY_V 0x00000001U +#define PCR_LEDC_READY_S 2 + +/** PCR_LEDC_SCLK_CONF_REG register + * LEDC_SCLK configuration register + */ +#define PCR_LEDC_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x38) +/** PCR_LEDC_SCLK_SEL : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of LEDC. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK + */ +#define PCR_LEDC_SCLK_SEL 0x00000003U +#define PCR_LEDC_SCLK_SEL_M (PCR_LEDC_SCLK_SEL_V << PCR_LEDC_SCLK_SEL_S) +#define PCR_LEDC_SCLK_SEL_V 0x00000003U +#define PCR_LEDC_SCLK_SEL_S 20 +/** PCR_LEDC_SCLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable ledc function clock + */ +#define PCR_LEDC_SCLK_EN (BIT(22)) +#define PCR_LEDC_SCLK_EN_M (PCR_LEDC_SCLK_EN_V << PCR_LEDC_SCLK_EN_S) +#define PCR_LEDC_SCLK_EN_V 0x00000001U +#define PCR_LEDC_SCLK_EN_S 22 + +/** PCR_LEDC_PD_CTRL_REG register + * LEDC power control register + */ +#define PCR_LEDC_PD_CTRL_REG (DR_REG_PCR_BASE + 0x3c) +/** PCR_LEDC_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1; + * Set this bit to force power down LEDC memory. + */ +#define PCR_LEDC_MEM_FORCE_PU (BIT(1)) +#define PCR_LEDC_MEM_FORCE_PU_M (PCR_LEDC_MEM_FORCE_PU_V << PCR_LEDC_MEM_FORCE_PU_S) +#define PCR_LEDC_MEM_FORCE_PU_V 0x00000001U +#define PCR_LEDC_MEM_FORCE_PU_S 1 +/** PCR_LEDC_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; + * Set this bit to force power up LEDC memory. + */ +#define PCR_LEDC_MEM_FORCE_PD (BIT(2)) +#define PCR_LEDC_MEM_FORCE_PD_M (PCR_LEDC_MEM_FORCE_PD_V << PCR_LEDC_MEM_FORCE_PD_S) +#define PCR_LEDC_MEM_FORCE_PD_V 0x00000001U +#define PCR_LEDC_MEM_FORCE_PD_S 2 + +/** PCR_TIMERGROUP0_CONF_REG register + * TIMERGROUP0 configuration register + */ +#define PCR_TIMERGROUP0_CONF_REG (DR_REG_PCR_BASE + 0x40) +/** PCR_TG0_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable timer_group0 apb clock + */ +#define PCR_TG0_CLK_EN (BIT(0)) +#define PCR_TG0_CLK_EN_M (PCR_TG0_CLK_EN_V << PCR_TG0_CLK_EN_S) +#define PCR_TG0_CLK_EN_V 0x00000001U +#define PCR_TG0_CLK_EN_S 0 +/** PCR_TG0_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset timer_group0 module + */ +#define PCR_TG0_RST_EN (BIT(1)) +#define PCR_TG0_RST_EN_M (PCR_TG0_RST_EN_V << PCR_TG0_RST_EN_S) +#define PCR_TG0_RST_EN_V 0x00000001U +#define PCR_TG0_RST_EN_S 1 +/** PCR_TG0_WDT_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset timer_group0 wdt module + */ +#define PCR_TG0_WDT_READY (BIT(2)) +#define PCR_TG0_WDT_READY_M (PCR_TG0_WDT_READY_V << PCR_TG0_WDT_READY_S) +#define PCR_TG0_WDT_READY_V 0x00000001U +#define PCR_TG0_WDT_READY_S 2 +/** PCR_TG0_TIMER0_READY : RO; bitpos: [3]; default: 1; + * Query this field after reset timer_group0 timer0 module + */ +#define PCR_TG0_TIMER0_READY (BIT(3)) +#define PCR_TG0_TIMER0_READY_M (PCR_TG0_TIMER0_READY_V << PCR_TG0_TIMER0_READY_S) +#define PCR_TG0_TIMER0_READY_V 0x00000001U +#define PCR_TG0_TIMER0_READY_S 3 +/** PCR_TG0_TIMER1_READY : RO; bitpos: [4]; default: 1; + * reserved + */ +#define PCR_TG0_TIMER1_READY (BIT(4)) +#define PCR_TG0_TIMER1_READY_M (PCR_TG0_TIMER1_READY_V << PCR_TG0_TIMER1_READY_S) +#define PCR_TG0_TIMER1_READY_V 0x00000001U +#define PCR_TG0_TIMER1_READY_S 4 + +/** PCR_TIMERGROUP0_TIMER_CLK_CONF_REG register + * TIMERGROUP0_TIMER_CLK configuration register + */ +#define PCR_TIMERGROUP0_TIMER_CLK_CONF_REG (DR_REG_PCR_BASE + 0x44) +/** PCR_TG0_TIMER_CLK_SEL : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of general-purpose timers in Timer Group 0. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK + */ +#define PCR_TG0_TIMER_CLK_SEL 0x00000003U +#define PCR_TG0_TIMER_CLK_SEL_M (PCR_TG0_TIMER_CLK_SEL_V << PCR_TG0_TIMER_CLK_SEL_S) +#define PCR_TG0_TIMER_CLK_SEL_V 0x00000003U +#define PCR_TG0_TIMER_CLK_SEL_S 20 +/** PCR_TG0_TIMER_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group0 timer clock + */ +#define PCR_TG0_TIMER_CLK_EN (BIT(22)) +#define PCR_TG0_TIMER_CLK_EN_M (PCR_TG0_TIMER_CLK_EN_V << PCR_TG0_TIMER_CLK_EN_S) +#define PCR_TG0_TIMER_CLK_EN_V 0x00000001U +#define PCR_TG0_TIMER_CLK_EN_S 22 + +/** PCR_TIMERGROUP0_WDT_CLK_CONF_REG register + * TIMERGROUP0_WDT_CLK configuration register + */ +#define PCR_TIMERGROUP0_WDT_CLK_CONF_REG (DR_REG_PCR_BASE + 0x48) +/** PCR_TG0_WDT_CLK_SEL : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of WDT in Timer Group 0. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK + */ +#define PCR_TG0_WDT_CLK_SEL 0x00000003U +#define PCR_TG0_WDT_CLK_SEL_M (PCR_TG0_WDT_CLK_SEL_V << PCR_TG0_WDT_CLK_SEL_S) +#define PCR_TG0_WDT_CLK_SEL_V 0x00000003U +#define PCR_TG0_WDT_CLK_SEL_S 20 +/** PCR_TG0_WDT_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group0 wdt clock + */ +#define PCR_TG0_WDT_CLK_EN (BIT(22)) +#define PCR_TG0_WDT_CLK_EN_M (PCR_TG0_WDT_CLK_EN_V << PCR_TG0_WDT_CLK_EN_S) +#define PCR_TG0_WDT_CLK_EN_V 0x00000001U +#define PCR_TG0_WDT_CLK_EN_S 22 + +/** PCR_TIMERGROUP1_CONF_REG register + * TIMERGROUP1 configuration register + */ +#define PCR_TIMERGROUP1_CONF_REG (DR_REG_PCR_BASE + 0x4c) +/** PCR_TG1_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable timer_group1 apb clock + */ +#define PCR_TG1_CLK_EN (BIT(0)) +#define PCR_TG1_CLK_EN_M (PCR_TG1_CLK_EN_V << PCR_TG1_CLK_EN_S) +#define PCR_TG1_CLK_EN_V 0x00000001U +#define PCR_TG1_CLK_EN_S 0 +/** PCR_TG1_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset timer_group1 module + */ +#define PCR_TG1_RST_EN (BIT(1)) +#define PCR_TG1_RST_EN_M (PCR_TG1_RST_EN_V << PCR_TG1_RST_EN_S) +#define PCR_TG1_RST_EN_V 0x00000001U +#define PCR_TG1_RST_EN_S 1 +/** PCR_TG1_WDT_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset timer_group1 wdt module + */ +#define PCR_TG1_WDT_READY (BIT(2)) +#define PCR_TG1_WDT_READY_M (PCR_TG1_WDT_READY_V << PCR_TG1_WDT_READY_S) +#define PCR_TG1_WDT_READY_V 0x00000001U +#define PCR_TG1_WDT_READY_S 2 +/** PCR_TG1_TIMER0_READY : RO; bitpos: [3]; default: 1; + * Query this field after reset timer_group1 timer0 module + */ +#define PCR_TG1_TIMER0_READY (BIT(3)) +#define PCR_TG1_TIMER0_READY_M (PCR_TG1_TIMER0_READY_V << PCR_TG1_TIMER0_READY_S) +#define PCR_TG1_TIMER0_READY_V 0x00000001U +#define PCR_TG1_TIMER0_READY_S 3 +/** PCR_TG1_TIMER1_READY : RO; bitpos: [4]; default: 1; + * reserved + */ +#define PCR_TG1_TIMER1_READY (BIT(4)) +#define PCR_TG1_TIMER1_READY_M (PCR_TG1_TIMER1_READY_V << PCR_TG1_TIMER1_READY_S) +#define PCR_TG1_TIMER1_READY_V 0x00000001U +#define PCR_TG1_TIMER1_READY_S 4 + +/** PCR_TIMERGROUP1_TIMER_CLK_CONF_REG register + * TIMERGROUP1_TIMER_CLK configuration register + */ +#define PCR_TIMERGROUP1_TIMER_CLK_CONF_REG (DR_REG_PCR_BASE + 0x50) +/** PCR_TG1_TIMER_CLK_SEL : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of general-purpose timers in Timer Group 1. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK + */ +#define PCR_TG1_TIMER_CLK_SEL 0x00000003U +#define PCR_TG1_TIMER_CLK_SEL_M (PCR_TG1_TIMER_CLK_SEL_V << PCR_TG1_TIMER_CLK_SEL_S) +#define PCR_TG1_TIMER_CLK_SEL_V 0x00000003U +#define PCR_TG1_TIMER_CLK_SEL_S 20 +/** PCR_TG1_TIMER_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group1 timer clock + */ +#define PCR_TG1_TIMER_CLK_EN (BIT(22)) +#define PCR_TG1_TIMER_CLK_EN_M (PCR_TG1_TIMER_CLK_EN_V << PCR_TG1_TIMER_CLK_EN_S) +#define PCR_TG1_TIMER_CLK_EN_V 0x00000001U +#define PCR_TG1_TIMER_CLK_EN_S 22 + +/** PCR_TIMERGROUP1_WDT_CLK_CONF_REG register + * TIMERGROUP1_WDT_CLK configuration register + */ +#define PCR_TIMERGROUP1_WDT_CLK_CONF_REG (DR_REG_PCR_BASE + 0x54) +/** PCR_TG1_WDT_CLK_SEL : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of WDT in Timer Group 1. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK + */ +#define PCR_TG1_WDT_CLK_SEL 0x00000003U +#define PCR_TG1_WDT_CLK_SEL_M (PCR_TG1_WDT_CLK_SEL_V << PCR_TG1_WDT_CLK_SEL_S) +#define PCR_TG1_WDT_CLK_SEL_V 0x00000003U +#define PCR_TG1_WDT_CLK_SEL_S 20 +/** PCR_TG1_WDT_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group0 wdt clock + */ +#define PCR_TG1_WDT_CLK_EN (BIT(22)) +#define PCR_TG1_WDT_CLK_EN_M (PCR_TG1_WDT_CLK_EN_V << PCR_TG1_WDT_CLK_EN_S) +#define PCR_TG1_WDT_CLK_EN_V 0x00000001U +#define PCR_TG1_WDT_CLK_EN_S 22 + +/** PCR_SYSTIMER_CONF_REG register + * SYSTIMER configuration register + */ +#define PCR_SYSTIMER_CONF_REG (DR_REG_PCR_BASE + 0x58) +/** PCR_SYSTIMER_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable systimer apb clock + */ +#define PCR_SYSTIMER_CLK_EN (BIT(0)) +#define PCR_SYSTIMER_CLK_EN_M (PCR_SYSTIMER_CLK_EN_V << PCR_SYSTIMER_CLK_EN_S) +#define PCR_SYSTIMER_CLK_EN_V 0x00000001U +#define PCR_SYSTIMER_CLK_EN_S 0 +/** PCR_SYSTIMER_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset systimer module + */ +#define PCR_SYSTIMER_RST_EN (BIT(1)) +#define PCR_SYSTIMER_RST_EN_M (PCR_SYSTIMER_RST_EN_V << PCR_SYSTIMER_RST_EN_S) +#define PCR_SYSTIMER_RST_EN_V 0x00000001U +#define PCR_SYSTIMER_RST_EN_S 1 +/** PCR_SYSTIMER_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset systimer module + */ +#define PCR_SYSTIMER_READY (BIT(2)) +#define PCR_SYSTIMER_READY_M (PCR_SYSTIMER_READY_V << PCR_SYSTIMER_READY_S) +#define PCR_SYSTIMER_READY_V 0x00000001U +#define PCR_SYSTIMER_READY_S 2 + +/** PCR_SYSTIMER_FUNC_CLK_CONF_REG register + * SYSTIMER_FUNC_CLK configuration register + */ +#define PCR_SYSTIMER_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x5c) +/** PCR_SYSTIMER_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0; + * Configures the clock source of System Timer. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + */ +#define PCR_SYSTIMER_FUNC_CLK_SEL (BIT(20)) +#define PCR_SYSTIMER_FUNC_CLK_SEL_M (PCR_SYSTIMER_FUNC_CLK_SEL_V << PCR_SYSTIMER_FUNC_CLK_SEL_S) +#define PCR_SYSTIMER_FUNC_CLK_SEL_V 0x00000001U +#define PCR_SYSTIMER_FUNC_CLK_SEL_S 20 +/** PCR_SYSTIMER_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable systimer function clock + */ +#define PCR_SYSTIMER_FUNC_CLK_EN (BIT(22)) +#define PCR_SYSTIMER_FUNC_CLK_EN_M (PCR_SYSTIMER_FUNC_CLK_EN_V << PCR_SYSTIMER_FUNC_CLK_EN_S) +#define PCR_SYSTIMER_FUNC_CLK_EN_V 0x00000001U +#define PCR_SYSTIMER_FUNC_CLK_EN_S 22 + +/** PCR_I2S_CONF_REG register + * I2S configuration register + */ +#define PCR_I2S_CONF_REG (DR_REG_PCR_BASE + 0x60) +/** PCR_I2S_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable i2s apb clock + */ +#define PCR_I2S_CLK_EN (BIT(0)) +#define PCR_I2S_CLK_EN_M (PCR_I2S_CLK_EN_V << PCR_I2S_CLK_EN_S) +#define PCR_I2S_CLK_EN_V 0x00000001U +#define PCR_I2S_CLK_EN_S 0 +/** PCR_I2S_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset i2s module + */ +#define PCR_I2S_RST_EN (BIT(1)) +#define PCR_I2S_RST_EN_M (PCR_I2S_RST_EN_V << PCR_I2S_RST_EN_S) +#define PCR_I2S_RST_EN_V 0x00000001U +#define PCR_I2S_RST_EN_S 1 +/** PCR_I2S_RX_READY : RO; bitpos: [2]; default: 1; + * Query this field before using i2s rx function, after reset i2s module + */ +#define PCR_I2S_RX_READY (BIT(2)) +#define PCR_I2S_RX_READY_M (PCR_I2S_RX_READY_V << PCR_I2S_RX_READY_S) +#define PCR_I2S_RX_READY_V 0x00000001U +#define PCR_I2S_RX_READY_S 2 +/** PCR_I2S_TX_READY : RO; bitpos: [3]; default: 1; + * Query this field before using i2s tx function, after reset i2s module + */ +#define PCR_I2S_TX_READY (BIT(3)) +#define PCR_I2S_TX_READY_M (PCR_I2S_TX_READY_V << PCR_I2S_TX_READY_S) +#define PCR_I2S_TX_READY_V 0x00000001U +#define PCR_I2S_TX_READY_S 3 + +/** PCR_I2S_TX_CLKM_CONF_REG register + * I2S_TX_CLKM configuration register + */ +#define PCR_I2S_TX_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x64) +/** PCR_I2S_TX_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 2; + * Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be + * (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= + * a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * + * (n+1)-div] + y * (n+1)-div. + */ +#define PCR_I2S_TX_CLKM_DIV_NUM 0x000000FFU +#define PCR_I2S_TX_CLKM_DIV_NUM_M (PCR_I2S_TX_CLKM_DIV_NUM_V << PCR_I2S_TX_CLKM_DIV_NUM_S) +#define PCR_I2S_TX_CLKM_DIV_NUM_V 0x000000FFU +#define PCR_I2S_TX_CLKM_DIV_NUM_S 12 +/** PCR_I2S_TX_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of I2S TX. + * 0 (default): XTAL_CLK + * 1: PLL_F120M_CLK + * 2: PLL_F160M_CLK + * 3: I2S_MCLK_in + */ +#define PCR_I2S_TX_CLKM_SEL 0x00000003U +#define PCR_I2S_TX_CLKM_SEL_M (PCR_I2S_TX_CLKM_SEL_V << PCR_I2S_TX_CLKM_SEL_S) +#define PCR_I2S_TX_CLKM_SEL_V 0x00000003U +#define PCR_I2S_TX_CLKM_SEL_S 20 +/** PCR_I2S_TX_CLKM_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable i2s_tx function clock + */ +#define PCR_I2S_TX_CLKM_EN (BIT(22)) +#define PCR_I2S_TX_CLKM_EN_M (PCR_I2S_TX_CLKM_EN_V << PCR_I2S_TX_CLKM_EN_S) +#define PCR_I2S_TX_CLKM_EN_V 0x00000001U +#define PCR_I2S_TX_CLKM_EN_S 22 + +/** PCR_I2S_TX_CLKM_DIV_CONF_REG register + * I2S_TX_CLKM_DIV configuration register + */ +#define PCR_I2S_TX_CLKM_DIV_CONF_REG (DR_REG_PCR_BASE + 0x68) +/** PCR_I2S_TX_CLKM_DIV_Z : R/W; bitpos: [8:0]; default: 0; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of + * I2S_TX_CLKM_DIV_Z is (a-b). + */ +#define PCR_I2S_TX_CLKM_DIV_Z 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_Z_M (PCR_I2S_TX_CLKM_DIV_Z_V << PCR_I2S_TX_CLKM_DIV_Z_S) +#define PCR_I2S_TX_CLKM_DIV_Z_V 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_Z_S 0 +/** PCR_I2S_TX_CLKM_DIV_Y : R/W; bitpos: [17:9]; default: 1; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of + * I2S_TX_CLKM_DIV_Y is (a%(a-b)). + */ +#define PCR_I2S_TX_CLKM_DIV_Y 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_Y_M (PCR_I2S_TX_CLKM_DIV_Y_V << PCR_I2S_TX_CLKM_DIV_Y_S) +#define PCR_I2S_TX_CLKM_DIV_Y_V 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_Y_S 9 +/** PCR_I2S_TX_CLKM_DIV_X : R/W; bitpos: [26:18]; default: 0; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value + * of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1. + */ +#define PCR_I2S_TX_CLKM_DIV_X 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_X_M (PCR_I2S_TX_CLKM_DIV_X_V << PCR_I2S_TX_CLKM_DIV_X_S) +#define PCR_I2S_TX_CLKM_DIV_X_V 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_X_S 18 +/** PCR_I2S_TX_CLKM_DIV_YN1 : R/W; bitpos: [27]; default: 0; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of + * I2S_TX_CLKM_DIV_YN1 is 1. + */ +#define PCR_I2S_TX_CLKM_DIV_YN1 (BIT(27)) +#define PCR_I2S_TX_CLKM_DIV_YN1_M (PCR_I2S_TX_CLKM_DIV_YN1_V << PCR_I2S_TX_CLKM_DIV_YN1_S) +#define PCR_I2S_TX_CLKM_DIV_YN1_V 0x00000001U +#define PCR_I2S_TX_CLKM_DIV_YN1_S 27 + +/** PCR_I2S_RX_CLKM_CONF_REG register + * I2S_RX_CLKM configuration register + */ +#define PCR_I2S_RX_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x6c) +/** PCR_I2S_RX_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 2; + * Integral I2S clock divider value + */ +#define PCR_I2S_RX_CLKM_DIV_NUM 0x000000FFU +#define PCR_I2S_RX_CLKM_DIV_NUM_M (PCR_I2S_RX_CLKM_DIV_NUM_V << PCR_I2S_RX_CLKM_DIV_NUM_S) +#define PCR_I2S_RX_CLKM_DIV_NUM_V 0x000000FFU +#define PCR_I2S_RX_CLKM_DIV_NUM_S 12 +/** PCR_I2S_RX_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of I2S RX. + * 0 (default): XTAL_CLK + * 1: PLL_F120M_CLK + * 2: PLL_F160M_CLK + * 3: I2S_MCLK_in + */ +#define PCR_I2S_RX_CLKM_SEL 0x00000003U +#define PCR_I2S_RX_CLKM_SEL_M (PCR_I2S_RX_CLKM_SEL_V << PCR_I2S_RX_CLKM_SEL_S) +#define PCR_I2S_RX_CLKM_SEL_V 0x00000003U +#define PCR_I2S_RX_CLKM_SEL_S 20 +/** PCR_I2S_RX_CLKM_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable i2s_rx function clock + */ +#define PCR_I2S_RX_CLKM_EN (BIT(22)) +#define PCR_I2S_RX_CLKM_EN_M (PCR_I2S_RX_CLKM_EN_V << PCR_I2S_RX_CLKM_EN_S) +#define PCR_I2S_RX_CLKM_EN_V 0x00000001U +#define PCR_I2S_RX_CLKM_EN_S 22 +/** PCR_I2S_MCLK_SEL : R/W; bitpos: [23]; default: 0; + * Configures to select master clock. + * 0 (default): I2S_TX_CLK + * 1: I2S_RX_CLK + */ +#define PCR_I2S_MCLK_SEL (BIT(23)) +#define PCR_I2S_MCLK_SEL_M (PCR_I2S_MCLK_SEL_V << PCR_I2S_MCLK_SEL_S) +#define PCR_I2S_MCLK_SEL_V 0x00000001U +#define PCR_I2S_MCLK_SEL_S 23 + +/** PCR_I2S_RX_CLKM_DIV_CONF_REG register + * I2S_RX_CLKM_DIV configuration register + */ +#define PCR_I2S_RX_CLKM_DIV_CONF_REG (DR_REG_PCR_BASE + 0x70) +/** PCR_I2S_RX_CLKM_DIV_Z : R/W; bitpos: [8:0]; default: 0; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of + * I2S_RX_CLKM_DIV_Z is (a-b). + */ +#define PCR_I2S_RX_CLKM_DIV_Z 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_Z_M (PCR_I2S_RX_CLKM_DIV_Z_V << PCR_I2S_RX_CLKM_DIV_Z_S) +#define PCR_I2S_RX_CLKM_DIV_Z_V 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_Z_S 0 +/** PCR_I2S_RX_CLKM_DIV_Y : R/W; bitpos: [17:9]; default: 1; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of + * I2S_RX_CLKM_DIV_Y is (a%(a-b)). + */ +#define PCR_I2S_RX_CLKM_DIV_Y 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_Y_M (PCR_I2S_RX_CLKM_DIV_Y_V << PCR_I2S_RX_CLKM_DIV_Y_S) +#define PCR_I2S_RX_CLKM_DIV_Y_V 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_Y_S 9 +/** PCR_I2S_RX_CLKM_DIV_X : R/W; bitpos: [26:18]; default: 0; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value + * of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1. + */ +#define PCR_I2S_RX_CLKM_DIV_X 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_X_M (PCR_I2S_RX_CLKM_DIV_X_V << PCR_I2S_RX_CLKM_DIV_X_S) +#define PCR_I2S_RX_CLKM_DIV_X_V 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_X_S 18 +/** PCR_I2S_RX_CLKM_DIV_YN1 : R/W; bitpos: [27]; default: 0; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of + * I2S_RX_CLKM_DIV_YN1 is 1. + */ +#define PCR_I2S_RX_CLKM_DIV_YN1 (BIT(27)) +#define PCR_I2S_RX_CLKM_DIV_YN1_M (PCR_I2S_RX_CLKM_DIV_YN1_V << PCR_I2S_RX_CLKM_DIV_YN1_S) +#define PCR_I2S_RX_CLKM_DIV_YN1_V 0x00000001U +#define PCR_I2S_RX_CLKM_DIV_YN1_S 27 + +/** PCR_SARADC_CONF_REG register + * SARADC configuration register + */ +#define PCR_SARADC_CONF_REG (DR_REG_PCR_BASE + 0x74) +/** PCR_SARADC_CLK_EN : R/W; bitpos: [0]; default: 1; + * no use + */ +#define PCR_SARADC_CLK_EN (BIT(0)) +#define PCR_SARADC_CLK_EN_M (PCR_SARADC_CLK_EN_V << PCR_SARADC_CLK_EN_S) +#define PCR_SARADC_CLK_EN_V 0x00000001U +#define PCR_SARADC_CLK_EN_S 0 +/** PCR_SARADC_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset function_register of saradc module + */ +#define PCR_SARADC_RST_EN (BIT(1)) +#define PCR_SARADC_RST_EN_M (PCR_SARADC_RST_EN_V << PCR_SARADC_RST_EN_S) +#define PCR_SARADC_RST_EN_V 0x00000001U +#define PCR_SARADC_RST_EN_S 1 +/** PCR_SARADC_REG_CLK_EN : R/W; bitpos: [2]; default: 1; + * Set 1 to enable saradc apb clock + */ +#define PCR_SARADC_REG_CLK_EN (BIT(2)) +#define PCR_SARADC_REG_CLK_EN_M (PCR_SARADC_REG_CLK_EN_V << PCR_SARADC_REG_CLK_EN_S) +#define PCR_SARADC_REG_CLK_EN_V 0x00000001U +#define PCR_SARADC_REG_CLK_EN_S 2 +/** PCR_SARADC_REG_RST_EN : R/W; bitpos: [3]; default: 0; + * Set 1 to reset apb_register of saradc module + */ +#define PCR_SARADC_REG_RST_EN (BIT(3)) +#define PCR_SARADC_REG_RST_EN_M (PCR_SARADC_REG_RST_EN_V << PCR_SARADC_REG_RST_EN_S) +#define PCR_SARADC_REG_RST_EN_V 0x00000001U +#define PCR_SARADC_REG_RST_EN_S 3 + +/** PCR_SARADC_CLKM_CONF_REG register + * SARADC_CLKM configuration register + */ +#define PCR_SARADC_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x78) +/** PCR_SARADC_CLKM_DIV_A : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the saradc function clock. + */ +#define PCR_SARADC_CLKM_DIV_A 0x0000003FU +#define PCR_SARADC_CLKM_DIV_A_M (PCR_SARADC_CLKM_DIV_A_V << PCR_SARADC_CLKM_DIV_A_S) +#define PCR_SARADC_CLKM_DIV_A_V 0x0000003FU +#define PCR_SARADC_CLKM_DIV_A_S 0 +/** PCR_SARADC_CLKM_DIV_B : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the saradc function clock. + */ +#define PCR_SARADC_CLKM_DIV_B 0x0000003FU +#define PCR_SARADC_CLKM_DIV_B_M (PCR_SARADC_CLKM_DIV_B_V << PCR_SARADC_CLKM_DIV_B_S) +#define PCR_SARADC_CLKM_DIV_B_V 0x0000003FU +#define PCR_SARADC_CLKM_DIV_B_S 6 +/** PCR_SARADC_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 4; + * The integral part of the frequency divider factor of the saradc function clock. + */ +#define PCR_SARADC_CLKM_DIV_NUM 0x000000FFU +#define PCR_SARADC_CLKM_DIV_NUM_M (PCR_SARADC_CLKM_DIV_NUM_V << PCR_SARADC_CLKM_DIV_NUM_S) +#define PCR_SARADC_CLKM_DIV_NUM_V 0x000000FFU +#define PCR_SARADC_CLKM_DIV_NUM_S 12 +/** PCR_SARADC_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of SAR ADC. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK + */ +#define PCR_SARADC_CLKM_SEL 0x00000003U +#define PCR_SARADC_CLKM_SEL_M (PCR_SARADC_CLKM_SEL_V << PCR_SARADC_CLKM_SEL_S) +#define PCR_SARADC_CLKM_SEL_V 0x00000003U +#define PCR_SARADC_CLKM_SEL_S 20 +/** PCR_SARADC_CLKM_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable saradc function clock + */ +#define PCR_SARADC_CLKM_EN (BIT(22)) +#define PCR_SARADC_CLKM_EN_M (PCR_SARADC_CLKM_EN_V << PCR_SARADC_CLKM_EN_S) +#define PCR_SARADC_CLKM_EN_V 0x00000001U +#define PCR_SARADC_CLKM_EN_S 22 + +/** PCR_TSENS_CLK_CONF_REG register + * TSENS_CLK configuration register + */ +#define PCR_TSENS_CLK_CONF_REG (DR_REG_PCR_BASE + 0x7c) +/** PCR_TSENS_CLK_SEL : R/W; bitpos: [20]; default: 0; + * Configures the clock source of the temperature sensor. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + */ +#define PCR_TSENS_CLK_SEL (BIT(20)) +#define PCR_TSENS_CLK_SEL_M (PCR_TSENS_CLK_SEL_V << PCR_TSENS_CLK_SEL_S) +#define PCR_TSENS_CLK_SEL_V 0x00000001U +#define PCR_TSENS_CLK_SEL_S 20 +/** PCR_TSENS_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable tsens clock + */ +#define PCR_TSENS_CLK_EN (BIT(22)) +#define PCR_TSENS_CLK_EN_M (PCR_TSENS_CLK_EN_V << PCR_TSENS_CLK_EN_S) +#define PCR_TSENS_CLK_EN_V 0x00000001U +#define PCR_TSENS_CLK_EN_S 22 +/** PCR_TSENS_RST_EN : R/W; bitpos: [23]; default: 0; + * Set 1 to reset tsens module + */ +#define PCR_TSENS_RST_EN (BIT(23)) +#define PCR_TSENS_RST_EN_M (PCR_TSENS_RST_EN_V << PCR_TSENS_RST_EN_S) +#define PCR_TSENS_RST_EN_V 0x00000001U +#define PCR_TSENS_RST_EN_S 23 + +/** PCR_USB_DEVICE_CONF_REG register + * USB_DEVICE configuration register + */ +#define PCR_USB_DEVICE_CONF_REG (DR_REG_PCR_BASE + 0x80) +/** PCR_USB_DEVICE_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable usb_device clock + */ +#define PCR_USB_DEVICE_CLK_EN (BIT(0)) +#define PCR_USB_DEVICE_CLK_EN_M (PCR_USB_DEVICE_CLK_EN_V << PCR_USB_DEVICE_CLK_EN_S) +#define PCR_USB_DEVICE_CLK_EN_V 0x00000001U +#define PCR_USB_DEVICE_CLK_EN_S 0 +/** PCR_USB_DEVICE_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset usb_device module + */ +#define PCR_USB_DEVICE_RST_EN (BIT(1)) +#define PCR_USB_DEVICE_RST_EN_M (PCR_USB_DEVICE_RST_EN_V << PCR_USB_DEVICE_RST_EN_S) +#define PCR_USB_DEVICE_RST_EN_V 0x00000001U +#define PCR_USB_DEVICE_RST_EN_S 1 +/** PCR_USB_DEVICE_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset usb_device module + */ +#define PCR_USB_DEVICE_READY (BIT(2)) +#define PCR_USB_DEVICE_READY_M (PCR_USB_DEVICE_READY_V << PCR_USB_DEVICE_READY_S) +#define PCR_USB_DEVICE_READY_V 0x00000001U +#define PCR_USB_DEVICE_READY_S 2 + +/** PCR_INTMTX_CONF_REG register + * INTMTX configuration register + */ +#define PCR_INTMTX_CONF_REG (DR_REG_PCR_BASE + 0x84) +/** PCR_INTMTX_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable intmtx clock + */ +#define PCR_INTMTX_CLK_EN (BIT(0)) +#define PCR_INTMTX_CLK_EN_M (PCR_INTMTX_CLK_EN_V << PCR_INTMTX_CLK_EN_S) +#define PCR_INTMTX_CLK_EN_V 0x00000001U +#define PCR_INTMTX_CLK_EN_S 0 +/** PCR_INTMTX_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset intmtx module + */ +#define PCR_INTMTX_RST_EN (BIT(1)) +#define PCR_INTMTX_RST_EN_M (PCR_INTMTX_RST_EN_V << PCR_INTMTX_RST_EN_S) +#define PCR_INTMTX_RST_EN_V 0x00000001U +#define PCR_INTMTX_RST_EN_S 1 +/** PCR_INTMTX_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset intmtx module + */ +#define PCR_INTMTX_READY (BIT(2)) +#define PCR_INTMTX_READY_M (PCR_INTMTX_READY_V << PCR_INTMTX_READY_S) +#define PCR_INTMTX_READY_V 0x00000001U +#define PCR_INTMTX_READY_S 2 + +/** PCR_PVT_MONITOR_CONF_REG register + * PVT_MONITOR configuration register + */ +#define PCR_PVT_MONITOR_CONF_REG (DR_REG_PCR_BASE + 0x88) +/** PCR_PVT_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable apb clock of pvt module + */ +#define PCR_PVT_MONITOR_CLK_EN (BIT(0)) +#define PCR_PVT_MONITOR_CLK_EN_M (PCR_PVT_MONITOR_CLK_EN_V << PCR_PVT_MONITOR_CLK_EN_S) +#define PCR_PVT_MONITOR_CLK_EN_V 0x00000001U +#define PCR_PVT_MONITOR_CLK_EN_S 0 +/** PCR_PVT_MONITOR_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset all pvt monitor module + */ +#define PCR_PVT_MONITOR_RST_EN (BIT(1)) +#define PCR_PVT_MONITOR_RST_EN_M (PCR_PVT_MONITOR_RST_EN_V << PCR_PVT_MONITOR_RST_EN_S) +#define PCR_PVT_MONITOR_RST_EN_V 0x00000001U +#define PCR_PVT_MONITOR_RST_EN_S 1 +/** PCR_PVT_MONITOR_SITE2_CLK_EN : R/W; bitpos: [3]; default: 1; + * Set 1 to enable function clock of cpu pvt module + */ +#define PCR_PVT_MONITOR_SITE2_CLK_EN (BIT(3)) +#define PCR_PVT_MONITOR_SITE2_CLK_EN_M (PCR_PVT_MONITOR_SITE2_CLK_EN_V << PCR_PVT_MONITOR_SITE2_CLK_EN_S) +#define PCR_PVT_MONITOR_SITE2_CLK_EN_V 0x00000001U +#define PCR_PVT_MONITOR_SITE2_CLK_EN_S 3 +/** PCR_PVT_MONITOR_SITE2_RST_EN : R/W; bitpos: [4]; default: 0; + * Set 1 to reset cpu pvt monitor site + */ +#define PCR_PVT_MONITOR_SITE2_RST_EN (BIT(4)) +#define PCR_PVT_MONITOR_SITE2_RST_EN_M (PCR_PVT_MONITOR_SITE2_RST_EN_V << PCR_PVT_MONITOR_SITE2_RST_EN_S) +#define PCR_PVT_MONITOR_SITE2_RST_EN_V 0x00000001U +#define PCR_PVT_MONITOR_SITE2_RST_EN_S 4 +/** PCR_PVT_MONITOR_SITE3_CLK_EN : R/W; bitpos: [5]; default: 1; + * Set 1 to enable function clock of modem pvt module + */ +#define PCR_PVT_MONITOR_SITE3_CLK_EN (BIT(5)) +#define PCR_PVT_MONITOR_SITE3_CLK_EN_M (PCR_PVT_MONITOR_SITE3_CLK_EN_V << PCR_PVT_MONITOR_SITE3_CLK_EN_S) +#define PCR_PVT_MONITOR_SITE3_CLK_EN_V 0x00000001U +#define PCR_PVT_MONITOR_SITE3_CLK_EN_S 5 + +/** PCR_PVT_MONITOR_FUNC_CLK_CONF_REG register + * PVT_MONITOR function clock configuration register + */ +#define PCR_PVT_MONITOR_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x8c) +/** PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM : R/W; bitpos: [3:0]; default: 0; + * The integral part of the frequency divider factor of the pvt_monitor function clock. + */ +#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM 0x0000000FU +#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_M (PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_V << PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_S) +#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_V 0x0000000FU +#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_S 0 +/** PCR_PVT_MONITOR_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0; + * Configures the clock source of PVT MONITOR. + * 0 (default): XTAL_CLK + * 1: PLL_F160M_CLK + */ +#define PCR_PVT_MONITOR_FUNC_CLK_SEL (BIT(20)) +#define PCR_PVT_MONITOR_FUNC_CLK_SEL_M (PCR_PVT_MONITOR_FUNC_CLK_SEL_V << PCR_PVT_MONITOR_FUNC_CLK_SEL_S) +#define PCR_PVT_MONITOR_FUNC_CLK_SEL_V 0x00000001U +#define PCR_PVT_MONITOR_FUNC_CLK_SEL_S 20 +/** PCR_PVT_MONITOR_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable source clock of pvt sitex + */ +#define PCR_PVT_MONITOR_FUNC_CLK_EN (BIT(22)) +#define PCR_PVT_MONITOR_FUNC_CLK_EN_M (PCR_PVT_MONITOR_FUNC_CLK_EN_V << PCR_PVT_MONITOR_FUNC_CLK_EN_S) +#define PCR_PVT_MONITOR_FUNC_CLK_EN_V 0x00000001U +#define PCR_PVT_MONITOR_FUNC_CLK_EN_S 22 + +/** PCR_GDMA_CONF_REG register + * GDMA configuration register + */ +#define PCR_GDMA_CONF_REG (DR_REG_PCR_BASE + 0x90) +/** PCR_GDMA_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable gdma clock + */ +#define PCR_GDMA_CLK_EN (BIT(0)) +#define PCR_GDMA_CLK_EN_M (PCR_GDMA_CLK_EN_V << PCR_GDMA_CLK_EN_S) +#define PCR_GDMA_CLK_EN_V 0x00000001U +#define PCR_GDMA_CLK_EN_S 0 +/** PCR_GDMA_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset gdma module + */ +#define PCR_GDMA_RST_EN (BIT(1)) +#define PCR_GDMA_RST_EN_M (PCR_GDMA_RST_EN_V << PCR_GDMA_RST_EN_S) +#define PCR_GDMA_RST_EN_V 0x00000001U +#define PCR_GDMA_RST_EN_S 1 + +/** PCR_SPI2_CONF_REG register + * SPI2 configuration register + */ +#define PCR_SPI2_CONF_REG (DR_REG_PCR_BASE + 0x94) +/** PCR_SPI2_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable spi2 apb clock + */ +#define PCR_SPI2_CLK_EN (BIT(0)) +#define PCR_SPI2_CLK_EN_M (PCR_SPI2_CLK_EN_V << PCR_SPI2_CLK_EN_S) +#define PCR_SPI2_CLK_EN_V 0x00000001U +#define PCR_SPI2_CLK_EN_S 0 +/** PCR_SPI2_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset spi2 module + */ +#define PCR_SPI2_RST_EN (BIT(1)) +#define PCR_SPI2_RST_EN_M (PCR_SPI2_RST_EN_V << PCR_SPI2_RST_EN_S) +#define PCR_SPI2_RST_EN_V 0x00000001U +#define PCR_SPI2_RST_EN_S 1 +/** PCR_SPI2_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset spi2 module + */ +#define PCR_SPI2_READY (BIT(2)) +#define PCR_SPI2_READY_M (PCR_SPI2_READY_V << PCR_SPI2_READY_S) +#define PCR_SPI2_READY_V 0x00000001U +#define PCR_SPI2_READY_S 2 + +/** PCR_SPI2_CLKM_CONF_REG register + * SPI2_CLKM configuration register + */ +#define PCR_SPI2_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x98) +/** PCR_SPI2_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the spi2_mst clock. + */ +#define PCR_SPI2_CLKM_DIV_NUM 0x000000FFU +#define PCR_SPI2_CLKM_DIV_NUM_M (PCR_SPI2_CLKM_DIV_NUM_V << PCR_SPI2_CLKM_DIV_NUM_S) +#define PCR_SPI2_CLKM_DIV_NUM_V 0x000000FFU +#define PCR_SPI2_CLKM_DIV_NUM_S 12 +/** PCR_SPI2_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of SPI2. + * 0 (default): XTAL_CLK + * 1: PLL_F160M_CLK + * 2: RC_FAST_CLK + */ +#define PCR_SPI2_CLKM_SEL 0x00000003U +#define PCR_SPI2_CLKM_SEL_M (PCR_SPI2_CLKM_SEL_V << PCR_SPI2_CLKM_SEL_S) +#define PCR_SPI2_CLKM_SEL_V 0x00000003U +#define PCR_SPI2_CLKM_SEL_S 20 +/** PCR_SPI2_CLKM_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable spi2 function clock + */ +#define PCR_SPI2_CLKM_EN (BIT(22)) +#define PCR_SPI2_CLKM_EN_M (PCR_SPI2_CLKM_EN_V << PCR_SPI2_CLKM_EN_S) +#define PCR_SPI2_CLKM_EN_V 0x00000001U +#define PCR_SPI2_CLKM_EN_S 22 + +/** PCR_AES_CONF_REG register + * AES configuration register + */ +#define PCR_AES_CONF_REG (DR_REG_PCR_BASE + 0x9c) +/** PCR_AES_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable aes clock + */ +#define PCR_AES_CLK_EN (BIT(0)) +#define PCR_AES_CLK_EN_M (PCR_AES_CLK_EN_V << PCR_AES_CLK_EN_S) +#define PCR_AES_CLK_EN_V 0x00000001U +#define PCR_AES_CLK_EN_S 0 +/** PCR_AES_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset aes module + */ +#define PCR_AES_RST_EN (BIT(1)) +#define PCR_AES_RST_EN_M (PCR_AES_RST_EN_V << PCR_AES_RST_EN_S) +#define PCR_AES_RST_EN_V 0x00000001U +#define PCR_AES_RST_EN_S 1 +/** PCR_AES_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset aes module + */ +#define PCR_AES_READY (BIT(2)) +#define PCR_AES_READY_M (PCR_AES_READY_V << PCR_AES_READY_S) +#define PCR_AES_READY_V 0x00000001U +#define PCR_AES_READY_S 2 + +/** PCR_SHA_CONF_REG register + * SHA configuration register + */ +#define PCR_SHA_CONF_REG (DR_REG_PCR_BASE + 0xa0) +/** PCR_SHA_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable sha clock + */ +#define PCR_SHA_CLK_EN (BIT(0)) +#define PCR_SHA_CLK_EN_M (PCR_SHA_CLK_EN_V << PCR_SHA_CLK_EN_S) +#define PCR_SHA_CLK_EN_V 0x00000001U +#define PCR_SHA_CLK_EN_S 0 +/** PCR_SHA_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset sha module + */ +#define PCR_SHA_RST_EN (BIT(1)) +#define PCR_SHA_RST_EN_M (PCR_SHA_RST_EN_V << PCR_SHA_RST_EN_S) +#define PCR_SHA_RST_EN_V 0x00000001U +#define PCR_SHA_RST_EN_S 1 +/** PCR_SHA_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset sha module + */ +#define PCR_SHA_READY (BIT(2)) +#define PCR_SHA_READY_M (PCR_SHA_READY_V << PCR_SHA_READY_S) +#define PCR_SHA_READY_V 0x00000001U +#define PCR_SHA_READY_S 2 + +/** PCR_RSA_CONF_REG register + * RSA configuration register + */ +#define PCR_RSA_CONF_REG (DR_REG_PCR_BASE + 0xa4) +/** PCR_RSA_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable rsa clock + */ +#define PCR_RSA_CLK_EN (BIT(0)) +#define PCR_RSA_CLK_EN_M (PCR_RSA_CLK_EN_V << PCR_RSA_CLK_EN_S) +#define PCR_RSA_CLK_EN_V 0x00000001U +#define PCR_RSA_CLK_EN_S 0 +/** PCR_RSA_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset rsa module + */ +#define PCR_RSA_RST_EN (BIT(1)) +#define PCR_RSA_RST_EN_M (PCR_RSA_RST_EN_V << PCR_RSA_RST_EN_S) +#define PCR_RSA_RST_EN_V 0x00000001U +#define PCR_RSA_RST_EN_S 1 +/** PCR_RSA_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset rsa module + */ +#define PCR_RSA_READY (BIT(2)) +#define PCR_RSA_READY_M (PCR_RSA_READY_V << PCR_RSA_READY_S) +#define PCR_RSA_READY_V 0x00000001U +#define PCR_RSA_READY_S 2 + +/** PCR_RSA_PD_CTRL_REG register + * RSA power control register + */ +#define PCR_RSA_PD_CTRL_REG (DR_REG_PCR_BASE + 0xa8) +/** PCR_RSA_MEM_PD : R/W; bitpos: [0]; default: 0; + * Set this bit to power down rsa internal memory. + */ +#define PCR_RSA_MEM_PD (BIT(0)) +#define PCR_RSA_MEM_PD_M (PCR_RSA_MEM_PD_V << PCR_RSA_MEM_PD_S) +#define PCR_RSA_MEM_PD_V 0x00000001U +#define PCR_RSA_MEM_PD_S 0 +/** PCR_RSA_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1; + * Set this bit to force power up rsa internal memory + */ +#define PCR_RSA_MEM_FORCE_PU (BIT(1)) +#define PCR_RSA_MEM_FORCE_PU_M (PCR_RSA_MEM_FORCE_PU_V << PCR_RSA_MEM_FORCE_PU_S) +#define PCR_RSA_MEM_FORCE_PU_V 0x00000001U +#define PCR_RSA_MEM_FORCE_PU_S 1 +/** PCR_RSA_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; + * Set this bit to force power down rsa internal memory. + */ +#define PCR_RSA_MEM_FORCE_PD (BIT(2)) +#define PCR_RSA_MEM_FORCE_PD_M (PCR_RSA_MEM_FORCE_PD_V << PCR_RSA_MEM_FORCE_PD_S) +#define PCR_RSA_MEM_FORCE_PD_V 0x00000001U +#define PCR_RSA_MEM_FORCE_PD_S 2 + +/** PCR_ECC_CONF_REG register + * ECC configuration register + */ +#define PCR_ECC_CONF_REG (DR_REG_PCR_BASE + 0xac) +/** PCR_ECC_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable ecc clock + */ +#define PCR_ECC_CLK_EN (BIT(0)) +#define PCR_ECC_CLK_EN_M (PCR_ECC_CLK_EN_V << PCR_ECC_CLK_EN_S) +#define PCR_ECC_CLK_EN_V 0x00000001U +#define PCR_ECC_CLK_EN_S 0 +/** PCR_ECC_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset ecc module + */ +#define PCR_ECC_RST_EN (BIT(1)) +#define PCR_ECC_RST_EN_M (PCR_ECC_RST_EN_V << PCR_ECC_RST_EN_S) +#define PCR_ECC_RST_EN_V 0x00000001U +#define PCR_ECC_RST_EN_S 1 +/** PCR_ECC_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset ecc module + */ +#define PCR_ECC_READY (BIT(2)) +#define PCR_ECC_READY_M (PCR_ECC_READY_V << PCR_ECC_READY_S) +#define PCR_ECC_READY_V 0x00000001U +#define PCR_ECC_READY_S 2 + +/** PCR_ECC_PD_CTRL_REG register + * ECC power control register + */ +#define PCR_ECC_PD_CTRL_REG (DR_REG_PCR_BASE + 0xb0) +/** PCR_ECC_MEM_PD : R/W; bitpos: [0]; default: 0; + * Set this bit to power down ecc internal memory. + */ +#define PCR_ECC_MEM_PD (BIT(0)) +#define PCR_ECC_MEM_PD_M (PCR_ECC_MEM_PD_V << PCR_ECC_MEM_PD_S) +#define PCR_ECC_MEM_PD_V 0x00000001U +#define PCR_ECC_MEM_PD_S 0 +/** PCR_ECC_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1; + * Set this bit to force power up ecc internal memory + */ +#define PCR_ECC_MEM_FORCE_PU (BIT(1)) +#define PCR_ECC_MEM_FORCE_PU_M (PCR_ECC_MEM_FORCE_PU_V << PCR_ECC_MEM_FORCE_PU_S) +#define PCR_ECC_MEM_FORCE_PU_V 0x00000001U +#define PCR_ECC_MEM_FORCE_PU_S 1 +/** PCR_ECC_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; + * Set this bit to force power down ecc internal memory. + */ +#define PCR_ECC_MEM_FORCE_PD (BIT(2)) +#define PCR_ECC_MEM_FORCE_PD_M (PCR_ECC_MEM_FORCE_PD_V << PCR_ECC_MEM_FORCE_PD_S) +#define PCR_ECC_MEM_FORCE_PD_V 0x00000001U +#define PCR_ECC_MEM_FORCE_PD_S 2 + +/** PCR_DS_CONF_REG register + * DS configuration register + */ +#define PCR_DS_CONF_REG (DR_REG_PCR_BASE + 0xb4) +/** PCR_DS_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable ds clock + */ +#define PCR_DS_CLK_EN (BIT(0)) +#define PCR_DS_CLK_EN_M (PCR_DS_CLK_EN_V << PCR_DS_CLK_EN_S) +#define PCR_DS_CLK_EN_V 0x00000001U +#define PCR_DS_CLK_EN_S 0 +/** PCR_DS_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset ds module + */ +#define PCR_DS_RST_EN (BIT(1)) +#define PCR_DS_RST_EN_M (PCR_DS_RST_EN_V << PCR_DS_RST_EN_S) +#define PCR_DS_RST_EN_V 0x00000001U +#define PCR_DS_RST_EN_S 1 +/** PCR_DS_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset ds module + */ +#define PCR_DS_READY (BIT(2)) +#define PCR_DS_READY_M (PCR_DS_READY_V << PCR_DS_READY_S) +#define PCR_DS_READY_V 0x00000001U +#define PCR_DS_READY_S 2 + +/** PCR_HMAC_CONF_REG register + * HMAC configuration register + */ +#define PCR_HMAC_CONF_REG (DR_REG_PCR_BASE + 0xb8) +/** PCR_HMAC_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable hmac clock + */ +#define PCR_HMAC_CLK_EN (BIT(0)) +#define PCR_HMAC_CLK_EN_M (PCR_HMAC_CLK_EN_V << PCR_HMAC_CLK_EN_S) +#define PCR_HMAC_CLK_EN_V 0x00000001U +#define PCR_HMAC_CLK_EN_S 0 +/** PCR_HMAC_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset hmac module + */ +#define PCR_HMAC_RST_EN (BIT(1)) +#define PCR_HMAC_RST_EN_M (PCR_HMAC_RST_EN_V << PCR_HMAC_RST_EN_S) +#define PCR_HMAC_RST_EN_V 0x00000001U +#define PCR_HMAC_RST_EN_S 1 +/** PCR_HMAC_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset hmac module + */ +#define PCR_HMAC_READY (BIT(2)) +#define PCR_HMAC_READY_M (PCR_HMAC_READY_V << PCR_HMAC_READY_S) +#define PCR_HMAC_READY_V 0x00000001U +#define PCR_HMAC_READY_S 2 + +/** PCR_ECDSA_CONF_REG register + * ECDSA configuration register + */ +#define PCR_ECDSA_CONF_REG (DR_REG_PCR_BASE + 0xbc) +/** PCR_ECDSA_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable ecdsa clock + */ +#define PCR_ECDSA_CLK_EN (BIT(0)) +#define PCR_ECDSA_CLK_EN_M (PCR_ECDSA_CLK_EN_V << PCR_ECDSA_CLK_EN_S) +#define PCR_ECDSA_CLK_EN_V 0x00000001U +#define PCR_ECDSA_CLK_EN_S 0 +/** PCR_ECDSA_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset ecdsa module + */ +#define PCR_ECDSA_RST_EN (BIT(1)) +#define PCR_ECDSA_RST_EN_M (PCR_ECDSA_RST_EN_V << PCR_ECDSA_RST_EN_S) +#define PCR_ECDSA_RST_EN_V 0x00000001U +#define PCR_ECDSA_RST_EN_S 1 +/** PCR_ECDSA_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset ecdsa module + */ +#define PCR_ECDSA_READY (BIT(2)) +#define PCR_ECDSA_READY_M (PCR_ECDSA_READY_V << PCR_ECDSA_READY_S) +#define PCR_ECDSA_READY_V 0x00000001U +#define PCR_ECDSA_READY_S 2 + +/** PCR_IOMUX_CONF_REG register + * IOMUX configuration register + */ +#define PCR_IOMUX_CONF_REG (DR_REG_PCR_BASE + 0xc0) +/** PCR_IOMUX_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable iomux apb clock + */ +#define PCR_IOMUX_CLK_EN (BIT(0)) +#define PCR_IOMUX_CLK_EN_M (PCR_IOMUX_CLK_EN_V << PCR_IOMUX_CLK_EN_S) +#define PCR_IOMUX_CLK_EN_V 0x00000001U +#define PCR_IOMUX_CLK_EN_S 0 +/** PCR_IOMUX_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset iomux module + */ +#define PCR_IOMUX_RST_EN (BIT(1)) +#define PCR_IOMUX_RST_EN_M (PCR_IOMUX_RST_EN_V << PCR_IOMUX_RST_EN_S) +#define PCR_IOMUX_RST_EN_V 0x00000001U +#define PCR_IOMUX_RST_EN_S 1 + +/** PCR_IOMUX_CLK_CONF_REG register + * IOMUX_CLK configuration register + */ +#define PCR_IOMUX_CLK_CONF_REG (DR_REG_PCR_BASE + 0xc4) +/** PCR_IOMUX_FUNC_CLK_SEL : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of IO MUX. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK + */ +#define PCR_IOMUX_FUNC_CLK_SEL 0x00000003U +#define PCR_IOMUX_FUNC_CLK_SEL_M (PCR_IOMUX_FUNC_CLK_SEL_V << PCR_IOMUX_FUNC_CLK_SEL_S) +#define PCR_IOMUX_FUNC_CLK_SEL_V 0x00000003U +#define PCR_IOMUX_FUNC_CLK_SEL_S 20 +/** PCR_IOMUX_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable iomux function clock + */ +#define PCR_IOMUX_FUNC_CLK_EN (BIT(22)) +#define PCR_IOMUX_FUNC_CLK_EN_M (PCR_IOMUX_FUNC_CLK_EN_V << PCR_IOMUX_FUNC_CLK_EN_S) +#define PCR_IOMUX_FUNC_CLK_EN_V 0x00000001U +#define PCR_IOMUX_FUNC_CLK_EN_S 22 + +/** PCR_TCM_MEM_MONITOR_CONF_REG register + * TCM_MEM_MONITOR configuration register + */ +#define PCR_TCM_MEM_MONITOR_CONF_REG (DR_REG_PCR_BASE + 0xc8) +/** PCR_TCM_MEM_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable tcm_mem_monitor clock + */ +#define PCR_TCM_MEM_MONITOR_CLK_EN (BIT(0)) +#define PCR_TCM_MEM_MONITOR_CLK_EN_M (PCR_TCM_MEM_MONITOR_CLK_EN_V << PCR_TCM_MEM_MONITOR_CLK_EN_S) +#define PCR_TCM_MEM_MONITOR_CLK_EN_V 0x00000001U +#define PCR_TCM_MEM_MONITOR_CLK_EN_S 0 +/** PCR_TCM_MEM_MONITOR_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset tcm_mem_monitor module + */ +#define PCR_TCM_MEM_MONITOR_RST_EN (BIT(1)) +#define PCR_TCM_MEM_MONITOR_RST_EN_M (PCR_TCM_MEM_MONITOR_RST_EN_V << PCR_TCM_MEM_MONITOR_RST_EN_S) +#define PCR_TCM_MEM_MONITOR_RST_EN_V 0x00000001U +#define PCR_TCM_MEM_MONITOR_RST_EN_S 1 +/** PCR_TCM_MEM_MONITOR_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset tcm_mem_monitor module + */ +#define PCR_TCM_MEM_MONITOR_READY (BIT(2)) +#define PCR_TCM_MEM_MONITOR_READY_M (PCR_TCM_MEM_MONITOR_READY_V << PCR_TCM_MEM_MONITOR_READY_S) +#define PCR_TCM_MEM_MONITOR_READY_V 0x00000001U +#define PCR_TCM_MEM_MONITOR_READY_S 2 + +/** PCR_PSRAM_MEM_MONITOR_CONF_REG register + * PSRAM_MEM_MONITOR configuration register + */ +#define PCR_PSRAM_MEM_MONITOR_CONF_REG (DR_REG_PCR_BASE + 0xcc) +/** PCR_PSRAM_MEM_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable psram_mem_monitor clock + */ +#define PCR_PSRAM_MEM_MONITOR_CLK_EN (BIT(0)) +#define PCR_PSRAM_MEM_MONITOR_CLK_EN_M (PCR_PSRAM_MEM_MONITOR_CLK_EN_V << PCR_PSRAM_MEM_MONITOR_CLK_EN_S) +#define PCR_PSRAM_MEM_MONITOR_CLK_EN_V 0x00000001U +#define PCR_PSRAM_MEM_MONITOR_CLK_EN_S 0 +/** PCR_PSRAM_MEM_MONITOR_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset psram_mem_monitor module + */ +#define PCR_PSRAM_MEM_MONITOR_RST_EN (BIT(1)) +#define PCR_PSRAM_MEM_MONITOR_RST_EN_M (PCR_PSRAM_MEM_MONITOR_RST_EN_V << PCR_PSRAM_MEM_MONITOR_RST_EN_S) +#define PCR_PSRAM_MEM_MONITOR_RST_EN_V 0x00000001U +#define PCR_PSRAM_MEM_MONITOR_RST_EN_S 1 +/** PCR_PSRAM_MEM_MONITOR_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset psram_mem_monitor module + */ +#define PCR_PSRAM_MEM_MONITOR_READY (BIT(2)) +#define PCR_PSRAM_MEM_MONITOR_READY_M (PCR_PSRAM_MEM_MONITOR_READY_V << PCR_PSRAM_MEM_MONITOR_READY_S) +#define PCR_PSRAM_MEM_MONITOR_READY_V 0x00000001U +#define PCR_PSRAM_MEM_MONITOR_READY_S 2 + +/** PCR_TRACE_CONF_REG register + * TRACE configuration register + */ +#define PCR_TRACE_CONF_REG (DR_REG_PCR_BASE + 0xd0) +/** PCR_TRACE_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable trace clock + */ +#define PCR_TRACE_CLK_EN (BIT(0)) +#define PCR_TRACE_CLK_EN_M (PCR_TRACE_CLK_EN_V << PCR_TRACE_CLK_EN_S) +#define PCR_TRACE_CLK_EN_V 0x00000001U +#define PCR_TRACE_CLK_EN_S 0 +/** PCR_TRACE_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset trace module + */ +#define PCR_TRACE_RST_EN (BIT(1)) +#define PCR_TRACE_RST_EN_M (PCR_TRACE_RST_EN_V << PCR_TRACE_RST_EN_S) +#define PCR_TRACE_RST_EN_V 0x00000001U +#define PCR_TRACE_RST_EN_S 1 + +/** PCR_ASSIST_CONF_REG register + * ASSIST configuration register + */ +#define PCR_ASSIST_CONF_REG (DR_REG_PCR_BASE + 0xd4) +/** PCR_ASSIST_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable assist clock + */ +#define PCR_ASSIST_CLK_EN (BIT(0)) +#define PCR_ASSIST_CLK_EN_M (PCR_ASSIST_CLK_EN_V << PCR_ASSIST_CLK_EN_S) +#define PCR_ASSIST_CLK_EN_V 0x00000001U +#define PCR_ASSIST_CLK_EN_S 0 +/** PCR_ASSIST_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset assist module + */ +#define PCR_ASSIST_RST_EN (BIT(1)) +#define PCR_ASSIST_RST_EN_M (PCR_ASSIST_RST_EN_V << PCR_ASSIST_RST_EN_S) +#define PCR_ASSIST_RST_EN_V 0x00000001U +#define PCR_ASSIST_RST_EN_S 1 + +/** PCR_CACHE_CONF_REG register + * CACHE configuration register + */ +#define PCR_CACHE_CONF_REG (DR_REG_PCR_BASE + 0xd8) +/** PCR_CACHE_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable cache clock + */ +#define PCR_CACHE_CLK_EN (BIT(0)) +#define PCR_CACHE_CLK_EN_M (PCR_CACHE_CLK_EN_V << PCR_CACHE_CLK_EN_S) +#define PCR_CACHE_CLK_EN_V 0x00000001U +#define PCR_CACHE_CLK_EN_S 0 +/** PCR_CACHE_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset cache module + */ +#define PCR_CACHE_RST_EN (BIT(1)) +#define PCR_CACHE_RST_EN_M (PCR_CACHE_RST_EN_V << PCR_CACHE_RST_EN_S) +#define PCR_CACHE_RST_EN_V 0x00000001U +#define PCR_CACHE_RST_EN_S 1 + +/** PCR_CACHE_PD_CTRL_REG register + * CACHE power control register + */ +#define PCR_CACHE_PD_CTRL_REG (DR_REG_PCR_BASE + 0xdc) +/** PCR_CACHE_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1; + * Set this bit to force power down CACHE memory. + */ +#define PCR_CACHE_MEM_FORCE_PU (BIT(1)) +#define PCR_CACHE_MEM_FORCE_PU_M (PCR_CACHE_MEM_FORCE_PU_V << PCR_CACHE_MEM_FORCE_PU_S) +#define PCR_CACHE_MEM_FORCE_PU_V 0x00000001U +#define PCR_CACHE_MEM_FORCE_PU_S 1 +/** PCR_CACHE_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; + * Set this bit to force power up CACHE memory. + */ +#define PCR_CACHE_MEM_FORCE_PD (BIT(2)) +#define PCR_CACHE_MEM_FORCE_PD_M (PCR_CACHE_MEM_FORCE_PD_V << PCR_CACHE_MEM_FORCE_PD_S) +#define PCR_CACHE_MEM_FORCE_PD_V 0x00000001U +#define PCR_CACHE_MEM_FORCE_PD_S 2 + +/** PCR_MODEM_CONF_REG register + * MODEM_APB configuration register + */ +#define PCR_MODEM_CONF_REG (DR_REG_PCR_BASE + 0xe0) +/** PCR_MODEM_APB_CLK_EN : R/W; bitpos: [0]; default: 1; + * This field indicates if modem_apb clock is enable. 0: disable, 1: enable(default). + */ +#define PCR_MODEM_APB_CLK_EN (BIT(0)) +#define PCR_MODEM_APB_CLK_EN_M (PCR_MODEM_APB_CLK_EN_V << PCR_MODEM_APB_CLK_EN_S) +#define PCR_MODEM_APB_CLK_EN_V 0x00000001U +#define PCR_MODEM_APB_CLK_EN_S 0 +/** PCR_MODEM_RST_EN : R/W; bitpos: [1]; default: 0; + * Set this file as 1 to reset modem-subsystem. + */ +#define PCR_MODEM_RST_EN (BIT(1)) +#define PCR_MODEM_RST_EN_M (PCR_MODEM_RST_EN_V << PCR_MODEM_RST_EN_S) +#define PCR_MODEM_RST_EN_V 0x00000001U +#define PCR_MODEM_RST_EN_S 1 +/** PCR_MODEM_CLK_EN : R/W; bitpos: [2]; default: 1; + * This field indicates if modem source clock is enable. 0: disable, 1: + * enable(default). + */ +#define PCR_MODEM_CLK_EN (BIT(2)) +#define PCR_MODEM_CLK_EN_M (PCR_MODEM_CLK_EN_V << PCR_MODEM_CLK_EN_S) +#define PCR_MODEM_CLK_EN_V 0x00000001U +#define PCR_MODEM_CLK_EN_S 2 + +/** PCR_TIMEOUT_CONF_REG register + * TIMEOUT configuration register + */ +#define PCR_TIMEOUT_CONF_REG (DR_REG_PCR_BASE + 0xe4) +/** PCR_CPU_TIMEOUT_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset cpu_peri timeout module + */ +#define PCR_CPU_TIMEOUT_RST_EN (BIT(1)) +#define PCR_CPU_TIMEOUT_RST_EN_M (PCR_CPU_TIMEOUT_RST_EN_V << PCR_CPU_TIMEOUT_RST_EN_S) +#define PCR_CPU_TIMEOUT_RST_EN_V 0x00000001U +#define PCR_CPU_TIMEOUT_RST_EN_S 1 +/** PCR_HP_TIMEOUT_RST_EN : R/W; bitpos: [2]; default: 0; + * Set 1 to reset hp_peri timeout module and hp_modem timeout module + */ +#define PCR_HP_TIMEOUT_RST_EN (BIT(2)) +#define PCR_HP_TIMEOUT_RST_EN_M (PCR_HP_TIMEOUT_RST_EN_V << PCR_HP_TIMEOUT_RST_EN_S) +#define PCR_HP_TIMEOUT_RST_EN_V 0x00000001U +#define PCR_HP_TIMEOUT_RST_EN_S 2 + +/** PCR_SYSCLK_CONF_REG register + * SYSCLK configuration register + */ +#define PCR_SYSCLK_CONF_REG (DR_REG_PCR_BASE + 0xe8) +/** PCR_LS_DIV_NUM : HRO; bitpos: [7:0]; default: 0; + * clk_hproot is div1 of low-speed clock-source if clck-source is a low-speed + * clock-source such as XTAL/FOSC. + */ +#define PCR_LS_DIV_NUM 0x000000FFU +#define PCR_LS_DIV_NUM_M (PCR_LS_DIV_NUM_V << PCR_LS_DIV_NUM_S) +#define PCR_LS_DIV_NUM_V 0x000000FFU +#define PCR_LS_DIV_NUM_S 0 +/** PCR_HS_DIV_NUM : HRO; bitpos: [15:8]; default: 2; + * clk_hproot is div3 of SPLL if the clock-source is high-speed clock SPLL. + */ +#define PCR_HS_DIV_NUM 0x000000FFU +#define PCR_HS_DIV_NUM_M (PCR_HS_DIV_NUM_V << PCR_HS_DIV_NUM_S) +#define PCR_HS_DIV_NUM_V 0x000000FFU +#define PCR_HS_DIV_NUM_S 8 +/** PCR_SOC_CLK_SEL : R/W; bitpos: [17:16]; default: 0; + * Configures to select the clock source of HP_ROOT_CLK. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F160M_CLK + */ +#define PCR_SOC_CLK_SEL 0x00000003U +#define PCR_SOC_CLK_SEL_M (PCR_SOC_CLK_SEL_V << PCR_SOC_CLK_SEL_S) +#define PCR_SOC_CLK_SEL_V 0x00000003U +#define PCR_SOC_CLK_SEL_S 16 +/** PCR_CLK_XTAL_FREQ : RO; bitpos: [30:24]; default: 40; + * This field indicates the frequency(MHz) of XTAL. + */ +#define PCR_CLK_XTAL_FREQ 0x0000007FU +#define PCR_CLK_XTAL_FREQ_M (PCR_CLK_XTAL_FREQ_V << PCR_CLK_XTAL_FREQ_S) +#define PCR_CLK_XTAL_FREQ_V 0x0000007FU +#define PCR_CLK_XTAL_FREQ_S 24 +/** PCR_CPU_DBGMD_CLK_EN : R/W; bitpos: [31]; default: 1; + * This field indicates if cpu debug mode clock is enable. 0: disable, 1: + * enable(default). + */ +#define PCR_CPU_DBGMD_CLK_EN (BIT(31)) +#define PCR_CPU_DBGMD_CLK_EN_M (PCR_CPU_DBGMD_CLK_EN_V << PCR_CPU_DBGMD_CLK_EN_S) +#define PCR_CPU_DBGMD_CLK_EN_V 0x00000001U +#define PCR_CPU_DBGMD_CLK_EN_S 31 + +/** PCR_CPU_WAITI_CONF_REG register + * CPU_WAITI configuration register + */ +#define PCR_CPU_WAITI_CONF_REG (DR_REG_PCR_BASE + 0xec) +/** PCR_CPU_WAIT_MODE_FORCE_ON : R/W; bitpos: [3]; default: 1; + * Set 1 to force cpu_waiti_clk enable. + */ +#define PCR_CPU_WAIT_MODE_FORCE_ON (BIT(3)) +#define PCR_CPU_WAIT_MODE_FORCE_ON_M (PCR_CPU_WAIT_MODE_FORCE_ON_V << PCR_CPU_WAIT_MODE_FORCE_ON_S) +#define PCR_CPU_WAIT_MODE_FORCE_ON_V 0x00000001U +#define PCR_CPU_WAIT_MODE_FORCE_ON_S 3 +/** PCR_CPU_WAITI_DELAY_NUM : R/W; bitpos: [7:4]; default: 0; + * This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk + * will close + */ +#define PCR_CPU_WAITI_DELAY_NUM 0x0000000FU +#define PCR_CPU_WAITI_DELAY_NUM_M (PCR_CPU_WAITI_DELAY_NUM_V << PCR_CPU_WAITI_DELAY_NUM_S) +#define PCR_CPU_WAITI_DELAY_NUM_V 0x0000000FU +#define PCR_CPU_WAITI_DELAY_NUM_S 4 + +/** PCR_CPU_FREQ_CONF_REG register + * CPU_FREQ configuration register + */ +#define PCR_CPU_FREQ_CONF_REG (DR_REG_PCR_BASE + 0xf0) +/** PCR_CPU_DIV_NUM : R/W; bitpos: [7:0]; default: 0; + * Set this field to generate clk_cpu driven by clk_hproot. The clk_cpu is + * div1(default)/div2/div4 of clk_hproot. This field is only available for low-speed + * clock-source such as XTAL/FOSC, and should be used together with PCR_AHB_DIV_NUM. + */ +#define PCR_CPU_DIV_NUM 0x000000FFU +#define PCR_CPU_DIV_NUM_M (PCR_CPU_DIV_NUM_V << PCR_CPU_DIV_NUM_S) +#define PCR_CPU_DIV_NUM_V 0x000000FFU +#define PCR_CPU_DIV_NUM_S 0 + +/** PCR_AHB_FREQ_CONF_REG register + * AHB_FREQ configuration register + */ +#define PCR_AHB_FREQ_CONF_REG (DR_REG_PCR_BASE + 0xf4) +/** PCR_AHB_DIV_NUM : R/W; bitpos: [7:0]; default: 0; + * Set this field to generate clk_ahb driven by clk_hproot. The clk_ahb is + * div1(default)/div2/div4/div8 of clk_hproot. This field is only available for + * low-speed clock-source such as XTAL/FOSC, and should be used together with + * PCR_CPU_DIV_NUM. + */ +#define PCR_AHB_DIV_NUM 0x000000FFU +#define PCR_AHB_DIV_NUM_M (PCR_AHB_DIV_NUM_V << PCR_AHB_DIV_NUM_S) +#define PCR_AHB_DIV_NUM_V 0x000000FFU +#define PCR_AHB_DIV_NUM_S 0 + +/** PCR_APB_FREQ_CONF_REG register + * APB_FREQ configuration register + */ +#define PCR_APB_FREQ_CONF_REG (DR_REG_PCR_BASE + 0xf8) +/** PCR_APB_DECREASE_DIV_NUM : R/W; bitpos: [7:0]; default: 0; + * If this field's value is grater than PCR_APB_DIV_NUM, the clk_apb will be + * automatically down to clk_apb_decrease only when no access is on apb-bus, and will + * recover to the previous frequency when a new access appears on apb-bus. Set as one + * within (0,1,3) to set clk_apb_decrease as div1/div2/div4(default) of clk_ahb. Note + * that enable this function will reduce performance. Users can set this field as zero + * to disable the auto-decrease-apb-freq function. By default, this function is + * disable. + */ +#define PCR_APB_DECREASE_DIV_NUM 0x000000FFU +#define PCR_APB_DECREASE_DIV_NUM_M (PCR_APB_DECREASE_DIV_NUM_V << PCR_APB_DECREASE_DIV_NUM_S) +#define PCR_APB_DECREASE_DIV_NUM_V 0x000000FFU +#define PCR_APB_DECREASE_DIV_NUM_S 0 +/** PCR_APB_DIV_NUM : R/W; bitpos: [15:8]; default: 0; + * Set as one within (0,1,3) to generate clk_apb driven by clk_ahb. The clk_apb is + * div1(default)/div2/div4 of clk_ahb. + */ +#define PCR_APB_DIV_NUM 0x000000FFU +#define PCR_APB_DIV_NUM_M (PCR_APB_DIV_NUM_V << PCR_APB_DIV_NUM_S) +#define PCR_APB_DIV_NUM_V 0x000000FFU +#define PCR_APB_DIV_NUM_S 8 + +/** PCR_SYSCLK_FREQ_QUERY_0_REG register + * SYSCLK frequency query 0 register + */ +#define PCR_SYSCLK_FREQ_QUERY_0_REG (DR_REG_PCR_BASE + 0xfc) +/** PCR_FOSC_FREQ : HRO; bitpos: [7:0]; default: 8; + * This field indicates the frequency(MHz) of FOSC. + */ +#define PCR_FOSC_FREQ 0x000000FFU +#define PCR_FOSC_FREQ_M (PCR_FOSC_FREQ_V << PCR_FOSC_FREQ_S) +#define PCR_FOSC_FREQ_V 0x000000FFU +#define PCR_FOSC_FREQ_S 0 +/** PCR_PLL_FREQ : HRO; bitpos: [17:8]; default: 96; + * This field indicates the frequency(MHz) of SPLL. + */ +#define PCR_PLL_FREQ 0x000003FFU +#define PCR_PLL_FREQ_M (PCR_PLL_FREQ_V << PCR_PLL_FREQ_S) +#define PCR_PLL_FREQ_V 0x000003FFU +#define PCR_PLL_FREQ_S 8 + +/** PCR_PLL_DIV_CLK_EN_REG register + * SPLL DIV clock-gating configuration register + */ +#define PCR_PLL_DIV_CLK_EN_REG (DR_REG_PCR_BASE + 0x100) +/** PCR_PLL_160M_CLK_EN : R/W; bitpos: [1]; default: 1; + * This field is used to open 160 MHz clock (div3 of SPLL) driven from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_160M_CLK_EN (BIT(1)) +#define PCR_PLL_160M_CLK_EN_M (PCR_PLL_160M_CLK_EN_V << PCR_PLL_160M_CLK_EN_S) +#define PCR_PLL_160M_CLK_EN_V 0x00000001U +#define PCR_PLL_160M_CLK_EN_S 1 +/** PCR_PLL_120M_CLK_EN : R/W; bitpos: [2]; default: 1; + * This field is used to open 120 MHz clock (div4 of SPLL) driven from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_120M_CLK_EN (BIT(2)) +#define PCR_PLL_120M_CLK_EN_M (PCR_PLL_120M_CLK_EN_V << PCR_PLL_120M_CLK_EN_S) +#define PCR_PLL_120M_CLK_EN_V 0x00000001U +#define PCR_PLL_120M_CLK_EN_S 2 +/** PCR_PLL_80M_CLK_EN : R/W; bitpos: [3]; default: 1; + * This field is used to open 80 MHz clock (div6 of SPLL) driven from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_80M_CLK_EN (BIT(3)) +#define PCR_PLL_80M_CLK_EN_M (PCR_PLL_80M_CLK_EN_V << PCR_PLL_80M_CLK_EN_S) +#define PCR_PLL_80M_CLK_EN_V 0x00000001U +#define PCR_PLL_80M_CLK_EN_S 3 +/** PCR_PLL_60M_CLK_EN : R/W; bitpos: [4]; default: 1; + * This field is used to open 60 MHz clock (div8 of SPLL) driven from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_60M_CLK_EN (BIT(4)) +#define PCR_PLL_60M_CLK_EN_M (PCR_PLL_60M_CLK_EN_V << PCR_PLL_60M_CLK_EN_S) +#define PCR_PLL_60M_CLK_EN_V 0x00000001U +#define PCR_PLL_60M_CLK_EN_S 4 +/** PCR_PLL_48M_CLK_EN : R/W; bitpos: [5]; default: 1; + * This field is used to open 48 MHz clock (div10 of SPLL) driven from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_48M_CLK_EN (BIT(5)) +#define PCR_PLL_48M_CLK_EN_M (PCR_PLL_48M_CLK_EN_V << PCR_PLL_48M_CLK_EN_S) +#define PCR_PLL_48M_CLK_EN_V 0x00000001U +#define PCR_PLL_48M_CLK_EN_S 5 +/** PCR_PLL_40M_CLK_EN : R/W; bitpos: [6]; default: 1; + * This field is used to open 40 MHz clock (div12 of SPLL) driven from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_40M_CLK_EN (BIT(6)) +#define PCR_PLL_40M_CLK_EN_M (PCR_PLL_40M_CLK_EN_V << PCR_PLL_40M_CLK_EN_S) +#define PCR_PLL_40M_CLK_EN_V 0x00000001U +#define PCR_PLL_40M_CLK_EN_S 6 +/** PCR_PLL_20M_CLK_EN : R/W; bitpos: [7]; default: 1; + * This field is used to open 20 MHz clock (div24 of SPLL) driven from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_20M_CLK_EN (BIT(7)) +#define PCR_PLL_20M_CLK_EN_M (PCR_PLL_20M_CLK_EN_V << PCR_PLL_20M_CLK_EN_S) +#define PCR_PLL_20M_CLK_EN_V 0x00000001U +#define PCR_PLL_20M_CLK_EN_S 7 + +/** PCR_CTRL_CLK_OUT_EN_REG register + * CLK_OUT_EN configuration register + */ +#define PCR_CTRL_CLK_OUT_EN_REG (DR_REG_PCR_BASE + 0x104) +/** PCR_CLK20_OEN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable 20m clock + */ +#define PCR_CLK20_OEN (BIT(0)) +#define PCR_CLK20_OEN_M (PCR_CLK20_OEN_V << PCR_CLK20_OEN_S) +#define PCR_CLK20_OEN_V 0x00000001U +#define PCR_CLK20_OEN_S 0 +/** PCR_CLK22_OEN : R/W; bitpos: [1]; default: 1; + * Set 1 to enable 22m clock + */ +#define PCR_CLK22_OEN (BIT(1)) +#define PCR_CLK22_OEN_M (PCR_CLK22_OEN_V << PCR_CLK22_OEN_S) +#define PCR_CLK22_OEN_V 0x00000001U +#define PCR_CLK22_OEN_S 1 +/** PCR_CLK44_OEN : R/W; bitpos: [2]; default: 1; + * Set 1 to enable 44m clock + */ +#define PCR_CLK44_OEN (BIT(2)) +#define PCR_CLK44_OEN_M (PCR_CLK44_OEN_V << PCR_CLK44_OEN_S) +#define PCR_CLK44_OEN_V 0x00000001U +#define PCR_CLK44_OEN_S 2 +/** PCR_CLK_BB_OEN : R/W; bitpos: [3]; default: 1; + * Set 1 to enable bb clock + */ +#define PCR_CLK_BB_OEN (BIT(3)) +#define PCR_CLK_BB_OEN_M (PCR_CLK_BB_OEN_V << PCR_CLK_BB_OEN_S) +#define PCR_CLK_BB_OEN_V 0x00000001U +#define PCR_CLK_BB_OEN_S 3 +/** PCR_CLK80_OEN : R/W; bitpos: [4]; default: 1; + * Set 1 to enable 80m clock + */ +#define PCR_CLK80_OEN (BIT(4)) +#define PCR_CLK80_OEN_M (PCR_CLK80_OEN_V << PCR_CLK80_OEN_S) +#define PCR_CLK80_OEN_V 0x00000001U +#define PCR_CLK80_OEN_S 4 +/** PCR_CLK160_OEN : R/W; bitpos: [5]; default: 1; + * Set 1 to enable 160m clock + */ +#define PCR_CLK160_OEN (BIT(5)) +#define PCR_CLK160_OEN_M (PCR_CLK160_OEN_V << PCR_CLK160_OEN_S) +#define PCR_CLK160_OEN_V 0x00000001U +#define PCR_CLK160_OEN_S 5 +/** PCR_CLK_320M_OEN : R/W; bitpos: [6]; default: 1; + * Set 1 to enable 320m clock + */ +#define PCR_CLK_320M_OEN (BIT(6)) +#define PCR_CLK_320M_OEN_M (PCR_CLK_320M_OEN_V << PCR_CLK_320M_OEN_S) +#define PCR_CLK_320M_OEN_V 0x00000001U +#define PCR_CLK_320M_OEN_S 6 +/** PCR_CLK_ADC_INF_OEN : R/W; bitpos: [7]; default: 1; + * Reserved + */ +#define PCR_CLK_ADC_INF_OEN (BIT(7)) +#define PCR_CLK_ADC_INF_OEN_M (PCR_CLK_ADC_INF_OEN_V << PCR_CLK_ADC_INF_OEN_S) +#define PCR_CLK_ADC_INF_OEN_V 0x00000001U +#define PCR_CLK_ADC_INF_OEN_S 7 +/** PCR_CLK_DAC_CPU_OEN : R/W; bitpos: [8]; default: 1; + * Reserved + */ +#define PCR_CLK_DAC_CPU_OEN (BIT(8)) +#define PCR_CLK_DAC_CPU_OEN_M (PCR_CLK_DAC_CPU_OEN_V << PCR_CLK_DAC_CPU_OEN_S) +#define PCR_CLK_DAC_CPU_OEN_V 0x00000001U +#define PCR_CLK_DAC_CPU_OEN_S 8 +/** PCR_CLK_XTAL_OEN : R/W; bitpos: [9]; default: 1; + * Set 1 to enable xtal clock + */ +#define PCR_CLK_XTAL_OEN (BIT(9)) +#define PCR_CLK_XTAL_OEN_M (PCR_CLK_XTAL_OEN_V << PCR_CLK_XTAL_OEN_S) +#define PCR_CLK_XTAL_OEN_V 0x00000001U +#define PCR_CLK_XTAL_OEN_S 9 + +/** PCR_CTRL_32K_CONF_REG register + * 32KHz clock configuration register + */ +#define PCR_CTRL_32K_CONF_REG (DR_REG_PCR_BASE + 0x10c) +/** PCR_32K_SEL : R/W; bitpos: [2:0]; default: 0; + * Configures the 32KHz clock for TIMER_GROUP. + * 0 (default): RC32K_CLK + * 1: XTAL32K_CLK + * 2: OSC_SLOW_CLK + * 3: RC_SLOW_CLK + * 4: RC_FAST_CLK + */ +#define PCR_32K_SEL 0x00000007U +#define PCR_32K_SEL_M (PCR_32K_SEL_V << PCR_32K_SEL_S) +#define PCR_32K_SEL_V 0x00000007U +#define PCR_32K_SEL_S 0 +/** PCR_FOSC_TICK_NUM : R/W; bitpos: [15:8]; default: 7; + * When PCR_32K_SEL set as 4, This field PCR_FOSC_TICK_NUM is used to set the divider + * number of fosc. + */ +#define PCR_FOSC_TICK_NUM 0x000000FFU +#define PCR_FOSC_TICK_NUM_M (PCR_FOSC_TICK_NUM_V << PCR_FOSC_TICK_NUM_S) +#define PCR_FOSC_TICK_NUM_V 0x000000FFU +#define PCR_FOSC_TICK_NUM_S 8 + +/** PCR_SRAM_POWER_CONF_0_REG register + * HP SRAM/ROM configuration register + */ +#define PCR_SRAM_POWER_CONF_0_REG (DR_REG_PCR_BASE + 0x110) +/** PCR_ROM_FORCE_PU : R/W; bitpos: [1:0]; default: 3; + * Set this bit to force power up ROM + */ +#define PCR_ROM_FORCE_PU 0x00000003U +#define PCR_ROM_FORCE_PU_M (PCR_ROM_FORCE_PU_V << PCR_ROM_FORCE_PU_S) +#define PCR_ROM_FORCE_PU_V 0x00000003U +#define PCR_ROM_FORCE_PU_S 0 +/** PCR_ROM_FORCE_PD : R/W; bitpos: [3:2]; default: 0; + * Set this bit to force power down ROM. + */ +#define PCR_ROM_FORCE_PD 0x00000003U +#define PCR_ROM_FORCE_PD_M (PCR_ROM_FORCE_PD_V << PCR_ROM_FORCE_PD_S) +#define PCR_ROM_FORCE_PD_V 0x00000003U +#define PCR_ROM_FORCE_PD_S 2 +/** PCR_ROM_CLKGATE_FORCE_ON : R/W; bitpos: [5:4]; default: 0; + * 1: Force to open the clock and bypass the gate-clock when accessing the ROM. 0: A + * gate-clock will be used when accessing the ROM. + */ +#define PCR_ROM_CLKGATE_FORCE_ON 0x00000003U +#define PCR_ROM_CLKGATE_FORCE_ON_M (PCR_ROM_CLKGATE_FORCE_ON_V << PCR_ROM_CLKGATE_FORCE_ON_S) +#define PCR_ROM_CLKGATE_FORCE_ON_V 0x00000003U +#define PCR_ROM_CLKGATE_FORCE_ON_S 4 + +/** PCR_SRAM_POWER_CONF_1_REG register + * HP SRAM/ROM configuration register + */ +#define PCR_SRAM_POWER_CONF_1_REG (DR_REG_PCR_BASE + 0x114) +/** PCR_SRAM_FORCE_PU : R/W; bitpos: [4:0]; default: 31; + * Set this bit to force power up SRAM + */ +#define PCR_SRAM_FORCE_PU 0x0000001FU +#define PCR_SRAM_FORCE_PU_M (PCR_SRAM_FORCE_PU_V << PCR_SRAM_FORCE_PU_S) +#define PCR_SRAM_FORCE_PU_V 0x0000001FU +#define PCR_SRAM_FORCE_PU_S 0 +/** PCR_SRAM_FORCE_PD : R/W; bitpos: [14:10]; default: 0; + * Set this bit to force power down SRAM. + */ +#define PCR_SRAM_FORCE_PD 0x0000001FU +#define PCR_SRAM_FORCE_PD_M (PCR_SRAM_FORCE_PD_V << PCR_SRAM_FORCE_PD_S) +#define PCR_SRAM_FORCE_PD_V 0x0000001FU +#define PCR_SRAM_FORCE_PD_S 10 +/** PCR_SRAM_CLKGATE_FORCE_ON : R/W; bitpos: [24:20]; default: 0; + * 1: Force to open the clock and bypass the gate-clock when accessing the SRAM. 0: A + * gate-clock will be used when accessing the SRAM. + */ +#define PCR_SRAM_CLKGATE_FORCE_ON 0x0000001FU +#define PCR_SRAM_CLKGATE_FORCE_ON_M (PCR_SRAM_CLKGATE_FORCE_ON_V << PCR_SRAM_CLKGATE_FORCE_ON_S) +#define PCR_SRAM_CLKGATE_FORCE_ON_V 0x0000001FU +#define PCR_SRAM_CLKGATE_FORCE_ON_S 20 + +/** PCR_SEC_CONF_REG register + * Clock source configuration register for External Memory Encryption and Decryption + */ +#define PCR_SEC_CONF_REG (DR_REG_PCR_BASE + 0x118) +/** PCR_SEC_CLK_SEL : R/W; bitpos: [1:0]; default: 0; + * Configures the clock source for the External Memory Encryption and Decryption + * module. + * 0(default): XTAL_CLK + * 1 RC_FAST_CLK + * 2: PLL_F480M_CLK + */ +#define PCR_SEC_CLK_SEL 0x00000003U +#define PCR_SEC_CLK_SEL_M (PCR_SEC_CLK_SEL_V << PCR_SEC_CLK_SEL_S) +#define PCR_SEC_CLK_SEL_V 0x00000003U +#define PCR_SEC_CLK_SEL_S 0 +/** PCR_SEC_RST_EN : R/W; bitpos: [2]; default: 0; + * Set 1 to reset sec module + */ +#define PCR_SEC_RST_EN (BIT(2)) +#define PCR_SEC_RST_EN_M (PCR_SEC_RST_EN_V << PCR_SEC_RST_EN_S) +#define PCR_SEC_RST_EN_V 0x00000001U +#define PCR_SEC_RST_EN_S 2 + +/** PCR_BUS_CLK_UPDATE_REG register + * Configuration register for applying updated high-performance system clock sources + */ +#define PCR_BUS_CLK_UPDATE_REG (DR_REG_PCR_BASE + 0x120) +/** PCR_BUS_CLOCK_UPDATE : R/W/WTC; bitpos: [0]; default: 0; + * Configures whether or not to update configurations for CPU_CLK division, AHB_CLK + * division and HP_ROOT_CLK clock source selection. + * 0: Not update configurations + * 1: Update configurations + * This bit is automatically cleared when configurations have been updated. + */ +#define PCR_BUS_CLOCK_UPDATE (BIT(0)) +#define PCR_BUS_CLOCK_UPDATE_M (PCR_BUS_CLOCK_UPDATE_V << PCR_BUS_CLOCK_UPDATE_S) +#define PCR_BUS_CLOCK_UPDATE_V 0x00000001U +#define PCR_BUS_CLOCK_UPDATE_S 0 + +/** PCR_SAR_CLK_DIV_REG register + * SAR ADC clock divisor configuration register + */ +#define PCR_SAR_CLK_DIV_REG (DR_REG_PCR_BASE + 0x124) +/** PCR_SAR2_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 4; + * Configures the divisor for SAR ADC 2 clock to generate ADC analog control signals. + */ +#define PCR_SAR2_CLK_DIV_NUM 0x000000FFU +#define PCR_SAR2_CLK_DIV_NUM_M (PCR_SAR2_CLK_DIV_NUM_V << PCR_SAR2_CLK_DIV_NUM_S) +#define PCR_SAR2_CLK_DIV_NUM_V 0x000000FFU +#define PCR_SAR2_CLK_DIV_NUM_S 0 +/** PCR_SAR1_CLK_DIV_NUM : R/W; bitpos: [15:8]; default: 4; + * Configures the divisor for SAR ADC 1 clock to generate ADC analog control signals. + */ +#define PCR_SAR1_CLK_DIV_NUM 0x000000FFU +#define PCR_SAR1_CLK_DIV_NUM_M (PCR_SAR1_CLK_DIV_NUM_V << PCR_SAR1_CLK_DIV_NUM_S) +#define PCR_SAR1_CLK_DIV_NUM_V 0x000000FFU +#define PCR_SAR1_CLK_DIV_NUM_S 8 + +/** PCR_TIMERGROUP_WDT_CONF_REG register + * TIMERGROUP_WDT configuration register + */ +#define PCR_TIMERGROUP_WDT_CONF_REG (DR_REG_PCR_BASE + 0x12c) +/** PCR_TG0_WDT_RST_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to reset timer_group0 wdt module + */ +#define PCR_TG0_WDT_RST_EN (BIT(0)) +#define PCR_TG0_WDT_RST_EN_M (PCR_TG0_WDT_RST_EN_V << PCR_TG0_WDT_RST_EN_S) +#define PCR_TG0_WDT_RST_EN_V 0x00000001U +#define PCR_TG0_WDT_RST_EN_S 0 +/** PCR_TG1_WDT_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset timer_group1 wdt module + */ +#define PCR_TG1_WDT_RST_EN (BIT(1)) +#define PCR_TG1_WDT_RST_EN_M (PCR_TG1_WDT_RST_EN_V << PCR_TG1_WDT_RST_EN_S) +#define PCR_TG1_WDT_RST_EN_V 0x00000001U +#define PCR_TG1_WDT_RST_EN_S 1 + +/** PCR_TIMERGROUP_XTAL_CONF_REG register + * TIMERGROUP1 configuration register + */ +#define PCR_TIMERGROUP_XTAL_CONF_REG (DR_REG_PCR_BASE + 0x130) +/** PCR_TG0_XTAL_RST_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to reset timer_group0 xtal clock domain + */ +#define PCR_TG0_XTAL_RST_EN (BIT(0)) +#define PCR_TG0_XTAL_RST_EN_M (PCR_TG0_XTAL_RST_EN_V << PCR_TG0_XTAL_RST_EN_S) +#define PCR_TG0_XTAL_RST_EN_V 0x00000001U +#define PCR_TG0_XTAL_RST_EN_S 0 +/** PCR_TG1_XTAL_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset timer_group1 xtal clock domain + */ +#define PCR_TG1_XTAL_RST_EN (BIT(1)) +#define PCR_TG1_XTAL_RST_EN_M (PCR_TG1_XTAL_RST_EN_V << PCR_TG1_XTAL_RST_EN_S) +#define PCR_TG1_XTAL_RST_EN_V 0x00000001U +#define PCR_TG1_XTAL_RST_EN_S 1 +/** PCR_TG0_XTAL_CLK_EN : R/W; bitpos: [2]; default: 1; + * Set 1 to enable tg0 xtal clock + */ +#define PCR_TG0_XTAL_CLK_EN (BIT(2)) +#define PCR_TG0_XTAL_CLK_EN_M (PCR_TG0_XTAL_CLK_EN_V << PCR_TG0_XTAL_CLK_EN_S) +#define PCR_TG0_XTAL_CLK_EN_V 0x00000001U +#define PCR_TG0_XTAL_CLK_EN_S 2 + +/** PCR_RESET_EVENT_BYPASS_REG register + * reset event bypass backdoor configuration register + */ +#define PCR_RESET_EVENT_BYPASS_REG (DR_REG_PCR_BASE + 0x134) +/** PCR_RESET_EVENT_BYPASS_APM : R/W; bitpos: [0]; default: 0; + * This field is used to control reset event relationship for + * tee_reg/apm_reg/hp_system_reg. 1: tee_reg/apm_reg/hp_system_reg will only be reset + * by power-reset. some reset event will be bypass. 0: tee_reg/apm_reg/hp_system_reg + * will not only be reset by power-reset, but also some reset event. + */ +#define PCR_RESET_EVENT_BYPASS_APM (BIT(0)) +#define PCR_RESET_EVENT_BYPASS_APM_M (PCR_RESET_EVENT_BYPASS_APM_V << PCR_RESET_EVENT_BYPASS_APM_S) +#define PCR_RESET_EVENT_BYPASS_APM_V 0x00000001U +#define PCR_RESET_EVENT_BYPASS_APM_S 0 +/** PCR_RESET_EVENT_BYPASS : R/W; bitpos: [1]; default: 1; + * This field is used to control reset event relationship for system-bus. 1: system + * bus (including arbiter/router) will only be reset by power-reset. some reset event + * will be bypass. 0: system bus (including arbiter/router) will not only be reset by + * power-reset, but also some reset event. + */ +#define PCR_RESET_EVENT_BYPASS (BIT(1)) +#define PCR_RESET_EVENT_BYPASS_M (PCR_RESET_EVENT_BYPASS_V << PCR_RESET_EVENT_BYPASS_S) +#define PCR_RESET_EVENT_BYPASS_V 0x00000001U +#define PCR_RESET_EVENT_BYPASS_S 1 + +/** PCR_REGDMA_CONF_REG register + * REGDMA configuration register + */ +#define PCR_REGDMA_CONF_REG (DR_REG_PCR_BASE + 0x138) +/** PCR_REGDMA_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable regdma clock + */ +#define PCR_REGDMA_CLK_EN (BIT(0)) +#define PCR_REGDMA_CLK_EN_M (PCR_REGDMA_CLK_EN_V << PCR_REGDMA_CLK_EN_S) +#define PCR_REGDMA_CLK_EN_V 0x00000001U +#define PCR_REGDMA_CLK_EN_S 0 +/** PCR_REGDMA_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset regdma module + */ +#define PCR_REGDMA_RST_EN (BIT(1)) +#define PCR_REGDMA_RST_EN_M (PCR_REGDMA_RST_EN_V << PCR_REGDMA_RST_EN_S) +#define PCR_REGDMA_RST_EN_V 0x00000001U +#define PCR_REGDMA_RST_EN_S 1 + +/** PCR_ETM_CONF_REG register + * ETM configuration register + */ +#define PCR_ETM_CONF_REG (DR_REG_PCR_BASE + 0x13c) +/** PCR_ETM_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable etm clock + */ +#define PCR_ETM_CLK_EN (BIT(0)) +#define PCR_ETM_CLK_EN_M (PCR_ETM_CLK_EN_V << PCR_ETM_CLK_EN_S) +#define PCR_ETM_CLK_EN_V 0x00000001U +#define PCR_ETM_CLK_EN_S 0 +/** PCR_ETM_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset etm module + */ +#define PCR_ETM_RST_EN (BIT(1)) +#define PCR_ETM_RST_EN_M (PCR_ETM_RST_EN_V << PCR_ETM_RST_EN_S) +#define PCR_ETM_RST_EN_V 0x00000001U +#define PCR_ETM_RST_EN_S 1 +/** PCR_ETM_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset etm module + */ +#define PCR_ETM_READY (BIT(2)) +#define PCR_ETM_READY_M (PCR_ETM_READY_V << PCR_ETM_READY_S) +#define PCR_ETM_READY_V 0x00000001U +#define PCR_ETM_READY_S 2 + +/** PCR_SDIO_SLAVE_CONF_REG register + * SDIO_SLAVE configuration register + */ +#define PCR_SDIO_SLAVE_CONF_REG (DR_REG_PCR_BASE + 0x158) +/** PCR_SDIO_SLAVE_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable sdio_slave clock + */ +#define PCR_SDIO_SLAVE_CLK_EN (BIT(0)) +#define PCR_SDIO_SLAVE_CLK_EN_M (PCR_SDIO_SLAVE_CLK_EN_V << PCR_SDIO_SLAVE_CLK_EN_S) +#define PCR_SDIO_SLAVE_CLK_EN_V 0x00000001U +#define PCR_SDIO_SLAVE_CLK_EN_S 0 +/** PCR_SDIO_SLAVE_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset sdio_slave module + */ +#define PCR_SDIO_SLAVE_RST_EN (BIT(1)) +#define PCR_SDIO_SLAVE_RST_EN_M (PCR_SDIO_SLAVE_RST_EN_V << PCR_SDIO_SLAVE_RST_EN_S) +#define PCR_SDIO_SLAVE_RST_EN_V 0x00000001U +#define PCR_SDIO_SLAVE_RST_EN_S 1 + +/** PCR_SDIO_SLAVE_PD_CTRL_REG register + * LEDC power control register + */ +#define PCR_SDIO_SLAVE_PD_CTRL_REG (DR_REG_PCR_BASE + 0x15c) +/** PCR_SDIO_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1; + * Set this bit to force power down SDIO memory. + */ +#define PCR_SDIO_MEM_FORCE_PU (BIT(1)) +#define PCR_SDIO_MEM_FORCE_PU_M (PCR_SDIO_MEM_FORCE_PU_V << PCR_SDIO_MEM_FORCE_PU_S) +#define PCR_SDIO_MEM_FORCE_PU_V 0x00000001U +#define PCR_SDIO_MEM_FORCE_PU_S 1 +/** PCR_SDIO_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; + * Set this bit to force power up SDIO memory. + */ +#define PCR_SDIO_MEM_FORCE_PD (BIT(2)) +#define PCR_SDIO_MEM_FORCE_PD_M (PCR_SDIO_MEM_FORCE_PD_V << PCR_SDIO_MEM_FORCE_PD_S) +#define PCR_SDIO_MEM_FORCE_PD_V 0x00000001U +#define PCR_SDIO_MEM_FORCE_PD_S 2 + +/** PCR_DATE_REG register + * Date register. + */ +#define PCR_DATE_REG (DR_REG_PCR_BASE + 0xffc) +/** PCR_DATE : R/W; bitpos: [27:0]; default: 37823120; + * PCR version information. + */ +#define PCR_DATE 0x0FFFFFFFU +#define PCR_DATE_M (PCR_DATE_V << PCR_DATE_S) +#define PCR_DATE_V 0x0FFFFFFFU +#define PCR_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/src/target/esp32c61/ld/esp32c61.rom.api.ld b/src/target/esp32c61/ld/esp32c61.rom.api.ld index 109939a..10b4c40 100644 --- a/src/target/esp32c61/ld/esp32c61.rom.api.ld +++ b/src/target/esp32c61/ld/esp32c61.rom.api.ld @@ -27,6 +27,8 @@ PROVIDE ( esp_rom_uart_init = Uart_Init ); PROVIDE ( esp_rom_uart_div_modify = uart_div_modify ); PROVIDE ( esp_rom_get_apb_freq = ets_get_apb_freq ); PROVIDE ( esp_rom_get_cpu_freq = ets_clk_get_cpu_freq ); +PROVIDE ( esp_rom_get_xtal_freq = ets_clk_get_xtal_freq ); +PROVIDE ( esp_rom_get_cpu_freq = ets_clk_get_cpu_freq ); PROVIDE ( esp_rom_get_uart_device = GetUartDevice ); PROVIDE ( esp_rom_usb_serial_putc = uart_tx_one_char3 ); diff --git a/src/target/esp32c61/src/clock.c b/src/target/esp32c61/src/clock.c new file mode 100644 index 0000000..01aefe6 --- /dev/null +++ b/src/target/esp32c61/src/clock.c @@ -0,0 +1,35 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 OR MIT + */ + +#include +#include +#include +#include +#include +#include + +#define MHZ 1000000 + +extern uint32_t esp_rom_get_cpu_freq(void); +extern void esp_rom_set_cpu_ticks_per_us(uint32_t ticks_per_us); + +static uint32_t s_cpu_freq = 0; + +void stub_target_clock_init(void) +{ + REG_SET_FIELD(PCR_SYSCLK_CONF_REG, PCR_SOC_CLK_SEL, 2); + REG_SET_FIELD(PCR_BUS_CLK_UPDATE_REG, PCR_BUS_CLOCK_UPDATE, 1); + s_cpu_freq = 160 * MHZ; + esp_rom_set_cpu_ticks_per_us(s_cpu_freq / MHZ); +} + +uint32_t stub_target_get_cpu_freq(void) +{ + if (s_cpu_freq == 0) { + return esp_rom_get_cpu_freq(); + } + return s_cpu_freq; +} diff --git a/src/target/esp32h2/CMakeLists.txt b/src/target/esp32h2/CMakeLists.txt index 95dc7ce..9f94851 100644 --- a/src/target/esp32h2/CMakeLists.txt +++ b/src/target/esp32h2/CMakeLists.txt @@ -1,6 +1,7 @@ set(srcs src/uart.c src/usb_serial_jtag.c + src/clock.c ) add_library(${ESP_TARGET_LIB} STATIC ${srcs}) diff --git a/src/target/esp32h2/include/soc/pcr_reg.h b/src/target/esp32h2/include/soc/pcr_reg.h new file mode 100644 index 0000000..acf97cf --- /dev/null +++ b/src/target/esp32h2/include/soc/pcr_reg.h @@ -0,0 +1,2348 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 OR MIT + */ +#pragma once + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** PCR_UART0_CONF_REG register + * UART0 configuration register + */ +#define PCR_UART0_CONF_REG (DR_REG_PCR_BASE + 0x0) +/** PCR_UART0_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable uart0 apb clock + */ +#define PCR_UART0_CLK_EN (BIT(0)) +#define PCR_UART0_CLK_EN_M (PCR_UART0_CLK_EN_V << PCR_UART0_CLK_EN_S) +#define PCR_UART0_CLK_EN_V 0x00000001U +#define PCR_UART0_CLK_EN_S 0 +/** PCR_UART0_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset uart0 module + */ +#define PCR_UART0_RST_EN (BIT(1)) +#define PCR_UART0_RST_EN_M (PCR_UART0_RST_EN_V << PCR_UART0_RST_EN_S) +#define PCR_UART0_RST_EN_V 0x00000001U +#define PCR_UART0_RST_EN_S 1 +/** PCR_UART0_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset uart0 module + */ +#define PCR_UART0_READY (BIT(2)) +#define PCR_UART0_READY_M (PCR_UART0_READY_V << PCR_UART0_READY_S) +#define PCR_UART0_READY_V 0x00000001U +#define PCR_UART0_READY_S 2 + +/** PCR_UART0_SCLK_CONF_REG register + * UART0_SCLK configuration register + */ +#define PCR_UART0_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x4) +/** PCR_UART0_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the uart0 function clock. + */ +#define PCR_UART0_SCLK_DIV_A 0x0000003FU +#define PCR_UART0_SCLK_DIV_A_M (PCR_UART0_SCLK_DIV_A_V << PCR_UART0_SCLK_DIV_A_S) +#define PCR_UART0_SCLK_DIV_A_V 0x0000003FU +#define PCR_UART0_SCLK_DIV_A_S 0 +/** PCR_UART0_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the uart0 function clock. + */ +#define PCR_UART0_SCLK_DIV_B 0x0000003FU +#define PCR_UART0_SCLK_DIV_B_M (PCR_UART0_SCLK_DIV_B_V << PCR_UART0_SCLK_DIV_B_S) +#define PCR_UART0_SCLK_DIV_B_V 0x0000003FU +#define PCR_UART0_SCLK_DIV_B_S 6 +/** PCR_UART0_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the uart0 function clock. + */ +#define PCR_UART0_SCLK_DIV_NUM 0x000000FFU +#define PCR_UART0_SCLK_DIV_NUM_M (PCR_UART0_SCLK_DIV_NUM_V << PCR_UART0_SCLK_DIV_NUM_S) +#define PCR_UART0_SCLK_DIV_NUM_V 0x000000FFU +#define PCR_UART0_SCLK_DIV_NUM_S 12 +/** PCR_UART0_SCLK_SEL : R/W; bitpos: [21:20]; default: 3; + * set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: + * FOSC, 3(default): XTAL. + */ +#define PCR_UART0_SCLK_SEL 0x00000003U +#define PCR_UART0_SCLK_SEL_M (PCR_UART0_SCLK_SEL_V << PCR_UART0_SCLK_SEL_S) +#define PCR_UART0_SCLK_SEL_V 0x00000003U +#define PCR_UART0_SCLK_SEL_S 20 +/** PCR_UART0_SCLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable uart0 function clock + */ +#define PCR_UART0_SCLK_EN (BIT(22)) +#define PCR_UART0_SCLK_EN_M (PCR_UART0_SCLK_EN_V << PCR_UART0_SCLK_EN_S) +#define PCR_UART0_SCLK_EN_V 0x00000001U +#define PCR_UART0_SCLK_EN_S 22 + +/** PCR_UART0_PD_CTRL_REG register + * UART0 power control register + */ +#define PCR_UART0_PD_CTRL_REG (DR_REG_PCR_BASE + 0x8) +/** PCR_UART0_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1; + * Set this bit to force power down UART0 memory. + */ +#define PCR_UART0_MEM_FORCE_PU (BIT(1)) +#define PCR_UART0_MEM_FORCE_PU_M (PCR_UART0_MEM_FORCE_PU_V << PCR_UART0_MEM_FORCE_PU_S) +#define PCR_UART0_MEM_FORCE_PU_V 0x00000001U +#define PCR_UART0_MEM_FORCE_PU_S 1 +/** PCR_UART0_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; + * Set this bit to force power up UART0 memory. + */ +#define PCR_UART0_MEM_FORCE_PD (BIT(2)) +#define PCR_UART0_MEM_FORCE_PD_M (PCR_UART0_MEM_FORCE_PD_V << PCR_UART0_MEM_FORCE_PD_S) +#define PCR_UART0_MEM_FORCE_PD_V 0x00000001U +#define PCR_UART0_MEM_FORCE_PD_S 2 + +/** PCR_UART1_CONF_REG register + * UART1 configuration register + */ +#define PCR_UART1_CONF_REG (DR_REG_PCR_BASE + 0xc) +/** PCR_UART1_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable uart1 apb clock + */ +#define PCR_UART1_CLK_EN (BIT(0)) +#define PCR_UART1_CLK_EN_M (PCR_UART1_CLK_EN_V << PCR_UART1_CLK_EN_S) +#define PCR_UART1_CLK_EN_V 0x00000001U +#define PCR_UART1_CLK_EN_S 0 +/** PCR_UART1_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset uart1 module + */ +#define PCR_UART1_RST_EN (BIT(1)) +#define PCR_UART1_RST_EN_M (PCR_UART1_RST_EN_V << PCR_UART1_RST_EN_S) +#define PCR_UART1_RST_EN_V 0x00000001U +#define PCR_UART1_RST_EN_S 1 +/** PCR_UART1_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset uart1 module + */ +#define PCR_UART1_READY (BIT(2)) +#define PCR_UART1_READY_M (PCR_UART1_READY_V << PCR_UART1_READY_S) +#define PCR_UART1_READY_V 0x00000001U +#define PCR_UART1_READY_S 2 + +/** PCR_UART1_SCLK_CONF_REG register + * UART1_SCLK configuration register + */ +#define PCR_UART1_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x10) +/** PCR_UART1_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the uart1 function clock. + */ +#define PCR_UART1_SCLK_DIV_A 0x0000003FU +#define PCR_UART1_SCLK_DIV_A_M (PCR_UART1_SCLK_DIV_A_V << PCR_UART1_SCLK_DIV_A_S) +#define PCR_UART1_SCLK_DIV_A_V 0x0000003FU +#define PCR_UART1_SCLK_DIV_A_S 0 +/** PCR_UART1_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the uart1 function clock. + */ +#define PCR_UART1_SCLK_DIV_B 0x0000003FU +#define PCR_UART1_SCLK_DIV_B_M (PCR_UART1_SCLK_DIV_B_V << PCR_UART1_SCLK_DIV_B_S) +#define PCR_UART1_SCLK_DIV_B_V 0x0000003FU +#define PCR_UART1_SCLK_DIV_B_S 6 +/** PCR_UART1_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the uart1 function clock. + */ +#define PCR_UART1_SCLK_DIV_NUM 0x000000FFU +#define PCR_UART1_SCLK_DIV_NUM_M (PCR_UART1_SCLK_DIV_NUM_V << PCR_UART1_SCLK_DIV_NUM_S) +#define PCR_UART1_SCLK_DIV_NUM_V 0x000000FFU +#define PCR_UART1_SCLK_DIV_NUM_S 12 +/** PCR_UART1_SCLK_SEL : R/W; bitpos: [21:20]; default: 3; + * set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: + * FOSC, 3(default): XTAL. + */ +#define PCR_UART1_SCLK_SEL 0x00000003U +#define PCR_UART1_SCLK_SEL_M (PCR_UART1_SCLK_SEL_V << PCR_UART1_SCLK_SEL_S) +#define PCR_UART1_SCLK_SEL_V 0x00000003U +#define PCR_UART1_SCLK_SEL_S 20 +/** PCR_UART1_SCLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable uart0 function clock + */ +#define PCR_UART1_SCLK_EN (BIT(22)) +#define PCR_UART1_SCLK_EN_M (PCR_UART1_SCLK_EN_V << PCR_UART1_SCLK_EN_S) +#define PCR_UART1_SCLK_EN_V 0x00000001U +#define PCR_UART1_SCLK_EN_S 22 + +/** PCR_UART1_PD_CTRL_REG register + * UART1 power control register + */ +#define PCR_UART1_PD_CTRL_REG (DR_REG_PCR_BASE + 0x14) +/** PCR_UART1_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1; + * Set this bit to force power down UART1 memory. + */ +#define PCR_UART1_MEM_FORCE_PU (BIT(1)) +#define PCR_UART1_MEM_FORCE_PU_M (PCR_UART1_MEM_FORCE_PU_V << PCR_UART1_MEM_FORCE_PU_S) +#define PCR_UART1_MEM_FORCE_PU_V 0x00000001U +#define PCR_UART1_MEM_FORCE_PU_S 1 +/** PCR_UART1_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; + * Set this bit to force power up UART1 memory. + */ +#define PCR_UART1_MEM_FORCE_PD (BIT(2)) +#define PCR_UART1_MEM_FORCE_PD_M (PCR_UART1_MEM_FORCE_PD_V << PCR_UART1_MEM_FORCE_PD_S) +#define PCR_UART1_MEM_FORCE_PD_V 0x00000001U +#define PCR_UART1_MEM_FORCE_PD_S 2 + +/** PCR_MSPI_CONF_REG register + * MSPI configuration register + */ +#define PCR_MSPI_CONF_REG (DR_REG_PCR_BASE + 0x18) +/** PCR_MSPI_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable mspi clock, include mspi pll clock + */ +#define PCR_MSPI_CLK_EN (BIT(0)) +#define PCR_MSPI_CLK_EN_M (PCR_MSPI_CLK_EN_V << PCR_MSPI_CLK_EN_S) +#define PCR_MSPI_CLK_EN_V 0x00000001U +#define PCR_MSPI_CLK_EN_S 0 +/** PCR_MSPI_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset mspi module + */ +#define PCR_MSPI_RST_EN (BIT(1)) +#define PCR_MSPI_RST_EN_M (PCR_MSPI_RST_EN_V << PCR_MSPI_RST_EN_S) +#define PCR_MSPI_RST_EN_V 0x00000001U +#define PCR_MSPI_RST_EN_S 1 +/** PCR_MSPI_PLL_CLK_EN : R/W; bitpos: [2]; default: 1; + * Set 1 to enable mspi pll clock + */ +#define PCR_MSPI_PLL_CLK_EN (BIT(2)) +#define PCR_MSPI_PLL_CLK_EN_M (PCR_MSPI_PLL_CLK_EN_V << PCR_MSPI_PLL_CLK_EN_S) +#define PCR_MSPI_PLL_CLK_EN_V 0x00000001U +#define PCR_MSPI_PLL_CLK_EN_S 2 +/** PCR_MSPI_CLK_SEL : R/W; bitpos: [4:3]; default: 0; + * set this field to select clock-source. + */ +#define PCR_MSPI_CLK_SEL 0x00000003U +#define PCR_MSPI_CLK_SEL_M (PCR_MSPI_CLK_SEL_V << PCR_MSPI_CLK_SEL_S) +#define PCR_MSPI_CLK_SEL_V 0x00000003U +#define PCR_MSPI_CLK_SEL_S 3 +/** PCR_MSPI_READY : RO; bitpos: [5]; default: 1; + * Query this field after reset mspi module + */ +#define PCR_MSPI_READY (BIT(5)) +#define PCR_MSPI_READY_M (PCR_MSPI_READY_V << PCR_MSPI_READY_S) +#define PCR_MSPI_READY_V 0x00000001U +#define PCR_MSPI_READY_S 5 + +/** PCR_MSPI_CLK_CONF_REG register + * MSPI_CLK configuration register + */ +#define PCR_MSPI_CLK_CONF_REG (DR_REG_PCR_BASE + 0x1c) +/** PCR_MSPI_FAST_DIV_NUM : R/W; bitpos: [7:0]; default: 0; + * Set as one within (0,1,2) to generate div1(default)/div2/div4 of low-speed + * clock-source to drive clk_mspi_fast. Only available when the clck-source is a + * low-speed clock-source such as XTAL/FOSC. + */ +#define PCR_MSPI_FAST_DIV_NUM 0x000000FFU +#define PCR_MSPI_FAST_DIV_NUM_M (PCR_MSPI_FAST_DIV_NUM_V << PCR_MSPI_FAST_DIV_NUM_S) +#define PCR_MSPI_FAST_DIV_NUM_V 0x000000FFU +#define PCR_MSPI_FAST_DIV_NUM_S 0 + +/** PCR_I2C0_CONF_REG register + * I2C configuration register + */ +#define PCR_I2C0_CONF_REG (DR_REG_PCR_BASE + 0x20) +/** PCR_I2C0_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable i2c apb clock + */ +#define PCR_I2C0_CLK_EN (BIT(0)) +#define PCR_I2C0_CLK_EN_M (PCR_I2C0_CLK_EN_V << PCR_I2C0_CLK_EN_S) +#define PCR_I2C0_CLK_EN_V 0x00000001U +#define PCR_I2C0_CLK_EN_S 0 +/** PCR_I2C0_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset i2c module + */ +#define PCR_I2C0_RST_EN (BIT(1)) +#define PCR_I2C0_RST_EN_M (PCR_I2C0_RST_EN_V << PCR_I2C0_RST_EN_S) +#define PCR_I2C0_RST_EN_V 0x00000001U +#define PCR_I2C0_RST_EN_S 1 +/** PCR_I2C0_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset i2c0 module + */ +#define PCR_I2C0_READY (BIT(2)) +#define PCR_I2C0_READY_M (PCR_I2C0_READY_V << PCR_I2C0_READY_S) +#define PCR_I2C0_READY_V 0x00000001U +#define PCR_I2C0_READY_S 2 + +/** PCR_I2C0_SCLK_CONF_REG register + * I2C_SCLK configuration register + */ +#define PCR_I2C0_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x24) +/** PCR_I2C0_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the i2c function clock. + */ +#define PCR_I2C0_SCLK_DIV_A 0x0000003FU +#define PCR_I2C0_SCLK_DIV_A_M (PCR_I2C0_SCLK_DIV_A_V << PCR_I2C0_SCLK_DIV_A_S) +#define PCR_I2C0_SCLK_DIV_A_V 0x0000003FU +#define PCR_I2C0_SCLK_DIV_A_S 0 +/** PCR_I2C0_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the i2c function clock. + */ +#define PCR_I2C0_SCLK_DIV_B 0x0000003FU +#define PCR_I2C0_SCLK_DIV_B_M (PCR_I2C0_SCLK_DIV_B_V << PCR_I2C0_SCLK_DIV_B_S) +#define PCR_I2C0_SCLK_DIV_B_V 0x0000003FU +#define PCR_I2C0_SCLK_DIV_B_S 6 +/** PCR_I2C0_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the i2c function clock. + */ +#define PCR_I2C0_SCLK_DIV_NUM 0x000000FFU +#define PCR_I2C0_SCLK_DIV_NUM_M (PCR_I2C0_SCLK_DIV_NUM_V << PCR_I2C0_SCLK_DIV_NUM_S) +#define PCR_I2C0_SCLK_DIV_NUM_V 0x000000FFU +#define PCR_I2C0_SCLK_DIV_NUM_S 12 +/** PCR_I2C0_SCLK_SEL : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: FOSC. + */ +#define PCR_I2C0_SCLK_SEL (BIT(20)) +#define PCR_I2C0_SCLK_SEL_M (PCR_I2C0_SCLK_SEL_V << PCR_I2C0_SCLK_SEL_S) +#define PCR_I2C0_SCLK_SEL_V 0x00000001U +#define PCR_I2C0_SCLK_SEL_S 20 +/** PCR_I2C0_SCLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable i2c function clock + */ +#define PCR_I2C0_SCLK_EN (BIT(22)) +#define PCR_I2C0_SCLK_EN_M (PCR_I2C0_SCLK_EN_V << PCR_I2C0_SCLK_EN_S) +#define PCR_I2C0_SCLK_EN_V 0x00000001U +#define PCR_I2C0_SCLK_EN_S 22 + +/** PCR_I2C1_CONF_REG register + * I2C configuration register + */ +#define PCR_I2C1_CONF_REG (DR_REG_PCR_BASE + 0x28) +/** PCR_I2C1_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable i2c apb clock + */ +#define PCR_I2C1_CLK_EN (BIT(0)) +#define PCR_I2C1_CLK_EN_M (PCR_I2C1_CLK_EN_V << PCR_I2C1_CLK_EN_S) +#define PCR_I2C1_CLK_EN_V 0x00000001U +#define PCR_I2C1_CLK_EN_S 0 +/** PCR_I2C1_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset i2c module + */ +#define PCR_I2C1_RST_EN (BIT(1)) +#define PCR_I2C1_RST_EN_M (PCR_I2C1_RST_EN_V << PCR_I2C1_RST_EN_S) +#define PCR_I2C1_RST_EN_V 0x00000001U +#define PCR_I2C1_RST_EN_S 1 +/** PCR_I2C1_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset i2c1 module + */ +#define PCR_I2C1_READY (BIT(2)) +#define PCR_I2C1_READY_M (PCR_I2C1_READY_V << PCR_I2C1_READY_S) +#define PCR_I2C1_READY_V 0x00000001U +#define PCR_I2C1_READY_S 2 + +/** PCR_I2C1_SCLK_CONF_REG register + * I2C_SCLK configuration register + */ +#define PCR_I2C1_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x2c) +/** PCR_I2C1_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the i2c function clock. + */ +#define PCR_I2C1_SCLK_DIV_A 0x0000003FU +#define PCR_I2C1_SCLK_DIV_A_M (PCR_I2C1_SCLK_DIV_A_V << PCR_I2C1_SCLK_DIV_A_S) +#define PCR_I2C1_SCLK_DIV_A_V 0x0000003FU +#define PCR_I2C1_SCLK_DIV_A_S 0 +/** PCR_I2C1_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the i2c function clock. + */ +#define PCR_I2C1_SCLK_DIV_B 0x0000003FU +#define PCR_I2C1_SCLK_DIV_B_M (PCR_I2C1_SCLK_DIV_B_V << PCR_I2C1_SCLK_DIV_B_S) +#define PCR_I2C1_SCLK_DIV_B_V 0x0000003FU +#define PCR_I2C1_SCLK_DIV_B_S 6 +/** PCR_I2C1_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the i2c function clock. + */ +#define PCR_I2C1_SCLK_DIV_NUM 0x000000FFU +#define PCR_I2C1_SCLK_DIV_NUM_M (PCR_I2C1_SCLK_DIV_NUM_V << PCR_I2C1_SCLK_DIV_NUM_S) +#define PCR_I2C1_SCLK_DIV_NUM_V 0x000000FFU +#define PCR_I2C1_SCLK_DIV_NUM_S 12 +/** PCR_I2C1_SCLK_SEL : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: FOSC. + */ +#define PCR_I2C1_SCLK_SEL (BIT(20)) +#define PCR_I2C1_SCLK_SEL_M (PCR_I2C1_SCLK_SEL_V << PCR_I2C1_SCLK_SEL_S) +#define PCR_I2C1_SCLK_SEL_V 0x00000001U +#define PCR_I2C1_SCLK_SEL_S 20 +/** PCR_I2C1_SCLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable i2c function clock + */ +#define PCR_I2C1_SCLK_EN (BIT(22)) +#define PCR_I2C1_SCLK_EN_M (PCR_I2C1_SCLK_EN_V << PCR_I2C1_SCLK_EN_S) +#define PCR_I2C1_SCLK_EN_V 0x00000001U +#define PCR_I2C1_SCLK_EN_S 22 + +/** PCR_UHCI_CONF_REG register + * UHCI configuration register + */ +#define PCR_UHCI_CONF_REG (DR_REG_PCR_BASE + 0x30) +/** PCR_UHCI_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable uhci clock + */ +#define PCR_UHCI_CLK_EN (BIT(0)) +#define PCR_UHCI_CLK_EN_M (PCR_UHCI_CLK_EN_V << PCR_UHCI_CLK_EN_S) +#define PCR_UHCI_CLK_EN_V 0x00000001U +#define PCR_UHCI_CLK_EN_S 0 +/** PCR_UHCI_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset uhci module + */ +#define PCR_UHCI_RST_EN (BIT(1)) +#define PCR_UHCI_RST_EN_M (PCR_UHCI_RST_EN_V << PCR_UHCI_RST_EN_S) +#define PCR_UHCI_RST_EN_V 0x00000001U +#define PCR_UHCI_RST_EN_S 1 +/** PCR_UHCI_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset uhci module + */ +#define PCR_UHCI_READY (BIT(2)) +#define PCR_UHCI_READY_M (PCR_UHCI_READY_V << PCR_UHCI_READY_S) +#define PCR_UHCI_READY_V 0x00000001U +#define PCR_UHCI_READY_S 2 + +/** PCR_RMT_CONF_REG register + * RMT configuration register + */ +#define PCR_RMT_CONF_REG (DR_REG_PCR_BASE + 0x34) +/** PCR_RMT_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable rmt apb clock + */ +#define PCR_RMT_CLK_EN (BIT(0)) +#define PCR_RMT_CLK_EN_M (PCR_RMT_CLK_EN_V << PCR_RMT_CLK_EN_S) +#define PCR_RMT_CLK_EN_V 0x00000001U +#define PCR_RMT_CLK_EN_S 0 +/** PCR_RMT_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset rmt module + */ +#define PCR_RMT_RST_EN (BIT(1)) +#define PCR_RMT_RST_EN_M (PCR_RMT_RST_EN_V << PCR_RMT_RST_EN_S) +#define PCR_RMT_RST_EN_V 0x00000001U +#define PCR_RMT_RST_EN_S 1 +/** PCR_RMT_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset rmt module + */ +#define PCR_RMT_READY (BIT(2)) +#define PCR_RMT_READY_M (PCR_RMT_READY_V << PCR_RMT_READY_S) +#define PCR_RMT_READY_V 0x00000001U +#define PCR_RMT_READY_S 2 + +/** PCR_RMT_SCLK_CONF_REG register + * RMT_SCLK configuration register + */ +#define PCR_RMT_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x38) +/** PCR_RMT_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the rmt function clock. + */ +#define PCR_RMT_SCLK_DIV_A 0x0000003FU +#define PCR_RMT_SCLK_DIV_A_M (PCR_RMT_SCLK_DIV_A_V << PCR_RMT_SCLK_DIV_A_S) +#define PCR_RMT_SCLK_DIV_A_V 0x0000003FU +#define PCR_RMT_SCLK_DIV_A_S 0 +/** PCR_RMT_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the rmt function clock. + */ +#define PCR_RMT_SCLK_DIV_B 0x0000003FU +#define PCR_RMT_SCLK_DIV_B_M (PCR_RMT_SCLK_DIV_B_V << PCR_RMT_SCLK_DIV_B_S) +#define PCR_RMT_SCLK_DIV_B_V 0x0000003FU +#define PCR_RMT_SCLK_DIV_B_S 6 +/** PCR_RMT_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 1; + * The integral part of the frequency divider factor of the rmt function clock. + */ +#define PCR_RMT_SCLK_DIV_NUM 0x000000FFU +#define PCR_RMT_SCLK_DIV_NUM_M (PCR_RMT_SCLK_DIV_NUM_V << PCR_RMT_SCLK_DIV_NUM_S) +#define PCR_RMT_SCLK_DIV_NUM_V 0x000000FFU +#define PCR_RMT_SCLK_DIV_NUM_S 12 +/** PCR_RMT_SCLK_SEL : R/W; bitpos: [20]; default: 1; + * set this field to select clock-source. 0: do not select anyone clock, 1(default): + * 80MHz, 2: FOSC, 3: XTAL. + */ +#define PCR_RMT_SCLK_SEL (BIT(20)) +#define PCR_RMT_SCLK_SEL_M (PCR_RMT_SCLK_SEL_V << PCR_RMT_SCLK_SEL_S) +#define PCR_RMT_SCLK_SEL_V 0x00000001U +#define PCR_RMT_SCLK_SEL_S 20 +/** PCR_RMT_SCLK_EN : R/W; bitpos: [21]; default: 1; + * Set 1 to enable rmt function clock + */ +#define PCR_RMT_SCLK_EN (BIT(21)) +#define PCR_RMT_SCLK_EN_M (PCR_RMT_SCLK_EN_V << PCR_RMT_SCLK_EN_S) +#define PCR_RMT_SCLK_EN_V 0x00000001U +#define PCR_RMT_SCLK_EN_S 21 + +/** PCR_LEDC_CONF_REG register + * LEDC configuration register + */ +#define PCR_LEDC_CONF_REG (DR_REG_PCR_BASE + 0x3c) +/** PCR_LEDC_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable ledc apb clock + */ +#define PCR_LEDC_CLK_EN (BIT(0)) +#define PCR_LEDC_CLK_EN_M (PCR_LEDC_CLK_EN_V << PCR_LEDC_CLK_EN_S) +#define PCR_LEDC_CLK_EN_V 0x00000001U +#define PCR_LEDC_CLK_EN_S 0 +/** PCR_LEDC_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset ledc module + */ +#define PCR_LEDC_RST_EN (BIT(1)) +#define PCR_LEDC_RST_EN_M (PCR_LEDC_RST_EN_V << PCR_LEDC_RST_EN_S) +#define PCR_LEDC_RST_EN_V 0x00000001U +#define PCR_LEDC_RST_EN_S 1 +/** PCR_LEDC_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset ledc module + */ +#define PCR_LEDC_READY (BIT(2)) +#define PCR_LEDC_READY_M (PCR_LEDC_READY_V << PCR_LEDC_READY_S) +#define PCR_LEDC_READY_V 0x00000001U +#define PCR_LEDC_READY_S 2 + +/** PCR_LEDC_SCLK_CONF_REG register + * LEDC_SCLK configuration register + */ +#define PCR_LEDC_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x40) +/** PCR_LEDC_SCLK_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): do not select anyone clock, 1: + * 80MHz, 2: FOSC, 3: XTAL. + */ +#define PCR_LEDC_SCLK_SEL 0x00000003U +#define PCR_LEDC_SCLK_SEL_M (PCR_LEDC_SCLK_SEL_V << PCR_LEDC_SCLK_SEL_S) +#define PCR_LEDC_SCLK_SEL_V 0x00000003U +#define PCR_LEDC_SCLK_SEL_S 20 +/** PCR_LEDC_SCLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable ledc function clock + */ +#define PCR_LEDC_SCLK_EN (BIT(22)) +#define PCR_LEDC_SCLK_EN_M (PCR_LEDC_SCLK_EN_V << PCR_LEDC_SCLK_EN_S) +#define PCR_LEDC_SCLK_EN_V 0x00000001U +#define PCR_LEDC_SCLK_EN_S 22 + +/** PCR_TIMERGROUP0_CONF_REG register + * TIMERGROUP0 configuration register + */ +#define PCR_TIMERGROUP0_CONF_REG (DR_REG_PCR_BASE + 0x44) +/** PCR_TG0_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable timer_group0 apb clock + */ +#define PCR_TG0_CLK_EN (BIT(0)) +#define PCR_TG0_CLK_EN_M (PCR_TG0_CLK_EN_V << PCR_TG0_CLK_EN_S) +#define PCR_TG0_CLK_EN_V 0x00000001U +#define PCR_TG0_CLK_EN_S 0 +/** PCR_TG0_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset timer_group0 module + */ +#define PCR_TG0_RST_EN (BIT(1)) +#define PCR_TG0_RST_EN_M (PCR_TG0_RST_EN_V << PCR_TG0_RST_EN_S) +#define PCR_TG0_RST_EN_V 0x00000001U +#define PCR_TG0_RST_EN_S 1 +/** PCR_TG0_WDT_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset timer_group0 wdt module + */ +#define PCR_TG0_WDT_READY (BIT(2)) +#define PCR_TG0_WDT_READY_M (PCR_TG0_WDT_READY_V << PCR_TG0_WDT_READY_S) +#define PCR_TG0_WDT_READY_V 0x00000001U +#define PCR_TG0_WDT_READY_S 2 +/** PCR_TG0_TIMER0_READY : RO; bitpos: [3]; default: 1; + * Query this field after reset timer_group0 timer0 module + */ +#define PCR_TG0_TIMER0_READY (BIT(3)) +#define PCR_TG0_TIMER0_READY_M (PCR_TG0_TIMER0_READY_V << PCR_TG0_TIMER0_READY_S) +#define PCR_TG0_TIMER0_READY_V 0x00000001U +#define PCR_TG0_TIMER0_READY_S 3 +/** PCR_TG0_TIMER1_READY : RO; bitpos: [4]; default: 1; + * reserved + */ +#define PCR_TG0_TIMER1_READY (BIT(4)) +#define PCR_TG0_TIMER1_READY_M (PCR_TG0_TIMER1_READY_V << PCR_TG0_TIMER1_READY_S) +#define PCR_TG0_TIMER1_READY_V 0x00000001U +#define PCR_TG0_TIMER1_READY_S 4 + +/** PCR_TIMERGROUP0_TIMER_CLK_CONF_REG register + * TIMERGROUP0_TIMER_CLK configuration register + */ +#define PCR_TIMERGROUP0_TIMER_CLK_CONF_REG (DR_REG_PCR_BASE + 0x48) +/** PCR_TG0_TIMER_CLK_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: + * reserved. + */ +#define PCR_TG0_TIMER_CLK_SEL 0x00000003U +#define PCR_TG0_TIMER_CLK_SEL_M (PCR_TG0_TIMER_CLK_SEL_V << PCR_TG0_TIMER_CLK_SEL_S) +#define PCR_TG0_TIMER_CLK_SEL_V 0x00000003U +#define PCR_TG0_TIMER_CLK_SEL_S 20 +/** PCR_TG0_TIMER_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group0 timer clock + */ +#define PCR_TG0_TIMER_CLK_EN (BIT(22)) +#define PCR_TG0_TIMER_CLK_EN_M (PCR_TG0_TIMER_CLK_EN_V << PCR_TG0_TIMER_CLK_EN_S) +#define PCR_TG0_TIMER_CLK_EN_V 0x00000001U +#define PCR_TG0_TIMER_CLK_EN_S 22 + +/** PCR_TIMERGROUP0_WDT_CLK_CONF_REG register + * TIMERGROUP0_WDT_CLK configuration register + */ +#define PCR_TIMERGROUP0_WDT_CLK_CONF_REG (DR_REG_PCR_BASE + 0x4c) +/** PCR_TG0_WDT_CLK_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: + * reserved. + */ +#define PCR_TG0_WDT_CLK_SEL 0x00000003U +#define PCR_TG0_WDT_CLK_SEL_M (PCR_TG0_WDT_CLK_SEL_V << PCR_TG0_WDT_CLK_SEL_S) +#define PCR_TG0_WDT_CLK_SEL_V 0x00000003U +#define PCR_TG0_WDT_CLK_SEL_S 20 +/** PCR_TG0_WDT_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group0 wdt clock + */ +#define PCR_TG0_WDT_CLK_EN (BIT(22)) +#define PCR_TG0_WDT_CLK_EN_M (PCR_TG0_WDT_CLK_EN_V << PCR_TG0_WDT_CLK_EN_S) +#define PCR_TG0_WDT_CLK_EN_V 0x00000001U +#define PCR_TG0_WDT_CLK_EN_S 22 + +/** PCR_TIMERGROUP1_CONF_REG register + * TIMERGROUP1 configuration register + */ +#define PCR_TIMERGROUP1_CONF_REG (DR_REG_PCR_BASE + 0x50) +/** PCR_TG1_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable timer_group1 apb clock + */ +#define PCR_TG1_CLK_EN (BIT(0)) +#define PCR_TG1_CLK_EN_M (PCR_TG1_CLK_EN_V << PCR_TG1_CLK_EN_S) +#define PCR_TG1_CLK_EN_V 0x00000001U +#define PCR_TG1_CLK_EN_S 0 +/** PCR_TG1_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset timer_group1 module + */ +#define PCR_TG1_RST_EN (BIT(1)) +#define PCR_TG1_RST_EN_M (PCR_TG1_RST_EN_V << PCR_TG1_RST_EN_S) +#define PCR_TG1_RST_EN_V 0x00000001U +#define PCR_TG1_RST_EN_S 1 +/** PCR_TG1_WDT_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset timer_group1 wdt module + */ +#define PCR_TG1_WDT_READY (BIT(2)) +#define PCR_TG1_WDT_READY_M (PCR_TG1_WDT_READY_V << PCR_TG1_WDT_READY_S) +#define PCR_TG1_WDT_READY_V 0x00000001U +#define PCR_TG1_WDT_READY_S 2 +/** PCR_TG1_TIMER0_READY : RO; bitpos: [3]; default: 1; + * Query this field after reset timer_group1 timer0 module + */ +#define PCR_TG1_TIMER0_READY (BIT(3)) +#define PCR_TG1_TIMER0_READY_M (PCR_TG1_TIMER0_READY_V << PCR_TG1_TIMER0_READY_S) +#define PCR_TG1_TIMER0_READY_V 0x00000001U +#define PCR_TG1_TIMER0_READY_S 3 +/** PCR_TG1_TIMER1_READY : RO; bitpos: [4]; default: 1; + * reserved + */ +#define PCR_TG1_TIMER1_READY (BIT(4)) +#define PCR_TG1_TIMER1_READY_M (PCR_TG1_TIMER1_READY_V << PCR_TG1_TIMER1_READY_S) +#define PCR_TG1_TIMER1_READY_V 0x00000001U +#define PCR_TG1_TIMER1_READY_S 4 + +/** PCR_TIMERGROUP1_TIMER_CLK_CONF_REG register + * TIMERGROUP1_TIMER_CLK configuration register + */ +#define PCR_TIMERGROUP1_TIMER_CLK_CONF_REG (DR_REG_PCR_BASE + 0x54) +/** PCR_TG1_TIMER_CLK_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: + * reserved. + */ +#define PCR_TG1_TIMER_CLK_SEL 0x00000003U +#define PCR_TG1_TIMER_CLK_SEL_M (PCR_TG1_TIMER_CLK_SEL_V << PCR_TG1_TIMER_CLK_SEL_S) +#define PCR_TG1_TIMER_CLK_SEL_V 0x00000003U +#define PCR_TG1_TIMER_CLK_SEL_S 20 +/** PCR_TG1_TIMER_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group1 timer clock + */ +#define PCR_TG1_TIMER_CLK_EN (BIT(22)) +#define PCR_TG1_TIMER_CLK_EN_M (PCR_TG1_TIMER_CLK_EN_V << PCR_TG1_TIMER_CLK_EN_S) +#define PCR_TG1_TIMER_CLK_EN_V 0x00000001U +#define PCR_TG1_TIMER_CLK_EN_S 22 + +/** PCR_TIMERGROUP1_WDT_CLK_CONF_REG register + * TIMERGROUP1_WDT_CLK configuration register + */ +#define PCR_TIMERGROUP1_WDT_CLK_CONF_REG (DR_REG_PCR_BASE + 0x58) +/** PCR_TG1_WDT_CLK_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: + * reserved. + */ +#define PCR_TG1_WDT_CLK_SEL 0x00000003U +#define PCR_TG1_WDT_CLK_SEL_M (PCR_TG1_WDT_CLK_SEL_V << PCR_TG1_WDT_CLK_SEL_S) +#define PCR_TG1_WDT_CLK_SEL_V 0x00000003U +#define PCR_TG1_WDT_CLK_SEL_S 20 +/** PCR_TG1_WDT_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group0 wdt clock + */ +#define PCR_TG1_WDT_CLK_EN (BIT(22)) +#define PCR_TG1_WDT_CLK_EN_M (PCR_TG1_WDT_CLK_EN_V << PCR_TG1_WDT_CLK_EN_S) +#define PCR_TG1_WDT_CLK_EN_V 0x00000001U +#define PCR_TG1_WDT_CLK_EN_S 22 + +/** PCR_SYSTIMER_CONF_REG register + * SYSTIMER configuration register + */ +#define PCR_SYSTIMER_CONF_REG (DR_REG_PCR_BASE + 0x5c) +/** PCR_SYSTIMER_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable systimer apb clock + */ +#define PCR_SYSTIMER_CLK_EN (BIT(0)) +#define PCR_SYSTIMER_CLK_EN_M (PCR_SYSTIMER_CLK_EN_V << PCR_SYSTIMER_CLK_EN_S) +#define PCR_SYSTIMER_CLK_EN_V 0x00000001U +#define PCR_SYSTIMER_CLK_EN_S 0 +/** PCR_SYSTIMER_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset systimer module + */ +#define PCR_SYSTIMER_RST_EN (BIT(1)) +#define PCR_SYSTIMER_RST_EN_M (PCR_SYSTIMER_RST_EN_V << PCR_SYSTIMER_RST_EN_S) +#define PCR_SYSTIMER_RST_EN_V 0x00000001U +#define PCR_SYSTIMER_RST_EN_S 1 +/** PCR_SYSTIMER_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset systimer module + */ +#define PCR_SYSTIMER_READY (BIT(2)) +#define PCR_SYSTIMER_READY_M (PCR_SYSTIMER_READY_V << PCR_SYSTIMER_READY_S) +#define PCR_SYSTIMER_READY_V 0x00000001U +#define PCR_SYSTIMER_READY_S 2 + +/** PCR_SYSTIMER_FUNC_CLK_CONF_REG register + * SYSTIMER_FUNC_CLK configuration register + */ +#define PCR_SYSTIMER_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x60) +/** PCR_SYSTIMER_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: FOSC. + */ +#define PCR_SYSTIMER_FUNC_CLK_SEL (BIT(20)) +#define PCR_SYSTIMER_FUNC_CLK_SEL_M (PCR_SYSTIMER_FUNC_CLK_SEL_V << PCR_SYSTIMER_FUNC_CLK_SEL_S) +#define PCR_SYSTIMER_FUNC_CLK_SEL_V 0x00000001U +#define PCR_SYSTIMER_FUNC_CLK_SEL_S 20 +/** PCR_SYSTIMER_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable systimer function clock + */ +#define PCR_SYSTIMER_FUNC_CLK_EN (BIT(22)) +#define PCR_SYSTIMER_FUNC_CLK_EN_M (PCR_SYSTIMER_FUNC_CLK_EN_V << PCR_SYSTIMER_FUNC_CLK_EN_S) +#define PCR_SYSTIMER_FUNC_CLK_EN_V 0x00000001U +#define PCR_SYSTIMER_FUNC_CLK_EN_S 22 + +/** PCR_TWAI0_CONF_REG register + * TWAI0 configuration register + */ +#define PCR_TWAI0_CONF_REG (DR_REG_PCR_BASE + 0x64) +/** PCR_TWAI0_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable twai0 apb clock + */ +#define PCR_TWAI0_CLK_EN (BIT(0)) +#define PCR_TWAI0_CLK_EN_M (PCR_TWAI0_CLK_EN_V << PCR_TWAI0_CLK_EN_S) +#define PCR_TWAI0_CLK_EN_V 0x00000001U +#define PCR_TWAI0_CLK_EN_S 0 +/** PCR_TWAI0_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset twai0 module + */ +#define PCR_TWAI0_RST_EN (BIT(1)) +#define PCR_TWAI0_RST_EN_M (PCR_TWAI0_RST_EN_V << PCR_TWAI0_RST_EN_S) +#define PCR_TWAI0_RST_EN_V 0x00000001U +#define PCR_TWAI0_RST_EN_S 1 +/** PCR_TWAI0_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset twai0 module + */ +#define PCR_TWAI0_READY (BIT(2)) +#define PCR_TWAI0_READY_M (PCR_TWAI0_READY_V << PCR_TWAI0_READY_S) +#define PCR_TWAI0_READY_V 0x00000001U +#define PCR_TWAI0_READY_S 2 + +/** PCR_TWAI0_FUNC_CLK_CONF_REG register + * TWAI0_FUNC_CLK configuration register + */ +#define PCR_TWAI0_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x68) +/** PCR_TWAI0_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: FOSC. + */ +#define PCR_TWAI0_FUNC_CLK_SEL (BIT(20)) +#define PCR_TWAI0_FUNC_CLK_SEL_M (PCR_TWAI0_FUNC_CLK_SEL_V << PCR_TWAI0_FUNC_CLK_SEL_S) +#define PCR_TWAI0_FUNC_CLK_SEL_V 0x00000001U +#define PCR_TWAI0_FUNC_CLK_SEL_S 20 +/** PCR_TWAI0_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable twai0 function clock + */ +#define PCR_TWAI0_FUNC_CLK_EN (BIT(22)) +#define PCR_TWAI0_FUNC_CLK_EN_M (PCR_TWAI0_FUNC_CLK_EN_V << PCR_TWAI0_FUNC_CLK_EN_S) +#define PCR_TWAI0_FUNC_CLK_EN_V 0x00000001U +#define PCR_TWAI0_FUNC_CLK_EN_S 22 + +/** PCR_I2S_CONF_REG register + * I2S configuration register + */ +#define PCR_I2S_CONF_REG (DR_REG_PCR_BASE + 0x6c) +/** PCR_I2S_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable i2s apb clock + */ +#define PCR_I2S_CLK_EN (BIT(0)) +#define PCR_I2S_CLK_EN_M (PCR_I2S_CLK_EN_V << PCR_I2S_CLK_EN_S) +#define PCR_I2S_CLK_EN_V 0x00000001U +#define PCR_I2S_CLK_EN_S 0 +/** PCR_I2S_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset i2s module + */ +#define PCR_I2S_RST_EN (BIT(1)) +#define PCR_I2S_RST_EN_M (PCR_I2S_RST_EN_V << PCR_I2S_RST_EN_S) +#define PCR_I2S_RST_EN_V 0x00000001U +#define PCR_I2S_RST_EN_S 1 +/** PCR_I2S_RX_READY : RO; bitpos: [2]; default: 1; + * Query this field before using i2s rx function, after reset i2s module + */ +#define PCR_I2S_RX_READY (BIT(2)) +#define PCR_I2S_RX_READY_M (PCR_I2S_RX_READY_V << PCR_I2S_RX_READY_S) +#define PCR_I2S_RX_READY_V 0x00000001U +#define PCR_I2S_RX_READY_S 2 +/** PCR_I2S_TX_READY : RO; bitpos: [3]; default: 1; + * Query this field before using i2s tx function, after reset i2s module + */ +#define PCR_I2S_TX_READY (BIT(3)) +#define PCR_I2S_TX_READY_M (PCR_I2S_TX_READY_V << PCR_I2S_TX_READY_S) +#define PCR_I2S_TX_READY_V 0x00000001U +#define PCR_I2S_TX_READY_S 3 + +/** PCR_I2S_TX_CLKM_CONF_REG register + * I2S_TX_CLKM configuration register + */ +#define PCR_I2S_TX_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x70) +/** PCR_I2S_TX_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 2; + * Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be + * (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= + * a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * + * (n+1)-div] + y * (n+1)-div. + */ +#define PCR_I2S_TX_CLKM_DIV_NUM 0x000000FFU +#define PCR_I2S_TX_CLKM_DIV_NUM_M (PCR_I2S_TX_CLKM_DIV_NUM_V << PCR_I2S_TX_CLKM_DIV_NUM_S) +#define PCR_I2S_TX_CLKM_DIV_NUM_V 0x000000FFU +#define PCR_I2S_TX_CLKM_DIV_NUM_S 12 +/** PCR_I2S_TX_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; + * Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: + * I2S_MCLK_in. + */ +#define PCR_I2S_TX_CLKM_SEL 0x00000003U +#define PCR_I2S_TX_CLKM_SEL_M (PCR_I2S_TX_CLKM_SEL_V << PCR_I2S_TX_CLKM_SEL_S) +#define PCR_I2S_TX_CLKM_SEL_V 0x00000003U +#define PCR_I2S_TX_CLKM_SEL_S 20 +/** PCR_I2S_TX_CLKM_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable i2s_tx function clock + */ +#define PCR_I2S_TX_CLKM_EN (BIT(22)) +#define PCR_I2S_TX_CLKM_EN_M (PCR_I2S_TX_CLKM_EN_V << PCR_I2S_TX_CLKM_EN_S) +#define PCR_I2S_TX_CLKM_EN_V 0x00000001U +#define PCR_I2S_TX_CLKM_EN_S 22 + +/** PCR_I2S_TX_CLKM_DIV_CONF_REG register + * I2S_TX_CLKM_DIV configuration register + */ +#define PCR_I2S_TX_CLKM_DIV_CONF_REG (DR_REG_PCR_BASE + 0x74) +/** PCR_I2S_TX_CLKM_DIV_Z : R/W; bitpos: [8:0]; default: 0; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of + * I2S_TX_CLKM_DIV_Z is (a-b). + */ +#define PCR_I2S_TX_CLKM_DIV_Z 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_Z_M (PCR_I2S_TX_CLKM_DIV_Z_V << PCR_I2S_TX_CLKM_DIV_Z_S) +#define PCR_I2S_TX_CLKM_DIV_Z_V 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_Z_S 0 +/** PCR_I2S_TX_CLKM_DIV_Y : R/W; bitpos: [17:9]; default: 1; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of + * I2S_TX_CLKM_DIV_Y is (a%(a-b)). + */ +#define PCR_I2S_TX_CLKM_DIV_Y 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_Y_M (PCR_I2S_TX_CLKM_DIV_Y_V << PCR_I2S_TX_CLKM_DIV_Y_S) +#define PCR_I2S_TX_CLKM_DIV_Y_V 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_Y_S 9 +/** PCR_I2S_TX_CLKM_DIV_X : R/W; bitpos: [26:18]; default: 0; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value + * of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1. + */ +#define PCR_I2S_TX_CLKM_DIV_X 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_X_M (PCR_I2S_TX_CLKM_DIV_X_V << PCR_I2S_TX_CLKM_DIV_X_S) +#define PCR_I2S_TX_CLKM_DIV_X_V 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_X_S 18 +/** PCR_I2S_TX_CLKM_DIV_YN1 : R/W; bitpos: [27]; default: 0; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of + * I2S_TX_CLKM_DIV_YN1 is 1. + */ +#define PCR_I2S_TX_CLKM_DIV_YN1 (BIT(27)) +#define PCR_I2S_TX_CLKM_DIV_YN1_M (PCR_I2S_TX_CLKM_DIV_YN1_V << PCR_I2S_TX_CLKM_DIV_YN1_S) +#define PCR_I2S_TX_CLKM_DIV_YN1_V 0x00000001U +#define PCR_I2S_TX_CLKM_DIV_YN1_S 27 + +/** PCR_I2S_RX_CLKM_CONF_REG register + * I2S_RX_CLKM configuration register + */ +#define PCR_I2S_RX_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x78) +/** PCR_I2S_RX_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 2; + * Integral I2S clock divider value + */ +#define PCR_I2S_RX_CLKM_DIV_NUM 0x000000FFU +#define PCR_I2S_RX_CLKM_DIV_NUM_M (PCR_I2S_RX_CLKM_DIV_NUM_V << PCR_I2S_RX_CLKM_DIV_NUM_S) +#define PCR_I2S_RX_CLKM_DIV_NUM_V 0x000000FFU +#define PCR_I2S_RX_CLKM_DIV_NUM_S 12 +/** PCR_I2S_RX_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; + * Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in. + */ +#define PCR_I2S_RX_CLKM_SEL 0x00000003U +#define PCR_I2S_RX_CLKM_SEL_M (PCR_I2S_RX_CLKM_SEL_V << PCR_I2S_RX_CLKM_SEL_S) +#define PCR_I2S_RX_CLKM_SEL_V 0x00000003U +#define PCR_I2S_RX_CLKM_SEL_S 20 +/** PCR_I2S_RX_CLKM_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable i2s_rx function clock + */ +#define PCR_I2S_RX_CLKM_EN (BIT(22)) +#define PCR_I2S_RX_CLKM_EN_M (PCR_I2S_RX_CLKM_EN_V << PCR_I2S_RX_CLKM_EN_S) +#define PCR_I2S_RX_CLKM_EN_V 0x00000001U +#define PCR_I2S_RX_CLKM_EN_S 22 +/** PCR_I2S_MCLK_SEL : R/W; bitpos: [23]; default: 0; + * This field is used to select master-clock. 0(default): clk_i2s_rx, 1: clk_i2s_tx + */ +#define PCR_I2S_MCLK_SEL (BIT(23)) +#define PCR_I2S_MCLK_SEL_M (PCR_I2S_MCLK_SEL_V << PCR_I2S_MCLK_SEL_S) +#define PCR_I2S_MCLK_SEL_V 0x00000001U +#define PCR_I2S_MCLK_SEL_S 23 + +/** PCR_I2S_RX_CLKM_DIV_CONF_REG register + * I2S_RX_CLKM_DIV configuration register + */ +#define PCR_I2S_RX_CLKM_DIV_CONF_REG (DR_REG_PCR_BASE + 0x7c) +/** PCR_I2S_RX_CLKM_DIV_Z : R/W; bitpos: [8:0]; default: 0; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of + * I2S_RX_CLKM_DIV_Z is (a-b). + */ +#define PCR_I2S_RX_CLKM_DIV_Z 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_Z_M (PCR_I2S_RX_CLKM_DIV_Z_V << PCR_I2S_RX_CLKM_DIV_Z_S) +#define PCR_I2S_RX_CLKM_DIV_Z_V 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_Z_S 0 +/** PCR_I2S_RX_CLKM_DIV_Y : R/W; bitpos: [17:9]; default: 1; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of + * I2S_RX_CLKM_DIV_Y is (a%(a-b)). + */ +#define PCR_I2S_RX_CLKM_DIV_Y 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_Y_M (PCR_I2S_RX_CLKM_DIV_Y_V << PCR_I2S_RX_CLKM_DIV_Y_S) +#define PCR_I2S_RX_CLKM_DIV_Y_V 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_Y_S 9 +/** PCR_I2S_RX_CLKM_DIV_X : R/W; bitpos: [26:18]; default: 0; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value + * of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1. + */ +#define PCR_I2S_RX_CLKM_DIV_X 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_X_M (PCR_I2S_RX_CLKM_DIV_X_V << PCR_I2S_RX_CLKM_DIV_X_S) +#define PCR_I2S_RX_CLKM_DIV_X_V 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_X_S 18 +/** PCR_I2S_RX_CLKM_DIV_YN1 : R/W; bitpos: [27]; default: 0; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of + * I2S_RX_CLKM_DIV_YN1 is 1. + */ +#define PCR_I2S_RX_CLKM_DIV_YN1 (BIT(27)) +#define PCR_I2S_RX_CLKM_DIV_YN1_M (PCR_I2S_RX_CLKM_DIV_YN1_V << PCR_I2S_RX_CLKM_DIV_YN1_S) +#define PCR_I2S_RX_CLKM_DIV_YN1_V 0x00000001U +#define PCR_I2S_RX_CLKM_DIV_YN1_S 27 + +/** PCR_SARADC_CONF_REG register + * SARADC configuration register + */ +#define PCR_SARADC_CONF_REG (DR_REG_PCR_BASE + 0x80) +/** PCR_SARADC_CLK_EN : R/W; bitpos: [0]; default: 1; + * no use + */ +#define PCR_SARADC_CLK_EN (BIT(0)) +#define PCR_SARADC_CLK_EN_M (PCR_SARADC_CLK_EN_V << PCR_SARADC_CLK_EN_S) +#define PCR_SARADC_CLK_EN_V 0x00000001U +#define PCR_SARADC_CLK_EN_S 0 +/** PCR_SARADC_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset function_register of saradc module + */ +#define PCR_SARADC_RST_EN (BIT(1)) +#define PCR_SARADC_RST_EN_M (PCR_SARADC_RST_EN_V << PCR_SARADC_RST_EN_S) +#define PCR_SARADC_RST_EN_V 0x00000001U +#define PCR_SARADC_RST_EN_S 1 +/** PCR_SARADC_REG_CLK_EN : R/W; bitpos: [2]; default: 1; + * Set 1 to enable saradc apb clock + */ +#define PCR_SARADC_REG_CLK_EN (BIT(2)) +#define PCR_SARADC_REG_CLK_EN_M (PCR_SARADC_REG_CLK_EN_V << PCR_SARADC_REG_CLK_EN_S) +#define PCR_SARADC_REG_CLK_EN_V 0x00000001U +#define PCR_SARADC_REG_CLK_EN_S 2 +/** PCR_SARADC_REG_RST_EN : R/W; bitpos: [3]; default: 0; + * Set 0 to reset apb_register of saradc module + */ +#define PCR_SARADC_REG_RST_EN (BIT(3)) +#define PCR_SARADC_REG_RST_EN_M (PCR_SARADC_REG_RST_EN_V << PCR_SARADC_REG_RST_EN_S) +#define PCR_SARADC_REG_RST_EN_V 0x00000001U +#define PCR_SARADC_REG_RST_EN_S 3 + +/** PCR_SARADC_CLKM_CONF_REG register + * SARADC_CLKM configuration register + */ +#define PCR_SARADC_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x84) +/** PCR_SARADC_CLKM_DIV_A : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the saradc function clock. + */ +#define PCR_SARADC_CLKM_DIV_A 0x0000003FU +#define PCR_SARADC_CLKM_DIV_A_M (PCR_SARADC_CLKM_DIV_A_V << PCR_SARADC_CLKM_DIV_A_S) +#define PCR_SARADC_CLKM_DIV_A_V 0x0000003FU +#define PCR_SARADC_CLKM_DIV_A_S 0 +/** PCR_SARADC_CLKM_DIV_B : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the saradc function clock. + */ +#define PCR_SARADC_CLKM_DIV_B 0x0000003FU +#define PCR_SARADC_CLKM_DIV_B_M (PCR_SARADC_CLKM_DIV_B_V << PCR_SARADC_CLKM_DIV_B_S) +#define PCR_SARADC_CLKM_DIV_B_V 0x0000003FU +#define PCR_SARADC_CLKM_DIV_B_S 6 +/** PCR_SARADC_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 4; + * The integral part of the frequency divider factor of the saradc function clock. + */ +#define PCR_SARADC_CLKM_DIV_NUM 0x000000FFU +#define PCR_SARADC_CLKM_DIV_NUM_M (PCR_SARADC_CLKM_DIV_NUM_V << PCR_SARADC_CLKM_DIV_NUM_S) +#define PCR_SARADC_CLKM_DIV_NUM_V 0x000000FFU +#define PCR_SARADC_CLKM_DIV_NUM_S 12 +/** PCR_SARADC_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3: + * reserved. + */ +#define PCR_SARADC_CLKM_SEL 0x00000003U +#define PCR_SARADC_CLKM_SEL_M (PCR_SARADC_CLKM_SEL_V << PCR_SARADC_CLKM_SEL_S) +#define PCR_SARADC_CLKM_SEL_V 0x00000003U +#define PCR_SARADC_CLKM_SEL_S 20 +/** PCR_SARADC_CLKM_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable saradc function clock + */ +#define PCR_SARADC_CLKM_EN (BIT(22)) +#define PCR_SARADC_CLKM_EN_M (PCR_SARADC_CLKM_EN_V << PCR_SARADC_CLKM_EN_S) +#define PCR_SARADC_CLKM_EN_V 0x00000001U +#define PCR_SARADC_CLKM_EN_S 22 + +/** PCR_TSENS_CLK_CONF_REG register + * TSENS_CLK configuration register + */ +#define PCR_TSENS_CLK_CONF_REG (DR_REG_PCR_BASE + 0x88) +/** PCR_TSENS_CLK_SEL : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0(default): FOSC, 1: XTAL. + */ +#define PCR_TSENS_CLK_SEL (BIT(20)) +#define PCR_TSENS_CLK_SEL_M (PCR_TSENS_CLK_SEL_V << PCR_TSENS_CLK_SEL_S) +#define PCR_TSENS_CLK_SEL_V 0x00000001U +#define PCR_TSENS_CLK_SEL_S 20 +/** PCR_TSENS_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable tsens clock + */ +#define PCR_TSENS_CLK_EN (BIT(22)) +#define PCR_TSENS_CLK_EN_M (PCR_TSENS_CLK_EN_V << PCR_TSENS_CLK_EN_S) +#define PCR_TSENS_CLK_EN_V 0x00000001U +#define PCR_TSENS_CLK_EN_S 22 +/** PCR_TSENS_RST_EN : R/W; bitpos: [23]; default: 0; + * Set 0 to reset tsens module + */ +#define PCR_TSENS_RST_EN (BIT(23)) +#define PCR_TSENS_RST_EN_M (PCR_TSENS_RST_EN_V << PCR_TSENS_RST_EN_S) +#define PCR_TSENS_RST_EN_V 0x00000001U +#define PCR_TSENS_RST_EN_S 23 + +/** PCR_USB_DEVICE_CONF_REG register + * USB_DEVICE configuration register + */ +#define PCR_USB_DEVICE_CONF_REG (DR_REG_PCR_BASE + 0x8c) +/** PCR_USB_DEVICE_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable usb_device clock + */ +#define PCR_USB_DEVICE_CLK_EN (BIT(0)) +#define PCR_USB_DEVICE_CLK_EN_M (PCR_USB_DEVICE_CLK_EN_V << PCR_USB_DEVICE_CLK_EN_S) +#define PCR_USB_DEVICE_CLK_EN_V 0x00000001U +#define PCR_USB_DEVICE_CLK_EN_S 0 +/** PCR_USB_DEVICE_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset usb_device module + */ +#define PCR_USB_DEVICE_RST_EN (BIT(1)) +#define PCR_USB_DEVICE_RST_EN_M (PCR_USB_DEVICE_RST_EN_V << PCR_USB_DEVICE_RST_EN_S) +#define PCR_USB_DEVICE_RST_EN_V 0x00000001U +#define PCR_USB_DEVICE_RST_EN_S 1 +/** PCR_USB_DEVICE_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset usb_device module + */ +#define PCR_USB_DEVICE_READY (BIT(2)) +#define PCR_USB_DEVICE_READY_M (PCR_USB_DEVICE_READY_V << PCR_USB_DEVICE_READY_S) +#define PCR_USB_DEVICE_READY_V 0x00000001U +#define PCR_USB_DEVICE_READY_S 2 + +/** PCR_INTMTX_CONF_REG register + * INTMTX configuration register + */ +#define PCR_INTMTX_CONF_REG (DR_REG_PCR_BASE + 0x90) +/** PCR_INTMTX_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable intmtx clock + */ +#define PCR_INTMTX_CLK_EN (BIT(0)) +#define PCR_INTMTX_CLK_EN_M (PCR_INTMTX_CLK_EN_V << PCR_INTMTX_CLK_EN_S) +#define PCR_INTMTX_CLK_EN_V 0x00000001U +#define PCR_INTMTX_CLK_EN_S 0 +/** PCR_INTMTX_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset intmtx module + */ +#define PCR_INTMTX_RST_EN (BIT(1)) +#define PCR_INTMTX_RST_EN_M (PCR_INTMTX_RST_EN_V << PCR_INTMTX_RST_EN_S) +#define PCR_INTMTX_RST_EN_V 0x00000001U +#define PCR_INTMTX_RST_EN_S 1 +/** PCR_INTMTX_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset intmtx module + */ +#define PCR_INTMTX_READY (BIT(2)) +#define PCR_INTMTX_READY_M (PCR_INTMTX_READY_V << PCR_INTMTX_READY_S) +#define PCR_INTMTX_READY_V 0x00000001U +#define PCR_INTMTX_READY_S 2 + +/** PCR_PCNT_CONF_REG register + * PCNT configuration register + */ +#define PCR_PCNT_CONF_REG (DR_REG_PCR_BASE + 0x94) +/** PCR_PCNT_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable pcnt clock + */ +#define PCR_PCNT_CLK_EN (BIT(0)) +#define PCR_PCNT_CLK_EN_M (PCR_PCNT_CLK_EN_V << PCR_PCNT_CLK_EN_S) +#define PCR_PCNT_CLK_EN_V 0x00000001U +#define PCR_PCNT_CLK_EN_S 0 +/** PCR_PCNT_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset pcnt module + */ +#define PCR_PCNT_RST_EN (BIT(1)) +#define PCR_PCNT_RST_EN_M (PCR_PCNT_RST_EN_V << PCR_PCNT_RST_EN_S) +#define PCR_PCNT_RST_EN_V 0x00000001U +#define PCR_PCNT_RST_EN_S 1 +/** PCR_PCNT_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset pcnt module + */ +#define PCR_PCNT_READY (BIT(2)) +#define PCR_PCNT_READY_M (PCR_PCNT_READY_V << PCR_PCNT_READY_S) +#define PCR_PCNT_READY_V 0x00000001U +#define PCR_PCNT_READY_S 2 + +/** PCR_ETM_CONF_REG register + * ETM configuration register + */ +#define PCR_ETM_CONF_REG (DR_REG_PCR_BASE + 0x98) +/** PCR_ETM_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable etm clock + */ +#define PCR_ETM_CLK_EN (BIT(0)) +#define PCR_ETM_CLK_EN_M (PCR_ETM_CLK_EN_V << PCR_ETM_CLK_EN_S) +#define PCR_ETM_CLK_EN_V 0x00000001U +#define PCR_ETM_CLK_EN_S 0 +/** PCR_ETM_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset etm module + */ +#define PCR_ETM_RST_EN (BIT(1)) +#define PCR_ETM_RST_EN_M (PCR_ETM_RST_EN_V << PCR_ETM_RST_EN_S) +#define PCR_ETM_RST_EN_V 0x00000001U +#define PCR_ETM_RST_EN_S 1 +/** PCR_ETM_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset etm module + */ +#define PCR_ETM_READY (BIT(2)) +#define PCR_ETM_READY_M (PCR_ETM_READY_V << PCR_ETM_READY_S) +#define PCR_ETM_READY_V 0x00000001U +#define PCR_ETM_READY_S 2 + +/** PCR_PWM_CONF_REG register + * PWM configuration register + */ +#define PCR_PWM_CONF_REG (DR_REG_PCR_BASE + 0x9c) +/** PCR_PWM_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable pwm clock + */ +#define PCR_PWM_CLK_EN (BIT(0)) +#define PCR_PWM_CLK_EN_M (PCR_PWM_CLK_EN_V << PCR_PWM_CLK_EN_S) +#define PCR_PWM_CLK_EN_V 0x00000001U +#define PCR_PWM_CLK_EN_S 0 +/** PCR_PWM_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset pwm module + */ +#define PCR_PWM_RST_EN (BIT(1)) +#define PCR_PWM_RST_EN_M (PCR_PWM_RST_EN_V << PCR_PWM_RST_EN_S) +#define PCR_PWM_RST_EN_V 0x00000001U +#define PCR_PWM_RST_EN_S 1 +/** PCR_PWM_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset pwm module + */ +#define PCR_PWM_READY (BIT(2)) +#define PCR_PWM_READY_M (PCR_PWM_READY_V << PCR_PWM_READY_S) +#define PCR_PWM_READY_V 0x00000001U +#define PCR_PWM_READY_S 2 + +/** PCR_PWM_CLK_CONF_REG register + * PWM_CLK configuration register + */ +#define PCR_PWM_CLK_CONF_REG (DR_REG_PCR_BASE + 0xa0) +/** PCR_PWM_DIV_NUM : R/W; bitpos: [19:12]; default: 4; + * The integral part of the frequency divider factor of the pwm function clock. + */ +#define PCR_PWM_DIV_NUM 0x000000FFU +#define PCR_PWM_DIV_NUM_M (PCR_PWM_DIV_NUM_V << PCR_PWM_DIV_NUM_S) +#define PCR_PWM_DIV_NUM_V 0x000000FFU +#define PCR_PWM_DIV_NUM_S 12 +/** PCR_PWM_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): do not select anyone clock, 1: + * 160MHz, 2: XTAL, 3: FOSC. + */ +#define PCR_PWM_CLKM_SEL 0x00000003U +#define PCR_PWM_CLKM_SEL_M (PCR_PWM_CLKM_SEL_V << PCR_PWM_CLKM_SEL_S) +#define PCR_PWM_CLKM_SEL_V 0x00000003U +#define PCR_PWM_CLKM_SEL_S 20 +/** PCR_PWM_CLKM_EN : R/W; bitpos: [22]; default: 1; + * set this field as 1 to activate pwm clkm. + */ +#define PCR_PWM_CLKM_EN (BIT(22)) +#define PCR_PWM_CLKM_EN_M (PCR_PWM_CLKM_EN_V << PCR_PWM_CLKM_EN_S) +#define PCR_PWM_CLKM_EN_V 0x00000001U +#define PCR_PWM_CLKM_EN_S 22 + +/** PCR_PARL_IO_CONF_REG register + * PARL_IO configuration register + */ +#define PCR_PARL_IO_CONF_REG (DR_REG_PCR_BASE + 0xa4) +/** PCR_PARL_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable parl apb clock + */ +#define PCR_PARL_CLK_EN (BIT(0)) +#define PCR_PARL_CLK_EN_M (PCR_PARL_CLK_EN_V << PCR_PARL_CLK_EN_S) +#define PCR_PARL_CLK_EN_V 0x00000001U +#define PCR_PARL_CLK_EN_S 0 +/** PCR_PARL_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset parl apb reg + */ +#define PCR_PARL_RST_EN (BIT(1)) +#define PCR_PARL_RST_EN_M (PCR_PARL_RST_EN_V << PCR_PARL_RST_EN_S) +#define PCR_PARL_RST_EN_V 0x00000001U +#define PCR_PARL_RST_EN_S 1 +/** PCR_PARL_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset parl module + */ +#define PCR_PARL_READY (BIT(2)) +#define PCR_PARL_READY_M (PCR_PARL_READY_V << PCR_PARL_READY_S) +#define PCR_PARL_READY_V 0x00000001U +#define PCR_PARL_READY_S 2 + +/** PCR_PARL_CLK_RX_CONF_REG register + * PARL_CLK_RX configuration register + */ +#define PCR_PARL_CLK_RX_CONF_REG (DR_REG_PCR_BASE + 0xa8) +/** PCR_PARL_CLK_RX_DIV_NUM : R/W; bitpos: [15:0]; default: 0; + * The integral part of the frequency divider factor of the parl rx clock. + */ +#define PCR_PARL_CLK_RX_DIV_NUM 0x0000FFFFU +#define PCR_PARL_CLK_RX_DIV_NUM_M (PCR_PARL_CLK_RX_DIV_NUM_V << PCR_PARL_CLK_RX_DIV_NUM_S) +#define PCR_PARL_CLK_RX_DIV_NUM_V 0x0000FFFFU +#define PCR_PARL_CLK_RX_DIV_NUM_S 0 +/** PCR_PARL_CLK_RX_SEL : R/W; bitpos: [17:16]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3: + * user clock from pad. + */ +#define PCR_PARL_CLK_RX_SEL 0x00000003U +#define PCR_PARL_CLK_RX_SEL_M (PCR_PARL_CLK_RX_SEL_V << PCR_PARL_CLK_RX_SEL_S) +#define PCR_PARL_CLK_RX_SEL_V 0x00000003U +#define PCR_PARL_CLK_RX_SEL_S 16 +/** PCR_PARL_CLK_RX_EN : R/W; bitpos: [18]; default: 1; + * Set 1 to enable parl rx clock + */ +#define PCR_PARL_CLK_RX_EN (BIT(18)) +#define PCR_PARL_CLK_RX_EN_M (PCR_PARL_CLK_RX_EN_V << PCR_PARL_CLK_RX_EN_S) +#define PCR_PARL_CLK_RX_EN_V 0x00000001U +#define PCR_PARL_CLK_RX_EN_S 18 +/** PCR_PARL_RX_RST_EN : R/W; bitpos: [19]; default: 0; + * Set 0 to reset parl rx module + */ +#define PCR_PARL_RX_RST_EN (BIT(19)) +#define PCR_PARL_RX_RST_EN_M (PCR_PARL_RX_RST_EN_V << PCR_PARL_RX_RST_EN_S) +#define PCR_PARL_RX_RST_EN_V 0x00000001U +#define PCR_PARL_RX_RST_EN_S 19 + +/** PCR_PARL_CLK_TX_CONF_REG register + * PARL_CLK_TX configuration register + */ +#define PCR_PARL_CLK_TX_CONF_REG (DR_REG_PCR_BASE + 0xac) +/** PCR_PARL_CLK_TX_DIV_NUM : R/W; bitpos: [15:0]; default: 0; + * The integral part of the frequency divider factor of the parl tx clock. + */ +#define PCR_PARL_CLK_TX_DIV_NUM 0x0000FFFFU +#define PCR_PARL_CLK_TX_DIV_NUM_M (PCR_PARL_CLK_TX_DIV_NUM_V << PCR_PARL_CLK_TX_DIV_NUM_S) +#define PCR_PARL_CLK_TX_DIV_NUM_V 0x0000FFFFU +#define PCR_PARL_CLK_TX_DIV_NUM_S 0 +/** PCR_PARL_CLK_TX_SEL : R/W; bitpos: [17:16]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3: + * user clock from pad. + */ +#define PCR_PARL_CLK_TX_SEL 0x00000003U +#define PCR_PARL_CLK_TX_SEL_M (PCR_PARL_CLK_TX_SEL_V << PCR_PARL_CLK_TX_SEL_S) +#define PCR_PARL_CLK_TX_SEL_V 0x00000003U +#define PCR_PARL_CLK_TX_SEL_S 16 +/** PCR_PARL_CLK_TX_EN : R/W; bitpos: [18]; default: 1; + * Set 1 to enable parl tx clock + */ +#define PCR_PARL_CLK_TX_EN (BIT(18)) +#define PCR_PARL_CLK_TX_EN_M (PCR_PARL_CLK_TX_EN_V << PCR_PARL_CLK_TX_EN_S) +#define PCR_PARL_CLK_TX_EN_V 0x00000001U +#define PCR_PARL_CLK_TX_EN_S 18 +/** PCR_PARL_TX_RST_EN : R/W; bitpos: [19]; default: 0; + * Set 0 to reset parl tx module + */ +#define PCR_PARL_TX_RST_EN (BIT(19)) +#define PCR_PARL_TX_RST_EN_M (PCR_PARL_TX_RST_EN_V << PCR_PARL_TX_RST_EN_S) +#define PCR_PARL_TX_RST_EN_V 0x00000001U +#define PCR_PARL_TX_RST_EN_S 19 + +/** PCR_PVT_MONITOR_CONF_REG register + * PVT_MONITOR configuration register + */ +#define PCR_PVT_MONITOR_CONF_REG (DR_REG_PCR_BASE + 0xb0) +/** PCR_PVT_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable apb clock of pvt module + */ +#define PCR_PVT_MONITOR_CLK_EN (BIT(0)) +#define PCR_PVT_MONITOR_CLK_EN_M (PCR_PVT_MONITOR_CLK_EN_V << PCR_PVT_MONITOR_CLK_EN_S) +#define PCR_PVT_MONITOR_CLK_EN_V 0x00000001U +#define PCR_PVT_MONITOR_CLK_EN_S 0 +/** PCR_PVT_MONITOR_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset all pvt monitor module + */ +#define PCR_PVT_MONITOR_RST_EN (BIT(1)) +#define PCR_PVT_MONITOR_RST_EN_M (PCR_PVT_MONITOR_RST_EN_V << PCR_PVT_MONITOR_RST_EN_S) +#define PCR_PVT_MONITOR_RST_EN_V 0x00000001U +#define PCR_PVT_MONITOR_RST_EN_S 1 +/** PCR_PVT_MONITOR_SITE1_CLK_EN : R/W; bitpos: [2]; default: 1; + * Set 1 to enable function clock of modem pvt module + */ +#define PCR_PVT_MONITOR_SITE1_CLK_EN (BIT(2)) +#define PCR_PVT_MONITOR_SITE1_CLK_EN_M (PCR_PVT_MONITOR_SITE1_CLK_EN_V << PCR_PVT_MONITOR_SITE1_CLK_EN_S) +#define PCR_PVT_MONITOR_SITE1_CLK_EN_V 0x00000001U +#define PCR_PVT_MONITOR_SITE1_CLK_EN_S 2 +/** PCR_PVT_MONITOR_SITE2_CLK_EN : R/W; bitpos: [3]; default: 1; + * Set 1 to enable function clock of cpu pvt module + */ +#define PCR_PVT_MONITOR_SITE2_CLK_EN (BIT(3)) +#define PCR_PVT_MONITOR_SITE2_CLK_EN_M (PCR_PVT_MONITOR_SITE2_CLK_EN_V << PCR_PVT_MONITOR_SITE2_CLK_EN_S) +#define PCR_PVT_MONITOR_SITE2_CLK_EN_V 0x00000001U +#define PCR_PVT_MONITOR_SITE2_CLK_EN_S 3 +/** PCR_PVT_MONITOR_SITE3_CLK_EN : R/W; bitpos: [4]; default: 1; + * Set 1 to enable function clock of hp_peri pvt module + */ +#define PCR_PVT_MONITOR_SITE3_CLK_EN (BIT(4)) +#define PCR_PVT_MONITOR_SITE3_CLK_EN_M (PCR_PVT_MONITOR_SITE3_CLK_EN_V << PCR_PVT_MONITOR_SITE3_CLK_EN_S) +#define PCR_PVT_MONITOR_SITE3_CLK_EN_V 0x00000001U +#define PCR_PVT_MONITOR_SITE3_CLK_EN_S 4 + +/** PCR_PVT_MONITOR_FUNC_CLK_CONF_REG register + * PVT_MONITOR function clock configuration register + */ +#define PCR_PVT_MONITOR_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0xb4) +/** PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM : R/W; bitpos: [3:0]; default: 0; + * The integral part of the frequency divider factor of the pvt_monitor function clock. + */ +#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM 0x0000000FU +#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_M (PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_V << PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_S) +#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_V 0x0000000FU +#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_S 0 +/** PCR_PVT_MONITOR_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0: XTAL, 1(default): 160MHz driven by SPLL + * divided by 3. + */ +#define PCR_PVT_MONITOR_FUNC_CLK_SEL (BIT(20)) +#define PCR_PVT_MONITOR_FUNC_CLK_SEL_M (PCR_PVT_MONITOR_FUNC_CLK_SEL_V << PCR_PVT_MONITOR_FUNC_CLK_SEL_S) +#define PCR_PVT_MONITOR_FUNC_CLK_SEL_V 0x00000001U +#define PCR_PVT_MONITOR_FUNC_CLK_SEL_S 20 +/** PCR_PVT_MONITOR_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable source clock of pvt sitex + */ +#define PCR_PVT_MONITOR_FUNC_CLK_EN (BIT(22)) +#define PCR_PVT_MONITOR_FUNC_CLK_EN_M (PCR_PVT_MONITOR_FUNC_CLK_EN_V << PCR_PVT_MONITOR_FUNC_CLK_EN_S) +#define PCR_PVT_MONITOR_FUNC_CLK_EN_V 0x00000001U +#define PCR_PVT_MONITOR_FUNC_CLK_EN_S 22 + +/** PCR_GDMA_CONF_REG register + * GDMA configuration register + */ +#define PCR_GDMA_CONF_REG (DR_REG_PCR_BASE + 0xb8) +/** PCR_GDMA_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable gdma clock + */ +#define PCR_GDMA_CLK_EN (BIT(0)) +#define PCR_GDMA_CLK_EN_M (PCR_GDMA_CLK_EN_V << PCR_GDMA_CLK_EN_S) +#define PCR_GDMA_CLK_EN_V 0x00000001U +#define PCR_GDMA_CLK_EN_S 0 +/** PCR_GDMA_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset gdma module + */ +#define PCR_GDMA_RST_EN (BIT(1)) +#define PCR_GDMA_RST_EN_M (PCR_GDMA_RST_EN_V << PCR_GDMA_RST_EN_S) +#define PCR_GDMA_RST_EN_V 0x00000001U +#define PCR_GDMA_RST_EN_S 1 + +/** PCR_SPI2_CONF_REG register + * SPI2 configuration register + */ +#define PCR_SPI2_CONF_REG (DR_REG_PCR_BASE + 0xbc) +/** PCR_SPI2_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable spi2 apb clock + */ +#define PCR_SPI2_CLK_EN (BIT(0)) +#define PCR_SPI2_CLK_EN_M (PCR_SPI2_CLK_EN_V << PCR_SPI2_CLK_EN_S) +#define PCR_SPI2_CLK_EN_V 0x00000001U +#define PCR_SPI2_CLK_EN_S 0 +/** PCR_SPI2_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset spi2 module + */ +#define PCR_SPI2_RST_EN (BIT(1)) +#define PCR_SPI2_RST_EN_M (PCR_SPI2_RST_EN_V << PCR_SPI2_RST_EN_S) +#define PCR_SPI2_RST_EN_V 0x00000001U +#define PCR_SPI2_RST_EN_S 1 +/** PCR_SPI2_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset spi2 module + */ +#define PCR_SPI2_READY (BIT(2)) +#define PCR_SPI2_READY_M (PCR_SPI2_READY_V << PCR_SPI2_READY_S) +#define PCR_SPI2_READY_V 0x00000001U +#define PCR_SPI2_READY_S 2 + +/** PCR_SPI2_CLKM_CONF_REG register + * SPI2_CLKM configuration register + */ +#define PCR_SPI2_CLKM_CONF_REG (DR_REG_PCR_BASE + 0xc0) +/** PCR_SPI2_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: + * reserved. + */ +#define PCR_SPI2_CLKM_SEL 0x00000003U +#define PCR_SPI2_CLKM_SEL_M (PCR_SPI2_CLKM_SEL_V << PCR_SPI2_CLKM_SEL_S) +#define PCR_SPI2_CLKM_SEL_V 0x00000003U +#define PCR_SPI2_CLKM_SEL_S 20 +/** PCR_SPI2_CLKM_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable spi2 function clock + */ +#define PCR_SPI2_CLKM_EN (BIT(22)) +#define PCR_SPI2_CLKM_EN_M (PCR_SPI2_CLKM_EN_V << PCR_SPI2_CLKM_EN_S) +#define PCR_SPI2_CLKM_EN_V 0x00000001U +#define PCR_SPI2_CLKM_EN_S 22 + +/** PCR_AES_CONF_REG register + * AES configuration register + */ +#define PCR_AES_CONF_REG (DR_REG_PCR_BASE + 0xc4) +/** PCR_AES_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable aes clock + */ +#define PCR_AES_CLK_EN (BIT(0)) +#define PCR_AES_CLK_EN_M (PCR_AES_CLK_EN_V << PCR_AES_CLK_EN_S) +#define PCR_AES_CLK_EN_V 0x00000001U +#define PCR_AES_CLK_EN_S 0 +/** PCR_AES_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset aes module + */ +#define PCR_AES_RST_EN (BIT(1)) +#define PCR_AES_RST_EN_M (PCR_AES_RST_EN_V << PCR_AES_RST_EN_S) +#define PCR_AES_RST_EN_V 0x00000001U +#define PCR_AES_RST_EN_S 1 +/** PCR_AES_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset aes module + */ +#define PCR_AES_READY (BIT(2)) +#define PCR_AES_READY_M (PCR_AES_READY_V << PCR_AES_READY_S) +#define PCR_AES_READY_V 0x00000001U +#define PCR_AES_READY_S 2 + +/** PCR_SHA_CONF_REG register + * SHA configuration register + */ +#define PCR_SHA_CONF_REG (DR_REG_PCR_BASE + 0xc8) +/** PCR_SHA_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable sha clock + */ +#define PCR_SHA_CLK_EN (BIT(0)) +#define PCR_SHA_CLK_EN_M (PCR_SHA_CLK_EN_V << PCR_SHA_CLK_EN_S) +#define PCR_SHA_CLK_EN_V 0x00000001U +#define PCR_SHA_CLK_EN_S 0 +/** PCR_SHA_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset sha module + */ +#define PCR_SHA_RST_EN (BIT(1)) +#define PCR_SHA_RST_EN_M (PCR_SHA_RST_EN_V << PCR_SHA_RST_EN_S) +#define PCR_SHA_RST_EN_V 0x00000001U +#define PCR_SHA_RST_EN_S 1 +/** PCR_SHA_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset sha module + */ +#define PCR_SHA_READY (BIT(2)) +#define PCR_SHA_READY_M (PCR_SHA_READY_V << PCR_SHA_READY_S) +#define PCR_SHA_READY_V 0x00000001U +#define PCR_SHA_READY_S 2 + +/** PCR_RSA_CONF_REG register + * RSA configuration register + */ +#define PCR_RSA_CONF_REG (DR_REG_PCR_BASE + 0xcc) +/** PCR_RSA_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable rsa clock + */ +#define PCR_RSA_CLK_EN (BIT(0)) +#define PCR_RSA_CLK_EN_M (PCR_RSA_CLK_EN_V << PCR_RSA_CLK_EN_S) +#define PCR_RSA_CLK_EN_V 0x00000001U +#define PCR_RSA_CLK_EN_S 0 +/** PCR_RSA_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset rsa module + */ +#define PCR_RSA_RST_EN (BIT(1)) +#define PCR_RSA_RST_EN_M (PCR_RSA_RST_EN_V << PCR_RSA_RST_EN_S) +#define PCR_RSA_RST_EN_V 0x00000001U +#define PCR_RSA_RST_EN_S 1 +/** PCR_RSA_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset rsa module + */ +#define PCR_RSA_READY (BIT(2)) +#define PCR_RSA_READY_M (PCR_RSA_READY_V << PCR_RSA_READY_S) +#define PCR_RSA_READY_V 0x00000001U +#define PCR_RSA_READY_S 2 + +/** PCR_RSA_PD_CTRL_REG register + * RSA power control register + */ +#define PCR_RSA_PD_CTRL_REG (DR_REG_PCR_BASE + 0xd0) +/** PCR_RSA_MEM_PD : R/W; bitpos: [0]; default: 0; + * Set this bit to power down rsa internal memory. + */ +#define PCR_RSA_MEM_PD (BIT(0)) +#define PCR_RSA_MEM_PD_M (PCR_RSA_MEM_PD_V << PCR_RSA_MEM_PD_S) +#define PCR_RSA_MEM_PD_V 0x00000001U +#define PCR_RSA_MEM_PD_S 0 +/** PCR_RSA_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1; + * Set this bit to force power up rsa internal memory + */ +#define PCR_RSA_MEM_FORCE_PU (BIT(1)) +#define PCR_RSA_MEM_FORCE_PU_M (PCR_RSA_MEM_FORCE_PU_V << PCR_RSA_MEM_FORCE_PU_S) +#define PCR_RSA_MEM_FORCE_PU_V 0x00000001U +#define PCR_RSA_MEM_FORCE_PU_S 1 +/** PCR_RSA_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; + * Set this bit to force power down rsa internal memory. + */ +#define PCR_RSA_MEM_FORCE_PD (BIT(2)) +#define PCR_RSA_MEM_FORCE_PD_M (PCR_RSA_MEM_FORCE_PD_V << PCR_RSA_MEM_FORCE_PD_S) +#define PCR_RSA_MEM_FORCE_PD_V 0x00000001U +#define PCR_RSA_MEM_FORCE_PD_S 2 + +/** PCR_ECC_CONF_REG register + * ECC configuration register + */ +#define PCR_ECC_CONF_REG (DR_REG_PCR_BASE + 0xd4) +/** PCR_ECC_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable ecc clock + */ +#define PCR_ECC_CLK_EN (BIT(0)) +#define PCR_ECC_CLK_EN_M (PCR_ECC_CLK_EN_V << PCR_ECC_CLK_EN_S) +#define PCR_ECC_CLK_EN_V 0x00000001U +#define PCR_ECC_CLK_EN_S 0 +/** PCR_ECC_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset ecc module + */ +#define PCR_ECC_RST_EN (BIT(1)) +#define PCR_ECC_RST_EN_M (PCR_ECC_RST_EN_V << PCR_ECC_RST_EN_S) +#define PCR_ECC_RST_EN_V 0x00000001U +#define PCR_ECC_RST_EN_S 1 +/** PCR_ECC_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset ecc module + */ +#define PCR_ECC_READY (BIT(2)) +#define PCR_ECC_READY_M (PCR_ECC_READY_V << PCR_ECC_READY_S) +#define PCR_ECC_READY_V 0x00000001U +#define PCR_ECC_READY_S 2 + +/** PCR_ECC_PD_CTRL_REG register + * ECC power control register + */ +#define PCR_ECC_PD_CTRL_REG (DR_REG_PCR_BASE + 0xd8) +/** PCR_ECC_MEM_PD : R/W; bitpos: [0]; default: 0; + * Set this bit to power down ecc internal memory. + */ +#define PCR_ECC_MEM_PD (BIT(0)) +#define PCR_ECC_MEM_PD_M (PCR_ECC_MEM_PD_V << PCR_ECC_MEM_PD_S) +#define PCR_ECC_MEM_PD_V 0x00000001U +#define PCR_ECC_MEM_PD_S 0 +/** PCR_ECC_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1; + * Set this bit to force power up ecc internal memory + */ +#define PCR_ECC_MEM_FORCE_PU (BIT(1)) +#define PCR_ECC_MEM_FORCE_PU_M (PCR_ECC_MEM_FORCE_PU_V << PCR_ECC_MEM_FORCE_PU_S) +#define PCR_ECC_MEM_FORCE_PU_V 0x00000001U +#define PCR_ECC_MEM_FORCE_PU_S 1 +/** PCR_ECC_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; + * Set this bit to force power down ecc internal memory. + */ +#define PCR_ECC_MEM_FORCE_PD (BIT(2)) +#define PCR_ECC_MEM_FORCE_PD_M (PCR_ECC_MEM_FORCE_PD_V << PCR_ECC_MEM_FORCE_PD_S) +#define PCR_ECC_MEM_FORCE_PD_V 0x00000001U +#define PCR_ECC_MEM_FORCE_PD_S 2 + +/** PCR_DS_CONF_REG register + * DS configuration register + */ +#define PCR_DS_CONF_REG (DR_REG_PCR_BASE + 0xdc) +/** PCR_DS_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable ds clock + */ +#define PCR_DS_CLK_EN (BIT(0)) +#define PCR_DS_CLK_EN_M (PCR_DS_CLK_EN_V << PCR_DS_CLK_EN_S) +#define PCR_DS_CLK_EN_V 0x00000001U +#define PCR_DS_CLK_EN_S 0 +/** PCR_DS_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset ds module + */ +#define PCR_DS_RST_EN (BIT(1)) +#define PCR_DS_RST_EN_M (PCR_DS_RST_EN_V << PCR_DS_RST_EN_S) +#define PCR_DS_RST_EN_V 0x00000001U +#define PCR_DS_RST_EN_S 1 +/** PCR_DS_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset ds module + */ +#define PCR_DS_READY (BIT(2)) +#define PCR_DS_READY_M (PCR_DS_READY_V << PCR_DS_READY_S) +#define PCR_DS_READY_V 0x00000001U +#define PCR_DS_READY_S 2 + +/** PCR_HMAC_CONF_REG register + * HMAC configuration register + */ +#define PCR_HMAC_CONF_REG (DR_REG_PCR_BASE + 0xe0) +/** PCR_HMAC_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable hmac clock + */ +#define PCR_HMAC_CLK_EN (BIT(0)) +#define PCR_HMAC_CLK_EN_M (PCR_HMAC_CLK_EN_V << PCR_HMAC_CLK_EN_S) +#define PCR_HMAC_CLK_EN_V 0x00000001U +#define PCR_HMAC_CLK_EN_S 0 +/** PCR_HMAC_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset hmac module + */ +#define PCR_HMAC_RST_EN (BIT(1)) +#define PCR_HMAC_RST_EN_M (PCR_HMAC_RST_EN_V << PCR_HMAC_RST_EN_S) +#define PCR_HMAC_RST_EN_V 0x00000001U +#define PCR_HMAC_RST_EN_S 1 +/** PCR_HMAC_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset hmac module + */ +#define PCR_HMAC_READY (BIT(2)) +#define PCR_HMAC_READY_M (PCR_HMAC_READY_V << PCR_HMAC_READY_S) +#define PCR_HMAC_READY_V 0x00000001U +#define PCR_HMAC_READY_S 2 + +/** PCR_ECDSA_CONF_REG register + * ECDSA configuration register + */ +#define PCR_ECDSA_CONF_REG (DR_REG_PCR_BASE + 0xe4) +/** PCR_ECDSA_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable ecdsa clock + */ +#define PCR_ECDSA_CLK_EN (BIT(0)) +#define PCR_ECDSA_CLK_EN_M (PCR_ECDSA_CLK_EN_V << PCR_ECDSA_CLK_EN_S) +#define PCR_ECDSA_CLK_EN_V 0x00000001U +#define PCR_ECDSA_CLK_EN_S 0 +/** PCR_ECDSA_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset ecdsa module + */ +#define PCR_ECDSA_RST_EN (BIT(1)) +#define PCR_ECDSA_RST_EN_M (PCR_ECDSA_RST_EN_V << PCR_ECDSA_RST_EN_S) +#define PCR_ECDSA_RST_EN_V 0x00000001U +#define PCR_ECDSA_RST_EN_S 1 +/** PCR_ECDSA_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset ecdsa module + */ +#define PCR_ECDSA_READY (BIT(2)) +#define PCR_ECDSA_READY_M (PCR_ECDSA_READY_V << PCR_ECDSA_READY_S) +#define PCR_ECDSA_READY_V 0x00000001U +#define PCR_ECDSA_READY_S 2 + +/** PCR_IOMUX_CONF_REG register + * IOMUX configuration register + */ +#define PCR_IOMUX_CONF_REG (DR_REG_PCR_BASE + 0xe8) +/** PCR_IOMUX_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable iomux apb clock + */ +#define PCR_IOMUX_CLK_EN (BIT(0)) +#define PCR_IOMUX_CLK_EN_M (PCR_IOMUX_CLK_EN_V << PCR_IOMUX_CLK_EN_S) +#define PCR_IOMUX_CLK_EN_V 0x00000001U +#define PCR_IOMUX_CLK_EN_S 0 +/** PCR_IOMUX_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset iomux module + */ +#define PCR_IOMUX_RST_EN (BIT(1)) +#define PCR_IOMUX_RST_EN_M (PCR_IOMUX_RST_EN_V << PCR_IOMUX_RST_EN_S) +#define PCR_IOMUX_RST_EN_V 0x00000001U +#define PCR_IOMUX_RST_EN_S 1 + +/** PCR_IOMUX_CLK_CONF_REG register + * IOMUX_CLK configuration register + */ +#define PCR_IOMUX_CLK_CONF_REG (DR_REG_PCR_BASE + 0xec) +/** PCR_IOMUX_FUNC_CLK_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: + * FOSC, 3(default): XTAL. + */ +#define PCR_IOMUX_FUNC_CLK_SEL 0x00000003U +#define PCR_IOMUX_FUNC_CLK_SEL_M (PCR_IOMUX_FUNC_CLK_SEL_V << PCR_IOMUX_FUNC_CLK_SEL_S) +#define PCR_IOMUX_FUNC_CLK_SEL_V 0x00000003U +#define PCR_IOMUX_FUNC_CLK_SEL_S 20 +/** PCR_IOMUX_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable iomux function clock + */ +#define PCR_IOMUX_FUNC_CLK_EN (BIT(22)) +#define PCR_IOMUX_FUNC_CLK_EN_M (PCR_IOMUX_FUNC_CLK_EN_V << PCR_IOMUX_FUNC_CLK_EN_S) +#define PCR_IOMUX_FUNC_CLK_EN_V 0x00000001U +#define PCR_IOMUX_FUNC_CLK_EN_S 22 + +/** PCR_MEM_MONITOR_CONF_REG register + * MEM_MONITOR configuration register + */ +#define PCR_MEM_MONITOR_CONF_REG (DR_REG_PCR_BASE + 0xf0) +/** PCR_MEM_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable mem_monitor clock + */ +#define PCR_MEM_MONITOR_CLK_EN (BIT(0)) +#define PCR_MEM_MONITOR_CLK_EN_M (PCR_MEM_MONITOR_CLK_EN_V << PCR_MEM_MONITOR_CLK_EN_S) +#define PCR_MEM_MONITOR_CLK_EN_V 0x00000001U +#define PCR_MEM_MONITOR_CLK_EN_S 0 +/** PCR_MEM_MONITOR_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset mem_monitor module + */ +#define PCR_MEM_MONITOR_RST_EN (BIT(1)) +#define PCR_MEM_MONITOR_RST_EN_M (PCR_MEM_MONITOR_RST_EN_V << PCR_MEM_MONITOR_RST_EN_S) +#define PCR_MEM_MONITOR_RST_EN_V 0x00000001U +#define PCR_MEM_MONITOR_RST_EN_S 1 +/** PCR_MEM_MONITOR_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset mem_monitor module + */ +#define PCR_MEM_MONITOR_READY (BIT(2)) +#define PCR_MEM_MONITOR_READY_M (PCR_MEM_MONITOR_READY_V << PCR_MEM_MONITOR_READY_S) +#define PCR_MEM_MONITOR_READY_V 0x00000001U +#define PCR_MEM_MONITOR_READY_S 2 + +/** PCR_REGDMA_CONF_REG register + * REGDMA configuration register + */ +#define PCR_REGDMA_CONF_REG (DR_REG_PCR_BASE + 0xf4) +/** PCR_REGDMA_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable regdma clock + */ +#define PCR_REGDMA_CLK_EN (BIT(0)) +#define PCR_REGDMA_CLK_EN_M (PCR_REGDMA_CLK_EN_V << PCR_REGDMA_CLK_EN_S) +#define PCR_REGDMA_CLK_EN_V 0x00000001U +#define PCR_REGDMA_CLK_EN_S 0 +/** PCR_REGDMA_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset regdma module + */ +#define PCR_REGDMA_RST_EN (BIT(1)) +#define PCR_REGDMA_RST_EN_M (PCR_REGDMA_RST_EN_V << PCR_REGDMA_RST_EN_S) +#define PCR_REGDMA_RST_EN_V 0x00000001U +#define PCR_REGDMA_RST_EN_S 1 + +/** PCR_TRACE_CONF_REG register + * TRACE configuration register + */ +#define PCR_TRACE_CONF_REG (DR_REG_PCR_BASE + 0xf8) +/** PCR_TRACE_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable trace clock + */ +#define PCR_TRACE_CLK_EN (BIT(0)) +#define PCR_TRACE_CLK_EN_M (PCR_TRACE_CLK_EN_V << PCR_TRACE_CLK_EN_S) +#define PCR_TRACE_CLK_EN_V 0x00000001U +#define PCR_TRACE_CLK_EN_S 0 +/** PCR_TRACE_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset trace module + */ +#define PCR_TRACE_RST_EN (BIT(1)) +#define PCR_TRACE_RST_EN_M (PCR_TRACE_RST_EN_V << PCR_TRACE_RST_EN_S) +#define PCR_TRACE_RST_EN_V 0x00000001U +#define PCR_TRACE_RST_EN_S 1 + +/** PCR_ASSIST_CONF_REG register + * ASSIST configuration register + */ +#define PCR_ASSIST_CONF_REG (DR_REG_PCR_BASE + 0xfc) +/** PCR_ASSIST_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable assist clock + */ +#define PCR_ASSIST_CLK_EN (BIT(0)) +#define PCR_ASSIST_CLK_EN_M (PCR_ASSIST_CLK_EN_V << PCR_ASSIST_CLK_EN_S) +#define PCR_ASSIST_CLK_EN_V 0x00000001U +#define PCR_ASSIST_CLK_EN_S 0 +/** PCR_ASSIST_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset assist module + */ +#define PCR_ASSIST_RST_EN (BIT(1)) +#define PCR_ASSIST_RST_EN_M (PCR_ASSIST_RST_EN_V << PCR_ASSIST_RST_EN_S) +#define PCR_ASSIST_RST_EN_V 0x00000001U +#define PCR_ASSIST_RST_EN_S 1 + +/** PCR_CACHE_CONF_REG register + * CACHE configuration register + */ +#define PCR_CACHE_CONF_REG (DR_REG_PCR_BASE + 0x100) +/** PCR_CACHE_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable cache clock + */ +#define PCR_CACHE_CLK_EN (BIT(0)) +#define PCR_CACHE_CLK_EN_M (PCR_CACHE_CLK_EN_V << PCR_CACHE_CLK_EN_S) +#define PCR_CACHE_CLK_EN_V 0x00000001U +#define PCR_CACHE_CLK_EN_S 0 +/** PCR_CACHE_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset cache module + */ +#define PCR_CACHE_RST_EN (BIT(1)) +#define PCR_CACHE_RST_EN_M (PCR_CACHE_RST_EN_V << PCR_CACHE_RST_EN_S) +#define PCR_CACHE_RST_EN_V 0x00000001U +#define PCR_CACHE_RST_EN_S 1 + +/** PCR_MODEM_CONF_REG register + * MODEM_APB configuration register + */ +#define PCR_MODEM_CONF_REG (DR_REG_PCR_BASE + 0x104) +/** PCR_MODEM_CLK_SEL : R/W; bitpos: [0]; default: 0; + * xxxx + */ +#define PCR_MODEM_CLK_SEL (BIT(0)) +#define PCR_MODEM_CLK_SEL_M (PCR_MODEM_CLK_SEL_V << PCR_MODEM_CLK_SEL_S) +#define PCR_MODEM_CLK_SEL_V 0x00000001U +#define PCR_MODEM_CLK_SEL_S 0 +/** PCR_MODEM_CLK_EN : R/W; bitpos: [1]; default: 1; + * xxxx + */ +#define PCR_MODEM_CLK_EN (BIT(1)) +#define PCR_MODEM_CLK_EN_M (PCR_MODEM_CLK_EN_V << PCR_MODEM_CLK_EN_S) +#define PCR_MODEM_CLK_EN_V 0x00000001U +#define PCR_MODEM_CLK_EN_S 1 +/** PCR_MODEM_RST_EN : R/W; bitpos: [2]; default: 0; + * Set this file as 1 to reset modem-subsystem. + */ +#define PCR_MODEM_RST_EN (BIT(2)) +#define PCR_MODEM_RST_EN_M (PCR_MODEM_RST_EN_V << PCR_MODEM_RST_EN_S) +#define PCR_MODEM_RST_EN_V 0x00000001U +#define PCR_MODEM_RST_EN_S 2 + +/** PCR_TIMEOUT_CONF_REG register + * TIMEOUT configuration register + */ +#define PCR_TIMEOUT_CONF_REG (DR_REG_PCR_BASE + 0x108) +/** PCR_CPU_TIMEOUT_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset cpu_peri timeout module + */ +#define PCR_CPU_TIMEOUT_RST_EN (BIT(1)) +#define PCR_CPU_TIMEOUT_RST_EN_M (PCR_CPU_TIMEOUT_RST_EN_V << PCR_CPU_TIMEOUT_RST_EN_S) +#define PCR_CPU_TIMEOUT_RST_EN_V 0x00000001U +#define PCR_CPU_TIMEOUT_RST_EN_S 1 +/** PCR_HP_TIMEOUT_RST_EN : R/W; bitpos: [2]; default: 0; + * Set 0 to reset hp_peri timeout module and hp_modem timeout module + */ +#define PCR_HP_TIMEOUT_RST_EN (BIT(2)) +#define PCR_HP_TIMEOUT_RST_EN_M (PCR_HP_TIMEOUT_RST_EN_V << PCR_HP_TIMEOUT_RST_EN_S) +#define PCR_HP_TIMEOUT_RST_EN_V 0x00000001U +#define PCR_HP_TIMEOUT_RST_EN_S 2 + +/** PCR_SYSCLK_CONF_REG register + * SYSCLK configuration register + */ +#define PCR_SYSCLK_CONF_REG (DR_REG_PCR_BASE + 0x10c) +/** PCR_LS_DIV_NUM : HRO; bitpos: [7:0]; default: 0; + * clk_hproot is div1 of low-speed clock-source if clck-source is a low-speed + * clock-source such as XTAL/FOSC. + */ +#define PCR_LS_DIV_NUM 0x000000FFU +#define PCR_LS_DIV_NUM_M (PCR_LS_DIV_NUM_V << PCR_LS_DIV_NUM_S) +#define PCR_LS_DIV_NUM_V 0x000000FFU +#define PCR_LS_DIV_NUM_S 0 +/** PCR_HS_DIV_NUM : HRO; bitpos: [15:8]; default: 2; + * clk_hproot is div3 of SPLL if the clock-source is high-speed clock SPLL. + */ +#define PCR_HS_DIV_NUM 0x000000FFU +#define PCR_HS_DIV_NUM_M (PCR_HS_DIV_NUM_V << PCR_HS_DIV_NUM_S) +#define PCR_HS_DIV_NUM_V 0x000000FFU +#define PCR_HS_DIV_NUM_S 8 +/** PCR_SOC_CLK_SEL : R/W; bitpos: [17:16]; default: 0; + * This field is used to select clock source. 0: XTAL, 1: SPLL, 2: FOSC, 3: reserved. + */ +#define PCR_SOC_CLK_SEL 0x00000003U +#define PCR_SOC_CLK_SEL_M (PCR_SOC_CLK_SEL_V << PCR_SOC_CLK_SEL_S) +#define PCR_SOC_CLK_SEL_V 0x00000003U +#define PCR_SOC_CLK_SEL_S 16 +/** PCR_CLK_XTAL_FREQ : RO; bitpos: [30:24]; default: 32; + * This field indicates the frequency(MHz) of XTAL. + */ +#define PCR_CLK_XTAL_FREQ 0x0000007FU +#define PCR_CLK_XTAL_FREQ_M (PCR_CLK_XTAL_FREQ_V << PCR_CLK_XTAL_FREQ_S) +#define PCR_CLK_XTAL_FREQ_V 0x0000007FU +#define PCR_CLK_XTAL_FREQ_S 24 + +/** PCR_CPU_WAITI_CONF_REG register + * CPU_WAITI configuration register + */ +#define PCR_CPU_WAITI_CONF_REG (DR_REG_PCR_BASE + 0x110) +/** PCR_CPUPERIOD_SEL : HRO; bitpos: [1:0]; default: 1; + * Reserved. This filed has been replaced by PCR_CPU_DIV_NUM + */ +#define PCR_CPUPERIOD_SEL 0x00000003U +#define PCR_CPUPERIOD_SEL_M (PCR_CPUPERIOD_SEL_V << PCR_CPUPERIOD_SEL_S) +#define PCR_CPUPERIOD_SEL_V 0x00000003U +#define PCR_CPUPERIOD_SEL_S 0 +/** PCR_PLL_FREQ_SEL : HRO; bitpos: [2]; default: 1; + * Reserved. This filed has been replaced by PCR_CPU_DIV_NUM + */ +#define PCR_PLL_FREQ_SEL (BIT(2)) +#define PCR_PLL_FREQ_SEL_M (PCR_PLL_FREQ_SEL_V << PCR_PLL_FREQ_SEL_S) +#define PCR_PLL_FREQ_SEL_V 0x00000001U +#define PCR_PLL_FREQ_SEL_S 2 +/** PCR_CPU_WAIT_MODE_FORCE_ON : R/W; bitpos: [3]; default: 1; + * Set 1 to force cpu_waiti_clk enable. + */ +#define PCR_CPU_WAIT_MODE_FORCE_ON (BIT(3)) +#define PCR_CPU_WAIT_MODE_FORCE_ON_M (PCR_CPU_WAIT_MODE_FORCE_ON_V << PCR_CPU_WAIT_MODE_FORCE_ON_S) +#define PCR_CPU_WAIT_MODE_FORCE_ON_V 0x00000001U +#define PCR_CPU_WAIT_MODE_FORCE_ON_S 3 +/** PCR_CPU_WAITI_DELAY_NUM : R/W; bitpos: [7:4]; default: 0; + * This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk + * will close + */ +#define PCR_CPU_WAITI_DELAY_NUM 0x0000000FU +#define PCR_CPU_WAITI_DELAY_NUM_M (PCR_CPU_WAITI_DELAY_NUM_V << PCR_CPU_WAITI_DELAY_NUM_S) +#define PCR_CPU_WAITI_DELAY_NUM_V 0x0000000FU +#define PCR_CPU_WAITI_DELAY_NUM_S 4 + +/** PCR_CPU_FREQ_CONF_REG register + * CPU_FREQ configuration register + */ +#define PCR_CPU_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x114) +/** PCR_CPU_DIV_NUM : R/W; bitpos: [7:0]; default: 0; + * Set this field to generate clk_cpu driven by clk_hproot. The clk_cpu is + * div1(default)/div2/div4 of clk_hproot. This field is only available for low-speed + * clock-source such as XTAL/FOSC, and should be used together with PCR_AHB_DIV_NUM. + */ +#define PCR_CPU_DIV_NUM 0x000000FFU +#define PCR_CPU_DIV_NUM_M (PCR_CPU_DIV_NUM_V << PCR_CPU_DIV_NUM_S) +#define PCR_CPU_DIV_NUM_V 0x000000FFU +#define PCR_CPU_DIV_NUM_S 0 + +/** PCR_AHB_FREQ_CONF_REG register + * AHB_FREQ configuration register + */ +#define PCR_AHB_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x118) +/** PCR_AHB_DIV_NUM : R/W; bitpos: [7:0]; default: 0; + * Set this field to generate clk_ahb driven by clk_hproot. The clk_ahb is + * div1(default)/div2/div4/div8 of clk_hproot. This field is only available for + * low-speed clock-source such as XTAL/FOSC, and should be used together with + * PCR_CPU_DIV_NUM. + */ +#define PCR_AHB_DIV_NUM 0x000000FFU +#define PCR_AHB_DIV_NUM_M (PCR_AHB_DIV_NUM_V << PCR_AHB_DIV_NUM_S) +#define PCR_AHB_DIV_NUM_V 0x000000FFU +#define PCR_AHB_DIV_NUM_S 0 + +/** PCR_APB_FREQ_CONF_REG register + * APB_FREQ configuration register + */ +#define PCR_APB_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x11c) +/** PCR_APB_DECREASE_DIV_NUM : R/W; bitpos: [7:0]; default: 0; + * If this field's value is grater than PCR_APB_DIV_NUM, the clk_apb will be + * automatically down to clk_apb_decrease only when no access is on apb-bus, and will + * recover to the previous frequency when a new access appears on apb-bus. Set as one + * within (0,1,3) to set clk_apb_decrease as div1/div2/div4(default) of clk_ahb. Note + * that enable this function will reduce performance. Users can set this field as zero + * to disable the auto-decrease-apb-freq function. By default, this function is + * disable. + */ +#define PCR_APB_DECREASE_DIV_NUM 0x000000FFU +#define PCR_APB_DECREASE_DIV_NUM_M (PCR_APB_DECREASE_DIV_NUM_V << PCR_APB_DECREASE_DIV_NUM_S) +#define PCR_APB_DECREASE_DIV_NUM_V 0x000000FFU +#define PCR_APB_DECREASE_DIV_NUM_S 0 +/** PCR_APB_DIV_NUM : R/W; bitpos: [15:8]; default: 0; + * Set as one within (0,1,3) to generate clk_apb driven by clk_ahb. The clk_apb is + * div1(default)/div2/div4 of clk_ahb. + */ +#define PCR_APB_DIV_NUM 0x000000FFU +#define PCR_APB_DIV_NUM_M (PCR_APB_DIV_NUM_V << PCR_APB_DIV_NUM_S) +#define PCR_APB_DIV_NUM_V 0x000000FFU +#define PCR_APB_DIV_NUM_S 8 + +/** PCR_SYSCLK_FREQ_QUERY_0_REG register + * SYSCLK frequency query 0 register + */ +#define PCR_SYSCLK_FREQ_QUERY_0_REG (DR_REG_PCR_BASE + 0x120) +/** PCR_FOSC_FREQ : HRO; bitpos: [7:0]; default: 8; + * This field indicates the frequency(MHz) of FOSC. + */ +#define PCR_FOSC_FREQ 0x000000FFU +#define PCR_FOSC_FREQ_M (PCR_FOSC_FREQ_V << PCR_FOSC_FREQ_S) +#define PCR_FOSC_FREQ_V 0x000000FFU +#define PCR_FOSC_FREQ_S 0 +/** PCR_PLL_FREQ : HRO; bitpos: [17:8]; default: 96; + * This field indicates the frequency(MHz) of SPLL. + */ +#define PCR_PLL_FREQ 0x000003FFU +#define PCR_PLL_FREQ_M (PCR_PLL_FREQ_V << PCR_PLL_FREQ_S) +#define PCR_PLL_FREQ_V 0x000003FFU +#define PCR_PLL_FREQ_S 8 + +/** PCR_PLL_DIV_CLK_EN_REG register + * SPLL DIV clock-gating configuration register + */ +#define PCR_PLL_DIV_CLK_EN_REG (DR_REG_PCR_BASE + 0x124) +/** PCR_PLL_240M_CLK_EN : R/W; bitpos: [0]; default: 1; + * This field is used to open 96 MHz clock (SPLL) driven from SPLL. 0: close, 1: + * open(default). Only available when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_240M_CLK_EN (BIT(0)) +#define PCR_PLL_240M_CLK_EN_M (PCR_PLL_240M_CLK_EN_V << PCR_PLL_240M_CLK_EN_S) +#define PCR_PLL_240M_CLK_EN_V 0x00000001U +#define PCR_PLL_240M_CLK_EN_S 0 +/** PCR_PLL_160M_CLK_EN : R/W; bitpos: [1]; default: 1; + * This field is used to open 64 MHz clock (div3 of SPLL) driven from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_160M_CLK_EN (BIT(1)) +#define PCR_PLL_160M_CLK_EN_M (PCR_PLL_160M_CLK_EN_V << PCR_PLL_160M_CLK_EN_S) +#define PCR_PLL_160M_CLK_EN_V 0x00000001U +#define PCR_PLL_160M_CLK_EN_S 1 +/** PCR_PLL_120M_CLK_EN : R/W; bitpos: [2]; default: 1; + * This field is used to open 48 MHz clock (div4 of SPLL) driven from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_120M_CLK_EN (BIT(2)) +#define PCR_PLL_120M_CLK_EN_M (PCR_PLL_120M_CLK_EN_V << PCR_PLL_120M_CLK_EN_S) +#define PCR_PLL_120M_CLK_EN_V 0x00000001U +#define PCR_PLL_120M_CLK_EN_S 2 +/** PCR_PLL_80M_CLK_EN : R/W; bitpos: [3]; default: 1; + * This field is used to open 32 MHz clock (div6 of SPLL) driven from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_80M_CLK_EN (BIT(3)) +#define PCR_PLL_80M_CLK_EN_M (PCR_PLL_80M_CLK_EN_V << PCR_PLL_80M_CLK_EN_S) +#define PCR_PLL_80M_CLK_EN_V 0x00000001U +#define PCR_PLL_80M_CLK_EN_S 3 +/** PCR_PLL_48M_CLK_EN : R/W; bitpos: [4]; default: 1; + * This field is used to open 16 MHz clock (div10 of SPLL) driven from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_48M_CLK_EN (BIT(4)) +#define PCR_PLL_48M_CLK_EN_M (PCR_PLL_48M_CLK_EN_V << PCR_PLL_48M_CLK_EN_S) +#define PCR_PLL_48M_CLK_EN_V 0x00000001U +#define PCR_PLL_48M_CLK_EN_S 4 +/** PCR_PLL_40M_CLK_EN : R/W; bitpos: [5]; default: 1; + * This field is used to open 8 MHz clock (div12 of SPLL) driven from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_40M_CLK_EN (BIT(5)) +#define PCR_PLL_40M_CLK_EN_M (PCR_PLL_40M_CLK_EN_V << PCR_PLL_40M_CLK_EN_S) +#define PCR_PLL_40M_CLK_EN_V 0x00000001U +#define PCR_PLL_40M_CLK_EN_S 5 + +/** PCR_CTRL_CLK_OUT_EN_REG register + * CLK_OUT_EN configuration register + */ +#define PCR_CTRL_CLK_OUT_EN_REG (DR_REG_PCR_BASE + 0x128) +/** PCR_CLK8_OEN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable 8m clock + */ +#define PCR_CLK8_OEN (BIT(0)) +#define PCR_CLK8_OEN_M (PCR_CLK8_OEN_V << PCR_CLK8_OEN_S) +#define PCR_CLK8_OEN_V 0x00000001U +#define PCR_CLK8_OEN_S 0 +/** PCR_CLK16_OEN : R/W; bitpos: [1]; default: 1; + * Set 1 to enable 16m clock + */ +#define PCR_CLK16_OEN (BIT(1)) +#define PCR_CLK16_OEN_M (PCR_CLK16_OEN_V << PCR_CLK16_OEN_S) +#define PCR_CLK16_OEN_V 0x00000001U +#define PCR_CLK16_OEN_S 1 +/** PCR_CLK32_OEN : R/W; bitpos: [2]; default: 1; + * Set 1 to enable 32m clock + */ +#define PCR_CLK32_OEN (BIT(2)) +#define PCR_CLK32_OEN_M (PCR_CLK32_OEN_V << PCR_CLK32_OEN_S) +#define PCR_CLK32_OEN_V 0x00000001U +#define PCR_CLK32_OEN_S 2 +/** PCR_CLK_ADC_INF_OEN : R/W; bitpos: [3]; default: 1; + * Reserved + */ +#define PCR_CLK_ADC_INF_OEN (BIT(3)) +#define PCR_CLK_ADC_INF_OEN_M (PCR_CLK_ADC_INF_OEN_V << PCR_CLK_ADC_INF_OEN_S) +#define PCR_CLK_ADC_INF_OEN_V 0x00000001U +#define PCR_CLK_ADC_INF_OEN_S 3 +/** PCR_CLK_DFM_INF_OEN : R/W; bitpos: [4]; default: 1; + * Reserved + */ +#define PCR_CLK_DFM_INF_OEN (BIT(4)) +#define PCR_CLK_DFM_INF_OEN_M (PCR_CLK_DFM_INF_OEN_V << PCR_CLK_DFM_INF_OEN_S) +#define PCR_CLK_DFM_INF_OEN_V 0x00000001U +#define PCR_CLK_DFM_INF_OEN_S 4 +/** PCR_CLK_SDM_MOD_OEN : R/W; bitpos: [5]; default: 1; + * Reserved + */ +#define PCR_CLK_SDM_MOD_OEN (BIT(5)) +#define PCR_CLK_SDM_MOD_OEN_M (PCR_CLK_SDM_MOD_OEN_V << PCR_CLK_SDM_MOD_OEN_S) +#define PCR_CLK_SDM_MOD_OEN_V 0x00000001U +#define PCR_CLK_SDM_MOD_OEN_S 5 +/** PCR_CLK_XTAL_OEN : R/W; bitpos: [6]; default: 1; + * Set 1 to enable xtal clock + */ +#define PCR_CLK_XTAL_OEN (BIT(6)) +#define PCR_CLK_XTAL_OEN_M (PCR_CLK_XTAL_OEN_V << PCR_CLK_XTAL_OEN_S) +#define PCR_CLK_XTAL_OEN_V 0x00000001U +#define PCR_CLK_XTAL_OEN_S 6 + +/** PCR_CTRL_TICK_CONF_REG register + * TICK configuration register + */ +#define PCR_CTRL_TICK_CONF_REG (DR_REG_PCR_BASE + 0x12c) +/** PCR_XTAL_TICK_NUM : R/W; bitpos: [7:0]; default: 39; + * ******* Description *********** + */ +#define PCR_XTAL_TICK_NUM 0x000000FFU +#define PCR_XTAL_TICK_NUM_M (PCR_XTAL_TICK_NUM_V << PCR_XTAL_TICK_NUM_S) +#define PCR_XTAL_TICK_NUM_V 0x000000FFU +#define PCR_XTAL_TICK_NUM_S 0 +/** PCR_FOSC_TICK_NUM : R/W; bitpos: [15:8]; default: 7; + * ******* Description *********** + */ +#define PCR_FOSC_TICK_NUM 0x000000FFU +#define PCR_FOSC_TICK_NUM_M (PCR_FOSC_TICK_NUM_V << PCR_FOSC_TICK_NUM_S) +#define PCR_FOSC_TICK_NUM_V 0x000000FFU +#define PCR_FOSC_TICK_NUM_S 8 +/** PCR_TICK_ENABLE : R/W; bitpos: [16]; default: 1; + * ******* Description *********** + */ +#define PCR_TICK_ENABLE (BIT(16)) +#define PCR_TICK_ENABLE_M (PCR_TICK_ENABLE_V << PCR_TICK_ENABLE_S) +#define PCR_TICK_ENABLE_V 0x00000001U +#define PCR_TICK_ENABLE_S 16 +/** PCR_RST_TICK_CNT : R/W; bitpos: [17]; default: 0; + * ******* Description *********** + */ +#define PCR_RST_TICK_CNT (BIT(17)) +#define PCR_RST_TICK_CNT_M (PCR_RST_TICK_CNT_V << PCR_RST_TICK_CNT_S) +#define PCR_RST_TICK_CNT_V 0x00000001U +#define PCR_RST_TICK_CNT_S 17 + +/** PCR_CTRL_32K_CONF_REG register + * 32KHz clock configuration register + */ +#define PCR_CTRL_32K_CONF_REG (DR_REG_PCR_BASE + 0x130) +/** PCR_32K_SEL : R/W; bitpos: [1:0]; default: 0; + * This field indicates which one 32KHz clock will be used by timergroup. 0: + * OSC32K(default), 1: XTAL32K, 2/3: 32KHz from pad GPIO0. + */ +#define PCR_32K_SEL 0x00000003U +#define PCR_32K_SEL_M (PCR_32K_SEL_V << PCR_32K_SEL_S) +#define PCR_32K_SEL_V 0x00000003U +#define PCR_32K_SEL_S 0 +/** PCR_32K_MODEM_SEL : R/W; bitpos: [3:2]; default: 0; + * This field indicates which one 32KHz clock will be used by MODEM_SYSTEM. 0: + * OSC32K(default), 1: XTAL32K, 2/3: 32KHz from pad GPIO0. + */ +#define PCR_32K_MODEM_SEL 0x00000003U +#define PCR_32K_MODEM_SEL_M (PCR_32K_MODEM_SEL_V << PCR_32K_MODEM_SEL_S) +#define PCR_32K_MODEM_SEL_V 0x00000003U +#define PCR_32K_MODEM_SEL_S 2 + +/** PCR_SRAM_POWER_CONF_0_REG register + * HP SRAM/ROM configuration register + */ +#define PCR_SRAM_POWER_CONF_0_REG (DR_REG_PCR_BASE + 0x134) +/** PCR_ROM_FORCE_PU : R/W; bitpos: [14:13]; default: 3; + * Set this bit to force power up ROM + */ +#define PCR_ROM_FORCE_PU 0x00000003U +#define PCR_ROM_FORCE_PU_M (PCR_ROM_FORCE_PU_V << PCR_ROM_FORCE_PU_S) +#define PCR_ROM_FORCE_PU_V 0x00000003U +#define PCR_ROM_FORCE_PU_S 13 +/** PCR_ROM_FORCE_PD : R/W; bitpos: [16:15]; default: 0; + * Set this bit to force power down ROM. + */ +#define PCR_ROM_FORCE_PD 0x00000003U +#define PCR_ROM_FORCE_PD_M (PCR_ROM_FORCE_PD_V << PCR_ROM_FORCE_PD_S) +#define PCR_ROM_FORCE_PD_V 0x00000003U +#define PCR_ROM_FORCE_PD_S 15 +/** PCR_ROM_CLKGATE_FORCE_ON : R/W; bitpos: [18:17]; default: 0; + * 1: Force to open the clock and bypass the gate-clock when accessing the ROM. 0: A + * gate-clock will be used when accessing the ROM. + */ +#define PCR_ROM_CLKGATE_FORCE_ON 0x00000003U +#define PCR_ROM_CLKGATE_FORCE_ON_M (PCR_ROM_CLKGATE_FORCE_ON_V << PCR_ROM_CLKGATE_FORCE_ON_S) +#define PCR_ROM_CLKGATE_FORCE_ON_V 0x00000003U +#define PCR_ROM_CLKGATE_FORCE_ON_S 17 + +/** PCR_SRAM_POWER_CONF_1_REG register + * HP SRAM/ROM configuration register + */ +#define PCR_SRAM_POWER_CONF_1_REG (DR_REG_PCR_BASE + 0x138) +/** PCR_SRAM_FORCE_PU : R/W; bitpos: [4:0]; default: 31; + * Set this bit to force power up SRAM + */ +#define PCR_SRAM_FORCE_PU 0x0000001FU +#define PCR_SRAM_FORCE_PU_M (PCR_SRAM_FORCE_PU_V << PCR_SRAM_FORCE_PU_S) +#define PCR_SRAM_FORCE_PU_V 0x0000001FU +#define PCR_SRAM_FORCE_PU_S 0 +/** PCR_SRAM_FORCE_PD : R/W; bitpos: [14:10]; default: 0; + * Set this bit to force power down SRAM. + */ +#define PCR_SRAM_FORCE_PD 0x0000001FU +#define PCR_SRAM_FORCE_PD_M (PCR_SRAM_FORCE_PD_V << PCR_SRAM_FORCE_PD_S) +#define PCR_SRAM_FORCE_PD_V 0x0000001FU +#define PCR_SRAM_FORCE_PD_S 10 +/** PCR_SRAM_CLKGATE_FORCE_ON : R/W; bitpos: [29:25]; default: 0; + * 1: Force to open the clock and bypass the gate-clock when accessing the SRAM. 0: A + * gate-clock will be used when accessing the SRAM. + */ +#define PCR_SRAM_CLKGATE_FORCE_ON 0x0000001FU +#define PCR_SRAM_CLKGATE_FORCE_ON_M (PCR_SRAM_CLKGATE_FORCE_ON_V << PCR_SRAM_CLKGATE_FORCE_ON_S) +#define PCR_SRAM_CLKGATE_FORCE_ON_V 0x0000001FU +#define PCR_SRAM_CLKGATE_FORCE_ON_S 25 + +/** PCR_SEC_CONF_REG register + * xxxx + */ +#define PCR_SEC_CONF_REG (DR_REG_PCR_BASE + 0x13c) +/** PCR_SEC_CLK_SEL : R/W; bitpos: [1:0]; default: 0; + * xxxx + */ +#define PCR_SEC_CLK_SEL 0x00000003U +#define PCR_SEC_CLK_SEL_M (PCR_SEC_CLK_SEL_V << PCR_SEC_CLK_SEL_S) +#define PCR_SEC_CLK_SEL_V 0x00000003U +#define PCR_SEC_CLK_SEL_S 0 + +/** PCR_ADC_INV_PHASE_CONF_REG register + * xxxx + */ +#define PCR_ADC_INV_PHASE_CONF_REG (DR_REG_PCR_BASE + 0x140) +/** PCR_CLK_ADC_INV_PHASE_ENA : R/W; bitpos: [0]; default: 0; + * xxxx + */ +#define PCR_CLK_ADC_INV_PHASE_ENA (BIT(0)) +#define PCR_CLK_ADC_INV_PHASE_ENA_M (PCR_CLK_ADC_INV_PHASE_ENA_V << PCR_CLK_ADC_INV_PHASE_ENA_S) +#define PCR_CLK_ADC_INV_PHASE_ENA_V 0x00000001U +#define PCR_CLK_ADC_INV_PHASE_ENA_S 0 + +/** PCR_SDM_INV_PHASE_CONF_REG register + * xxxx + */ +#define PCR_SDM_INV_PHASE_CONF_REG (DR_REG_PCR_BASE + 0x144) +/** PCR_CLK_SDM_INV_PHASE_ENA : R/W; bitpos: [0]; default: 0; + * xxxx + */ +#define PCR_CLK_SDM_INV_PHASE_ENA (BIT(0)) +#define PCR_CLK_SDM_INV_PHASE_ENA_M (PCR_CLK_SDM_INV_PHASE_ENA_V << PCR_CLK_SDM_INV_PHASE_ENA_S) +#define PCR_CLK_SDM_INV_PHASE_ENA_V 0x00000001U +#define PCR_CLK_SDM_INV_PHASE_ENA_S 0 +/** PCR_CLK_SDM_INV_PHASE_SEL : R/W; bitpos: [3:1]; default: 0; + * xxxx + */ +#define PCR_CLK_SDM_INV_PHASE_SEL 0x00000007U +#define PCR_CLK_SDM_INV_PHASE_SEL_M (PCR_CLK_SDM_INV_PHASE_SEL_V << PCR_CLK_SDM_INV_PHASE_SEL_S) +#define PCR_CLK_SDM_INV_PHASE_SEL_V 0x00000007U +#define PCR_CLK_SDM_INV_PHASE_SEL_S 1 + +/** PCR_BUS_CLK_UPDATE_REG register + * xxxx + */ +#define PCR_BUS_CLK_UPDATE_REG (DR_REG_PCR_BASE + 0x148) +/** PCR_BUS_CLOCK_UPDATE : R/W/WTC; bitpos: [0]; default: 0; + * xxxx + */ +#define PCR_BUS_CLOCK_UPDATE (BIT(0)) +#define PCR_BUS_CLOCK_UPDATE_M (PCR_BUS_CLOCK_UPDATE_V << PCR_BUS_CLOCK_UPDATE_S) +#define PCR_BUS_CLOCK_UPDATE_V 0x00000001U +#define PCR_BUS_CLOCK_UPDATE_S 0 + +/** PCR_SAR_CLK_DIV_REG register + * xxxx + */ +#define PCR_SAR_CLK_DIV_REG (DR_REG_PCR_BASE + 0x14c) +/** PCR_SAR2_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 4; + * xxxx + */ +#define PCR_SAR2_CLK_DIV_NUM 0x000000FFU +#define PCR_SAR2_CLK_DIV_NUM_M (PCR_SAR2_CLK_DIV_NUM_V << PCR_SAR2_CLK_DIV_NUM_S) +#define PCR_SAR2_CLK_DIV_NUM_V 0x000000FFU +#define PCR_SAR2_CLK_DIV_NUM_S 0 +/** PCR_SAR1_CLK_DIV_NUM : R/W; bitpos: [15:8]; default: 4; + * xxxx + */ +#define PCR_SAR1_CLK_DIV_NUM 0x000000FFU +#define PCR_SAR1_CLK_DIV_NUM_M (PCR_SAR1_CLK_DIV_NUM_V << PCR_SAR1_CLK_DIV_NUM_S) +#define PCR_SAR1_CLK_DIV_NUM_V 0x000000FFU +#define PCR_SAR1_CLK_DIV_NUM_S 8 + +/** PCR_PWDET_SAR_CLK_CONF_REG register + * xxxx + */ +#define PCR_PWDET_SAR_CLK_CONF_REG (DR_REG_PCR_BASE + 0x150) +/** PCR_PWDET_SAR_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 7; + * xxxx + */ +#define PCR_PWDET_SAR_CLK_DIV_NUM 0x000000FFU +#define PCR_PWDET_SAR_CLK_DIV_NUM_M (PCR_PWDET_SAR_CLK_DIV_NUM_V << PCR_PWDET_SAR_CLK_DIV_NUM_S) +#define PCR_PWDET_SAR_CLK_DIV_NUM_V 0x000000FFU +#define PCR_PWDET_SAR_CLK_DIV_NUM_S 0 +/** PCR_PWDET_SAR_READER_EN : R/W; bitpos: [8]; default: 1; + * xxxx + */ +#define PCR_PWDET_SAR_READER_EN (BIT(8)) +#define PCR_PWDET_SAR_READER_EN_M (PCR_PWDET_SAR_READER_EN_V << PCR_PWDET_SAR_READER_EN_S) +#define PCR_PWDET_SAR_READER_EN_V 0x00000001U +#define PCR_PWDET_SAR_READER_EN_S 8 + +/** PCR_RESET_EVENT_BYPASS_REG register + * reset event bypass backdoor configuration register + */ +#define PCR_RESET_EVENT_BYPASS_REG (DR_REG_PCR_BASE + 0xff0) +/** PCR_RESET_EVENT_BYPASS_APM : R/W; bitpos: [0]; default: 0; + * This field is used to control reset event relationship for + * tee_reg/apm_reg/hp_system_reg. 1: tee_reg/apm_reg/hp_system_reg will only be reset + * by power-reset. some reset event will be bypass. 0: tee_reg/apm_reg/hp_system_reg + * will not only be reset by power-reset, but also some reset event. + */ +#define PCR_RESET_EVENT_BYPASS_APM (BIT(0)) +#define PCR_RESET_EVENT_BYPASS_APM_M (PCR_RESET_EVENT_BYPASS_APM_V << PCR_RESET_EVENT_BYPASS_APM_S) +#define PCR_RESET_EVENT_BYPASS_APM_V 0x00000001U +#define PCR_RESET_EVENT_BYPASS_APM_S 0 +/** PCR_RESET_EVENT_BYPASS : R/W; bitpos: [1]; default: 1; + * This field is used to control reset event relationship for system-bus. 1: system + * bus (including arbiter/router) will only be reset by power-reset. some reset event + * will be bypass. 0: system bus (including arbiter/router) will not only be reset by + * power-reset, but also some reset event. + */ +#define PCR_RESET_EVENT_BYPASS (BIT(1)) +#define PCR_RESET_EVENT_BYPASS_M (PCR_RESET_EVENT_BYPASS_V << PCR_RESET_EVENT_BYPASS_S) +#define PCR_RESET_EVENT_BYPASS_V 0x00000001U +#define PCR_RESET_EVENT_BYPASS_S 1 + +/** PCR_FPGA_DEBUG_REG register + * fpga debug register + */ +#define PCR_FPGA_DEBUG_REG (DR_REG_PCR_BASE + 0xff4) +/** PCR_FPGA_DEBUG : R/W; bitpos: [31:0]; default: 4294967295; + * Only used in fpga debug. + */ +#define PCR_FPGA_DEBUG 0xFFFFFFFFU +#define PCR_FPGA_DEBUG_M (PCR_FPGA_DEBUG_V << PCR_FPGA_DEBUG_S) +#define PCR_FPGA_DEBUG_V 0xFFFFFFFFU +#define PCR_FPGA_DEBUG_S 0 + +/** PCR_CLOCK_GATE_REG register + * PCR clock gating configure register + */ +#define PCR_CLOCK_GATE_REG (DR_REG_PCR_BASE + 0xff8) +/** PCR_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set this bit as 1 to force on clock gating. + */ +#define PCR_CLK_EN (BIT(0)) +#define PCR_CLK_EN_M (PCR_CLK_EN_V << PCR_CLK_EN_S) +#define PCR_CLK_EN_V 0x00000001U +#define PCR_CLK_EN_S 0 + +/** PCR_DATE_REG register + * Date register. + */ +#define PCR_DATE_REG (DR_REG_PCR_BASE + 0xffc) +/** PCR_DATE : R/W; bitpos: [27:0]; default: 35717248; + * PCR version information. + */ +#define PCR_DATE 0x0FFFFFFFU +#define PCR_DATE_M (PCR_DATE_V << PCR_DATE_S) +#define PCR_DATE_V 0x0FFFFFFFU +#define PCR_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/src/target/esp32h2/ld/esp32h2.rom.api.ld b/src/target/esp32h2/ld/esp32h2.rom.api.ld index 23dbb89..59e4861 100644 --- a/src/target/esp32h2/ld/esp32h2.rom.api.ld +++ b/src/target/esp32h2/ld/esp32h2.rom.api.ld @@ -28,9 +28,9 @@ PROVIDE ( esp_rom_uart_putc = ets_write_char_uart ); PROVIDE ( esp_rom_uart_attach = uartAttach ); PROVIDE ( esp_rom_uart_init = Uart_Init ); PROVIDE ( esp_rom_uart_div_modify = uart_div_modify ); -PROVIDE ( esp_rom_get_apb_freq = ets_get_apb_freq ); PROVIDE ( esp_rom_get_cpu_freq = ets_clk_get_cpu_freq ); PROVIDE ( esp_rom_get_uart_device = GetUartDevice ); +PROVIDE ( esp_rom_get_xtal_freq = ets_clk_get_xtal_freq ); PROVIDE ( esp_rom_output_flush_tx = uart_tx_flush ); PROVIDE ( esp_rom_output_tx_one_char = uart_tx_one_char ); diff --git a/src/target/esp32h2/src/clock.c b/src/target/esp32h2/src/clock.c new file mode 100644 index 0000000..039f122 --- /dev/null +++ b/src/target/esp32h2/src/clock.c @@ -0,0 +1,35 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 OR MIT + */ + +#include +#include +#include +#include +#include +#include + +#define MHZ 1000000 + +extern uint32_t esp_rom_get_cpu_freq(void); +extern void esp_rom_set_cpu_ticks_per_us(uint32_t ticks_per_us); + +static uint32_t s_cpu_freq = 0; + +void stub_target_clock_init(void) +{ + REG_SET_FIELD(PCR_SYSCLK_CONF_REG, PCR_SOC_CLK_SEL, 1); + REG_SET_FIELD(PCR_BUS_CLK_UPDATE_REG, PCR_BUS_CLOCK_UPDATE, 1); + s_cpu_freq = 96 * MHZ; + esp_rom_set_cpu_ticks_per_us(s_cpu_freq / MHZ); +} + +uint32_t stub_target_get_cpu_freq(void) +{ + if (s_cpu_freq == 0) { + return esp_rom_get_cpu_freq(); + } + return s_cpu_freq; +} diff --git a/src/target/esp32h21/include/soc/pcr_reg.h b/src/target/esp32h21/include/soc/pcr_reg.h new file mode 100644 index 0000000..7ac0e1e --- /dev/null +++ b/src/target/esp32h21/include/soc/pcr_reg.h @@ -0,0 +1,2238 @@ +/** + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 OR MIT + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** PCR_UART0_CONF_REG register + * UART0 configuration register + */ +#define PCR_UART0_CONF_REG (DR_REG_PCR_BASE + 0x0) +/** PCR_UART0_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable uart0 apb clock + */ +#define PCR_UART0_CLK_EN (BIT(0)) +#define PCR_UART0_CLK_EN_M (PCR_UART0_CLK_EN_V << PCR_UART0_CLK_EN_S) +#define PCR_UART0_CLK_EN_V 0x00000001U +#define PCR_UART0_CLK_EN_S 0 +/** PCR_UART0_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset uart0 module + */ +#define PCR_UART0_RST_EN (BIT(1)) +#define PCR_UART0_RST_EN_M (PCR_UART0_RST_EN_V << PCR_UART0_RST_EN_S) +#define PCR_UART0_RST_EN_V 0x00000001U +#define PCR_UART0_RST_EN_S 1 +/** PCR_UART0_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset uart0 module + */ +#define PCR_UART0_READY (BIT(2)) +#define PCR_UART0_READY_M (PCR_UART0_READY_V << PCR_UART0_READY_S) +#define PCR_UART0_READY_V 0x00000001U +#define PCR_UART0_READY_S 2 + +/** PCR_UART0_SCLK_CONF_REG register + * UART0_SCLK configuration register + */ +#define PCR_UART0_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x4) +/** PCR_UART0_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the uart0 function clock. + */ +#define PCR_UART0_SCLK_DIV_A 0x0000003FU +#define PCR_UART0_SCLK_DIV_A_M (PCR_UART0_SCLK_DIV_A_V << PCR_UART0_SCLK_DIV_A_S) +#define PCR_UART0_SCLK_DIV_A_V 0x0000003FU +#define PCR_UART0_SCLK_DIV_A_S 0 +/** PCR_UART0_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the uart0 function clock. + */ +#define PCR_UART0_SCLK_DIV_B 0x0000003FU +#define PCR_UART0_SCLK_DIV_B_M (PCR_UART0_SCLK_DIV_B_V << PCR_UART0_SCLK_DIV_B_S) +#define PCR_UART0_SCLK_DIV_B_V 0x0000003FU +#define PCR_UART0_SCLK_DIV_B_S 6 +/** PCR_UART0_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the uart0 function clock. + */ +#define PCR_UART0_SCLK_DIV_NUM 0x000000FFU +#define PCR_UART0_SCLK_DIV_NUM_M (PCR_UART0_SCLK_DIV_NUM_V << PCR_UART0_SCLK_DIV_NUM_S) +#define PCR_UART0_SCLK_DIV_NUM_V 0x000000FFU +#define PCR_UART0_SCLK_DIV_NUM_S 12 +/** PCR_UART0_SCLK_SEL : R/W; bitpos: [21:20]; default: 3; + * set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: + * FOSC, 3(default): XTAL. + */ +#define PCR_UART0_SCLK_SEL 0x00000003U +#define PCR_UART0_SCLK_SEL_M (PCR_UART0_SCLK_SEL_V << PCR_UART0_SCLK_SEL_S) +#define PCR_UART0_SCLK_SEL_V 0x00000003U +#define PCR_UART0_SCLK_SEL_S 20 +/** PCR_UART0_SCLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable uart0 function clock + */ +#define PCR_UART0_SCLK_EN (BIT(22)) +#define PCR_UART0_SCLK_EN_M (PCR_UART0_SCLK_EN_V << PCR_UART0_SCLK_EN_S) +#define PCR_UART0_SCLK_EN_V 0x00000001U +#define PCR_UART0_SCLK_EN_S 22 + +/** PCR_UART0_PD_CTRL_REG register + * UART0 power control register + */ +#define PCR_UART0_PD_CTRL_REG (DR_REG_PCR_BASE + 0x8) +/** PCR_UART0_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1; + * Set this bit to force power down UART0 memory. + */ +#define PCR_UART0_MEM_FORCE_PU (BIT(1)) +#define PCR_UART0_MEM_FORCE_PU_M (PCR_UART0_MEM_FORCE_PU_V << PCR_UART0_MEM_FORCE_PU_S) +#define PCR_UART0_MEM_FORCE_PU_V 0x00000001U +#define PCR_UART0_MEM_FORCE_PU_S 1 +/** PCR_UART0_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; + * Set this bit to force power up UART0 memory. + */ +#define PCR_UART0_MEM_FORCE_PD (BIT(2)) +#define PCR_UART0_MEM_FORCE_PD_M (PCR_UART0_MEM_FORCE_PD_V << PCR_UART0_MEM_FORCE_PD_S) +#define PCR_UART0_MEM_FORCE_PD_V 0x00000001U +#define PCR_UART0_MEM_FORCE_PD_S 2 + +/** PCR_UART1_CONF_REG register + * UART1 configuration register + */ +#define PCR_UART1_CONF_REG (DR_REG_PCR_BASE + 0xc) +/** PCR_UART1_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable uart1 apb clock + */ +#define PCR_UART1_CLK_EN (BIT(0)) +#define PCR_UART1_CLK_EN_M (PCR_UART1_CLK_EN_V << PCR_UART1_CLK_EN_S) +#define PCR_UART1_CLK_EN_V 0x00000001U +#define PCR_UART1_CLK_EN_S 0 +/** PCR_UART1_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset uart1 module + */ +#define PCR_UART1_RST_EN (BIT(1)) +#define PCR_UART1_RST_EN_M (PCR_UART1_RST_EN_V << PCR_UART1_RST_EN_S) +#define PCR_UART1_RST_EN_V 0x00000001U +#define PCR_UART1_RST_EN_S 1 +/** PCR_UART1_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset uart1 module + */ +#define PCR_UART1_READY (BIT(2)) +#define PCR_UART1_READY_M (PCR_UART1_READY_V << PCR_UART1_READY_S) +#define PCR_UART1_READY_V 0x00000001U +#define PCR_UART1_READY_S 2 + +/** PCR_UART1_SCLK_CONF_REG register + * UART1_SCLK configuration register + */ +#define PCR_UART1_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x10) +/** PCR_UART1_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the uart1 function clock. + */ +#define PCR_UART1_SCLK_DIV_A 0x0000003FU +#define PCR_UART1_SCLK_DIV_A_M (PCR_UART1_SCLK_DIV_A_V << PCR_UART1_SCLK_DIV_A_S) +#define PCR_UART1_SCLK_DIV_A_V 0x0000003FU +#define PCR_UART1_SCLK_DIV_A_S 0 +/** PCR_UART1_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the uart1 function clock. + */ +#define PCR_UART1_SCLK_DIV_B 0x0000003FU +#define PCR_UART1_SCLK_DIV_B_M (PCR_UART1_SCLK_DIV_B_V << PCR_UART1_SCLK_DIV_B_S) +#define PCR_UART1_SCLK_DIV_B_V 0x0000003FU +#define PCR_UART1_SCLK_DIV_B_S 6 +/** PCR_UART1_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the uart1 function clock. + */ +#define PCR_UART1_SCLK_DIV_NUM 0x000000FFU +#define PCR_UART1_SCLK_DIV_NUM_M (PCR_UART1_SCLK_DIV_NUM_V << PCR_UART1_SCLK_DIV_NUM_S) +#define PCR_UART1_SCLK_DIV_NUM_V 0x000000FFU +#define PCR_UART1_SCLK_DIV_NUM_S 12 +/** PCR_UART1_SCLK_SEL : R/W; bitpos: [21:20]; default: 3; + * set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: + * FOSC, 3(default): XTAL. + */ +#define PCR_UART1_SCLK_SEL 0x00000003U +#define PCR_UART1_SCLK_SEL_M (PCR_UART1_SCLK_SEL_V << PCR_UART1_SCLK_SEL_S) +#define PCR_UART1_SCLK_SEL_V 0x00000003U +#define PCR_UART1_SCLK_SEL_S 20 +/** PCR_UART1_SCLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable uart0 function clock + */ +#define PCR_UART1_SCLK_EN (BIT(22)) +#define PCR_UART1_SCLK_EN_M (PCR_UART1_SCLK_EN_V << PCR_UART1_SCLK_EN_S) +#define PCR_UART1_SCLK_EN_V 0x00000001U +#define PCR_UART1_SCLK_EN_S 22 + +/** PCR_UART1_PD_CTRL_REG register + * UART1 power control register + */ +#define PCR_UART1_PD_CTRL_REG (DR_REG_PCR_BASE + 0x14) +/** PCR_UART1_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1; + * Set this bit to force power down UART1 memory. + */ +#define PCR_UART1_MEM_FORCE_PU (BIT(1)) +#define PCR_UART1_MEM_FORCE_PU_M (PCR_UART1_MEM_FORCE_PU_V << PCR_UART1_MEM_FORCE_PU_S) +#define PCR_UART1_MEM_FORCE_PU_V 0x00000001U +#define PCR_UART1_MEM_FORCE_PU_S 1 +/** PCR_UART1_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; + * Set this bit to force power up UART1 memory. + */ +#define PCR_UART1_MEM_FORCE_PD (BIT(2)) +#define PCR_UART1_MEM_FORCE_PD_M (PCR_UART1_MEM_FORCE_PD_V << PCR_UART1_MEM_FORCE_PD_S) +#define PCR_UART1_MEM_FORCE_PD_V 0x00000001U +#define PCR_UART1_MEM_FORCE_PD_S 2 + +/** PCR_MSPI_CONF_REG register + * MSPI configuration register + */ +#define PCR_MSPI_CONF_REG (DR_REG_PCR_BASE + 0x18) +/** PCR_MSPI_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable mspi clock, include mspi pll clock + */ +#define PCR_MSPI_CLK_EN (BIT(0)) +#define PCR_MSPI_CLK_EN_M (PCR_MSPI_CLK_EN_V << PCR_MSPI_CLK_EN_S) +#define PCR_MSPI_CLK_EN_V 0x00000001U +#define PCR_MSPI_CLK_EN_S 0 +/** PCR_MSPI_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset mspi module + */ +#define PCR_MSPI_RST_EN (BIT(1)) +#define PCR_MSPI_RST_EN_M (PCR_MSPI_RST_EN_V << PCR_MSPI_RST_EN_S) +#define PCR_MSPI_RST_EN_V 0x00000001U +#define PCR_MSPI_RST_EN_S 1 +/** PCR_MSPI_PLL_CLK_EN : R/W; bitpos: [2]; default: 1; + * Set 1 to enable mspi pll clock + */ +#define PCR_MSPI_PLL_CLK_EN (BIT(2)) +#define PCR_MSPI_PLL_CLK_EN_M (PCR_MSPI_PLL_CLK_EN_V << PCR_MSPI_PLL_CLK_EN_S) +#define PCR_MSPI_PLL_CLK_EN_V 0x00000001U +#define PCR_MSPI_PLL_CLK_EN_S 2 +/** PCR_MSPI_CLK_SEL : R/W; bitpos: [4:3]; default: 0; + * set this field to select clock-source. + */ +#define PCR_MSPI_CLK_SEL 0x00000003U +#define PCR_MSPI_CLK_SEL_M (PCR_MSPI_CLK_SEL_V << PCR_MSPI_CLK_SEL_S) +#define PCR_MSPI_CLK_SEL_V 0x00000003U +#define PCR_MSPI_CLK_SEL_S 3 +/** PCR_MSPI_READY : RO; bitpos: [5]; default: 1; + * Query this field after reset mspi module + */ +#define PCR_MSPI_READY (BIT(5)) +#define PCR_MSPI_READY_M (PCR_MSPI_READY_V << PCR_MSPI_READY_S) +#define PCR_MSPI_READY_V 0x00000001U +#define PCR_MSPI_READY_S 5 + +/** PCR_MSPI_CLK_CONF_REG register + * MSPI_CLK configuration register + */ +#define PCR_MSPI_CLK_CONF_REG (DR_REG_PCR_BASE + 0x1c) +/** PCR_MSPI_FAST_DIV_NUM : R/W; bitpos: [7:0]; default: 0; + * Set as one within (0,1,2) to generate div1(default)/div2/div4 of low-speed + * clock-source to drive clk_mspi_fast. Only available when the clck-source is a + * low-speed clock-source such as XTAL/FOSC. + */ +#define PCR_MSPI_FAST_DIV_NUM 0x000000FFU +#define PCR_MSPI_FAST_DIV_NUM_M (PCR_MSPI_FAST_DIV_NUM_V << PCR_MSPI_FAST_DIV_NUM_S) +#define PCR_MSPI_FAST_DIV_NUM_V 0x000000FFU +#define PCR_MSPI_FAST_DIV_NUM_S 0 + +/** PCR_I2C0_CONF_REG register + * I2C configuration register + */ +#define PCR_I2C0_CONF_REG (DR_REG_PCR_BASE + 0x20) +/** PCR_I2C0_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable i2c apb clock + */ +#define PCR_I2C0_CLK_EN (BIT(0)) +#define PCR_I2C0_CLK_EN_M (PCR_I2C0_CLK_EN_V << PCR_I2C0_CLK_EN_S) +#define PCR_I2C0_CLK_EN_V 0x00000001U +#define PCR_I2C0_CLK_EN_S 0 +/** PCR_I2C0_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset i2c module + */ +#define PCR_I2C0_RST_EN (BIT(1)) +#define PCR_I2C0_RST_EN_M (PCR_I2C0_RST_EN_V << PCR_I2C0_RST_EN_S) +#define PCR_I2C0_RST_EN_V 0x00000001U +#define PCR_I2C0_RST_EN_S 1 +/** PCR_I2C0_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset i2c0 module + */ +#define PCR_I2C0_READY (BIT(2)) +#define PCR_I2C0_READY_M (PCR_I2C0_READY_V << PCR_I2C0_READY_S) +#define PCR_I2C0_READY_V 0x00000001U +#define PCR_I2C0_READY_S 2 + +/** PCR_I2C0_SCLK_CONF_REG register + * I2C_SCLK configuration register + */ +#define PCR_I2C0_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x24) +/** PCR_I2C0_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the i2c function clock. + */ +#define PCR_I2C0_SCLK_DIV_A 0x0000003FU +#define PCR_I2C0_SCLK_DIV_A_M (PCR_I2C0_SCLK_DIV_A_V << PCR_I2C0_SCLK_DIV_A_S) +#define PCR_I2C0_SCLK_DIV_A_V 0x0000003FU +#define PCR_I2C0_SCLK_DIV_A_S 0 +/** PCR_I2C0_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the i2c function clock. + */ +#define PCR_I2C0_SCLK_DIV_B 0x0000003FU +#define PCR_I2C0_SCLK_DIV_B_M (PCR_I2C0_SCLK_DIV_B_V << PCR_I2C0_SCLK_DIV_B_S) +#define PCR_I2C0_SCLK_DIV_B_V 0x0000003FU +#define PCR_I2C0_SCLK_DIV_B_S 6 +/** PCR_I2C0_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the i2c function clock. + */ +#define PCR_I2C0_SCLK_DIV_NUM 0x000000FFU +#define PCR_I2C0_SCLK_DIV_NUM_M (PCR_I2C0_SCLK_DIV_NUM_V << PCR_I2C0_SCLK_DIV_NUM_S) +#define PCR_I2C0_SCLK_DIV_NUM_V 0x000000FFU +#define PCR_I2C0_SCLK_DIV_NUM_S 12 +/** PCR_I2C0_SCLK_SEL : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: FOSC. + */ +#define PCR_I2C0_SCLK_SEL (BIT(20)) +#define PCR_I2C0_SCLK_SEL_M (PCR_I2C0_SCLK_SEL_V << PCR_I2C0_SCLK_SEL_S) +#define PCR_I2C0_SCLK_SEL_V 0x00000001U +#define PCR_I2C0_SCLK_SEL_S 20 +/** PCR_I2C0_SCLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable i2c function clock + */ +#define PCR_I2C0_SCLK_EN (BIT(22)) +#define PCR_I2C0_SCLK_EN_M (PCR_I2C0_SCLK_EN_V << PCR_I2C0_SCLK_EN_S) +#define PCR_I2C0_SCLK_EN_V 0x00000001U +#define PCR_I2C0_SCLK_EN_S 22 + +/** PCR_I2C1_CONF_REG register + * I2C configuration register + */ +#define PCR_I2C1_CONF_REG (DR_REG_PCR_BASE + 0x28) +/** PCR_I2C1_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable i2c apb clock + */ +#define PCR_I2C1_CLK_EN (BIT(0)) +#define PCR_I2C1_CLK_EN_M (PCR_I2C1_CLK_EN_V << PCR_I2C1_CLK_EN_S) +#define PCR_I2C1_CLK_EN_V 0x00000001U +#define PCR_I2C1_CLK_EN_S 0 +/** PCR_I2C1_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset i2c module + */ +#define PCR_I2C1_RST_EN (BIT(1)) +#define PCR_I2C1_RST_EN_M (PCR_I2C1_RST_EN_V << PCR_I2C1_RST_EN_S) +#define PCR_I2C1_RST_EN_V 0x00000001U +#define PCR_I2C1_RST_EN_S 1 +/** PCR_I2C1_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset i2c1 module + */ +#define PCR_I2C1_READY (BIT(2)) +#define PCR_I2C1_READY_M (PCR_I2C1_READY_V << PCR_I2C1_READY_S) +#define PCR_I2C1_READY_V 0x00000001U +#define PCR_I2C1_READY_S 2 + +/** PCR_I2C1_SCLK_CONF_REG register + * I2C_SCLK configuration register + */ +#define PCR_I2C1_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x2c) +/** PCR_I2C1_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the i2c function clock. + */ +#define PCR_I2C1_SCLK_DIV_A 0x0000003FU +#define PCR_I2C1_SCLK_DIV_A_M (PCR_I2C1_SCLK_DIV_A_V << PCR_I2C1_SCLK_DIV_A_S) +#define PCR_I2C1_SCLK_DIV_A_V 0x0000003FU +#define PCR_I2C1_SCLK_DIV_A_S 0 +/** PCR_I2C1_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the i2c function clock. + */ +#define PCR_I2C1_SCLK_DIV_B 0x0000003FU +#define PCR_I2C1_SCLK_DIV_B_M (PCR_I2C1_SCLK_DIV_B_V << PCR_I2C1_SCLK_DIV_B_S) +#define PCR_I2C1_SCLK_DIV_B_V 0x0000003FU +#define PCR_I2C1_SCLK_DIV_B_S 6 +/** PCR_I2C1_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the i2c function clock. + */ +#define PCR_I2C1_SCLK_DIV_NUM 0x000000FFU +#define PCR_I2C1_SCLK_DIV_NUM_M (PCR_I2C1_SCLK_DIV_NUM_V << PCR_I2C1_SCLK_DIV_NUM_S) +#define PCR_I2C1_SCLK_DIV_NUM_V 0x000000FFU +#define PCR_I2C1_SCLK_DIV_NUM_S 12 +/** PCR_I2C1_SCLK_SEL : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: FOSC. + */ +#define PCR_I2C1_SCLK_SEL (BIT(20)) +#define PCR_I2C1_SCLK_SEL_M (PCR_I2C1_SCLK_SEL_V << PCR_I2C1_SCLK_SEL_S) +#define PCR_I2C1_SCLK_SEL_V 0x00000001U +#define PCR_I2C1_SCLK_SEL_S 20 +/** PCR_I2C1_SCLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable i2c function clock + */ +#define PCR_I2C1_SCLK_EN (BIT(22)) +#define PCR_I2C1_SCLK_EN_M (PCR_I2C1_SCLK_EN_V << PCR_I2C1_SCLK_EN_S) +#define PCR_I2C1_SCLK_EN_V 0x00000001U +#define PCR_I2C1_SCLK_EN_S 22 + +/** PCR_UHCI_CONF_REG register + * UHCI configuration register + */ +#define PCR_UHCI_CONF_REG (DR_REG_PCR_BASE + 0x30) +/** PCR_UHCI_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable uhci clock + */ +#define PCR_UHCI_CLK_EN (BIT(0)) +#define PCR_UHCI_CLK_EN_M (PCR_UHCI_CLK_EN_V << PCR_UHCI_CLK_EN_S) +#define PCR_UHCI_CLK_EN_V 0x00000001U +#define PCR_UHCI_CLK_EN_S 0 +/** PCR_UHCI_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset uhci module + */ +#define PCR_UHCI_RST_EN (BIT(1)) +#define PCR_UHCI_RST_EN_M (PCR_UHCI_RST_EN_V << PCR_UHCI_RST_EN_S) +#define PCR_UHCI_RST_EN_V 0x00000001U +#define PCR_UHCI_RST_EN_S 1 +/** PCR_UHCI_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset uhci module + */ +#define PCR_UHCI_READY (BIT(2)) +#define PCR_UHCI_READY_M (PCR_UHCI_READY_V << PCR_UHCI_READY_S) +#define PCR_UHCI_READY_V 0x00000001U +#define PCR_UHCI_READY_S 2 + +/** PCR_RMT_CONF_REG register + * RMT configuration register + */ +#define PCR_RMT_CONF_REG (DR_REG_PCR_BASE + 0x34) +/** PCR_RMT_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable rmt apb clock + */ +#define PCR_RMT_CLK_EN (BIT(0)) +#define PCR_RMT_CLK_EN_M (PCR_RMT_CLK_EN_V << PCR_RMT_CLK_EN_S) +#define PCR_RMT_CLK_EN_V 0x00000001U +#define PCR_RMT_CLK_EN_S 0 +/** PCR_RMT_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset rmt module + */ +#define PCR_RMT_RST_EN (BIT(1)) +#define PCR_RMT_RST_EN_M (PCR_RMT_RST_EN_V << PCR_RMT_RST_EN_S) +#define PCR_RMT_RST_EN_V 0x00000001U +#define PCR_RMT_RST_EN_S 1 +/** PCR_RMT_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset rmt module + */ +#define PCR_RMT_READY (BIT(2)) +#define PCR_RMT_READY_M (PCR_RMT_READY_V << PCR_RMT_READY_S) +#define PCR_RMT_READY_V 0x00000001U +#define PCR_RMT_READY_S 2 + +/** PCR_RMT_SCLK_CONF_REG register + * RMT_SCLK configuration register + */ +#define PCR_RMT_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x38) +/** PCR_RMT_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the rmt function clock. + */ +#define PCR_RMT_SCLK_DIV_A 0x0000003FU +#define PCR_RMT_SCLK_DIV_A_M (PCR_RMT_SCLK_DIV_A_V << PCR_RMT_SCLK_DIV_A_S) +#define PCR_RMT_SCLK_DIV_A_V 0x0000003FU +#define PCR_RMT_SCLK_DIV_A_S 0 +/** PCR_RMT_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the rmt function clock. + */ +#define PCR_RMT_SCLK_DIV_B 0x0000003FU +#define PCR_RMT_SCLK_DIV_B_M (PCR_RMT_SCLK_DIV_B_V << PCR_RMT_SCLK_DIV_B_S) +#define PCR_RMT_SCLK_DIV_B_V 0x0000003FU +#define PCR_RMT_SCLK_DIV_B_S 6 +/** PCR_RMT_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 1; + * The integral part of the frequency divider factor of the rmt function clock. + */ +#define PCR_RMT_SCLK_DIV_NUM 0x000000FFU +#define PCR_RMT_SCLK_DIV_NUM_M (PCR_RMT_SCLK_DIV_NUM_V << PCR_RMT_SCLK_DIV_NUM_S) +#define PCR_RMT_SCLK_DIV_NUM_V 0x000000FFU +#define PCR_RMT_SCLK_DIV_NUM_S 12 +/** PCR_RMT_SCLK_SEL : R/W; bitpos: [20]; default: 1; + * set this field to select clock-source. 0: do not select anyone clock, 1(default): + * 80MHz, 2: FOSC, 3: XTAL. + */ +#define PCR_RMT_SCLK_SEL (BIT(20)) +#define PCR_RMT_SCLK_SEL_M (PCR_RMT_SCLK_SEL_V << PCR_RMT_SCLK_SEL_S) +#define PCR_RMT_SCLK_SEL_V 0x00000001U +#define PCR_RMT_SCLK_SEL_S 20 +/** PCR_RMT_SCLK_EN : R/W; bitpos: [21]; default: 1; + * Set 1 to enable rmt function clock + */ +#define PCR_RMT_SCLK_EN (BIT(21)) +#define PCR_RMT_SCLK_EN_M (PCR_RMT_SCLK_EN_V << PCR_RMT_SCLK_EN_S) +#define PCR_RMT_SCLK_EN_V 0x00000001U +#define PCR_RMT_SCLK_EN_S 21 + +/** PCR_LEDC_CONF_REG register + * LEDC configuration register + */ +#define PCR_LEDC_CONF_REG (DR_REG_PCR_BASE + 0x3c) +/** PCR_LEDC_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable ledc apb clock + */ +#define PCR_LEDC_CLK_EN (BIT(0)) +#define PCR_LEDC_CLK_EN_M (PCR_LEDC_CLK_EN_V << PCR_LEDC_CLK_EN_S) +#define PCR_LEDC_CLK_EN_V 0x00000001U +#define PCR_LEDC_CLK_EN_S 0 +/** PCR_LEDC_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset ledc module + */ +#define PCR_LEDC_RST_EN (BIT(1)) +#define PCR_LEDC_RST_EN_M (PCR_LEDC_RST_EN_V << PCR_LEDC_RST_EN_S) +#define PCR_LEDC_RST_EN_V 0x00000001U +#define PCR_LEDC_RST_EN_S 1 +/** PCR_LEDC_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset ledc module + */ +#define PCR_LEDC_READY (BIT(2)) +#define PCR_LEDC_READY_M (PCR_LEDC_READY_V << PCR_LEDC_READY_S) +#define PCR_LEDC_READY_V 0x00000001U +#define PCR_LEDC_READY_S 2 + +/** PCR_LEDC_SCLK_CONF_REG register + * LEDC_SCLK configuration register + */ +#define PCR_LEDC_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x40) +/** PCR_LEDC_SCLK_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: + * FOSC, 2: 96MHz. + */ +#define PCR_LEDC_SCLK_SEL 0x00000003U +#define PCR_LEDC_SCLK_SEL_M (PCR_LEDC_SCLK_SEL_V << PCR_LEDC_SCLK_SEL_S) +#define PCR_LEDC_SCLK_SEL_V 0x00000003U +#define PCR_LEDC_SCLK_SEL_S 20 +/** PCR_LEDC_SCLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable ledc function clock + */ +#define PCR_LEDC_SCLK_EN (BIT(22)) +#define PCR_LEDC_SCLK_EN_M (PCR_LEDC_SCLK_EN_V << PCR_LEDC_SCLK_EN_S) +#define PCR_LEDC_SCLK_EN_V 0x00000001U +#define PCR_LEDC_SCLK_EN_S 22 + +/** PCR_TIMERGROUP0_CONF_REG register + * TIMERGROUP0 configuration register + */ +#define PCR_TIMERGROUP0_CONF_REG (DR_REG_PCR_BASE + 0x44) +/** PCR_TG0_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable timer_group0 apb clock + */ +#define PCR_TG0_CLK_EN (BIT(0)) +#define PCR_TG0_CLK_EN_M (PCR_TG0_CLK_EN_V << PCR_TG0_CLK_EN_S) +#define PCR_TG0_CLK_EN_V 0x00000001U +#define PCR_TG0_CLK_EN_S 0 +/** PCR_TG0_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset timer_group0 module + */ +#define PCR_TG0_RST_EN (BIT(1)) +#define PCR_TG0_RST_EN_M (PCR_TG0_RST_EN_V << PCR_TG0_RST_EN_S) +#define PCR_TG0_RST_EN_V 0x00000001U +#define PCR_TG0_RST_EN_S 1 +/** PCR_TG0_WDT_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset timer_group0 wdt module + */ +#define PCR_TG0_WDT_READY (BIT(2)) +#define PCR_TG0_WDT_READY_M (PCR_TG0_WDT_READY_V << PCR_TG0_WDT_READY_S) +#define PCR_TG0_WDT_READY_V 0x00000001U +#define PCR_TG0_WDT_READY_S 2 +/** PCR_TG0_TIMER0_READY : RO; bitpos: [3]; default: 1; + * Query this field after reset timer_group0 timer0 module + */ +#define PCR_TG0_TIMER0_READY (BIT(3)) +#define PCR_TG0_TIMER0_READY_M (PCR_TG0_TIMER0_READY_V << PCR_TG0_TIMER0_READY_S) +#define PCR_TG0_TIMER0_READY_V 0x00000001U +#define PCR_TG0_TIMER0_READY_S 3 +/** PCR_TG0_TIMER1_READY : RO; bitpos: [4]; default: 1; + * reserved + */ +#define PCR_TG0_TIMER1_READY (BIT(4)) +#define PCR_TG0_TIMER1_READY_M (PCR_TG0_TIMER1_READY_V << PCR_TG0_TIMER1_READY_S) +#define PCR_TG0_TIMER1_READY_V 0x00000001U +#define PCR_TG0_TIMER1_READY_S 4 + +/** PCR_TIMERGROUP0_TIMER_CLK_CONF_REG register + * TIMERGROUP0_TIMER_CLK configuration register + */ +#define PCR_TIMERGROUP0_TIMER_CLK_CONF_REG (DR_REG_PCR_BASE + 0x48) +/** PCR_TG0_TIMER_CLK_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: + * reserved. + */ +#define PCR_TG0_TIMER_CLK_SEL 0x00000003U +#define PCR_TG0_TIMER_CLK_SEL_M (PCR_TG0_TIMER_CLK_SEL_V << PCR_TG0_TIMER_CLK_SEL_S) +#define PCR_TG0_TIMER_CLK_SEL_V 0x00000003U +#define PCR_TG0_TIMER_CLK_SEL_S 20 +/** PCR_TG0_TIMER_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group0 timer clock + */ +#define PCR_TG0_TIMER_CLK_EN (BIT(22)) +#define PCR_TG0_TIMER_CLK_EN_M (PCR_TG0_TIMER_CLK_EN_V << PCR_TG0_TIMER_CLK_EN_S) +#define PCR_TG0_TIMER_CLK_EN_V 0x00000001U +#define PCR_TG0_TIMER_CLK_EN_S 22 + +/** PCR_TIMERGROUP0_WDT_CLK_CONF_REG register + * TIMERGROUP0_WDT_CLK configuration register + */ +#define PCR_TIMERGROUP0_WDT_CLK_CONF_REG (DR_REG_PCR_BASE + 0x4c) +/** PCR_TG0_WDT_CLK_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: + * reserved. + */ +#define PCR_TG0_WDT_CLK_SEL 0x00000003U +#define PCR_TG0_WDT_CLK_SEL_M (PCR_TG0_WDT_CLK_SEL_V << PCR_TG0_WDT_CLK_SEL_S) +#define PCR_TG0_WDT_CLK_SEL_V 0x00000003U +#define PCR_TG0_WDT_CLK_SEL_S 20 +/** PCR_TG0_WDT_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group0 wdt clock + */ +#define PCR_TG0_WDT_CLK_EN (BIT(22)) +#define PCR_TG0_WDT_CLK_EN_M (PCR_TG0_WDT_CLK_EN_V << PCR_TG0_WDT_CLK_EN_S) +#define PCR_TG0_WDT_CLK_EN_V 0x00000001U +#define PCR_TG0_WDT_CLK_EN_S 22 + +/** PCR_TIMERGROUP1_CONF_REG register + * TIMERGROUP1 configuration register + */ +#define PCR_TIMERGROUP1_CONF_REG (DR_REG_PCR_BASE + 0x50) +/** PCR_TG1_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable timer_group1 apb clock + */ +#define PCR_TG1_CLK_EN (BIT(0)) +#define PCR_TG1_CLK_EN_M (PCR_TG1_CLK_EN_V << PCR_TG1_CLK_EN_S) +#define PCR_TG1_CLK_EN_V 0x00000001U +#define PCR_TG1_CLK_EN_S 0 +/** PCR_TG1_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset timer_group1 module + */ +#define PCR_TG1_RST_EN (BIT(1)) +#define PCR_TG1_RST_EN_M (PCR_TG1_RST_EN_V << PCR_TG1_RST_EN_S) +#define PCR_TG1_RST_EN_V 0x00000001U +#define PCR_TG1_RST_EN_S 1 +/** PCR_TG1_WDT_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset timer_group1 wdt module + */ +#define PCR_TG1_WDT_READY (BIT(2)) +#define PCR_TG1_WDT_READY_M (PCR_TG1_WDT_READY_V << PCR_TG1_WDT_READY_S) +#define PCR_TG1_WDT_READY_V 0x00000001U +#define PCR_TG1_WDT_READY_S 2 +/** PCR_TG1_TIMER0_READY : RO; bitpos: [3]; default: 1; + * Query this field after reset timer_group1 timer0 module + */ +#define PCR_TG1_TIMER0_READY (BIT(3)) +#define PCR_TG1_TIMER0_READY_M (PCR_TG1_TIMER0_READY_V << PCR_TG1_TIMER0_READY_S) +#define PCR_TG1_TIMER0_READY_V 0x00000001U +#define PCR_TG1_TIMER0_READY_S 3 +/** PCR_TG1_TIMER1_READY : RO; bitpos: [4]; default: 1; + * reserved + */ +#define PCR_TG1_TIMER1_READY (BIT(4)) +#define PCR_TG1_TIMER1_READY_M (PCR_TG1_TIMER1_READY_V << PCR_TG1_TIMER1_READY_S) +#define PCR_TG1_TIMER1_READY_V 0x00000001U +#define PCR_TG1_TIMER1_READY_S 4 + +/** PCR_TIMERGROUP1_TIMER_CLK_CONF_REG register + * TIMERGROUP1_TIMER_CLK configuration register + */ +#define PCR_TIMERGROUP1_TIMER_CLK_CONF_REG (DR_REG_PCR_BASE + 0x54) +/** PCR_TG1_TIMER_CLK_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: + * reserved. + */ +#define PCR_TG1_TIMER_CLK_SEL 0x00000003U +#define PCR_TG1_TIMER_CLK_SEL_M (PCR_TG1_TIMER_CLK_SEL_V << PCR_TG1_TIMER_CLK_SEL_S) +#define PCR_TG1_TIMER_CLK_SEL_V 0x00000003U +#define PCR_TG1_TIMER_CLK_SEL_S 20 +/** PCR_TG1_TIMER_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group1 timer clock + */ +#define PCR_TG1_TIMER_CLK_EN (BIT(22)) +#define PCR_TG1_TIMER_CLK_EN_M (PCR_TG1_TIMER_CLK_EN_V << PCR_TG1_TIMER_CLK_EN_S) +#define PCR_TG1_TIMER_CLK_EN_V 0x00000001U +#define PCR_TG1_TIMER_CLK_EN_S 22 + +/** PCR_TIMERGROUP1_WDT_CLK_CONF_REG register + * TIMERGROUP1_WDT_CLK configuration register + */ +#define PCR_TIMERGROUP1_WDT_CLK_CONF_REG (DR_REG_PCR_BASE + 0x58) +/** PCR_TG1_WDT_CLK_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: + * reserved. + */ +#define PCR_TG1_WDT_CLK_SEL 0x00000003U +#define PCR_TG1_WDT_CLK_SEL_M (PCR_TG1_WDT_CLK_SEL_V << PCR_TG1_WDT_CLK_SEL_S) +#define PCR_TG1_WDT_CLK_SEL_V 0x00000003U +#define PCR_TG1_WDT_CLK_SEL_S 20 +/** PCR_TG1_WDT_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group0 wdt clock + */ +#define PCR_TG1_WDT_CLK_EN (BIT(22)) +#define PCR_TG1_WDT_CLK_EN_M (PCR_TG1_WDT_CLK_EN_V << PCR_TG1_WDT_CLK_EN_S) +#define PCR_TG1_WDT_CLK_EN_V 0x00000001U +#define PCR_TG1_WDT_CLK_EN_S 22 + +/** PCR_SYSTIMER_CONF_REG register + * SYSTIMER configuration register + */ +#define PCR_SYSTIMER_CONF_REG (DR_REG_PCR_BASE + 0x5c) +/** PCR_SYSTIMER_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable systimer apb clock + */ +#define PCR_SYSTIMER_CLK_EN (BIT(0)) +#define PCR_SYSTIMER_CLK_EN_M (PCR_SYSTIMER_CLK_EN_V << PCR_SYSTIMER_CLK_EN_S) +#define PCR_SYSTIMER_CLK_EN_V 0x00000001U +#define PCR_SYSTIMER_CLK_EN_S 0 +/** PCR_SYSTIMER_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset systimer module + */ +#define PCR_SYSTIMER_RST_EN (BIT(1)) +#define PCR_SYSTIMER_RST_EN_M (PCR_SYSTIMER_RST_EN_V << PCR_SYSTIMER_RST_EN_S) +#define PCR_SYSTIMER_RST_EN_V 0x00000001U +#define PCR_SYSTIMER_RST_EN_S 1 +/** PCR_SYSTIMER_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset systimer module + */ +#define PCR_SYSTIMER_READY (BIT(2)) +#define PCR_SYSTIMER_READY_M (PCR_SYSTIMER_READY_V << PCR_SYSTIMER_READY_S) +#define PCR_SYSTIMER_READY_V 0x00000001U +#define PCR_SYSTIMER_READY_S 2 + +/** PCR_SYSTIMER_FUNC_CLK_CONF_REG register + * SYSTIMER_FUNC_CLK configuration register + */ +#define PCR_SYSTIMER_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x60) +/** PCR_SYSTIMER_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: FOSC. + */ +#define PCR_SYSTIMER_FUNC_CLK_SEL (BIT(20)) +#define PCR_SYSTIMER_FUNC_CLK_SEL_M (PCR_SYSTIMER_FUNC_CLK_SEL_V << PCR_SYSTIMER_FUNC_CLK_SEL_S) +#define PCR_SYSTIMER_FUNC_CLK_SEL_V 0x00000001U +#define PCR_SYSTIMER_FUNC_CLK_SEL_S 20 +/** PCR_SYSTIMER_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable systimer function clock + */ +#define PCR_SYSTIMER_FUNC_CLK_EN (BIT(22)) +#define PCR_SYSTIMER_FUNC_CLK_EN_M (PCR_SYSTIMER_FUNC_CLK_EN_V << PCR_SYSTIMER_FUNC_CLK_EN_S) +#define PCR_SYSTIMER_FUNC_CLK_EN_V 0x00000001U +#define PCR_SYSTIMER_FUNC_CLK_EN_S 22 + +/** PCR_TWAI0_CONF_REG register + * TWAI0 configuration register + */ +#define PCR_TWAI0_CONF_REG (DR_REG_PCR_BASE + 0x64) +/** PCR_TWAI0_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable twai0 apb clock + */ +#define PCR_TWAI0_CLK_EN (BIT(0)) +#define PCR_TWAI0_CLK_EN_M (PCR_TWAI0_CLK_EN_V << PCR_TWAI0_CLK_EN_S) +#define PCR_TWAI0_CLK_EN_V 0x00000001U +#define PCR_TWAI0_CLK_EN_S 0 +/** PCR_TWAI0_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset twai0 module + */ +#define PCR_TWAI0_RST_EN (BIT(1)) +#define PCR_TWAI0_RST_EN_M (PCR_TWAI0_RST_EN_V << PCR_TWAI0_RST_EN_S) +#define PCR_TWAI0_RST_EN_V 0x00000001U +#define PCR_TWAI0_RST_EN_S 1 +/** PCR_TWAI0_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset twai0 module + */ +#define PCR_TWAI0_READY (BIT(2)) +#define PCR_TWAI0_READY_M (PCR_TWAI0_READY_V << PCR_TWAI0_READY_S) +#define PCR_TWAI0_READY_V 0x00000001U +#define PCR_TWAI0_READY_S 2 + +/** PCR_TWAI0_FUNC_CLK_CONF_REG register + * TWAI0_FUNC_CLK configuration register + */ +#define PCR_TWAI0_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x68) +/** PCR_TWAI0_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: FOSC. + */ +#define PCR_TWAI0_FUNC_CLK_SEL (BIT(20)) +#define PCR_TWAI0_FUNC_CLK_SEL_M (PCR_TWAI0_FUNC_CLK_SEL_V << PCR_TWAI0_FUNC_CLK_SEL_S) +#define PCR_TWAI0_FUNC_CLK_SEL_V 0x00000001U +#define PCR_TWAI0_FUNC_CLK_SEL_S 20 +/** PCR_TWAI0_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable twai0 function clock + */ +#define PCR_TWAI0_FUNC_CLK_EN (BIT(22)) +#define PCR_TWAI0_FUNC_CLK_EN_M (PCR_TWAI0_FUNC_CLK_EN_V << PCR_TWAI0_FUNC_CLK_EN_S) +#define PCR_TWAI0_FUNC_CLK_EN_V 0x00000001U +#define PCR_TWAI0_FUNC_CLK_EN_S 22 + +/** PCR_I2S_CONF_REG register + * I2S configuration register + */ +#define PCR_I2S_CONF_REG (DR_REG_PCR_BASE + 0x6c) +/** PCR_I2S_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable i2s apb clock + */ +#define PCR_I2S_CLK_EN (BIT(0)) +#define PCR_I2S_CLK_EN_M (PCR_I2S_CLK_EN_V << PCR_I2S_CLK_EN_S) +#define PCR_I2S_CLK_EN_V 0x00000001U +#define PCR_I2S_CLK_EN_S 0 +/** PCR_I2S_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset i2s module + */ +#define PCR_I2S_RST_EN (BIT(1)) +#define PCR_I2S_RST_EN_M (PCR_I2S_RST_EN_V << PCR_I2S_RST_EN_S) +#define PCR_I2S_RST_EN_V 0x00000001U +#define PCR_I2S_RST_EN_S 1 +/** PCR_I2S_RX_READY : RO; bitpos: [2]; default: 1; + * Query this field before using i2s rx function, after reset i2s module + */ +#define PCR_I2S_RX_READY (BIT(2)) +#define PCR_I2S_RX_READY_M (PCR_I2S_RX_READY_V << PCR_I2S_RX_READY_S) +#define PCR_I2S_RX_READY_V 0x00000001U +#define PCR_I2S_RX_READY_S 2 +/** PCR_I2S_TX_READY : RO; bitpos: [3]; default: 1; + * Query this field before using i2s tx function, after reset i2s module + */ +#define PCR_I2S_TX_READY (BIT(3)) +#define PCR_I2S_TX_READY_M (PCR_I2S_TX_READY_V << PCR_I2S_TX_READY_S) +#define PCR_I2S_TX_READY_V 0x00000001U +#define PCR_I2S_TX_READY_S 3 + +/** PCR_I2S_TX_CLKM_CONF_REG register + * I2S_TX_CLKM configuration register + */ +#define PCR_I2S_TX_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x70) +/** PCR_I2S_TX_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 2; + * Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be + * (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= + * a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * + * (n+1)-div] + y * (n+1)-div. + */ +#define PCR_I2S_TX_CLKM_DIV_NUM 0x000000FFU +#define PCR_I2S_TX_CLKM_DIV_NUM_M (PCR_I2S_TX_CLKM_DIV_NUM_V << PCR_I2S_TX_CLKM_DIV_NUM_S) +#define PCR_I2S_TX_CLKM_DIV_NUM_V 0x000000FFU +#define PCR_I2S_TX_CLKM_DIV_NUM_S 12 +/** PCR_I2S_TX_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; + * Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: + * I2S_MCLK_in. + */ +#define PCR_I2S_TX_CLKM_SEL 0x00000003U +#define PCR_I2S_TX_CLKM_SEL_M (PCR_I2S_TX_CLKM_SEL_V << PCR_I2S_TX_CLKM_SEL_S) +#define PCR_I2S_TX_CLKM_SEL_V 0x00000003U +#define PCR_I2S_TX_CLKM_SEL_S 20 +/** PCR_I2S_TX_CLKM_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable i2s_tx function clock + */ +#define PCR_I2S_TX_CLKM_EN (BIT(22)) +#define PCR_I2S_TX_CLKM_EN_M (PCR_I2S_TX_CLKM_EN_V << PCR_I2S_TX_CLKM_EN_S) +#define PCR_I2S_TX_CLKM_EN_V 0x00000001U +#define PCR_I2S_TX_CLKM_EN_S 22 + +/** PCR_I2S_TX_CLKM_DIV_CONF_REG register + * I2S_TX_CLKM_DIV configuration register + */ +#define PCR_I2S_TX_CLKM_DIV_CONF_REG (DR_REG_PCR_BASE + 0x74) +/** PCR_I2S_TX_CLKM_DIV_Z : R/W; bitpos: [8:0]; default: 0; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of + * I2S_TX_CLKM_DIV_Z is (a-b). + */ +#define PCR_I2S_TX_CLKM_DIV_Z 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_Z_M (PCR_I2S_TX_CLKM_DIV_Z_V << PCR_I2S_TX_CLKM_DIV_Z_S) +#define PCR_I2S_TX_CLKM_DIV_Z_V 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_Z_S 0 +/** PCR_I2S_TX_CLKM_DIV_Y : R/W; bitpos: [17:9]; default: 1; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of + * I2S_TX_CLKM_DIV_Y is (a%(a-b)). + */ +#define PCR_I2S_TX_CLKM_DIV_Y 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_Y_M (PCR_I2S_TX_CLKM_DIV_Y_V << PCR_I2S_TX_CLKM_DIV_Y_S) +#define PCR_I2S_TX_CLKM_DIV_Y_V 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_Y_S 9 +/** PCR_I2S_TX_CLKM_DIV_X : R/W; bitpos: [26:18]; default: 0; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value + * of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1. + */ +#define PCR_I2S_TX_CLKM_DIV_X 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_X_M (PCR_I2S_TX_CLKM_DIV_X_V << PCR_I2S_TX_CLKM_DIV_X_S) +#define PCR_I2S_TX_CLKM_DIV_X_V 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_X_S 18 +/** PCR_I2S_TX_CLKM_DIV_YN1 : R/W; bitpos: [27]; default: 0; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of + * I2S_TX_CLKM_DIV_YN1 is 1. + */ +#define PCR_I2S_TX_CLKM_DIV_YN1 (BIT(27)) +#define PCR_I2S_TX_CLKM_DIV_YN1_M (PCR_I2S_TX_CLKM_DIV_YN1_V << PCR_I2S_TX_CLKM_DIV_YN1_S) +#define PCR_I2S_TX_CLKM_DIV_YN1_V 0x00000001U +#define PCR_I2S_TX_CLKM_DIV_YN1_S 27 + +/** PCR_I2S_RX_CLKM_CONF_REG register + * I2S_RX_CLKM configuration register + */ +#define PCR_I2S_RX_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x78) +/** PCR_I2S_RX_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 2; + * Integral I2S clock divider value + */ +#define PCR_I2S_RX_CLKM_DIV_NUM 0x000000FFU +#define PCR_I2S_RX_CLKM_DIV_NUM_M (PCR_I2S_RX_CLKM_DIV_NUM_V << PCR_I2S_RX_CLKM_DIV_NUM_S) +#define PCR_I2S_RX_CLKM_DIV_NUM_V 0x000000FFU +#define PCR_I2S_RX_CLKM_DIV_NUM_S 12 +/** PCR_I2S_RX_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; + * Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in. + */ +#define PCR_I2S_RX_CLKM_SEL 0x00000003U +#define PCR_I2S_RX_CLKM_SEL_M (PCR_I2S_RX_CLKM_SEL_V << PCR_I2S_RX_CLKM_SEL_S) +#define PCR_I2S_RX_CLKM_SEL_V 0x00000003U +#define PCR_I2S_RX_CLKM_SEL_S 20 +/** PCR_I2S_RX_CLKM_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable i2s_rx function clock + */ +#define PCR_I2S_RX_CLKM_EN (BIT(22)) +#define PCR_I2S_RX_CLKM_EN_M (PCR_I2S_RX_CLKM_EN_V << PCR_I2S_RX_CLKM_EN_S) +#define PCR_I2S_RX_CLKM_EN_V 0x00000001U +#define PCR_I2S_RX_CLKM_EN_S 22 +/** PCR_I2S_MCLK_SEL : R/W; bitpos: [23]; default: 0; + * This field is used to select master-clock. 0(default): clk_i2s_rx, 1: clk_i2s_tx + */ +#define PCR_I2S_MCLK_SEL (BIT(23)) +#define PCR_I2S_MCLK_SEL_M (PCR_I2S_MCLK_SEL_V << PCR_I2S_MCLK_SEL_S) +#define PCR_I2S_MCLK_SEL_V 0x00000001U +#define PCR_I2S_MCLK_SEL_S 23 + +/** PCR_I2S_RX_CLKM_DIV_CONF_REG register + * I2S_RX_CLKM_DIV configuration register + */ +#define PCR_I2S_RX_CLKM_DIV_CONF_REG (DR_REG_PCR_BASE + 0x7c) +/** PCR_I2S_RX_CLKM_DIV_Z : R/W; bitpos: [8:0]; default: 0; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of + * I2S_RX_CLKM_DIV_Z is (a-b). + */ +#define PCR_I2S_RX_CLKM_DIV_Z 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_Z_M (PCR_I2S_RX_CLKM_DIV_Z_V << PCR_I2S_RX_CLKM_DIV_Z_S) +#define PCR_I2S_RX_CLKM_DIV_Z_V 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_Z_S 0 +/** PCR_I2S_RX_CLKM_DIV_Y : R/W; bitpos: [17:9]; default: 1; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of + * I2S_RX_CLKM_DIV_Y is (a%(a-b)). + */ +#define PCR_I2S_RX_CLKM_DIV_Y 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_Y_M (PCR_I2S_RX_CLKM_DIV_Y_V << PCR_I2S_RX_CLKM_DIV_Y_S) +#define PCR_I2S_RX_CLKM_DIV_Y_V 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_Y_S 9 +/** PCR_I2S_RX_CLKM_DIV_X : R/W; bitpos: [26:18]; default: 0; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value + * of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1. + */ +#define PCR_I2S_RX_CLKM_DIV_X 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_X_M (PCR_I2S_RX_CLKM_DIV_X_V << PCR_I2S_RX_CLKM_DIV_X_S) +#define PCR_I2S_RX_CLKM_DIV_X_V 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_X_S 18 +/** PCR_I2S_RX_CLKM_DIV_YN1 : R/W; bitpos: [27]; default: 0; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of + * I2S_RX_CLKM_DIV_YN1 is 1. + */ +#define PCR_I2S_RX_CLKM_DIV_YN1 (BIT(27)) +#define PCR_I2S_RX_CLKM_DIV_YN1_M (PCR_I2S_RX_CLKM_DIV_YN1_V << PCR_I2S_RX_CLKM_DIV_YN1_S) +#define PCR_I2S_RX_CLKM_DIV_YN1_V 0x00000001U +#define PCR_I2S_RX_CLKM_DIV_YN1_S 27 + +/** PCR_SARADC_CONF_REG register + * SARADC configuration register + */ +#define PCR_SARADC_CONF_REG (DR_REG_PCR_BASE + 0x80) +/** PCR_SARADC_CLK_EN : R/W; bitpos: [0]; default: 1; + * no use + */ +#define PCR_SARADC_CLK_EN (BIT(0)) +#define PCR_SARADC_CLK_EN_M (PCR_SARADC_CLK_EN_V << PCR_SARADC_CLK_EN_S) +#define PCR_SARADC_CLK_EN_V 0x00000001U +#define PCR_SARADC_CLK_EN_S 0 +/** PCR_SARADC_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset function_register of saradc module + */ +#define PCR_SARADC_RST_EN (BIT(1)) +#define PCR_SARADC_RST_EN_M (PCR_SARADC_RST_EN_V << PCR_SARADC_RST_EN_S) +#define PCR_SARADC_RST_EN_V 0x00000001U +#define PCR_SARADC_RST_EN_S 1 +/** PCR_SARADC_REG_CLK_EN : R/W; bitpos: [2]; default: 1; + * Set 1 to enable saradc apb clock + */ +#define PCR_SARADC_REG_CLK_EN (BIT(2)) +#define PCR_SARADC_REG_CLK_EN_M (PCR_SARADC_REG_CLK_EN_V << PCR_SARADC_REG_CLK_EN_S) +#define PCR_SARADC_REG_CLK_EN_V 0x00000001U +#define PCR_SARADC_REG_CLK_EN_S 2 +/** PCR_SARADC_REG_RST_EN : R/W; bitpos: [3]; default: 0; + * Set 0 to reset apb_register of saradc module + */ +#define PCR_SARADC_REG_RST_EN (BIT(3)) +#define PCR_SARADC_REG_RST_EN_M (PCR_SARADC_REG_RST_EN_V << PCR_SARADC_REG_RST_EN_S) +#define PCR_SARADC_REG_RST_EN_V 0x00000001U +#define PCR_SARADC_REG_RST_EN_S 3 + +/** PCR_SARADC_CLKM_CONF_REG register + * SARADC_CLKM configuration register + */ +#define PCR_SARADC_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x84) +/** PCR_SARADC_CLKM_DIV_A : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the saradc function clock. + */ +#define PCR_SARADC_CLKM_DIV_A 0x0000003FU +#define PCR_SARADC_CLKM_DIV_A_M (PCR_SARADC_CLKM_DIV_A_V << PCR_SARADC_CLKM_DIV_A_S) +#define PCR_SARADC_CLKM_DIV_A_V 0x0000003FU +#define PCR_SARADC_CLKM_DIV_A_S 0 +/** PCR_SARADC_CLKM_DIV_B : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the saradc function clock. + */ +#define PCR_SARADC_CLKM_DIV_B 0x0000003FU +#define PCR_SARADC_CLKM_DIV_B_M (PCR_SARADC_CLKM_DIV_B_V << PCR_SARADC_CLKM_DIV_B_S) +#define PCR_SARADC_CLKM_DIV_B_V 0x0000003FU +#define PCR_SARADC_CLKM_DIV_B_S 6 +/** PCR_SARADC_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 4; + * The integral part of the frequency divider factor of the saradc function clock. + */ +#define PCR_SARADC_CLKM_DIV_NUM 0x000000FFU +#define PCR_SARADC_CLKM_DIV_NUM_M (PCR_SARADC_CLKM_DIV_NUM_V << PCR_SARADC_CLKM_DIV_NUM_S) +#define PCR_SARADC_CLKM_DIV_NUM_V 0x000000FFU +#define PCR_SARADC_CLKM_DIV_NUM_S 12 +/** PCR_SARADC_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3: + * reserved. + */ +#define PCR_SARADC_CLKM_SEL 0x00000003U +#define PCR_SARADC_CLKM_SEL_M (PCR_SARADC_CLKM_SEL_V << PCR_SARADC_CLKM_SEL_S) +#define PCR_SARADC_CLKM_SEL_V 0x00000003U +#define PCR_SARADC_CLKM_SEL_S 20 +/** PCR_SARADC_CLKM_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable saradc function clock + */ +#define PCR_SARADC_CLKM_EN (BIT(22)) +#define PCR_SARADC_CLKM_EN_M (PCR_SARADC_CLKM_EN_V << PCR_SARADC_CLKM_EN_S) +#define PCR_SARADC_CLKM_EN_V 0x00000001U +#define PCR_SARADC_CLKM_EN_S 22 + +/** PCR_TSENS_CLK_CONF_REG register + * TSENS_CLK configuration register + */ +#define PCR_TSENS_CLK_CONF_REG (DR_REG_PCR_BASE + 0x88) +/** PCR_TSENS_CLK_SEL : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0(default): FOSC, 1: XTAL. + */ +#define PCR_TSENS_CLK_SEL (BIT(20)) +#define PCR_TSENS_CLK_SEL_M (PCR_TSENS_CLK_SEL_V << PCR_TSENS_CLK_SEL_S) +#define PCR_TSENS_CLK_SEL_V 0x00000001U +#define PCR_TSENS_CLK_SEL_S 20 +/** PCR_TSENS_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable tsens clock + */ +#define PCR_TSENS_CLK_EN (BIT(22)) +#define PCR_TSENS_CLK_EN_M (PCR_TSENS_CLK_EN_V << PCR_TSENS_CLK_EN_S) +#define PCR_TSENS_CLK_EN_V 0x00000001U +#define PCR_TSENS_CLK_EN_S 22 +/** PCR_TSENS_RST_EN : R/W; bitpos: [23]; default: 0; + * Set 0 to reset tsens module + */ +#define PCR_TSENS_RST_EN (BIT(23)) +#define PCR_TSENS_RST_EN_M (PCR_TSENS_RST_EN_V << PCR_TSENS_RST_EN_S) +#define PCR_TSENS_RST_EN_V 0x00000001U +#define PCR_TSENS_RST_EN_S 23 + +/** PCR_USB_DEVICE_CONF_REG register + * USB_DEVICE configuration register + */ +#define PCR_USB_DEVICE_CONF_REG (DR_REG_PCR_BASE + 0x8c) +/** PCR_USB_DEVICE_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable usb_device clock + */ +#define PCR_USB_DEVICE_CLK_EN (BIT(0)) +#define PCR_USB_DEVICE_CLK_EN_M (PCR_USB_DEVICE_CLK_EN_V << PCR_USB_DEVICE_CLK_EN_S) +#define PCR_USB_DEVICE_CLK_EN_V 0x00000001U +#define PCR_USB_DEVICE_CLK_EN_S 0 +/** PCR_USB_DEVICE_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset usb_device module + */ +#define PCR_USB_DEVICE_RST_EN (BIT(1)) +#define PCR_USB_DEVICE_RST_EN_M (PCR_USB_DEVICE_RST_EN_V << PCR_USB_DEVICE_RST_EN_S) +#define PCR_USB_DEVICE_RST_EN_V 0x00000001U +#define PCR_USB_DEVICE_RST_EN_S 1 +/** PCR_USB_DEVICE_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset usb_device module + */ +#define PCR_USB_DEVICE_READY (BIT(2)) +#define PCR_USB_DEVICE_READY_M (PCR_USB_DEVICE_READY_V << PCR_USB_DEVICE_READY_S) +#define PCR_USB_DEVICE_READY_V 0x00000001U +#define PCR_USB_DEVICE_READY_S 2 + +/** PCR_INTMTX_CONF_REG register + * INTMTX configuration register + */ +#define PCR_INTMTX_CONF_REG (DR_REG_PCR_BASE + 0x90) +/** PCR_INTMTX_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable intmtx clock + */ +#define PCR_INTMTX_CLK_EN (BIT(0)) +#define PCR_INTMTX_CLK_EN_M (PCR_INTMTX_CLK_EN_V << PCR_INTMTX_CLK_EN_S) +#define PCR_INTMTX_CLK_EN_V 0x00000001U +#define PCR_INTMTX_CLK_EN_S 0 +/** PCR_INTMTX_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset intmtx module + */ +#define PCR_INTMTX_RST_EN (BIT(1)) +#define PCR_INTMTX_RST_EN_M (PCR_INTMTX_RST_EN_V << PCR_INTMTX_RST_EN_S) +#define PCR_INTMTX_RST_EN_V 0x00000001U +#define PCR_INTMTX_RST_EN_S 1 +/** PCR_INTMTX_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset intmtx module + */ +#define PCR_INTMTX_READY (BIT(2)) +#define PCR_INTMTX_READY_M (PCR_INTMTX_READY_V << PCR_INTMTX_READY_S) +#define PCR_INTMTX_READY_V 0x00000001U +#define PCR_INTMTX_READY_S 2 + +/** PCR_PCNT_CONF_REG register + * PCNT configuration register + */ +#define PCR_PCNT_CONF_REG (DR_REG_PCR_BASE + 0x94) +/** PCR_PCNT_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable pcnt clock + */ +#define PCR_PCNT_CLK_EN (BIT(0)) +#define PCR_PCNT_CLK_EN_M (PCR_PCNT_CLK_EN_V << PCR_PCNT_CLK_EN_S) +#define PCR_PCNT_CLK_EN_V 0x00000001U +#define PCR_PCNT_CLK_EN_S 0 +/** PCR_PCNT_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset pcnt module + */ +#define PCR_PCNT_RST_EN (BIT(1)) +#define PCR_PCNT_RST_EN_M (PCR_PCNT_RST_EN_V << PCR_PCNT_RST_EN_S) +#define PCR_PCNT_RST_EN_V 0x00000001U +#define PCR_PCNT_RST_EN_S 1 +/** PCR_PCNT_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset pcnt module + */ +#define PCR_PCNT_READY (BIT(2)) +#define PCR_PCNT_READY_M (PCR_PCNT_READY_V << PCR_PCNT_READY_S) +#define PCR_PCNT_READY_V 0x00000001U +#define PCR_PCNT_READY_S 2 + +/** PCR_ETM_CONF_REG register + * ETM configuration register + */ +#define PCR_ETM_CONF_REG (DR_REG_PCR_BASE + 0x98) +/** PCR_ETM_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable etm clock + */ +#define PCR_ETM_CLK_EN (BIT(0)) +#define PCR_ETM_CLK_EN_M (PCR_ETM_CLK_EN_V << PCR_ETM_CLK_EN_S) +#define PCR_ETM_CLK_EN_V 0x00000001U +#define PCR_ETM_CLK_EN_S 0 +/** PCR_ETM_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset etm module + */ +#define PCR_ETM_RST_EN (BIT(1)) +#define PCR_ETM_RST_EN_M (PCR_ETM_RST_EN_V << PCR_ETM_RST_EN_S) +#define PCR_ETM_RST_EN_V 0x00000001U +#define PCR_ETM_RST_EN_S 1 +/** PCR_ETM_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset etm module + */ +#define PCR_ETM_READY (BIT(2)) +#define PCR_ETM_READY_M (PCR_ETM_READY_V << PCR_ETM_READY_S) +#define PCR_ETM_READY_V 0x00000001U +#define PCR_ETM_READY_S 2 + +/** PCR_PWM_CONF_REG register + * PWM configuration register + */ +#define PCR_PWM_CONF_REG (DR_REG_PCR_BASE + 0x9c) +/** PCR_PWM_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable pwm clock + */ +#define PCR_PWM_CLK_EN (BIT(0)) +#define PCR_PWM_CLK_EN_M (PCR_PWM_CLK_EN_V << PCR_PWM_CLK_EN_S) +#define PCR_PWM_CLK_EN_V 0x00000001U +#define PCR_PWM_CLK_EN_S 0 +/** PCR_PWM_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset pwm module + */ +#define PCR_PWM_RST_EN (BIT(1)) +#define PCR_PWM_RST_EN_M (PCR_PWM_RST_EN_V << PCR_PWM_RST_EN_S) +#define PCR_PWM_RST_EN_V 0x00000001U +#define PCR_PWM_RST_EN_S 1 +/** PCR_PWM_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset pwm module + */ +#define PCR_PWM_READY (BIT(2)) +#define PCR_PWM_READY_M (PCR_PWM_READY_V << PCR_PWM_READY_S) +#define PCR_PWM_READY_V 0x00000001U +#define PCR_PWM_READY_S 2 + +/** PCR_PWM_CLK_CONF_REG register + * PWM_CLK configuration register + */ +#define PCR_PWM_CLK_CONF_REG (DR_REG_PCR_BASE + 0xa0) +/** PCR_PWM_DIV_NUM : R/W; bitpos: [19:12]; default: 4; + * The integral part of the frequency divider factor of the pwm function clock. + */ +#define PCR_PWM_DIV_NUM 0x000000FFU +#define PCR_PWM_DIV_NUM_M (PCR_PWM_DIV_NUM_V << PCR_PWM_DIV_NUM_S) +#define PCR_PWM_DIV_NUM_V 0x000000FFU +#define PCR_PWM_DIV_NUM_S 12 +/** PCR_PWM_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): do not select anyone clock, 1: + * 160MHz, 2: XTAL, 3: FOSC. + */ +#define PCR_PWM_CLKM_SEL 0x00000003U +#define PCR_PWM_CLKM_SEL_M (PCR_PWM_CLKM_SEL_V << PCR_PWM_CLKM_SEL_S) +#define PCR_PWM_CLKM_SEL_V 0x00000003U +#define PCR_PWM_CLKM_SEL_S 20 +/** PCR_PWM_CLKM_EN : R/W; bitpos: [22]; default: 1; + * set this field as 1 to activate pwm clkm. + */ +#define PCR_PWM_CLKM_EN (BIT(22)) +#define PCR_PWM_CLKM_EN_M (PCR_PWM_CLKM_EN_V << PCR_PWM_CLKM_EN_S) +#define PCR_PWM_CLKM_EN_V 0x00000001U +#define PCR_PWM_CLKM_EN_S 22 + +/** PCR_PARL_IO_CONF_REG register + * PARL_IO configuration register + */ +#define PCR_PARL_IO_CONF_REG (DR_REG_PCR_BASE + 0xa4) +/** PCR_PARL_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable parl apb clock + */ +#define PCR_PARL_CLK_EN (BIT(0)) +#define PCR_PARL_CLK_EN_M (PCR_PARL_CLK_EN_V << PCR_PARL_CLK_EN_S) +#define PCR_PARL_CLK_EN_V 0x00000001U +#define PCR_PARL_CLK_EN_S 0 +/** PCR_PARL_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset parl apb reg + */ +#define PCR_PARL_RST_EN (BIT(1)) +#define PCR_PARL_RST_EN_M (PCR_PARL_RST_EN_V << PCR_PARL_RST_EN_S) +#define PCR_PARL_RST_EN_V 0x00000001U +#define PCR_PARL_RST_EN_S 1 +/** PCR_PARL_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset parl module + */ +#define PCR_PARL_READY (BIT(2)) +#define PCR_PARL_READY_M (PCR_PARL_READY_V << PCR_PARL_READY_S) +#define PCR_PARL_READY_V 0x00000001U +#define PCR_PARL_READY_S 2 + +/** PCR_PARL_CLK_RX_CONF_REG register + * PARL_CLK_RX configuration register + */ +#define PCR_PARL_CLK_RX_CONF_REG (DR_REG_PCR_BASE + 0xa8) +/** PCR_PARL_CLK_RX_DIV_NUM : R/W; bitpos: [15:0]; default: 0; + * The integral part of the frequency divider factor of the parl rx clock. + */ +#define PCR_PARL_CLK_RX_DIV_NUM 0x0000FFFFU +#define PCR_PARL_CLK_RX_DIV_NUM_M (PCR_PARL_CLK_RX_DIV_NUM_V << PCR_PARL_CLK_RX_DIV_NUM_S) +#define PCR_PARL_CLK_RX_DIV_NUM_V 0x0000FFFFU +#define PCR_PARL_CLK_RX_DIV_NUM_S 0 +/** PCR_PARL_CLK_RX_SEL : R/W; bitpos: [17:16]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3: + * user clock from pad. + */ +#define PCR_PARL_CLK_RX_SEL 0x00000003U +#define PCR_PARL_CLK_RX_SEL_M (PCR_PARL_CLK_RX_SEL_V << PCR_PARL_CLK_RX_SEL_S) +#define PCR_PARL_CLK_RX_SEL_V 0x00000003U +#define PCR_PARL_CLK_RX_SEL_S 16 +/** PCR_PARL_CLK_RX_EN : R/W; bitpos: [18]; default: 1; + * Set 1 to enable parl rx clock + */ +#define PCR_PARL_CLK_RX_EN (BIT(18)) +#define PCR_PARL_CLK_RX_EN_M (PCR_PARL_CLK_RX_EN_V << PCR_PARL_CLK_RX_EN_S) +#define PCR_PARL_CLK_RX_EN_V 0x00000001U +#define PCR_PARL_CLK_RX_EN_S 18 +/** PCR_PARL_RX_RST_EN : R/W; bitpos: [19]; default: 0; + * Set 0 to reset parl rx module + */ +#define PCR_PARL_RX_RST_EN (BIT(19)) +#define PCR_PARL_RX_RST_EN_M (PCR_PARL_RX_RST_EN_V << PCR_PARL_RX_RST_EN_S) +#define PCR_PARL_RX_RST_EN_V 0x00000001U +#define PCR_PARL_RX_RST_EN_S 19 + +/** PCR_PARL_CLK_TX_CONF_REG register + * PARL_CLK_TX configuration register + */ +#define PCR_PARL_CLK_TX_CONF_REG (DR_REG_PCR_BASE + 0xac) +/** PCR_PARL_CLK_TX_DIV_NUM : R/W; bitpos: [15:0]; default: 0; + * The integral part of the frequency divider factor of the parl tx clock. + */ +#define PCR_PARL_CLK_TX_DIV_NUM 0x0000FFFFU +#define PCR_PARL_CLK_TX_DIV_NUM_M (PCR_PARL_CLK_TX_DIV_NUM_V << PCR_PARL_CLK_TX_DIV_NUM_S) +#define PCR_PARL_CLK_TX_DIV_NUM_V 0x0000FFFFU +#define PCR_PARL_CLK_TX_DIV_NUM_S 0 +/** PCR_PARL_CLK_TX_SEL : R/W; bitpos: [17:16]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3: + * user clock from pad. + */ +#define PCR_PARL_CLK_TX_SEL 0x00000003U +#define PCR_PARL_CLK_TX_SEL_M (PCR_PARL_CLK_TX_SEL_V << PCR_PARL_CLK_TX_SEL_S) +#define PCR_PARL_CLK_TX_SEL_V 0x00000003U +#define PCR_PARL_CLK_TX_SEL_S 16 +/** PCR_PARL_CLK_TX_EN : R/W; bitpos: [18]; default: 1; + * Set 1 to enable parl tx clock + */ +#define PCR_PARL_CLK_TX_EN (BIT(18)) +#define PCR_PARL_CLK_TX_EN_M (PCR_PARL_CLK_TX_EN_V << PCR_PARL_CLK_TX_EN_S) +#define PCR_PARL_CLK_TX_EN_V 0x00000001U +#define PCR_PARL_CLK_TX_EN_S 18 +/** PCR_PARL_TX_RST_EN : R/W; bitpos: [19]; default: 0; + * Set 0 to reset parl tx module + */ +#define PCR_PARL_TX_RST_EN (BIT(19)) +#define PCR_PARL_TX_RST_EN_M (PCR_PARL_TX_RST_EN_V << PCR_PARL_TX_RST_EN_S) +#define PCR_PARL_TX_RST_EN_V 0x00000001U +#define PCR_PARL_TX_RST_EN_S 19 + +/** PCR_PVT_MONITOR_CONF_REG register + * PVT_MONITOR configuration register + */ +#define PCR_PVT_MONITOR_CONF_REG (DR_REG_PCR_BASE + 0xb0) +/** PCR_PVT_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable apb clock of pvt module + */ +#define PCR_PVT_MONITOR_CLK_EN (BIT(0)) +#define PCR_PVT_MONITOR_CLK_EN_M (PCR_PVT_MONITOR_CLK_EN_V << PCR_PVT_MONITOR_CLK_EN_S) +#define PCR_PVT_MONITOR_CLK_EN_V 0x00000001U +#define PCR_PVT_MONITOR_CLK_EN_S 0 +/** PCR_PVT_MONITOR_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset all pvt monitor module + */ +#define PCR_PVT_MONITOR_RST_EN (BIT(1)) +#define PCR_PVT_MONITOR_RST_EN_M (PCR_PVT_MONITOR_RST_EN_V << PCR_PVT_MONITOR_RST_EN_S) +#define PCR_PVT_MONITOR_RST_EN_V 0x00000001U +#define PCR_PVT_MONITOR_RST_EN_S 1 +/** PCR_PVT_MONITOR_SITE1_CLK_EN : R/W; bitpos: [2]; default: 1; + * Set 1 to enable function clock of modem pvt module + */ +#define PCR_PVT_MONITOR_SITE1_CLK_EN (BIT(2)) +#define PCR_PVT_MONITOR_SITE1_CLK_EN_M (PCR_PVT_MONITOR_SITE1_CLK_EN_V << PCR_PVT_MONITOR_SITE1_CLK_EN_S) +#define PCR_PVT_MONITOR_SITE1_CLK_EN_V 0x00000001U +#define PCR_PVT_MONITOR_SITE1_CLK_EN_S 2 +/** PCR_PVT_MONITOR_SITE2_CLK_EN : R/W; bitpos: [3]; default: 1; + * Set 1 to enable function clock of cpu pvt module + */ +#define PCR_PVT_MONITOR_SITE2_CLK_EN (BIT(3)) +#define PCR_PVT_MONITOR_SITE2_CLK_EN_M (PCR_PVT_MONITOR_SITE2_CLK_EN_V << PCR_PVT_MONITOR_SITE2_CLK_EN_S) +#define PCR_PVT_MONITOR_SITE2_CLK_EN_V 0x00000001U +#define PCR_PVT_MONITOR_SITE2_CLK_EN_S 3 +/** PCR_PVT_MONITOR_SITE3_CLK_EN : R/W; bitpos: [4]; default: 1; + * Set 1 to enable function clock of hp_peri pvt module + */ +#define PCR_PVT_MONITOR_SITE3_CLK_EN (BIT(4)) +#define PCR_PVT_MONITOR_SITE3_CLK_EN_M (PCR_PVT_MONITOR_SITE3_CLK_EN_V << PCR_PVT_MONITOR_SITE3_CLK_EN_S) +#define PCR_PVT_MONITOR_SITE3_CLK_EN_V 0x00000001U +#define PCR_PVT_MONITOR_SITE3_CLK_EN_S 4 + +/** PCR_PVT_MONITOR_FUNC_CLK_CONF_REG register + * PVT_MONITOR function clock configuration register + */ +#define PCR_PVT_MONITOR_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0xb4) +/** PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM : R/W; bitpos: [3:0]; default: 0; + * The integral part of the frequency divider factor of the pvt_monitor function clock. + */ +#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM 0x0000000FU +#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_M (PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_V << PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_S) +#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_V 0x0000000FU +#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_S 0 +/** PCR_PVT_MONITOR_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0: XTAL, 1(default): 160MHz driven by SPLL + * divided by 3. + */ +#define PCR_PVT_MONITOR_FUNC_CLK_SEL (BIT(20)) +#define PCR_PVT_MONITOR_FUNC_CLK_SEL_M (PCR_PVT_MONITOR_FUNC_CLK_SEL_V << PCR_PVT_MONITOR_FUNC_CLK_SEL_S) +#define PCR_PVT_MONITOR_FUNC_CLK_SEL_V 0x00000001U +#define PCR_PVT_MONITOR_FUNC_CLK_SEL_S 20 +/** PCR_PVT_MONITOR_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable source clock of pvt sitex + */ +#define PCR_PVT_MONITOR_FUNC_CLK_EN (BIT(22)) +#define PCR_PVT_MONITOR_FUNC_CLK_EN_M (PCR_PVT_MONITOR_FUNC_CLK_EN_V << PCR_PVT_MONITOR_FUNC_CLK_EN_S) +#define PCR_PVT_MONITOR_FUNC_CLK_EN_V 0x00000001U +#define PCR_PVT_MONITOR_FUNC_CLK_EN_S 22 + +/** PCR_GDMA_CONF_REG register + * GDMA configuration register + */ +#define PCR_GDMA_CONF_REG (DR_REG_PCR_BASE + 0xb8) +/** PCR_GDMA_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable gdma clock + */ +#define PCR_GDMA_CLK_EN (BIT(0)) +#define PCR_GDMA_CLK_EN_M (PCR_GDMA_CLK_EN_V << PCR_GDMA_CLK_EN_S) +#define PCR_GDMA_CLK_EN_V 0x00000001U +#define PCR_GDMA_CLK_EN_S 0 +/** PCR_GDMA_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset gdma module + */ +#define PCR_GDMA_RST_EN (BIT(1)) +#define PCR_GDMA_RST_EN_M (PCR_GDMA_RST_EN_V << PCR_GDMA_RST_EN_S) +#define PCR_GDMA_RST_EN_V 0x00000001U +#define PCR_GDMA_RST_EN_S 1 + +/** PCR_SPI2_CONF_REG register + * SPI2 configuration register + */ +#define PCR_SPI2_CONF_REG (DR_REG_PCR_BASE + 0xbc) +/** PCR_SPI2_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable spi2 apb clock + */ +#define PCR_SPI2_CLK_EN (BIT(0)) +#define PCR_SPI2_CLK_EN_M (PCR_SPI2_CLK_EN_V << PCR_SPI2_CLK_EN_S) +#define PCR_SPI2_CLK_EN_V 0x00000001U +#define PCR_SPI2_CLK_EN_S 0 +/** PCR_SPI2_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset spi2 module + */ +#define PCR_SPI2_RST_EN (BIT(1)) +#define PCR_SPI2_RST_EN_M (PCR_SPI2_RST_EN_V << PCR_SPI2_RST_EN_S) +#define PCR_SPI2_RST_EN_V 0x00000001U +#define PCR_SPI2_RST_EN_S 1 +/** PCR_SPI2_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset spi2 module + */ +#define PCR_SPI2_READY (BIT(2)) +#define PCR_SPI2_READY_M (PCR_SPI2_READY_V << PCR_SPI2_READY_S) +#define PCR_SPI2_READY_V 0x00000001U +#define PCR_SPI2_READY_S 2 + +/** PCR_SPI2_CLKM_CONF_REG register + * SPI2_CLKM configuration register + */ +#define PCR_SPI2_CLKM_CONF_REG (DR_REG_PCR_BASE + 0xc0) +/** PCR_SPI2_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: + * reserved. + */ +#define PCR_SPI2_CLKM_SEL 0x00000003U +#define PCR_SPI2_CLKM_SEL_M (PCR_SPI2_CLKM_SEL_V << PCR_SPI2_CLKM_SEL_S) +#define PCR_SPI2_CLKM_SEL_V 0x00000003U +#define PCR_SPI2_CLKM_SEL_S 20 +/** PCR_SPI2_CLKM_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable spi2 function clock + */ +#define PCR_SPI2_CLKM_EN (BIT(22)) +#define PCR_SPI2_CLKM_EN_M (PCR_SPI2_CLKM_EN_V << PCR_SPI2_CLKM_EN_S) +#define PCR_SPI2_CLKM_EN_V 0x00000001U +#define PCR_SPI2_CLKM_EN_S 22 + +/** PCR_AES_CONF_REG register + * AES configuration register + */ +#define PCR_AES_CONF_REG (DR_REG_PCR_BASE + 0xc4) +/** PCR_AES_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable aes clock + */ +#define PCR_AES_CLK_EN (BIT(0)) +#define PCR_AES_CLK_EN_M (PCR_AES_CLK_EN_V << PCR_AES_CLK_EN_S) +#define PCR_AES_CLK_EN_V 0x00000001U +#define PCR_AES_CLK_EN_S 0 +/** PCR_AES_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset aes module + */ +#define PCR_AES_RST_EN (BIT(1)) +#define PCR_AES_RST_EN_M (PCR_AES_RST_EN_V << PCR_AES_RST_EN_S) +#define PCR_AES_RST_EN_V 0x00000001U +#define PCR_AES_RST_EN_S 1 +/** PCR_AES_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset aes module + */ +#define PCR_AES_READY (BIT(2)) +#define PCR_AES_READY_M (PCR_AES_READY_V << PCR_AES_READY_S) +#define PCR_AES_READY_V 0x00000001U +#define PCR_AES_READY_S 2 + +/** PCR_SHA_CONF_REG register + * SHA configuration register + */ +#define PCR_SHA_CONF_REG (DR_REG_PCR_BASE + 0xc8) +/** PCR_SHA_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable sha clock + */ +#define PCR_SHA_CLK_EN (BIT(0)) +#define PCR_SHA_CLK_EN_M (PCR_SHA_CLK_EN_V << PCR_SHA_CLK_EN_S) +#define PCR_SHA_CLK_EN_V 0x00000001U +#define PCR_SHA_CLK_EN_S 0 +/** PCR_SHA_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset sha module + */ +#define PCR_SHA_RST_EN (BIT(1)) +#define PCR_SHA_RST_EN_M (PCR_SHA_RST_EN_V << PCR_SHA_RST_EN_S) +#define PCR_SHA_RST_EN_V 0x00000001U +#define PCR_SHA_RST_EN_S 1 +/** PCR_SHA_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset sha module + */ +#define PCR_SHA_READY (BIT(2)) +#define PCR_SHA_READY_M (PCR_SHA_READY_V << PCR_SHA_READY_S) +#define PCR_SHA_READY_V 0x00000001U +#define PCR_SHA_READY_S 2 + +/** PCR_RSA_CONF_REG register + * RSA configuration register + */ +#define PCR_RSA_CONF_REG (DR_REG_PCR_BASE + 0xcc) +/** PCR_RSA_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable rsa clock + */ +#define PCR_RSA_CLK_EN (BIT(0)) +#define PCR_RSA_CLK_EN_M (PCR_RSA_CLK_EN_V << PCR_RSA_CLK_EN_S) +#define PCR_RSA_CLK_EN_V 0x00000001U +#define PCR_RSA_CLK_EN_S 0 +/** PCR_RSA_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset rsa module + */ +#define PCR_RSA_RST_EN (BIT(1)) +#define PCR_RSA_RST_EN_M (PCR_RSA_RST_EN_V << PCR_RSA_RST_EN_S) +#define PCR_RSA_RST_EN_V 0x00000001U +#define PCR_RSA_RST_EN_S 1 +/** PCR_RSA_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset rsa module + */ +#define PCR_RSA_READY (BIT(2)) +#define PCR_RSA_READY_M (PCR_RSA_READY_V << PCR_RSA_READY_S) +#define PCR_RSA_READY_V 0x00000001U +#define PCR_RSA_READY_S 2 + +/** PCR_RSA_PD_CTRL_REG register + * RSA power control register + */ +#define PCR_RSA_PD_CTRL_REG (DR_REG_PCR_BASE + 0xd0) +/** PCR_RSA_MEM_PD : R/W; bitpos: [0]; default: 0; + * Set this bit to power down rsa internal memory. + */ +#define PCR_RSA_MEM_PD (BIT(0)) +#define PCR_RSA_MEM_PD_M (PCR_RSA_MEM_PD_V << PCR_RSA_MEM_PD_S) +#define PCR_RSA_MEM_PD_V 0x00000001U +#define PCR_RSA_MEM_PD_S 0 +/** PCR_RSA_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1; + * Set this bit to force power up rsa internal memory + */ +#define PCR_RSA_MEM_FORCE_PU (BIT(1)) +#define PCR_RSA_MEM_FORCE_PU_M (PCR_RSA_MEM_FORCE_PU_V << PCR_RSA_MEM_FORCE_PU_S) +#define PCR_RSA_MEM_FORCE_PU_V 0x00000001U +#define PCR_RSA_MEM_FORCE_PU_S 1 +/** PCR_RSA_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; + * Set this bit to force power down rsa internal memory. + */ +#define PCR_RSA_MEM_FORCE_PD (BIT(2)) +#define PCR_RSA_MEM_FORCE_PD_M (PCR_RSA_MEM_FORCE_PD_V << PCR_RSA_MEM_FORCE_PD_S) +#define PCR_RSA_MEM_FORCE_PD_V 0x00000001U +#define PCR_RSA_MEM_FORCE_PD_S 2 + +/** PCR_ECC_CONF_REG register + * ECC configuration register + */ +#define PCR_ECC_CONF_REG (DR_REG_PCR_BASE + 0xd4) +/** PCR_ECC_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable ecc clock + */ +#define PCR_ECC_CLK_EN (BIT(0)) +#define PCR_ECC_CLK_EN_M (PCR_ECC_CLK_EN_V << PCR_ECC_CLK_EN_S) +#define PCR_ECC_CLK_EN_V 0x00000001U +#define PCR_ECC_CLK_EN_S 0 +/** PCR_ECC_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset ecc module + */ +#define PCR_ECC_RST_EN (BIT(1)) +#define PCR_ECC_RST_EN_M (PCR_ECC_RST_EN_V << PCR_ECC_RST_EN_S) +#define PCR_ECC_RST_EN_V 0x00000001U +#define PCR_ECC_RST_EN_S 1 +/** PCR_ECC_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset ecc module + */ +#define PCR_ECC_READY (BIT(2)) +#define PCR_ECC_READY_M (PCR_ECC_READY_V << PCR_ECC_READY_S) +#define PCR_ECC_READY_V 0x00000001U +#define PCR_ECC_READY_S 2 + +/** PCR_ECC_PD_CTRL_REG register + * ECC power control register + */ +#define PCR_ECC_PD_CTRL_REG (DR_REG_PCR_BASE + 0xd8) +/** PCR_ECC_MEM_PD : R/W; bitpos: [0]; default: 0; + * Set this bit to power down ecc internal memory. + */ +#define PCR_ECC_MEM_PD (BIT(0)) +#define PCR_ECC_MEM_PD_M (PCR_ECC_MEM_PD_V << PCR_ECC_MEM_PD_S) +#define PCR_ECC_MEM_PD_V 0x00000001U +#define PCR_ECC_MEM_PD_S 0 +/** PCR_ECC_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1; + * Set this bit to force power up ecc internal memory + */ +#define PCR_ECC_MEM_FORCE_PU (BIT(1)) +#define PCR_ECC_MEM_FORCE_PU_M (PCR_ECC_MEM_FORCE_PU_V << PCR_ECC_MEM_FORCE_PU_S) +#define PCR_ECC_MEM_FORCE_PU_V 0x00000001U +#define PCR_ECC_MEM_FORCE_PU_S 1 +/** PCR_ECC_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; + * Set this bit to force power down ecc internal memory. + */ +#define PCR_ECC_MEM_FORCE_PD (BIT(2)) +#define PCR_ECC_MEM_FORCE_PD_M (PCR_ECC_MEM_FORCE_PD_V << PCR_ECC_MEM_FORCE_PD_S) +#define PCR_ECC_MEM_FORCE_PD_V 0x00000001U +#define PCR_ECC_MEM_FORCE_PD_S 2 + +/** PCR_DS_CONF_REG register + * DS configuration register + */ +#define PCR_DS_CONF_REG (DR_REG_PCR_BASE + 0xdc) +/** PCR_DS_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable ds clock + */ +#define PCR_DS_CLK_EN (BIT(0)) +#define PCR_DS_CLK_EN_M (PCR_DS_CLK_EN_V << PCR_DS_CLK_EN_S) +#define PCR_DS_CLK_EN_V 0x00000001U +#define PCR_DS_CLK_EN_S 0 +/** PCR_DS_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset ds module + */ +#define PCR_DS_RST_EN (BIT(1)) +#define PCR_DS_RST_EN_M (PCR_DS_RST_EN_V << PCR_DS_RST_EN_S) +#define PCR_DS_RST_EN_V 0x00000001U +#define PCR_DS_RST_EN_S 1 +/** PCR_DS_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset ds module + */ +#define PCR_DS_READY (BIT(2)) +#define PCR_DS_READY_M (PCR_DS_READY_V << PCR_DS_READY_S) +#define PCR_DS_READY_V 0x00000001U +#define PCR_DS_READY_S 2 + +/** PCR_HMAC_CONF_REG register + * HMAC configuration register + */ +#define PCR_HMAC_CONF_REG (DR_REG_PCR_BASE + 0xe0) +/** PCR_HMAC_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable hmac clock + */ +#define PCR_HMAC_CLK_EN (BIT(0)) +#define PCR_HMAC_CLK_EN_M (PCR_HMAC_CLK_EN_V << PCR_HMAC_CLK_EN_S) +#define PCR_HMAC_CLK_EN_V 0x00000001U +#define PCR_HMAC_CLK_EN_S 0 +/** PCR_HMAC_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset hmac module + */ +#define PCR_HMAC_RST_EN (BIT(1)) +#define PCR_HMAC_RST_EN_M (PCR_HMAC_RST_EN_V << PCR_HMAC_RST_EN_S) +#define PCR_HMAC_RST_EN_V 0x00000001U +#define PCR_HMAC_RST_EN_S 1 +/** PCR_HMAC_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset hmac module + */ +#define PCR_HMAC_READY (BIT(2)) +#define PCR_HMAC_READY_M (PCR_HMAC_READY_V << PCR_HMAC_READY_S) +#define PCR_HMAC_READY_V 0x00000001U +#define PCR_HMAC_READY_S 2 + +/** PCR_ECDSA_CONF_REG register + * ECDSA configuration register + */ +#define PCR_ECDSA_CONF_REG (DR_REG_PCR_BASE + 0xe4) +/** PCR_ECDSA_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable ecdsa clock + */ +#define PCR_ECDSA_CLK_EN (BIT(0)) +#define PCR_ECDSA_CLK_EN_M (PCR_ECDSA_CLK_EN_V << PCR_ECDSA_CLK_EN_S) +#define PCR_ECDSA_CLK_EN_V 0x00000001U +#define PCR_ECDSA_CLK_EN_S 0 +/** PCR_ECDSA_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset ecdsa module + */ +#define PCR_ECDSA_RST_EN (BIT(1)) +#define PCR_ECDSA_RST_EN_M (PCR_ECDSA_RST_EN_V << PCR_ECDSA_RST_EN_S) +#define PCR_ECDSA_RST_EN_V 0x00000001U +#define PCR_ECDSA_RST_EN_S 1 +/** PCR_ECDSA_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset ecdsa module + */ +#define PCR_ECDSA_READY (BIT(2)) +#define PCR_ECDSA_READY_M (PCR_ECDSA_READY_V << PCR_ECDSA_READY_S) +#define PCR_ECDSA_READY_V 0x00000001U +#define PCR_ECDSA_READY_S 2 + +/** PCR_IOMUX_CONF_REG register + * IOMUX configuration register + */ +#define PCR_IOMUX_CONF_REG (DR_REG_PCR_BASE + 0xe8) +/** PCR_IOMUX_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable iomux apb clock + */ +#define PCR_IOMUX_CLK_EN (BIT(0)) +#define PCR_IOMUX_CLK_EN_M (PCR_IOMUX_CLK_EN_V << PCR_IOMUX_CLK_EN_S) +#define PCR_IOMUX_CLK_EN_V 0x00000001U +#define PCR_IOMUX_CLK_EN_S 0 +/** PCR_IOMUX_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset iomux module + */ +#define PCR_IOMUX_RST_EN (BIT(1)) +#define PCR_IOMUX_RST_EN_M (PCR_IOMUX_RST_EN_V << PCR_IOMUX_RST_EN_S) +#define PCR_IOMUX_RST_EN_V 0x00000001U +#define PCR_IOMUX_RST_EN_S 1 + +/** PCR_IOMUX_CLK_CONF_REG register + * IOMUX_CLK configuration register + */ +#define PCR_IOMUX_CLK_CONF_REG (DR_REG_PCR_BASE + 0xec) +/** PCR_IOMUX_FUNC_CLK_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: + * FOSC, 3(default): XTAL. + */ +#define PCR_IOMUX_FUNC_CLK_SEL 0x00000003U +#define PCR_IOMUX_FUNC_CLK_SEL_M (PCR_IOMUX_FUNC_CLK_SEL_V << PCR_IOMUX_FUNC_CLK_SEL_S) +#define PCR_IOMUX_FUNC_CLK_SEL_V 0x00000003U +#define PCR_IOMUX_FUNC_CLK_SEL_S 20 +/** PCR_IOMUX_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable iomux function clock + */ +#define PCR_IOMUX_FUNC_CLK_EN (BIT(22)) +#define PCR_IOMUX_FUNC_CLK_EN_M (PCR_IOMUX_FUNC_CLK_EN_V << PCR_IOMUX_FUNC_CLK_EN_S) +#define PCR_IOMUX_FUNC_CLK_EN_V 0x00000001U +#define PCR_IOMUX_FUNC_CLK_EN_S 22 + +/** PCR_MEM_MONITOR_CONF_REG register + * MEM_MONITOR configuration register + */ +#define PCR_MEM_MONITOR_CONF_REG (DR_REG_PCR_BASE + 0xf0) +/** PCR_MEM_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable mem_monitor clock + */ +#define PCR_MEM_MONITOR_CLK_EN (BIT(0)) +#define PCR_MEM_MONITOR_CLK_EN_M (PCR_MEM_MONITOR_CLK_EN_V << PCR_MEM_MONITOR_CLK_EN_S) +#define PCR_MEM_MONITOR_CLK_EN_V 0x00000001U +#define PCR_MEM_MONITOR_CLK_EN_S 0 +/** PCR_MEM_MONITOR_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset mem_monitor module + */ +#define PCR_MEM_MONITOR_RST_EN (BIT(1)) +#define PCR_MEM_MONITOR_RST_EN_M (PCR_MEM_MONITOR_RST_EN_V << PCR_MEM_MONITOR_RST_EN_S) +#define PCR_MEM_MONITOR_RST_EN_V 0x00000001U +#define PCR_MEM_MONITOR_RST_EN_S 1 +/** PCR_MEM_MONITOR_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset mem_monitor module + */ +#define PCR_MEM_MONITOR_READY (BIT(2)) +#define PCR_MEM_MONITOR_READY_M (PCR_MEM_MONITOR_READY_V << PCR_MEM_MONITOR_READY_S) +#define PCR_MEM_MONITOR_READY_V 0x00000001U +#define PCR_MEM_MONITOR_READY_S 2 + +/** PCR_REGDMA_CONF_REG register + * REGDMA configuration register + */ +#define PCR_REGDMA_CONF_REG (DR_REG_PCR_BASE + 0xf4) +/** PCR_REGDMA_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable regdma clock + */ +#define PCR_REGDMA_CLK_EN (BIT(0)) +#define PCR_REGDMA_CLK_EN_M (PCR_REGDMA_CLK_EN_V << PCR_REGDMA_CLK_EN_S) +#define PCR_REGDMA_CLK_EN_V 0x00000001U +#define PCR_REGDMA_CLK_EN_S 0 +/** PCR_REGDMA_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset regdma module + */ +#define PCR_REGDMA_RST_EN (BIT(1)) +#define PCR_REGDMA_RST_EN_M (PCR_REGDMA_RST_EN_V << PCR_REGDMA_RST_EN_S) +#define PCR_REGDMA_RST_EN_V 0x00000001U +#define PCR_REGDMA_RST_EN_S 1 + +/** PCR_TRACE_CONF_REG register + * TRACE configuration register + */ +#define PCR_TRACE_CONF_REG (DR_REG_PCR_BASE + 0xf8) +/** PCR_TRACE_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable trace clock + */ +#define PCR_TRACE_CLK_EN (BIT(0)) +#define PCR_TRACE_CLK_EN_M (PCR_TRACE_CLK_EN_V << PCR_TRACE_CLK_EN_S) +#define PCR_TRACE_CLK_EN_V 0x00000001U +#define PCR_TRACE_CLK_EN_S 0 +/** PCR_TRACE_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset trace module + */ +#define PCR_TRACE_RST_EN (BIT(1)) +#define PCR_TRACE_RST_EN_M (PCR_TRACE_RST_EN_V << PCR_TRACE_RST_EN_S) +#define PCR_TRACE_RST_EN_V 0x00000001U +#define PCR_TRACE_RST_EN_S 1 + +/** PCR_ASSIST_CONF_REG register + * ASSIST configuration register + */ +#define PCR_ASSIST_CONF_REG (DR_REG_PCR_BASE + 0xfc) +/** PCR_ASSIST_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable assist clock + */ +#define PCR_ASSIST_CLK_EN (BIT(0)) +#define PCR_ASSIST_CLK_EN_M (PCR_ASSIST_CLK_EN_V << PCR_ASSIST_CLK_EN_S) +#define PCR_ASSIST_CLK_EN_V 0x00000001U +#define PCR_ASSIST_CLK_EN_S 0 +/** PCR_ASSIST_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset assist module + */ +#define PCR_ASSIST_RST_EN (BIT(1)) +#define PCR_ASSIST_RST_EN_M (PCR_ASSIST_RST_EN_V << PCR_ASSIST_RST_EN_S) +#define PCR_ASSIST_RST_EN_V 0x00000001U +#define PCR_ASSIST_RST_EN_S 1 + +/** PCR_CACHE_CONF_REG register + * CACHE configuration register + */ +#define PCR_CACHE_CONF_REG (DR_REG_PCR_BASE + 0x100) +/** PCR_CACHE_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable cache clock + */ +#define PCR_CACHE_CLK_EN (BIT(0)) +#define PCR_CACHE_CLK_EN_M (PCR_CACHE_CLK_EN_V << PCR_CACHE_CLK_EN_S) +#define PCR_CACHE_CLK_EN_V 0x00000001U +#define PCR_CACHE_CLK_EN_S 0 +/** PCR_CACHE_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset cache module + */ +#define PCR_CACHE_RST_EN (BIT(1)) +#define PCR_CACHE_RST_EN_M (PCR_CACHE_RST_EN_V << PCR_CACHE_RST_EN_S) +#define PCR_CACHE_RST_EN_V 0x00000001U +#define PCR_CACHE_RST_EN_S 1 + +/** PCR_MODEM_CONF_REG register + * MODEM_APB configuration register + */ +#define PCR_MODEM_CONF_REG (DR_REG_PCR_BASE + 0x104) +/** PCR_MODEM_CLK_SEL : R/W; bitpos: [0]; default: 0; + * xxxx + */ +#define PCR_MODEM_CLK_SEL (BIT(0)) +#define PCR_MODEM_CLK_SEL_M (PCR_MODEM_CLK_SEL_V << PCR_MODEM_CLK_SEL_S) +#define PCR_MODEM_CLK_SEL_V 0x00000001U +#define PCR_MODEM_CLK_SEL_S 0 +/** PCR_MODEM_CLK_EN : R/W; bitpos: [1]; default: 1; + * xxxx + */ +#define PCR_MODEM_CLK_EN (BIT(1)) +#define PCR_MODEM_CLK_EN_M (PCR_MODEM_CLK_EN_V << PCR_MODEM_CLK_EN_S) +#define PCR_MODEM_CLK_EN_V 0x00000001U +#define PCR_MODEM_CLK_EN_S 1 +/** PCR_MODEM_RST_EN : R/W; bitpos: [2]; default: 0; + * Set this file as 1 to reset modem-subsystem. + */ +#define PCR_MODEM_RST_EN (BIT(2)) +#define PCR_MODEM_RST_EN_M (PCR_MODEM_RST_EN_V << PCR_MODEM_RST_EN_S) +#define PCR_MODEM_RST_EN_V 0x00000001U +#define PCR_MODEM_RST_EN_S 2 + +/** PCR_TIMEOUT_CONF_REG register + * TIMEOUT configuration register + */ +#define PCR_TIMEOUT_CONF_REG (DR_REG_PCR_BASE + 0x108) +/** PCR_CPU_TIMEOUT_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset cpu_peri timeout module + */ +#define PCR_CPU_TIMEOUT_RST_EN (BIT(1)) +#define PCR_CPU_TIMEOUT_RST_EN_M (PCR_CPU_TIMEOUT_RST_EN_V << PCR_CPU_TIMEOUT_RST_EN_S) +#define PCR_CPU_TIMEOUT_RST_EN_V 0x00000001U +#define PCR_CPU_TIMEOUT_RST_EN_S 1 +/** PCR_HP_TIMEOUT_RST_EN : R/W; bitpos: [2]; default: 0; + * Set 0 to reset hp_peri timeout module and hp_modem timeout module + */ +#define PCR_HP_TIMEOUT_RST_EN (BIT(2)) +#define PCR_HP_TIMEOUT_RST_EN_M (PCR_HP_TIMEOUT_RST_EN_V << PCR_HP_TIMEOUT_RST_EN_S) +#define PCR_HP_TIMEOUT_RST_EN_V 0x00000001U +#define PCR_HP_TIMEOUT_RST_EN_S 2 + +/** PCR_SYSCLK_CONF_REG register + * SYSCLK configuration register + */ +#define PCR_SYSCLK_CONF_REG (DR_REG_PCR_BASE + 0x10c) +/** PCR_SOC_CLK_SEL : R/W; bitpos: [17:16]; default: 0; + * This field is used to select clock source. 0: XTAL, 1: SPLL, 2: FOSC, 3: reserved. + */ +#define PCR_SOC_CLK_SEL 0x00000003U +#define PCR_SOC_CLK_SEL_M (PCR_SOC_CLK_SEL_V << PCR_SOC_CLK_SEL_S) +#define PCR_SOC_CLK_SEL_V 0x00000003U +#define PCR_SOC_CLK_SEL_S 16 +/** PCR_CLK_XTAL_FREQ : RO; bitpos: [30:24]; default: 32; + * This field indicates the frequency(MHz) of XTAL. + */ +#define PCR_CLK_XTAL_FREQ 0x0000007FU +#define PCR_CLK_XTAL_FREQ_M (PCR_CLK_XTAL_FREQ_V << PCR_CLK_XTAL_FREQ_S) +#define PCR_CLK_XTAL_FREQ_V 0x0000007FU +#define PCR_CLK_XTAL_FREQ_S 24 + +/** PCR_CPU_WAITI_CONF_REG register + * CPU_WAITI configuration register + */ +#define PCR_CPU_WAITI_CONF_REG (DR_REG_PCR_BASE + 0x110) +/** PCR_CPU_WAIT_MODE_FORCE_ON : R/W; bitpos: [3]; default: 1; + * Set 1 to force cpu_waiti_clk enable. + */ +#define PCR_CPU_WAIT_MODE_FORCE_ON (BIT(3)) +#define PCR_CPU_WAIT_MODE_FORCE_ON_M (PCR_CPU_WAIT_MODE_FORCE_ON_V << PCR_CPU_WAIT_MODE_FORCE_ON_S) +#define PCR_CPU_WAIT_MODE_FORCE_ON_V 0x00000001U +#define PCR_CPU_WAIT_MODE_FORCE_ON_S 3 +/** PCR_CPU_WAITI_DELAY_NUM : R/W; bitpos: [7:4]; default: 0; + * This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk + * will close + */ +#define PCR_CPU_WAITI_DELAY_NUM 0x0000000FU +#define PCR_CPU_WAITI_DELAY_NUM_M (PCR_CPU_WAITI_DELAY_NUM_V << PCR_CPU_WAITI_DELAY_NUM_S) +#define PCR_CPU_WAITI_DELAY_NUM_V 0x0000000FU +#define PCR_CPU_WAITI_DELAY_NUM_S 4 + +/** PCR_CPU_FREQ_CONF_REG register + * CPU_FREQ configuration register + */ +#define PCR_CPU_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x114) +/** PCR_CPU_DIV_NUM : R/W; bitpos: [7:0]; default: 0; + * Set this field to generate clk_cpu driven by clk_hproot. The clk_cpu is + * div1(default)/div2/div4 of clk_hproot. This field is only available for low-speed + * clock-source such as XTAL/FOSC, and should be used together with PCR_AHB_DIV_NUM. + */ +#define PCR_CPU_DIV_NUM 0x000000FFU +#define PCR_CPU_DIV_NUM_M (PCR_CPU_DIV_NUM_V << PCR_CPU_DIV_NUM_S) +#define PCR_CPU_DIV_NUM_V 0x000000FFU +#define PCR_CPU_DIV_NUM_S 0 + +/** PCR_AHB_FREQ_CONF_REG register + * AHB_FREQ configuration register + */ +#define PCR_AHB_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x118) +/** PCR_AHB_DIV_NUM : R/W; bitpos: [7:0]; default: 0; + * Set this field to generate clk_ahb driven by clk_hproot. The clk_ahb is + * div1(default)/div2/div4/div8 of clk_hproot. This field is only available for + * low-speed clock-source such as XTAL/FOSC, and should be used together with + * PCR_CPU_DIV_NUM. + */ +#define PCR_AHB_DIV_NUM 0x000000FFU +#define PCR_AHB_DIV_NUM_M (PCR_AHB_DIV_NUM_V << PCR_AHB_DIV_NUM_S) +#define PCR_AHB_DIV_NUM_V 0x000000FFU +#define PCR_AHB_DIV_NUM_S 0 + +/** PCR_APB_FREQ_CONF_REG register + * APB_FREQ configuration register + */ +#define PCR_APB_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x11c) +/** PCR_APB_DECREASE_DIV_NUM : R/W; bitpos: [7:0]; default: 0; + * If this field's value is grater than PCR_APB_DIV_NUM, the clk_apb will be + * automatically down to clk_apb_decrease only when no access is on apb-bus, and will + * recover to the previous frequency when a new access appears on apb-bus. Set as one + * within (0,1,3) to set clk_apb_decrease as div1/div2/div4(default) of clk_ahb. Note + * that enable this function will reduce performance. Users can set this field as zero + * to disable the auto-decrease-apb-freq function. By default, this function is + * disable. + */ +#define PCR_APB_DECREASE_DIV_NUM 0x000000FFU +#define PCR_APB_DECREASE_DIV_NUM_M (PCR_APB_DECREASE_DIV_NUM_V << PCR_APB_DECREASE_DIV_NUM_S) +#define PCR_APB_DECREASE_DIV_NUM_V 0x000000FFU +#define PCR_APB_DECREASE_DIV_NUM_S 0 +/** PCR_APB_DIV_NUM : R/W; bitpos: [15:8]; default: 0; + * Set as one within (0,1,3) to generate clk_apb driven by clk_ahb. The clk_apb is + * div1(default)/div2/div4 of clk_ahb. + */ +#define PCR_APB_DIV_NUM 0x000000FFU +#define PCR_APB_DIV_NUM_M (PCR_APB_DIV_NUM_V << PCR_APB_DIV_NUM_S) +#define PCR_APB_DIV_NUM_V 0x000000FFU +#define PCR_APB_DIV_NUM_S 8 + +/** PCR_SYSCLK_FREQ_QUERY_0_REG register + * SYSCLK frequency query 0 register + */ +#define PCR_SYSCLK_FREQ_QUERY_0_REG (DR_REG_PCR_BASE + 0x120) +/** PCR_FOSC_FREQ : HRO; bitpos: [7:0]; default: 8; + * This field indicates the frequency(MHz) of FOSC. + */ +#define PCR_FOSC_FREQ 0x000000FFU +#define PCR_FOSC_FREQ_M (PCR_FOSC_FREQ_V << PCR_FOSC_FREQ_S) +#define PCR_FOSC_FREQ_V 0x000000FFU +#define PCR_FOSC_FREQ_S 0 +/** PCR_PLL_FREQ : HRO; bitpos: [17:8]; default: 96; + * This field indicates the frequency(MHz) of SPLL. + */ +#define PCR_PLL_FREQ 0x000003FFU +#define PCR_PLL_FREQ_M (PCR_PLL_FREQ_V << PCR_PLL_FREQ_S) +#define PCR_PLL_FREQ_V 0x000003FFU +#define PCR_PLL_FREQ_S 8 + +/** PCR_PLL_DIV_CLK_EN_REG register + * SPLL DIV clock-gating configuration register + */ +#define PCR_PLL_DIV_CLK_EN_REG (DR_REG_PCR_BASE + 0x124) +/** PCR_PLL_240M_CLK_EN : R/W; bitpos: [0]; default: 1; + * This field is used to open 96 MHz clock (SPLL) driven from SPLL. 0: close, 1: + * open(default). Only available when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_240M_CLK_EN (BIT(0)) +#define PCR_PLL_240M_CLK_EN_M (PCR_PLL_240M_CLK_EN_V << PCR_PLL_240M_CLK_EN_S) +#define PCR_PLL_240M_CLK_EN_V 0x00000001U +#define PCR_PLL_240M_CLK_EN_S 0 +/** PCR_PLL_160M_CLK_EN : R/W; bitpos: [1]; default: 1; + * This field is used to open 64 MHz clock (div3 of SPLL) driven from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_160M_CLK_EN (BIT(1)) +#define PCR_PLL_160M_CLK_EN_M (PCR_PLL_160M_CLK_EN_V << PCR_PLL_160M_CLK_EN_S) +#define PCR_PLL_160M_CLK_EN_V 0x00000001U +#define PCR_PLL_160M_CLK_EN_S 1 +/** PCR_PLL_120M_CLK_EN : R/W; bitpos: [2]; default: 1; + * This field is used to open 48 MHz clock (div4 of SPLL) driven from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_120M_CLK_EN (BIT(2)) +#define PCR_PLL_120M_CLK_EN_M (PCR_PLL_120M_CLK_EN_V << PCR_PLL_120M_CLK_EN_S) +#define PCR_PLL_120M_CLK_EN_V 0x00000001U +#define PCR_PLL_120M_CLK_EN_S 2 +/** PCR_PLL_80M_CLK_EN : R/W; bitpos: [3]; default: 1; + * This field is used to open 32 MHz clock (div6 of SPLL) driven from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_80M_CLK_EN (BIT(3)) +#define PCR_PLL_80M_CLK_EN_M (PCR_PLL_80M_CLK_EN_V << PCR_PLL_80M_CLK_EN_S) +#define PCR_PLL_80M_CLK_EN_V 0x00000001U +#define PCR_PLL_80M_CLK_EN_S 3 +/** PCR_PLL_48M_CLK_EN : R/W; bitpos: [4]; default: 1; + * This field is used to open 16 MHz clock (div10 of SPLL) driven from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_48M_CLK_EN (BIT(4)) +#define PCR_PLL_48M_CLK_EN_M (PCR_PLL_48M_CLK_EN_V << PCR_PLL_48M_CLK_EN_S) +#define PCR_PLL_48M_CLK_EN_V 0x00000001U +#define PCR_PLL_48M_CLK_EN_S 4 +/** PCR_PLL_40M_CLK_EN : R/W; bitpos: [5]; default: 1; + * This field is used to open 8 MHz clock (div12 of SPLL) driven from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_40M_CLK_EN (BIT(5)) +#define PCR_PLL_40M_CLK_EN_M (PCR_PLL_40M_CLK_EN_V << PCR_PLL_40M_CLK_EN_S) +#define PCR_PLL_40M_CLK_EN_V 0x00000001U +#define PCR_PLL_40M_CLK_EN_S 5 + +/** PCR_CTRL_CLK_OUT_EN_REG register + * CLK_OUT_EN configuration register + */ +#define PCR_CTRL_CLK_OUT_EN_REG (DR_REG_PCR_BASE + 0x128) +/** PCR_CLK8_OEN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable 8m clock + */ +#define PCR_CLK8_OEN (BIT(0)) +#define PCR_CLK8_OEN_M (PCR_CLK8_OEN_V << PCR_CLK8_OEN_S) +#define PCR_CLK8_OEN_V 0x00000001U +#define PCR_CLK8_OEN_S 0 +/** PCR_CLK16_OEN : R/W; bitpos: [1]; default: 1; + * Set 1 to enable 16m clock + */ +#define PCR_CLK16_OEN (BIT(1)) +#define PCR_CLK16_OEN_M (PCR_CLK16_OEN_V << PCR_CLK16_OEN_S) +#define PCR_CLK16_OEN_V 0x00000001U +#define PCR_CLK16_OEN_S 1 +/** PCR_CLK32_OEN : R/W; bitpos: [2]; default: 1; + * Set 1 to enable 32m clock + */ +#define PCR_CLK32_OEN (BIT(2)) +#define PCR_CLK32_OEN_M (PCR_CLK32_OEN_V << PCR_CLK32_OEN_S) +#define PCR_CLK32_OEN_V 0x00000001U +#define PCR_CLK32_OEN_S 2 +/** PCR_CLK_ADC_INF_OEN : R/W; bitpos: [3]; default: 1; + * Reserved + */ +#define PCR_CLK_ADC_INF_OEN (BIT(3)) +#define PCR_CLK_ADC_INF_OEN_M (PCR_CLK_ADC_INF_OEN_V << PCR_CLK_ADC_INF_OEN_S) +#define PCR_CLK_ADC_INF_OEN_V 0x00000001U +#define PCR_CLK_ADC_INF_OEN_S 3 +/** PCR_CLK_DFM_INF_OEN : R/W; bitpos: [4]; default: 1; + * Reserved + */ +#define PCR_CLK_DFM_INF_OEN (BIT(4)) +#define PCR_CLK_DFM_INF_OEN_M (PCR_CLK_DFM_INF_OEN_V << PCR_CLK_DFM_INF_OEN_S) +#define PCR_CLK_DFM_INF_OEN_V 0x00000001U +#define PCR_CLK_DFM_INF_OEN_S 4 +/** PCR_CLK_SDM_MOD_OEN : R/W; bitpos: [5]; default: 1; + * Reserved + */ +#define PCR_CLK_SDM_MOD_OEN (BIT(5)) +#define PCR_CLK_SDM_MOD_OEN_M (PCR_CLK_SDM_MOD_OEN_V << PCR_CLK_SDM_MOD_OEN_S) +#define PCR_CLK_SDM_MOD_OEN_V 0x00000001U +#define PCR_CLK_SDM_MOD_OEN_S 5 +/** PCR_CLK_XTAL_OEN : R/W; bitpos: [6]; default: 1; + * Set 1 to enable xtal clock + */ +#define PCR_CLK_XTAL_OEN (BIT(6)) +#define PCR_CLK_XTAL_OEN_M (PCR_CLK_XTAL_OEN_V << PCR_CLK_XTAL_OEN_S) +#define PCR_CLK_XTAL_OEN_V 0x00000001U +#define PCR_CLK_XTAL_OEN_S 6 + +/** PCR_CTRL_TICK_CONF_REG register + * TICK configuration register + */ +#define PCR_CTRL_TICK_CONF_REG (DR_REG_PCR_BASE + 0x12c) +/** PCR_XTAL_TICK_NUM : R/W; bitpos: [7:0]; default: 39; + * ******* Description *********** + */ +#define PCR_XTAL_TICK_NUM 0x000000FFU +#define PCR_XTAL_TICK_NUM_M (PCR_XTAL_TICK_NUM_V << PCR_XTAL_TICK_NUM_S) +#define PCR_XTAL_TICK_NUM_V 0x000000FFU +#define PCR_XTAL_TICK_NUM_S 0 +/** PCR_FOSC_TICK_NUM : R/W; bitpos: [15:8]; default: 7; + * ******* Description *********** + */ +#define PCR_FOSC_TICK_NUM 0x000000FFU +#define PCR_FOSC_TICK_NUM_M (PCR_FOSC_TICK_NUM_V << PCR_FOSC_TICK_NUM_S) +#define PCR_FOSC_TICK_NUM_V 0x000000FFU +#define PCR_FOSC_TICK_NUM_S 8 +/** PCR_TICK_ENABLE : R/W; bitpos: [16]; default: 1; + * ******* Description *********** + */ +#define PCR_TICK_ENABLE (BIT(16)) +#define PCR_TICK_ENABLE_M (PCR_TICK_ENABLE_V << PCR_TICK_ENABLE_S) +#define PCR_TICK_ENABLE_V 0x00000001U +#define PCR_TICK_ENABLE_S 16 +/** PCR_RST_TICK_CNT : R/W; bitpos: [17]; default: 0; + * ******* Description *********** + */ +#define PCR_RST_TICK_CNT (BIT(17)) +#define PCR_RST_TICK_CNT_M (PCR_RST_TICK_CNT_V << PCR_RST_TICK_CNT_S) +#define PCR_RST_TICK_CNT_V 0x00000001U +#define PCR_RST_TICK_CNT_S 17 + +/** PCR_CTRL_32K_CONF_REG register + * 32KHz clock configuration register + */ +#define PCR_CTRL_32K_CONF_REG (DR_REG_PCR_BASE + 0x130) +/** PCR_32K_SEL : R/W; bitpos: [1:0]; default: 1; + * This field indicates which one 32KHz clock will be used by timergroup. 1: XTAL32K + * (default), 2/3: 32KHz from pad GPIO0. + */ +#define PCR_32K_SEL 0x00000003U +#define PCR_32K_SEL_M (PCR_32K_SEL_V << PCR_32K_SEL_S) +#define PCR_32K_SEL_V 0x00000003U +#define PCR_32K_SEL_S 0 +/** PCR_32K_MODEM_SEL : R/W; bitpos: [3:2]; default: 1; + * This field indicates which one 32KHz clock will be used by MODEM_SYSTEM. 1: + * XTAL32K(default), 2/3: 32KHz from pad GPIO0. + */ +#define PCR_32K_MODEM_SEL 0x00000003U +#define PCR_32K_MODEM_SEL_M (PCR_32K_MODEM_SEL_V << PCR_32K_MODEM_SEL_S) +#define PCR_32K_MODEM_SEL_V 0x00000003U +#define PCR_32K_MODEM_SEL_S 2 + +/** PCR_SRAM_POWER_CONF_0_REG register + * HP SRAM/ROM configuration register + */ +#define PCR_SRAM_POWER_CONF_0_REG (DR_REG_PCR_BASE + 0x134) +/** PCR_ROM_FORCE_PU : R/W; bitpos: [14:13]; default: 3; + * Set this bit to force power up ROM + */ +#define PCR_ROM_FORCE_PU 0x00000003U +#define PCR_ROM_FORCE_PU_M (PCR_ROM_FORCE_PU_V << PCR_ROM_FORCE_PU_S) +#define PCR_ROM_FORCE_PU_V 0x00000003U +#define PCR_ROM_FORCE_PU_S 13 +/** PCR_ROM_FORCE_PD : R/W; bitpos: [16:15]; default: 0; + * Set this bit to force power down ROM. + */ +#define PCR_ROM_FORCE_PD 0x00000003U +#define PCR_ROM_FORCE_PD_M (PCR_ROM_FORCE_PD_V << PCR_ROM_FORCE_PD_S) +#define PCR_ROM_FORCE_PD_V 0x00000003U +#define PCR_ROM_FORCE_PD_S 15 +/** PCR_ROM_CLKGATE_FORCE_ON : R/W; bitpos: [18:17]; default: 0; + * 1: Force to open the clock and bypass the gate-clock when accessing the ROM. 0: A + * gate-clock will be used when accessing the ROM. + */ +#define PCR_ROM_CLKGATE_FORCE_ON 0x00000003U +#define PCR_ROM_CLKGATE_FORCE_ON_M (PCR_ROM_CLKGATE_FORCE_ON_V << PCR_ROM_CLKGATE_FORCE_ON_S) +#define PCR_ROM_CLKGATE_FORCE_ON_V 0x00000003U +#define PCR_ROM_CLKGATE_FORCE_ON_S 17 + +/** PCR_SRAM_POWER_CONF_1_REG register + * HP SRAM/ROM configuration register + */ +#define PCR_SRAM_POWER_CONF_1_REG (DR_REG_PCR_BASE + 0x138) +/** PCR_SRAM_FORCE_PU : R/W; bitpos: [4:0]; default: 31; + * Set this bit to force power up SRAM + */ +#define PCR_SRAM_FORCE_PU 0x0000001FU +#define PCR_SRAM_FORCE_PU_M (PCR_SRAM_FORCE_PU_V << PCR_SRAM_FORCE_PU_S) +#define PCR_SRAM_FORCE_PU_V 0x0000001FU +#define PCR_SRAM_FORCE_PU_S 0 +/** PCR_SRAM_FORCE_PD : R/W; bitpos: [14:10]; default: 0; + * Set this bit to force power down SRAM. + */ +#define PCR_SRAM_FORCE_PD 0x0000001FU +#define PCR_SRAM_FORCE_PD_M (PCR_SRAM_FORCE_PD_V << PCR_SRAM_FORCE_PD_S) +#define PCR_SRAM_FORCE_PD_V 0x0000001FU +#define PCR_SRAM_FORCE_PD_S 10 +/** PCR_SRAM_CLKGATE_FORCE_ON : R/W; bitpos: [29:25]; default: 0; + * 1: Force to open the clock and bypass the gate-clock when accessing the SRAM. 0: A + * gate-clock will be used when accessing the SRAM. + */ +#define PCR_SRAM_CLKGATE_FORCE_ON 0x0000001FU +#define PCR_SRAM_CLKGATE_FORCE_ON_M (PCR_SRAM_CLKGATE_FORCE_ON_V << PCR_SRAM_CLKGATE_FORCE_ON_S) +#define PCR_SRAM_CLKGATE_FORCE_ON_V 0x0000001FU +#define PCR_SRAM_CLKGATE_FORCE_ON_S 25 + +/** PCR_SEC_CONF_REG register + * xxxx + */ +#define PCR_SEC_CONF_REG (DR_REG_PCR_BASE + 0x13c) +/** PCR_SEC_CLK_SEL : R/W; bitpos: [1:0]; default: 0; + * xxxx + */ +#define PCR_SEC_CLK_SEL 0x00000003U +#define PCR_SEC_CLK_SEL_M (PCR_SEC_CLK_SEL_V << PCR_SEC_CLK_SEL_S) +#define PCR_SEC_CLK_SEL_V 0x00000003U +#define PCR_SEC_CLK_SEL_S 0 + +/** PCR_BUS_CLK_UPDATE_REG register + * xxxx + */ +#define PCR_BUS_CLK_UPDATE_REG (DR_REG_PCR_BASE + 0x148) +/** PCR_BUS_CLOCK_UPDATE : R/W/WTC; bitpos: [0]; default: 0; + * xxxx + */ +#define PCR_BUS_CLOCK_UPDATE (BIT(0)) +#define PCR_BUS_CLOCK_UPDATE_M (PCR_BUS_CLOCK_UPDATE_V << PCR_BUS_CLOCK_UPDATE_S) +#define PCR_BUS_CLOCK_UPDATE_V 0x00000001U +#define PCR_BUS_CLOCK_UPDATE_S 0 + +/** PCR_SAR_CLK_DIV_REG register + * xxxx + */ +#define PCR_SAR_CLK_DIV_REG (DR_REG_PCR_BASE + 0x14c) +/** PCR_SAR2_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 4; + * xxxx + */ +#define PCR_SAR2_CLK_DIV_NUM 0x000000FFU +#define PCR_SAR2_CLK_DIV_NUM_M (PCR_SAR2_CLK_DIV_NUM_V << PCR_SAR2_CLK_DIV_NUM_S) +#define PCR_SAR2_CLK_DIV_NUM_V 0x000000FFU +#define PCR_SAR2_CLK_DIV_NUM_S 0 +/** PCR_SAR1_CLK_DIV_NUM : R/W; bitpos: [15:8]; default: 4; + * xxxx + */ +#define PCR_SAR1_CLK_DIV_NUM 0x000000FFU +#define PCR_SAR1_CLK_DIV_NUM_M (PCR_SAR1_CLK_DIV_NUM_V << PCR_SAR1_CLK_DIV_NUM_S) +#define PCR_SAR1_CLK_DIV_NUM_V 0x000000FFU +#define PCR_SAR1_CLK_DIV_NUM_S 8 + +/** PCR_PWDET_SAR_CLK_CONF_REG register + * xxxx + */ +#define PCR_PWDET_SAR_CLK_CONF_REG (DR_REG_PCR_BASE + 0x150) +/** PCR_PWDET_SAR_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 7; + * xxxx + */ +#define PCR_PWDET_SAR_CLK_DIV_NUM 0x000000FFU +#define PCR_PWDET_SAR_CLK_DIV_NUM_M (PCR_PWDET_SAR_CLK_DIV_NUM_V << PCR_PWDET_SAR_CLK_DIV_NUM_S) +#define PCR_PWDET_SAR_CLK_DIV_NUM_V 0x000000FFU +#define PCR_PWDET_SAR_CLK_DIV_NUM_S 0 +/** PCR_PWDET_SAR_READER_EN : R/W; bitpos: [8]; default: 1; + * xxxx + */ +#define PCR_PWDET_SAR_READER_EN (BIT(8)) +#define PCR_PWDET_SAR_READER_EN_M (PCR_PWDET_SAR_READER_EN_V << PCR_PWDET_SAR_READER_EN_S) +#define PCR_PWDET_SAR_READER_EN_V 0x00000001U +#define PCR_PWDET_SAR_READER_EN_S 8 + +/** PCR_DATE_REG register + * Date register. + */ +#define PCR_DATE_REG (DR_REG_PCR_BASE + 0xffc) +/** PCR_DATE : R/W; bitpos: [27:0]; default: 37786000; + * PCR version information. + */ +#define PCR_DATE 0x0FFFFFFFU +#define PCR_DATE_M (PCR_DATE_V << PCR_DATE_S) +#define PCR_DATE_V 0x0FFFFFFFU +#define PCR_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/src/target/esp32h21/ld/esp32h21.rom.api.ld b/src/target/esp32h21/ld/esp32h21.rom.api.ld index c978fdc..bf69e7d 100644 --- a/src/target/esp32h21/ld/esp32h21.rom.api.ld +++ b/src/target/esp32h21/ld/esp32h21.rom.api.ld @@ -25,7 +25,6 @@ PROVIDE ( esp_rom_uart_putc = ets_write_char_uart ); PROVIDE ( esp_rom_uart_attach = uartAttach ); PROVIDE ( esp_rom_uart_init = Uart_Init ); PROVIDE ( esp_rom_uart_div_modify = uart_div_modify ); -PROVIDE ( esp_rom_get_apb_freq = ets_get_apb_freq ); PROVIDE ( esp_rom_get_cpu_freq = ets_clk_get_cpu_freq ); PROVIDE ( esp_rom_get_uart_device = GetUartDevice ); @@ -55,6 +54,7 @@ PROVIDE ( esp_rom_isr_attach = ets_isr_attach ); PROVIDE ( esp_rom_isr_unmask = ets_isr_unmask ); PROVIDE ( esp_rom_get_cpu_ticks_per_us = ets_get_cpu_frequency ); PROVIDE ( esp_rom_set_cpu_ticks_per_us = ets_update_cpu_frequency ); +PROVIDE ( esp_rom_get_xtal_freq = ets_clk_get_xtal_freq); PROVIDE ( esp_rom_spiflash_attach = spi_flash_attach ); PROVIDE ( esp_rom_spiflash_clear_bp = esp_rom_spiflash_unlock ); diff --git a/src/target/esp32h21/src/clock.c b/src/target/esp32h21/src/clock.c new file mode 100644 index 0000000..039f122 --- /dev/null +++ b/src/target/esp32h21/src/clock.c @@ -0,0 +1,35 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 OR MIT + */ + +#include +#include +#include +#include +#include +#include + +#define MHZ 1000000 + +extern uint32_t esp_rom_get_cpu_freq(void); +extern void esp_rom_set_cpu_ticks_per_us(uint32_t ticks_per_us); + +static uint32_t s_cpu_freq = 0; + +void stub_target_clock_init(void) +{ + REG_SET_FIELD(PCR_SYSCLK_CONF_REG, PCR_SOC_CLK_SEL, 1); + REG_SET_FIELD(PCR_BUS_CLK_UPDATE_REG, PCR_BUS_CLOCK_UPDATE, 1); + s_cpu_freq = 96 * MHZ; + esp_rom_set_cpu_ticks_per_us(s_cpu_freq / MHZ); +} + +uint32_t stub_target_get_cpu_freq(void) +{ + if (s_cpu_freq == 0) { + return esp_rom_get_cpu_freq(); + } + return s_cpu_freq; +} diff --git a/src/target/esp32h4/include/soc/pcr_reg.h b/src/target/esp32h4/include/soc/pcr_reg.h new file mode 100644 index 0000000..ed03310 --- /dev/null +++ b/src/target/esp32h4/include/soc/pcr_reg.h @@ -0,0 +1,3048 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 OR MIT + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** PCR_UART0_CONF_REG register + * UART0 configuration register + */ +#define PCR_UART0_CONF_REG (DR_REG_PCR_BASE + 0x0) +/** PCR_UART0_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable uart0 apb clock + */ +#define PCR_UART0_CLK_EN (BIT(0)) +#define PCR_UART0_CLK_EN_M (PCR_UART0_CLK_EN_V << PCR_UART0_CLK_EN_S) +#define PCR_UART0_CLK_EN_V 0x00000001U +#define PCR_UART0_CLK_EN_S 0 +/** PCR_UART0_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset uart0 module + */ +#define PCR_UART0_RST_EN (BIT(1)) +#define PCR_UART0_RST_EN_M (PCR_UART0_RST_EN_V << PCR_UART0_RST_EN_S) +#define PCR_UART0_RST_EN_V 0x00000001U +#define PCR_UART0_RST_EN_S 1 +/** PCR_UART0_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset uart0 module + */ +#define PCR_UART0_READY (BIT(2)) +#define PCR_UART0_READY_M (PCR_UART0_READY_V << PCR_UART0_READY_S) +#define PCR_UART0_READY_V 0x00000001U +#define PCR_UART0_READY_S 2 + +/** PCR_UART0_SCLK_CONF_REG register + * UART0_SCLK configuration register + */ +#define PCR_UART0_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x4) +/** PCR_UART0_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the uart0 function clock. + */ +#define PCR_UART0_SCLK_DIV_A 0x0000003FU +#define PCR_UART0_SCLK_DIV_A_M (PCR_UART0_SCLK_DIV_A_V << PCR_UART0_SCLK_DIV_A_S) +#define PCR_UART0_SCLK_DIV_A_V 0x0000003FU +#define PCR_UART0_SCLK_DIV_A_S 0 +/** PCR_UART0_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the uart0 function clock. + */ +#define PCR_UART0_SCLK_DIV_B 0x0000003FU +#define PCR_UART0_SCLK_DIV_B_M (PCR_UART0_SCLK_DIV_B_V << PCR_UART0_SCLK_DIV_B_S) +#define PCR_UART0_SCLK_DIV_B_V 0x0000003FU +#define PCR_UART0_SCLK_DIV_B_S 6 +/** PCR_UART0_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the uart0 function clock. + */ +#define PCR_UART0_SCLK_DIV_NUM 0x000000FFU +#define PCR_UART0_SCLK_DIV_NUM_M (PCR_UART0_SCLK_DIV_NUM_V << PCR_UART0_SCLK_DIV_NUM_S) +#define PCR_UART0_SCLK_DIV_NUM_V 0x000000FFU +#define PCR_UART0_SCLK_DIV_NUM_S 12 +/** PCR_UART0_SCLK_SEL : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of UART0. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK + */ +#define PCR_UART0_SCLK_SEL 0x00000003U +#define PCR_UART0_SCLK_SEL_M (PCR_UART0_SCLK_SEL_V << PCR_UART0_SCLK_SEL_S) +#define PCR_UART0_SCLK_SEL_V 0x00000003U +#define PCR_UART0_SCLK_SEL_S 20 +/** PCR_UART0_SCLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable uart0 function clock + */ +#define PCR_UART0_SCLK_EN (BIT(22)) +#define PCR_UART0_SCLK_EN_M (PCR_UART0_SCLK_EN_V << PCR_UART0_SCLK_EN_S) +#define PCR_UART0_SCLK_EN_V 0x00000001U +#define PCR_UART0_SCLK_EN_S 22 + +/** PCR_UART0_MEM_LP_CTRL_REG register + * UART0 memory power control register + */ +#define PCR_UART0_MEM_LP_CTRL_REG (DR_REG_PCR_BASE + 0x8) +/** PCR_UART0_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures uart0 memory low power mode in low power stage. + * 0(default): deep sleep + * 1: light sleep + * 2: shut down + * 3: disable low power stage + */ +#define PCR_UART0_MEM_LP_MODE 0x00000003U +#define PCR_UART0_MEM_LP_MODE_M (PCR_UART0_MEM_LP_MODE_V << PCR_UART0_MEM_LP_MODE_S) +#define PCR_UART0_MEM_LP_MODE_V 0x00000003U +#define PCR_UART0_MEM_LP_MODE_S 0 +/** PCR_UART0_MEM_LP_EN : R/W; bitpos: [2]; default: 0; + * Set this bit to power down uart0 memory. + */ +#define PCR_UART0_MEM_LP_EN (BIT(2)) +#define PCR_UART0_MEM_LP_EN_M (PCR_UART0_MEM_LP_EN_V << PCR_UART0_MEM_LP_EN_S) +#define PCR_UART0_MEM_LP_EN_V 0x00000001U +#define PCR_UART0_MEM_LP_EN_S 2 +/** PCR_UART0_MEM_FORCE_CTRL : R/W; bitpos: [3]; default: 0; + * Set this bit to force software control uart0 memory, disable hardware control. + */ +#define PCR_UART0_MEM_FORCE_CTRL (BIT(3)) +#define PCR_UART0_MEM_FORCE_CTRL_M (PCR_UART0_MEM_FORCE_CTRL_V << PCR_UART0_MEM_FORCE_CTRL_S) +#define PCR_UART0_MEM_FORCE_CTRL_V 0x00000001U +#define PCR_UART0_MEM_FORCE_CTRL_S 3 + +/** PCR_UART1_CONF_REG register + * UART1 configuration register + */ +#define PCR_UART1_CONF_REG (DR_REG_PCR_BASE + 0xc) +/** PCR_UART1_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable uart1 apb clock + */ +#define PCR_UART1_CLK_EN (BIT(0)) +#define PCR_UART1_CLK_EN_M (PCR_UART1_CLK_EN_V << PCR_UART1_CLK_EN_S) +#define PCR_UART1_CLK_EN_V 0x00000001U +#define PCR_UART1_CLK_EN_S 0 +/** PCR_UART1_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset uart1 module + */ +#define PCR_UART1_RST_EN (BIT(1)) +#define PCR_UART1_RST_EN_M (PCR_UART1_RST_EN_V << PCR_UART1_RST_EN_S) +#define PCR_UART1_RST_EN_V 0x00000001U +#define PCR_UART1_RST_EN_S 1 +/** PCR_UART1_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset uart1 module + */ +#define PCR_UART1_READY (BIT(2)) +#define PCR_UART1_READY_M (PCR_UART1_READY_V << PCR_UART1_READY_S) +#define PCR_UART1_READY_V 0x00000001U +#define PCR_UART1_READY_S 2 + +/** PCR_UART1_SCLK_CONF_REG register + * UART1_SCLK configuration register + */ +#define PCR_UART1_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x10) +/** PCR_UART1_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the uart1 function clock. + */ +#define PCR_UART1_SCLK_DIV_A 0x0000003FU +#define PCR_UART1_SCLK_DIV_A_M (PCR_UART1_SCLK_DIV_A_V << PCR_UART1_SCLK_DIV_A_S) +#define PCR_UART1_SCLK_DIV_A_V 0x0000003FU +#define PCR_UART1_SCLK_DIV_A_S 0 +/** PCR_UART1_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the uart1 function clock. + */ +#define PCR_UART1_SCLK_DIV_B 0x0000003FU +#define PCR_UART1_SCLK_DIV_B_M (PCR_UART1_SCLK_DIV_B_V << PCR_UART1_SCLK_DIV_B_S) +#define PCR_UART1_SCLK_DIV_B_V 0x0000003FU +#define PCR_UART1_SCLK_DIV_B_S 6 +/** PCR_UART1_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the uart1 function clock. + */ +#define PCR_UART1_SCLK_DIV_NUM 0x000000FFU +#define PCR_UART1_SCLK_DIV_NUM_M (PCR_UART1_SCLK_DIV_NUM_V << PCR_UART1_SCLK_DIV_NUM_S) +#define PCR_UART1_SCLK_DIV_NUM_V 0x000000FFU +#define PCR_UART1_SCLK_DIV_NUM_S 12 +/** PCR_UART1_SCLK_SEL : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of UART1. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK + */ +#define PCR_UART1_SCLK_SEL 0x00000003U +#define PCR_UART1_SCLK_SEL_M (PCR_UART1_SCLK_SEL_V << PCR_UART1_SCLK_SEL_S) +#define PCR_UART1_SCLK_SEL_V 0x00000003U +#define PCR_UART1_SCLK_SEL_S 20 +/** PCR_UART1_SCLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable uart0 function clock + */ +#define PCR_UART1_SCLK_EN (BIT(22)) +#define PCR_UART1_SCLK_EN_M (PCR_UART1_SCLK_EN_V << PCR_UART1_SCLK_EN_S) +#define PCR_UART1_SCLK_EN_V 0x00000001U +#define PCR_UART1_SCLK_EN_S 22 + +/** PCR_UART1_MEM_LP_CTRL_REG register + * UART1 memory power control register + */ +#define PCR_UART1_MEM_LP_CTRL_REG (DR_REG_PCR_BASE + 0x14) +/** PCR_UART1_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures uart1 memory low power mode in low power stage. + * 0(default): deep sleep + * 1: light sleep + * 2: shut down + * 3: disable low power stage + */ +#define PCR_UART1_MEM_LP_MODE 0x00000003U +#define PCR_UART1_MEM_LP_MODE_M (PCR_UART1_MEM_LP_MODE_V << PCR_UART1_MEM_LP_MODE_S) +#define PCR_UART1_MEM_LP_MODE_V 0x00000003U +#define PCR_UART1_MEM_LP_MODE_S 0 +/** PCR_UART1_MEM_LP_EN : R/W; bitpos: [2]; default: 0; + * Set this bit to power down uart1 memory. + */ +#define PCR_UART1_MEM_LP_EN (BIT(2)) +#define PCR_UART1_MEM_LP_EN_M (PCR_UART1_MEM_LP_EN_V << PCR_UART1_MEM_LP_EN_S) +#define PCR_UART1_MEM_LP_EN_V 0x00000001U +#define PCR_UART1_MEM_LP_EN_S 2 +/** PCR_UART1_MEM_FORCE_CTRL : R/W; bitpos: [3]; default: 0; + * Set this bit to force software control uart1 memory, disable hardware control. + */ +#define PCR_UART1_MEM_FORCE_CTRL (BIT(3)) +#define PCR_UART1_MEM_FORCE_CTRL_M (PCR_UART1_MEM_FORCE_CTRL_V << PCR_UART1_MEM_FORCE_CTRL_S) +#define PCR_UART1_MEM_FORCE_CTRL_V 0x00000001U +#define PCR_UART1_MEM_FORCE_CTRL_S 3 + +/** PCR_MSPI_CONF_REG register + * MSPI configuration register + */ +#define PCR_MSPI_CONF_REG (DR_REG_PCR_BASE + 0x18) +/** PCR_MSPI_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable mspi apb clock and mspi pll clock + */ +#define PCR_MSPI_CLK_EN (BIT(0)) +#define PCR_MSPI_CLK_EN_M (PCR_MSPI_CLK_EN_V << PCR_MSPI_CLK_EN_S) +#define PCR_MSPI_CLK_EN_V 0x00000001U +#define PCR_MSPI_CLK_EN_S 0 +/** PCR_MSPI_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset mspi module + */ +#define PCR_MSPI_RST_EN (BIT(1)) +#define PCR_MSPI_RST_EN_M (PCR_MSPI_RST_EN_V << PCR_MSPI_RST_EN_S) +#define PCR_MSPI_RST_EN_V 0x00000001U +#define PCR_MSPI_RST_EN_S 1 +/** PCR_MSPI_PLL_CLK_EN : R/W; bitpos: [2]; default: 1; + * Set 1 to enable mspi pll clock + */ +#define PCR_MSPI_PLL_CLK_EN (BIT(2)) +#define PCR_MSPI_PLL_CLK_EN_M (PCR_MSPI_PLL_CLK_EN_V << PCR_MSPI_PLL_CLK_EN_S) +#define PCR_MSPI_PLL_CLK_EN_V 0x00000001U +#define PCR_MSPI_PLL_CLK_EN_S 2 +/** PCR_MSPI_READY : RO; bitpos: [3]; default: 1; + * Query this field after reset mspi module + */ +#define PCR_MSPI_READY (BIT(3)) +#define PCR_MSPI_READY_M (PCR_MSPI_READY_V << PCR_MSPI_READY_S) +#define PCR_MSPI_READY_V 0x00000001U +#define PCR_MSPI_READY_S 3 + +/** PCR_MSPI_CLK_CONF_REG register + * MSPI_CLK configuration register + */ +#define PCR_MSPI_CLK_CONF_REG (DR_REG_PCR_BASE + 0x1c) +/** PCR_MSPI_FAST_DIV_NUM : R/W; bitpos: [7:0]; default: 0; + * Set as one within (0,1,2) to generate div1(default)/div2/div4 of low-speed + * clock-source to drive clk_mspi_fast. Only available when the clck-source is a + * low-speed clock-source such as XTAL/FOSC. + */ +#define PCR_MSPI_FAST_DIV_NUM 0x000000FFU +#define PCR_MSPI_FAST_DIV_NUM_M (PCR_MSPI_FAST_DIV_NUM_V << PCR_MSPI_FAST_DIV_NUM_S) +#define PCR_MSPI_FAST_DIV_NUM_V 0x000000FFU +#define PCR_MSPI_FAST_DIV_NUM_S 0 +/** PCR_MSPI_FUNC_CLK_SEL : R/W; bitpos: [9:8]; default: 0; + * Configures the clock source for MSPI. + * 0(default): XTAL_CLK + * 1 RC_FAST_CLK + * 2: PLL_F480M_CLK + */ +#define PCR_MSPI_FUNC_CLK_SEL 0x00000003U +#define PCR_MSPI_FUNC_CLK_SEL_M (PCR_MSPI_FUNC_CLK_SEL_V << PCR_MSPI_FUNC_CLK_SEL_S) +#define PCR_MSPI_FUNC_CLK_SEL_V 0x00000003U +#define PCR_MSPI_FUNC_CLK_SEL_S 8 +/** PCR_MSPI_FUNC_CLK_EN : R/W; bitpos: [10]; default: 1; + * Set 1 to enable mspi func clock + */ +#define PCR_MSPI_FUNC_CLK_EN (BIT(10)) +#define PCR_MSPI_FUNC_CLK_EN_M (PCR_MSPI_FUNC_CLK_EN_V << PCR_MSPI_FUNC_CLK_EN_S) +#define PCR_MSPI_FUNC_CLK_EN_V 0x00000001U +#define PCR_MSPI_FUNC_CLK_EN_S 10 +/** PCR_MSPI_AXI_RST_EN : R/W; bitpos: [11]; default: 0; + * Set 1 to reset axi_clock domain of mspi module + */ +#define PCR_MSPI_AXI_RST_EN (BIT(11)) +#define PCR_MSPI_AXI_RST_EN_M (PCR_MSPI_AXI_RST_EN_V << PCR_MSPI_AXI_RST_EN_S) +#define PCR_MSPI_AXI_RST_EN_V 0x00000001U +#define PCR_MSPI_AXI_RST_EN_S 11 + +/** PCR_MSPI_MEM_LP_CTRL_REG register + * MSPI memory power control register + */ +#define PCR_MSPI_MEM_LP_CTRL_REG (DR_REG_PCR_BASE + 0x20) +/** PCR_MSPI_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures mspi memory low power mode in low power stage. + * 0(default): deep sleep + * 1: light sleep + * 2: shut down + * 3: disable low power stage + */ +#define PCR_MSPI_MEM_LP_MODE 0x00000003U +#define PCR_MSPI_MEM_LP_MODE_M (PCR_MSPI_MEM_LP_MODE_V << PCR_MSPI_MEM_LP_MODE_S) +#define PCR_MSPI_MEM_LP_MODE_V 0x00000003U +#define PCR_MSPI_MEM_LP_MODE_S 0 +/** PCR_MSPI_MEM_LP_EN : R/W; bitpos: [2]; default: 0; + * Set this bit to power down mspi memory. + */ +#define PCR_MSPI_MEM_LP_EN (BIT(2)) +#define PCR_MSPI_MEM_LP_EN_M (PCR_MSPI_MEM_LP_EN_V << PCR_MSPI_MEM_LP_EN_S) +#define PCR_MSPI_MEM_LP_EN_V 0x00000001U +#define PCR_MSPI_MEM_LP_EN_S 2 +/** PCR_MSPI_MEM_FORCE_CTRL : R/W; bitpos: [3]; default: 0; + * Set this bit to force software control mspi memory, disable hardware control. + */ +#define PCR_MSPI_MEM_FORCE_CTRL (BIT(3)) +#define PCR_MSPI_MEM_FORCE_CTRL_M (PCR_MSPI_MEM_FORCE_CTRL_V << PCR_MSPI_MEM_FORCE_CTRL_S) +#define PCR_MSPI_MEM_FORCE_CTRL_V 0x00000001U +#define PCR_MSPI_MEM_FORCE_CTRL_S 3 + +/** PCR_I2C0_CONF_REG register + * I2C configuration register + */ +#define PCR_I2C0_CONF_REG (DR_REG_PCR_BASE + 0x24) +/** PCR_I2C0_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable i2c0 apb clock + */ +#define PCR_I2C0_CLK_EN (BIT(0)) +#define PCR_I2C0_CLK_EN_M (PCR_I2C0_CLK_EN_V << PCR_I2C0_CLK_EN_S) +#define PCR_I2C0_CLK_EN_V 0x00000001U +#define PCR_I2C0_CLK_EN_S 0 +/** PCR_I2C0_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset i2c0 module + */ +#define PCR_I2C0_RST_EN (BIT(1)) +#define PCR_I2C0_RST_EN_M (PCR_I2C0_RST_EN_V << PCR_I2C0_RST_EN_S) +#define PCR_I2C0_RST_EN_V 0x00000001U +#define PCR_I2C0_RST_EN_S 1 + +/** PCR_I2C0_SCLK_CONF_REG register + * I2C_SCLK configuration register + */ +#define PCR_I2C0_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x28) +/** PCR_I2C0_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the i2c0 function clock. + */ +#define PCR_I2C0_SCLK_DIV_A 0x0000003FU +#define PCR_I2C0_SCLK_DIV_A_M (PCR_I2C0_SCLK_DIV_A_V << PCR_I2C0_SCLK_DIV_A_S) +#define PCR_I2C0_SCLK_DIV_A_V 0x0000003FU +#define PCR_I2C0_SCLK_DIV_A_S 0 +/** PCR_I2C0_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the i2c0 function clock. + */ +#define PCR_I2C0_SCLK_DIV_B 0x0000003FU +#define PCR_I2C0_SCLK_DIV_B_M (PCR_I2C0_SCLK_DIV_B_V << PCR_I2C0_SCLK_DIV_B_S) +#define PCR_I2C0_SCLK_DIV_B_V 0x0000003FU +#define PCR_I2C0_SCLK_DIV_B_S 6 +/** PCR_I2C0_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the i2c0 function clock. + */ +#define PCR_I2C0_SCLK_DIV_NUM 0x000000FFU +#define PCR_I2C0_SCLK_DIV_NUM_M (PCR_I2C0_SCLK_DIV_NUM_V << PCR_I2C0_SCLK_DIV_NUM_S) +#define PCR_I2C0_SCLK_DIV_NUM_V 0x000000FFU +#define PCR_I2C0_SCLK_DIV_NUM_S 12 +/** PCR_I2C0_SCLK_SEL : R/W; bitpos: [20]; default: 0; + * Configures the clock source of I2C. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + */ +#define PCR_I2C0_SCLK_SEL (BIT(20)) +#define PCR_I2C0_SCLK_SEL_M (PCR_I2C0_SCLK_SEL_V << PCR_I2C0_SCLK_SEL_S) +#define PCR_I2C0_SCLK_SEL_V 0x00000001U +#define PCR_I2C0_SCLK_SEL_S 20 +/** PCR_I2C0_SCLK_EN : R/W; bitpos: [22]; default: 0; + * Set 1 to enable i2c function clock + */ +#define PCR_I2C0_SCLK_EN (BIT(22)) +#define PCR_I2C0_SCLK_EN_M (PCR_I2C0_SCLK_EN_V << PCR_I2C0_SCLK_EN_S) +#define PCR_I2C0_SCLK_EN_V 0x00000001U +#define PCR_I2C0_SCLK_EN_S 22 + +/** PCR_TWAI0_CONF_REG register + * TWAI0 configuration register + */ +#define PCR_TWAI0_CONF_REG (DR_REG_PCR_BASE + 0x2c) +/** PCR_TWAI0_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable twai0 apb clock + */ +#define PCR_TWAI0_CLK_EN (BIT(0)) +#define PCR_TWAI0_CLK_EN_M (PCR_TWAI0_CLK_EN_V << PCR_TWAI0_CLK_EN_S) +#define PCR_TWAI0_CLK_EN_V 0x00000001U +#define PCR_TWAI0_CLK_EN_S 0 +/** PCR_TWAI0_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset twai0 module + */ +#define PCR_TWAI0_RST_EN (BIT(1)) +#define PCR_TWAI0_RST_EN_M (PCR_TWAI0_RST_EN_V << PCR_TWAI0_RST_EN_S) +#define PCR_TWAI0_RST_EN_V 0x00000001U +#define PCR_TWAI0_RST_EN_S 1 +/** PCR_TWAI0_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset twai0 module + */ +#define PCR_TWAI0_READY (BIT(2)) +#define PCR_TWAI0_READY_M (PCR_TWAI0_READY_V << PCR_TWAI0_READY_S) +#define PCR_TWAI0_READY_V 0x00000001U +#define PCR_TWAI0_READY_S 2 + +/** PCR_TWAI0_FUNC_CLK_CONF_REG register + * TWAI0_FUNC_CLK configuration register + */ +#define PCR_TWAI0_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x30) +/** PCR_TWAI0_FUNC_CLK_SEL : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of TWAI0. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F96M_CLK + */ +#define PCR_TWAI0_FUNC_CLK_SEL 0x00000003U +#define PCR_TWAI0_FUNC_CLK_SEL_M (PCR_TWAI0_FUNC_CLK_SEL_V << PCR_TWAI0_FUNC_CLK_SEL_S) +#define PCR_TWAI0_FUNC_CLK_SEL_V 0x00000003U +#define PCR_TWAI0_FUNC_CLK_SEL_S 20 +/** PCR_TWAI0_FUNC_CLK_EN : R/W; bitpos: [22]; default: 0; + * Set 1 to enable twai0 function clock + */ +#define PCR_TWAI0_FUNC_CLK_EN (BIT(22)) +#define PCR_TWAI0_FUNC_CLK_EN_M (PCR_TWAI0_FUNC_CLK_EN_V << PCR_TWAI0_FUNC_CLK_EN_S) +#define PCR_TWAI0_FUNC_CLK_EN_V 0x00000001U +#define PCR_TWAI0_FUNC_CLK_EN_S 22 + +/** PCR_UHCI_CONF_REG register + * UHCI configuration register + */ +#define PCR_UHCI_CONF_REG (DR_REG_PCR_BASE + 0x34) +/** PCR_UHCI_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable uhci clock + */ +#define PCR_UHCI_CLK_EN (BIT(0)) +#define PCR_UHCI_CLK_EN_M (PCR_UHCI_CLK_EN_V << PCR_UHCI_CLK_EN_S) +#define PCR_UHCI_CLK_EN_V 0x00000001U +#define PCR_UHCI_CLK_EN_S 0 +/** PCR_UHCI_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset uhci module + */ +#define PCR_UHCI_RST_EN (BIT(1)) +#define PCR_UHCI_RST_EN_M (PCR_UHCI_RST_EN_V << PCR_UHCI_RST_EN_S) +#define PCR_UHCI_RST_EN_V 0x00000001U +#define PCR_UHCI_RST_EN_S 1 +/** PCR_UHCI_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset uhci module + */ +#define PCR_UHCI_READY (BIT(2)) +#define PCR_UHCI_READY_M (PCR_UHCI_READY_V << PCR_UHCI_READY_S) +#define PCR_UHCI_READY_V 0x00000001U +#define PCR_UHCI_READY_S 2 + +/** PCR_RMT_CONF_REG register + * RMT configuration register + */ +#define PCR_RMT_CONF_REG (DR_REG_PCR_BASE + 0x38) +/** PCR_RMT_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable rmt apb clock + */ +#define PCR_RMT_CLK_EN (BIT(0)) +#define PCR_RMT_CLK_EN_M (PCR_RMT_CLK_EN_V << PCR_RMT_CLK_EN_S) +#define PCR_RMT_CLK_EN_V 0x00000001U +#define PCR_RMT_CLK_EN_S 0 +/** PCR_RMT_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset rmt module + */ +#define PCR_RMT_RST_EN (BIT(1)) +#define PCR_RMT_RST_EN_M (PCR_RMT_RST_EN_V << PCR_RMT_RST_EN_S) +#define PCR_RMT_RST_EN_V 0x00000001U +#define PCR_RMT_RST_EN_S 1 + +/** PCR_RMT_SCLK_CONF_REG register + * RMT_SCLK configuration register + */ +#define PCR_RMT_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x3c) +/** PCR_RMT_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the rmt function clock. + */ +#define PCR_RMT_SCLK_DIV_A 0x0000003FU +#define PCR_RMT_SCLK_DIV_A_M (PCR_RMT_SCLK_DIV_A_V << PCR_RMT_SCLK_DIV_A_S) +#define PCR_RMT_SCLK_DIV_A_V 0x0000003FU +#define PCR_RMT_SCLK_DIV_A_S 0 +/** PCR_RMT_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the rmt function clock. + */ +#define PCR_RMT_SCLK_DIV_B 0x0000003FU +#define PCR_RMT_SCLK_DIV_B_M (PCR_RMT_SCLK_DIV_B_V << PCR_RMT_SCLK_DIV_B_S) +#define PCR_RMT_SCLK_DIV_B_V 0x0000003FU +#define PCR_RMT_SCLK_DIV_B_S 6 +/** PCR_RMT_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 1; + * The integral part of the frequency divider factor of the rmt function clock. + */ +#define PCR_RMT_SCLK_DIV_NUM 0x000000FFU +#define PCR_RMT_SCLK_DIV_NUM_M (PCR_RMT_SCLK_DIV_NUM_V << PCR_RMT_SCLK_DIV_NUM_S) +#define PCR_RMT_SCLK_DIV_NUM_V 0x000000FFU +#define PCR_RMT_SCLK_DIV_NUM_S 12 +/** PCR_RMT_SCLK_SEL : R/W; bitpos: [20]; default: 1; + * Configures the clock source of RMT. + * 0: XTAL_CLK + * 1 (default): RC_FAST_CLK + * 2: PLL_F80M_CLK + */ +#define PCR_RMT_SCLK_SEL (BIT(20)) +#define PCR_RMT_SCLK_SEL_M (PCR_RMT_SCLK_SEL_V << PCR_RMT_SCLK_SEL_S) +#define PCR_RMT_SCLK_SEL_V 0x00000001U +#define PCR_RMT_SCLK_SEL_S 20 +/** PCR_RMT_SCLK_EN : R/W; bitpos: [21]; default: 0; + * Set 1 to enable rmt function clock + */ +#define PCR_RMT_SCLK_EN (BIT(21)) +#define PCR_RMT_SCLK_EN_M (PCR_RMT_SCLK_EN_V << PCR_RMT_SCLK_EN_S) +#define PCR_RMT_SCLK_EN_V 0x00000001U +#define PCR_RMT_SCLK_EN_S 21 + +/** PCR_RMT_MEM_LP_CTRL_REG register + * RMT memory power control register + */ +#define PCR_RMT_MEM_LP_CTRL_REG (DR_REG_PCR_BASE + 0x40) +/** PCR_RMT_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures rmt memory low power mode in low power stage. + * 0(default): deep sleep + * 1: light sleep + * 2: shut down + * 3: disable low power stage + */ +#define PCR_RMT_MEM_LP_MODE 0x00000003U +#define PCR_RMT_MEM_LP_MODE_M (PCR_RMT_MEM_LP_MODE_V << PCR_RMT_MEM_LP_MODE_S) +#define PCR_RMT_MEM_LP_MODE_V 0x00000003U +#define PCR_RMT_MEM_LP_MODE_S 0 +/** PCR_RMT_MEM_LP_EN : R/W; bitpos: [2]; default: 1; + * Set this bit to power down rmt memory. + */ +#define PCR_RMT_MEM_LP_EN (BIT(2)) +#define PCR_RMT_MEM_LP_EN_M (PCR_RMT_MEM_LP_EN_V << PCR_RMT_MEM_LP_EN_S) +#define PCR_RMT_MEM_LP_EN_V 0x00000001U +#define PCR_RMT_MEM_LP_EN_S 2 +/** PCR_RMT_MEM_FORCE_CTRL : R/W; bitpos: [3]; default: 0; + * Set this bit to force software control rmt memory, disable hardware control. + */ +#define PCR_RMT_MEM_FORCE_CTRL (BIT(3)) +#define PCR_RMT_MEM_FORCE_CTRL_M (PCR_RMT_MEM_FORCE_CTRL_V << PCR_RMT_MEM_FORCE_CTRL_S) +#define PCR_RMT_MEM_FORCE_CTRL_V 0x00000001U +#define PCR_RMT_MEM_FORCE_CTRL_S 3 + +/** PCR_LEDC_CONF_REG register + * LEDC configuration register + */ +#define PCR_LEDC_CONF_REG (DR_REG_PCR_BASE + 0x44) +/** PCR_LEDC_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable ledc apb clock + */ +#define PCR_LEDC_CLK_EN (BIT(0)) +#define PCR_LEDC_CLK_EN_M (PCR_LEDC_CLK_EN_V << PCR_LEDC_CLK_EN_S) +#define PCR_LEDC_CLK_EN_V 0x00000001U +#define PCR_LEDC_CLK_EN_S 0 +/** PCR_LEDC_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset ledc module + */ +#define PCR_LEDC_RST_EN (BIT(1)) +#define PCR_LEDC_RST_EN_M (PCR_LEDC_RST_EN_V << PCR_LEDC_RST_EN_S) +#define PCR_LEDC_RST_EN_V 0x00000001U +#define PCR_LEDC_RST_EN_S 1 +/** PCR_LEDC_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset ledc module + */ +#define PCR_LEDC_READY (BIT(2)) +#define PCR_LEDC_READY_M (PCR_LEDC_READY_V << PCR_LEDC_READY_S) +#define PCR_LEDC_READY_V 0x00000001U +#define PCR_LEDC_READY_S 2 + +/** PCR_LEDC_SCLK_CONF_REG register + * LEDC_SCLK configuration register + */ +#define PCR_LEDC_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x48) +/** PCR_LEDC_SCLK_SEL : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of LEDC. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F96M_CLK + */ +#define PCR_LEDC_SCLK_SEL 0x00000003U +#define PCR_LEDC_SCLK_SEL_M (PCR_LEDC_SCLK_SEL_V << PCR_LEDC_SCLK_SEL_S) +#define PCR_LEDC_SCLK_SEL_V 0x00000003U +#define PCR_LEDC_SCLK_SEL_S 20 +/** PCR_LEDC_SCLK_EN : R/W; bitpos: [22]; default: 0; + * Set 1 to enable ledc function clock + */ +#define PCR_LEDC_SCLK_EN (BIT(22)) +#define PCR_LEDC_SCLK_EN_M (PCR_LEDC_SCLK_EN_V << PCR_LEDC_SCLK_EN_S) +#define PCR_LEDC_SCLK_EN_V 0x00000001U +#define PCR_LEDC_SCLK_EN_S 22 + +/** PCR_TIMERGROUP0_CONF_REG register + * TIMERGROUP0 configuration register + */ +#define PCR_TIMERGROUP0_CONF_REG (DR_REG_PCR_BASE + 0x50) +/** PCR_TG0_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable timer_group0 apb clock + */ +#define PCR_TG0_CLK_EN (BIT(0)) +#define PCR_TG0_CLK_EN_M (PCR_TG0_CLK_EN_V << PCR_TG0_CLK_EN_S) +#define PCR_TG0_CLK_EN_V 0x00000001U +#define PCR_TG0_CLK_EN_S 0 +/** PCR_TG0_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset timer_group0 module + */ +#define PCR_TG0_RST_EN (BIT(1)) +#define PCR_TG0_RST_EN_M (PCR_TG0_RST_EN_V << PCR_TG0_RST_EN_S) +#define PCR_TG0_RST_EN_V 0x00000001U +#define PCR_TG0_RST_EN_S 1 +/** PCR_TG0_WDT_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset timer_group0 wdt module + */ +#define PCR_TG0_WDT_READY (BIT(2)) +#define PCR_TG0_WDT_READY_M (PCR_TG0_WDT_READY_V << PCR_TG0_WDT_READY_S) +#define PCR_TG0_WDT_READY_V 0x00000001U +#define PCR_TG0_WDT_READY_S 2 +/** PCR_TG0_TIMER0_READY : RO; bitpos: [3]; default: 1; + * Query this field after reset timer_group0 timer0 module + */ +#define PCR_TG0_TIMER0_READY (BIT(3)) +#define PCR_TG0_TIMER0_READY_M (PCR_TG0_TIMER0_READY_V << PCR_TG0_TIMER0_READY_S) +#define PCR_TG0_TIMER0_READY_V 0x00000001U +#define PCR_TG0_TIMER0_READY_S 3 +/** PCR_TG0_TIMER1_READY : RO; bitpos: [4]; default: 1; + * Query this field after reset timer_group0 timer1 module + */ +#define PCR_TG0_TIMER1_READY (BIT(4)) +#define PCR_TG0_TIMER1_READY_M (PCR_TG0_TIMER1_READY_V << PCR_TG0_TIMER1_READY_S) +#define PCR_TG0_TIMER1_READY_V 0x00000001U +#define PCR_TG0_TIMER1_READY_S 4 + +/** PCR_TIMERGROUP0_TIMER_CLK_CONF_REG register + * TIMERGROUP0_TIMER_CLK configuration register + */ +#define PCR_TIMERGROUP0_TIMER_CLK_CONF_REG (DR_REG_PCR_BASE + 0x54) +/** PCR_TG0_TIMER_CLK_SEL : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of general-purpose timers in Timer Group 0. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK + */ +#define PCR_TG0_TIMER_CLK_SEL 0x00000003U +#define PCR_TG0_TIMER_CLK_SEL_M (PCR_TG0_TIMER_CLK_SEL_V << PCR_TG0_TIMER_CLK_SEL_S) +#define PCR_TG0_TIMER_CLK_SEL_V 0x00000003U +#define PCR_TG0_TIMER_CLK_SEL_S 20 +/** PCR_TG0_TIMER_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group0 timer clock + */ +#define PCR_TG0_TIMER_CLK_EN (BIT(22)) +#define PCR_TG0_TIMER_CLK_EN_M (PCR_TG0_TIMER_CLK_EN_V << PCR_TG0_TIMER_CLK_EN_S) +#define PCR_TG0_TIMER_CLK_EN_V 0x00000001U +#define PCR_TG0_TIMER_CLK_EN_S 22 + +/** PCR_TIMERGROUP0_WDT_CLK_CONF_REG register + * TIMERGROUP0_WDT_CLK configuration register + */ +#define PCR_TIMERGROUP0_WDT_CLK_CONF_REG (DR_REG_PCR_BASE + 0x58) +/** PCR_TG0_WDT_CLK_SEL : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of WDT in Timer Group 0. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK + */ +#define PCR_TG0_WDT_CLK_SEL 0x00000003U +#define PCR_TG0_WDT_CLK_SEL_M (PCR_TG0_WDT_CLK_SEL_V << PCR_TG0_WDT_CLK_SEL_S) +#define PCR_TG0_WDT_CLK_SEL_V 0x00000003U +#define PCR_TG0_WDT_CLK_SEL_S 20 +/** PCR_TG0_WDT_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group0 wdt clock + */ +#define PCR_TG0_WDT_CLK_EN (BIT(22)) +#define PCR_TG0_WDT_CLK_EN_M (PCR_TG0_WDT_CLK_EN_V << PCR_TG0_WDT_CLK_EN_S) +#define PCR_TG0_WDT_CLK_EN_V 0x00000001U +#define PCR_TG0_WDT_CLK_EN_S 22 + +/** PCR_TIMERGROUP1_CONF_REG register + * TIMERGROUP1 configuration register + */ +#define PCR_TIMERGROUP1_CONF_REG (DR_REG_PCR_BASE + 0x5c) +/** PCR_TG1_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable timer_group1 apb clock + */ +#define PCR_TG1_CLK_EN (BIT(0)) +#define PCR_TG1_CLK_EN_M (PCR_TG1_CLK_EN_V << PCR_TG1_CLK_EN_S) +#define PCR_TG1_CLK_EN_V 0x00000001U +#define PCR_TG1_CLK_EN_S 0 +/** PCR_TG1_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset timer_group1 module + */ +#define PCR_TG1_RST_EN (BIT(1)) +#define PCR_TG1_RST_EN_M (PCR_TG1_RST_EN_V << PCR_TG1_RST_EN_S) +#define PCR_TG1_RST_EN_V 0x00000001U +#define PCR_TG1_RST_EN_S 1 +/** PCR_TG1_WDT_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset timer_group1 wdt module + */ +#define PCR_TG1_WDT_READY (BIT(2)) +#define PCR_TG1_WDT_READY_M (PCR_TG1_WDT_READY_V << PCR_TG1_WDT_READY_S) +#define PCR_TG1_WDT_READY_V 0x00000001U +#define PCR_TG1_WDT_READY_S 2 +/** PCR_TG1_TIMER0_READY : RO; bitpos: [3]; default: 1; + * Query this field after reset timer_group1 timer0 module + */ +#define PCR_TG1_TIMER0_READY (BIT(3)) +#define PCR_TG1_TIMER0_READY_M (PCR_TG1_TIMER0_READY_V << PCR_TG1_TIMER0_READY_S) +#define PCR_TG1_TIMER0_READY_V 0x00000001U +#define PCR_TG1_TIMER0_READY_S 3 +/** PCR_TG1_TIMER1_READY : RO; bitpos: [4]; default: 1; + * Query this field after reset timer_group1 timer1 module + */ +#define PCR_TG1_TIMER1_READY (BIT(4)) +#define PCR_TG1_TIMER1_READY_M (PCR_TG1_TIMER1_READY_V << PCR_TG1_TIMER1_READY_S) +#define PCR_TG1_TIMER1_READY_V 0x00000001U +#define PCR_TG1_TIMER1_READY_S 4 + +/** PCR_TIMERGROUP1_TIMER_CLK_CONF_REG register + * TIMERGROUP1_TIMER_CLK configuration register + */ +#define PCR_TIMERGROUP1_TIMER_CLK_CONF_REG (DR_REG_PCR_BASE + 0x60) +/** PCR_TG1_TIMER_CLK_SEL : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of general-purpose timers in Timer Group 1. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK + */ +#define PCR_TG1_TIMER_CLK_SEL 0x00000003U +#define PCR_TG1_TIMER_CLK_SEL_M (PCR_TG1_TIMER_CLK_SEL_V << PCR_TG1_TIMER_CLK_SEL_S) +#define PCR_TG1_TIMER_CLK_SEL_V 0x00000003U +#define PCR_TG1_TIMER_CLK_SEL_S 20 +/** PCR_TG1_TIMER_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group1 timer clock + */ +#define PCR_TG1_TIMER_CLK_EN (BIT(22)) +#define PCR_TG1_TIMER_CLK_EN_M (PCR_TG1_TIMER_CLK_EN_V << PCR_TG1_TIMER_CLK_EN_S) +#define PCR_TG1_TIMER_CLK_EN_V 0x00000001U +#define PCR_TG1_TIMER_CLK_EN_S 22 + +/** PCR_TIMERGROUP1_WDT_CLK_CONF_REG register + * TIMERGROUP1_WDT_CLK configuration register + */ +#define PCR_TIMERGROUP1_WDT_CLK_CONF_REG (DR_REG_PCR_BASE + 0x64) +/** PCR_TG1_WDT_CLK_SEL : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of WDT in Timer Group 1. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK + */ +#define PCR_TG1_WDT_CLK_SEL 0x00000003U +#define PCR_TG1_WDT_CLK_SEL_M (PCR_TG1_WDT_CLK_SEL_V << PCR_TG1_WDT_CLK_SEL_S) +#define PCR_TG1_WDT_CLK_SEL_V 0x00000003U +#define PCR_TG1_WDT_CLK_SEL_S 20 +/** PCR_TG1_WDT_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group0 wdt clock + */ +#define PCR_TG1_WDT_CLK_EN (BIT(22)) +#define PCR_TG1_WDT_CLK_EN_M (PCR_TG1_WDT_CLK_EN_V << PCR_TG1_WDT_CLK_EN_S) +#define PCR_TG1_WDT_CLK_EN_V 0x00000001U +#define PCR_TG1_WDT_CLK_EN_S 22 + +/** PCR_SYSTIMER_CONF_REG register + * SYSTIMER configuration register + */ +#define PCR_SYSTIMER_CONF_REG (DR_REG_PCR_BASE + 0x68) +/** PCR_SYSTIMER_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable systimer apb clock + */ +#define PCR_SYSTIMER_CLK_EN (BIT(0)) +#define PCR_SYSTIMER_CLK_EN_M (PCR_SYSTIMER_CLK_EN_V << PCR_SYSTIMER_CLK_EN_S) +#define PCR_SYSTIMER_CLK_EN_V 0x00000001U +#define PCR_SYSTIMER_CLK_EN_S 0 +/** PCR_SYSTIMER_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset systimer module + */ +#define PCR_SYSTIMER_RST_EN (BIT(1)) +#define PCR_SYSTIMER_RST_EN_M (PCR_SYSTIMER_RST_EN_V << PCR_SYSTIMER_RST_EN_S) +#define PCR_SYSTIMER_RST_EN_V 0x00000001U +#define PCR_SYSTIMER_RST_EN_S 1 +/** PCR_SYSTIMER_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset systimer module + */ +#define PCR_SYSTIMER_READY (BIT(2)) +#define PCR_SYSTIMER_READY_M (PCR_SYSTIMER_READY_V << PCR_SYSTIMER_READY_S) +#define PCR_SYSTIMER_READY_V 0x00000001U +#define PCR_SYSTIMER_READY_S 2 + +/** PCR_SYSTIMER_FUNC_CLK_CONF_REG register + * SYSTIMER_FUNC_CLK configuration register + */ +#define PCR_SYSTIMER_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x6c) +/** PCR_SYSTIMER_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0; + * Configures the clock source of System Timer. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + */ +#define PCR_SYSTIMER_FUNC_CLK_SEL (BIT(20)) +#define PCR_SYSTIMER_FUNC_CLK_SEL_M (PCR_SYSTIMER_FUNC_CLK_SEL_V << PCR_SYSTIMER_FUNC_CLK_SEL_S) +#define PCR_SYSTIMER_FUNC_CLK_SEL_V 0x00000001U +#define PCR_SYSTIMER_FUNC_CLK_SEL_S 20 +/** PCR_SYSTIMER_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable systimer function clock + */ +#define PCR_SYSTIMER_FUNC_CLK_EN (BIT(22)) +#define PCR_SYSTIMER_FUNC_CLK_EN_M (PCR_SYSTIMER_FUNC_CLK_EN_V << PCR_SYSTIMER_FUNC_CLK_EN_S) +#define PCR_SYSTIMER_FUNC_CLK_EN_V 0x00000001U +#define PCR_SYSTIMER_FUNC_CLK_EN_S 22 + +/** PCR_I2S_CONF_REG register + * I2S configuration register + */ +#define PCR_I2S_CONF_REG (DR_REG_PCR_BASE + 0x70) +/** PCR_I2S_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable i2s apb clock + */ +#define PCR_I2S_CLK_EN (BIT(0)) +#define PCR_I2S_CLK_EN_M (PCR_I2S_CLK_EN_V << PCR_I2S_CLK_EN_S) +#define PCR_I2S_CLK_EN_V 0x00000001U +#define PCR_I2S_CLK_EN_S 0 +/** PCR_I2S_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset i2s module + */ +#define PCR_I2S_RST_EN (BIT(1)) +#define PCR_I2S_RST_EN_M (PCR_I2S_RST_EN_V << PCR_I2S_RST_EN_S) +#define PCR_I2S_RST_EN_V 0x00000001U +#define PCR_I2S_RST_EN_S 1 +/** PCR_I2S_RX_READY : RO; bitpos: [2]; default: 1; + * Query this field before using i2s rx function, after reset i2s module + */ +#define PCR_I2S_RX_READY (BIT(2)) +#define PCR_I2S_RX_READY_M (PCR_I2S_RX_READY_V << PCR_I2S_RX_READY_S) +#define PCR_I2S_RX_READY_V 0x00000001U +#define PCR_I2S_RX_READY_S 2 +/** PCR_I2S_TX_READY : RO; bitpos: [3]; default: 1; + * Query this field before using i2s tx function, after reset i2s module + */ +#define PCR_I2S_TX_READY (BIT(3)) +#define PCR_I2S_TX_READY_M (PCR_I2S_TX_READY_V << PCR_I2S_TX_READY_S) +#define PCR_I2S_TX_READY_V 0x00000001U +#define PCR_I2S_TX_READY_S 3 + +/** PCR_I2S_TX_CLKM_CONF_REG register + * I2S_TX_CLKM configuration register + */ +#define PCR_I2S_TX_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x74) +/** PCR_I2S_TX_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 2; + * Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be + * (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= + * a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * + * (n+1)-div] + y * (n+1)-div. + */ +#define PCR_I2S_TX_CLKM_DIV_NUM 0x000000FFU +#define PCR_I2S_TX_CLKM_DIV_NUM_M (PCR_I2S_TX_CLKM_DIV_NUM_V << PCR_I2S_TX_CLKM_DIV_NUM_S) +#define PCR_I2S_TX_CLKM_DIV_NUM_V 0x000000FFU +#define PCR_I2S_TX_CLKM_DIV_NUM_S 12 +/** PCR_I2S_TX_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of I2S TX. + * 0 (default): XTAL_CLK + * 1: PLL_F240M_CLK + * 2: PLL_F160M_CLK + * 3: I2S_MCLK_in + */ +#define PCR_I2S_TX_CLKM_SEL 0x00000003U +#define PCR_I2S_TX_CLKM_SEL_M (PCR_I2S_TX_CLKM_SEL_V << PCR_I2S_TX_CLKM_SEL_S) +#define PCR_I2S_TX_CLKM_SEL_V 0x00000003U +#define PCR_I2S_TX_CLKM_SEL_S 20 +/** PCR_I2S_TX_CLKM_EN : R/W; bitpos: [22]; default: 0; + * Set 1 to enable i2s_tx function clock + */ +#define PCR_I2S_TX_CLKM_EN (BIT(22)) +#define PCR_I2S_TX_CLKM_EN_M (PCR_I2S_TX_CLKM_EN_V << PCR_I2S_TX_CLKM_EN_S) +#define PCR_I2S_TX_CLKM_EN_V 0x00000001U +#define PCR_I2S_TX_CLKM_EN_S 22 + +/** PCR_I2S_TX_CLKM_DIV_CONF_REG register + * I2S_TX_CLKM_DIV configuration register + */ +#define PCR_I2S_TX_CLKM_DIV_CONF_REG (DR_REG_PCR_BASE + 0x78) +/** PCR_I2S_TX_CLKM_DIV_Z : R/W; bitpos: [8:0]; default: 0; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of + * I2S_TX_CLKM_DIV_Z is (a-b). + */ +#define PCR_I2S_TX_CLKM_DIV_Z 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_Z_M (PCR_I2S_TX_CLKM_DIV_Z_V << PCR_I2S_TX_CLKM_DIV_Z_S) +#define PCR_I2S_TX_CLKM_DIV_Z_V 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_Z_S 0 +/** PCR_I2S_TX_CLKM_DIV_Y : R/W; bitpos: [17:9]; default: 1; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of + * I2S_TX_CLKM_DIV_Y is (a%(a-b)). + */ +#define PCR_I2S_TX_CLKM_DIV_Y 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_Y_M (PCR_I2S_TX_CLKM_DIV_Y_V << PCR_I2S_TX_CLKM_DIV_Y_S) +#define PCR_I2S_TX_CLKM_DIV_Y_V 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_Y_S 9 +/** PCR_I2S_TX_CLKM_DIV_X : R/W; bitpos: [26:18]; default: 0; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value + * of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1. + */ +#define PCR_I2S_TX_CLKM_DIV_X 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_X_M (PCR_I2S_TX_CLKM_DIV_X_V << PCR_I2S_TX_CLKM_DIV_X_S) +#define PCR_I2S_TX_CLKM_DIV_X_V 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_X_S 18 +/** PCR_I2S_TX_CLKM_DIV_YN1 : R/W; bitpos: [27]; default: 0; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of + * I2S_TX_CLKM_DIV_YN1 is 1. + */ +#define PCR_I2S_TX_CLKM_DIV_YN1 (BIT(27)) +#define PCR_I2S_TX_CLKM_DIV_YN1_M (PCR_I2S_TX_CLKM_DIV_YN1_V << PCR_I2S_TX_CLKM_DIV_YN1_S) +#define PCR_I2S_TX_CLKM_DIV_YN1_V 0x00000001U +#define PCR_I2S_TX_CLKM_DIV_YN1_S 27 + +/** PCR_I2S_RX_CLKM_CONF_REG register + * I2S_RX_CLKM configuration register + */ +#define PCR_I2S_RX_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x7c) +/** PCR_I2S_RX_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 2; + * Integral I2S clock divider value + */ +#define PCR_I2S_RX_CLKM_DIV_NUM 0x000000FFU +#define PCR_I2S_RX_CLKM_DIV_NUM_M (PCR_I2S_RX_CLKM_DIV_NUM_V << PCR_I2S_RX_CLKM_DIV_NUM_S) +#define PCR_I2S_RX_CLKM_DIV_NUM_V 0x000000FFU +#define PCR_I2S_RX_CLKM_DIV_NUM_S 12 +/** PCR_I2S_RX_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of I2S RX. + * 0 (default): XTAL_CLK + * 1: PLL_F240M_CLK + * 2: PLL_F160M_CLK + * 3: I2S_MCLK_in + */ +#define PCR_I2S_RX_CLKM_SEL 0x00000003U +#define PCR_I2S_RX_CLKM_SEL_M (PCR_I2S_RX_CLKM_SEL_V << PCR_I2S_RX_CLKM_SEL_S) +#define PCR_I2S_RX_CLKM_SEL_V 0x00000003U +#define PCR_I2S_RX_CLKM_SEL_S 20 +/** PCR_I2S_RX_CLKM_EN : R/W; bitpos: [22]; default: 0; + * Set 1 to enable i2s_rx function clock + */ +#define PCR_I2S_RX_CLKM_EN (BIT(22)) +#define PCR_I2S_RX_CLKM_EN_M (PCR_I2S_RX_CLKM_EN_V << PCR_I2S_RX_CLKM_EN_S) +#define PCR_I2S_RX_CLKM_EN_V 0x00000001U +#define PCR_I2S_RX_CLKM_EN_S 22 +/** PCR_I2S_MCLK_SEL : R/W; bitpos: [23]; default: 0; + * Configures to select master clock. + * 0 (default): I2S_TX_CLK + * 1: I2S_RX_CLK + */ +#define PCR_I2S_MCLK_SEL (BIT(23)) +#define PCR_I2S_MCLK_SEL_M (PCR_I2S_MCLK_SEL_V << PCR_I2S_MCLK_SEL_S) +#define PCR_I2S_MCLK_SEL_V 0x00000001U +#define PCR_I2S_MCLK_SEL_S 23 + +/** PCR_I2S_RX_CLKM_DIV_CONF_REG register + * I2S_RX_CLKM_DIV configuration register + */ +#define PCR_I2S_RX_CLKM_DIV_CONF_REG (DR_REG_PCR_BASE + 0x80) +/** PCR_I2S_RX_CLKM_DIV_Z : R/W; bitpos: [8:0]; default: 0; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of + * I2S_RX_CLKM_DIV_Z is (a-b). + */ +#define PCR_I2S_RX_CLKM_DIV_Z 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_Z_M (PCR_I2S_RX_CLKM_DIV_Z_V << PCR_I2S_RX_CLKM_DIV_Z_S) +#define PCR_I2S_RX_CLKM_DIV_Z_V 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_Z_S 0 +/** PCR_I2S_RX_CLKM_DIV_Y : R/W; bitpos: [17:9]; default: 1; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of + * I2S_RX_CLKM_DIV_Y is (a%(a-b)). + */ +#define PCR_I2S_RX_CLKM_DIV_Y 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_Y_M (PCR_I2S_RX_CLKM_DIV_Y_V << PCR_I2S_RX_CLKM_DIV_Y_S) +#define PCR_I2S_RX_CLKM_DIV_Y_V 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_Y_S 9 +/** PCR_I2S_RX_CLKM_DIV_X : R/W; bitpos: [26:18]; default: 0; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value + * of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1. + */ +#define PCR_I2S_RX_CLKM_DIV_X 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_X_M (PCR_I2S_RX_CLKM_DIV_X_V << PCR_I2S_RX_CLKM_DIV_X_S) +#define PCR_I2S_RX_CLKM_DIV_X_V 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_X_S 18 +/** PCR_I2S_RX_CLKM_DIV_YN1 : R/W; bitpos: [27]; default: 0; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of + * I2S_RX_CLKM_DIV_YN1 is 1. + */ +#define PCR_I2S_RX_CLKM_DIV_YN1 (BIT(27)) +#define PCR_I2S_RX_CLKM_DIV_YN1_M (PCR_I2S_RX_CLKM_DIV_YN1_V << PCR_I2S_RX_CLKM_DIV_YN1_S) +#define PCR_I2S_RX_CLKM_DIV_YN1_V 0x00000001U +#define PCR_I2S_RX_CLKM_DIV_YN1_S 27 + +/** PCR_SARADC_CONF_REG register + * SARADC configuration register + */ +#define PCR_SARADC_CONF_REG (DR_REG_PCR_BASE + 0x84) +/** PCR_SARADC_CLK_EN : R/W; bitpos: [0]; default: 1; + * no use + */ +#define PCR_SARADC_CLK_EN (BIT(0)) +#define PCR_SARADC_CLK_EN_M (PCR_SARADC_CLK_EN_V << PCR_SARADC_CLK_EN_S) +#define PCR_SARADC_CLK_EN_V 0x00000001U +#define PCR_SARADC_CLK_EN_S 0 +/** PCR_SARADC_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset function_register of saradc module + */ +#define PCR_SARADC_RST_EN (BIT(1)) +#define PCR_SARADC_RST_EN_M (PCR_SARADC_RST_EN_V << PCR_SARADC_RST_EN_S) +#define PCR_SARADC_RST_EN_V 0x00000001U +#define PCR_SARADC_RST_EN_S 1 +/** PCR_SARADC_REG_CLK_EN : R/W; bitpos: [2]; default: 0; + * Set 1 to enable saradc apb clock + */ +#define PCR_SARADC_REG_CLK_EN (BIT(2)) +#define PCR_SARADC_REG_CLK_EN_M (PCR_SARADC_REG_CLK_EN_V << PCR_SARADC_REG_CLK_EN_S) +#define PCR_SARADC_REG_CLK_EN_V 0x00000001U +#define PCR_SARADC_REG_CLK_EN_S 2 +/** PCR_SARADC_REG_RST_EN : R/W; bitpos: [3]; default: 0; + * Set 1 to reset apb_register of saradc module + */ +#define PCR_SARADC_REG_RST_EN (BIT(3)) +#define PCR_SARADC_REG_RST_EN_M (PCR_SARADC_REG_RST_EN_V << PCR_SARADC_REG_RST_EN_S) +#define PCR_SARADC_REG_RST_EN_V 0x00000001U +#define PCR_SARADC_REG_RST_EN_S 3 + +/** PCR_SARADC_CLKM_CONF_REG register + * SARADC_CLKM configuration register + */ +#define PCR_SARADC_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x88) +/** PCR_SARADC_CLKM_DIV_A : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the saradc function clock. + */ +#define PCR_SARADC_CLKM_DIV_A 0x0000003FU +#define PCR_SARADC_CLKM_DIV_A_M (PCR_SARADC_CLKM_DIV_A_V << PCR_SARADC_CLKM_DIV_A_S) +#define PCR_SARADC_CLKM_DIV_A_V 0x0000003FU +#define PCR_SARADC_CLKM_DIV_A_S 0 +/** PCR_SARADC_CLKM_DIV_B : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the saradc function clock. + */ +#define PCR_SARADC_CLKM_DIV_B 0x0000003FU +#define PCR_SARADC_CLKM_DIV_B_M (PCR_SARADC_CLKM_DIV_B_V << PCR_SARADC_CLKM_DIV_B_S) +#define PCR_SARADC_CLKM_DIV_B_V 0x0000003FU +#define PCR_SARADC_CLKM_DIV_B_S 6 +/** PCR_SARADC_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the saradc function clock. + */ +#define PCR_SARADC_CLKM_DIV_NUM 0x000000FFU +#define PCR_SARADC_CLKM_DIV_NUM_M (PCR_SARADC_CLKM_DIV_NUM_V << PCR_SARADC_CLKM_DIV_NUM_S) +#define PCR_SARADC_CLKM_DIV_NUM_V 0x000000FFU +#define PCR_SARADC_CLKM_DIV_NUM_S 12 +/** PCR_SARADC_CLKM_SEL : R/W; bitpos: [20]; default: 0; + * Configures the clock source of SAR ADC. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + */ +#define PCR_SARADC_CLKM_SEL (BIT(20)) +#define PCR_SARADC_CLKM_SEL_M (PCR_SARADC_CLKM_SEL_V << PCR_SARADC_CLKM_SEL_S) +#define PCR_SARADC_CLKM_SEL_V 0x00000001U +#define PCR_SARADC_CLKM_SEL_S 20 +/** PCR_SARADC_CLKM_EN : R/W; bitpos: [22]; default: 0; + * Set 1 to enable saradc function clock + */ +#define PCR_SARADC_CLKM_EN (BIT(22)) +#define PCR_SARADC_CLKM_EN_M (PCR_SARADC_CLKM_EN_V << PCR_SARADC_CLKM_EN_S) +#define PCR_SARADC_CLKM_EN_V 0x00000001U +#define PCR_SARADC_CLKM_EN_S 22 + +/** PCR_TSENS_CLK_CONF_REG register + * TSENS_CLK configuration register + */ +#define PCR_TSENS_CLK_CONF_REG (DR_REG_PCR_BASE + 0x8c) +/** PCR_TSENS_CLK_SEL : R/W; bitpos: [20]; default: 0; + * Configures the clock source of the temperature sensor. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + */ +#define PCR_TSENS_CLK_SEL (BIT(20)) +#define PCR_TSENS_CLK_SEL_M (PCR_TSENS_CLK_SEL_V << PCR_TSENS_CLK_SEL_S) +#define PCR_TSENS_CLK_SEL_V 0x00000001U +#define PCR_TSENS_CLK_SEL_S 20 +/** PCR_TSENS_CLK_EN : R/W; bitpos: [22]; default: 0; + * Set 1 to enable tsens clock + */ +#define PCR_TSENS_CLK_EN (BIT(22)) +#define PCR_TSENS_CLK_EN_M (PCR_TSENS_CLK_EN_V << PCR_TSENS_CLK_EN_S) +#define PCR_TSENS_CLK_EN_V 0x00000001U +#define PCR_TSENS_CLK_EN_S 22 +/** PCR_TSENS_RST_EN : R/W; bitpos: [23]; default: 0; + * Set 1 to reset tsens module + */ +#define PCR_TSENS_RST_EN (BIT(23)) +#define PCR_TSENS_RST_EN_M (PCR_TSENS_RST_EN_V << PCR_TSENS_RST_EN_S) +#define PCR_TSENS_RST_EN_V 0x00000001U +#define PCR_TSENS_RST_EN_S 23 + +/** PCR_USB_DEVICE_CONF_REG register + * USB_DEVICE configuration register + */ +#define PCR_USB_DEVICE_CONF_REG (DR_REG_PCR_BASE + 0x90) +/** PCR_USB_DEVICE_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable usb_device clock + */ +#define PCR_USB_DEVICE_CLK_EN (BIT(0)) +#define PCR_USB_DEVICE_CLK_EN_M (PCR_USB_DEVICE_CLK_EN_V << PCR_USB_DEVICE_CLK_EN_S) +#define PCR_USB_DEVICE_CLK_EN_V 0x00000001U +#define PCR_USB_DEVICE_CLK_EN_S 0 +/** PCR_USB_DEVICE_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset usb_device module + */ +#define PCR_USB_DEVICE_RST_EN (BIT(1)) +#define PCR_USB_DEVICE_RST_EN_M (PCR_USB_DEVICE_RST_EN_V << PCR_USB_DEVICE_RST_EN_S) +#define PCR_USB_DEVICE_RST_EN_V 0x00000001U +#define PCR_USB_DEVICE_RST_EN_S 1 +/** PCR_USB_DEVICE_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset usb_device module + */ +#define PCR_USB_DEVICE_READY (BIT(2)) +#define PCR_USB_DEVICE_READY_M (PCR_USB_DEVICE_READY_V << PCR_USB_DEVICE_READY_S) +#define PCR_USB_DEVICE_READY_V 0x00000001U +#define PCR_USB_DEVICE_READY_S 2 + +/** PCR_USB_DEVICE_MEM_LP_CTRL_REG register + * USB_DEVICE memory power control register + */ +#define PCR_USB_DEVICE_MEM_LP_CTRL_REG (DR_REG_PCR_BASE + 0x94) +/** PCR_USB_DEVICE_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures usb_device memory low power mode in low power stage. + * 0(default): deep sleep + * 1: light sleep + * 2: shut down + * 3: disable low power stage + */ +#define PCR_USB_DEVICE_MEM_LP_MODE 0x00000003U +#define PCR_USB_DEVICE_MEM_LP_MODE_M (PCR_USB_DEVICE_MEM_LP_MODE_V << PCR_USB_DEVICE_MEM_LP_MODE_S) +#define PCR_USB_DEVICE_MEM_LP_MODE_V 0x00000003U +#define PCR_USB_DEVICE_MEM_LP_MODE_S 0 +/** PCR_USB_DEVICE_MEM_LP_EN : R/W; bitpos: [2]; default: 0; + * Set this bit to power down usb_device memory. + */ +#define PCR_USB_DEVICE_MEM_LP_EN (BIT(2)) +#define PCR_USB_DEVICE_MEM_LP_EN_M (PCR_USB_DEVICE_MEM_LP_EN_V << PCR_USB_DEVICE_MEM_LP_EN_S) +#define PCR_USB_DEVICE_MEM_LP_EN_V 0x00000001U +#define PCR_USB_DEVICE_MEM_LP_EN_S 2 +/** PCR_USB_DEVICE_MEM_FORCE_CTRL : R/W; bitpos: [3]; default: 0; + * Set this bit to force software control usb_device memory, disable hardware control. + */ +#define PCR_USB_DEVICE_MEM_FORCE_CTRL (BIT(3)) +#define PCR_USB_DEVICE_MEM_FORCE_CTRL_M (PCR_USB_DEVICE_MEM_FORCE_CTRL_V << PCR_USB_DEVICE_MEM_FORCE_CTRL_S) +#define PCR_USB_DEVICE_MEM_FORCE_CTRL_V 0x00000001U +#define PCR_USB_DEVICE_MEM_FORCE_CTRL_S 3 + +/** PCR_INTMTX_CONF_REG register + * INTMTX configuration register + */ +#define PCR_INTMTX_CONF_REG (DR_REG_PCR_BASE + 0x98) +/** PCR_INTMTX_CORE0_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable core0 intmtx clock + */ +#define PCR_INTMTX_CORE0_CLK_EN (BIT(0)) +#define PCR_INTMTX_CORE0_CLK_EN_M (PCR_INTMTX_CORE0_CLK_EN_V << PCR_INTMTX_CORE0_CLK_EN_S) +#define PCR_INTMTX_CORE0_CLK_EN_V 0x00000001U +#define PCR_INTMTX_CORE0_CLK_EN_S 0 +/** PCR_INTMTX_CORE0_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset core0 intmtx module + */ +#define PCR_INTMTX_CORE0_RST_EN (BIT(1)) +#define PCR_INTMTX_CORE0_RST_EN_M (PCR_INTMTX_CORE0_RST_EN_V << PCR_INTMTX_CORE0_RST_EN_S) +#define PCR_INTMTX_CORE0_RST_EN_V 0x00000001U +#define PCR_INTMTX_CORE0_RST_EN_S 1 +/** PCR_INTMTX_CORE1_CLK_EN : R/W; bitpos: [2]; default: 0; + * Set 1 to enable core1 intmtx clock + */ +#define PCR_INTMTX_CORE1_CLK_EN (BIT(2)) +#define PCR_INTMTX_CORE1_CLK_EN_M (PCR_INTMTX_CORE1_CLK_EN_V << PCR_INTMTX_CORE1_CLK_EN_S) +#define PCR_INTMTX_CORE1_CLK_EN_V 0x00000001U +#define PCR_INTMTX_CORE1_CLK_EN_S 2 +/** PCR_INTMTX_CORE1_RST_EN : R/W; bitpos: [3]; default: 1; + * Set 1 to reset core1 intmtx module + */ +#define PCR_INTMTX_CORE1_RST_EN (BIT(3)) +#define PCR_INTMTX_CORE1_RST_EN_M (PCR_INTMTX_CORE1_RST_EN_V << PCR_INTMTX_CORE1_RST_EN_S) +#define PCR_INTMTX_CORE1_RST_EN_V 0x00000001U +#define PCR_INTMTX_CORE1_RST_EN_S 3 +/** PCR_INTMTX_CORE0_READY : RO; bitpos: [4]; default: 1; + * Query this field after reset intmtx module + */ +#define PCR_INTMTX_CORE0_READY (BIT(4)) +#define PCR_INTMTX_CORE0_READY_M (PCR_INTMTX_CORE0_READY_V << PCR_INTMTX_CORE0_READY_S) +#define PCR_INTMTX_CORE0_READY_V 0x00000001U +#define PCR_INTMTX_CORE0_READY_S 4 +/** PCR_INTMTX_CORE1_READY : RO; bitpos: [5]; default: 1; + * Query this field after reset intmtx module + */ +#define PCR_INTMTX_CORE1_READY (BIT(5)) +#define PCR_INTMTX_CORE1_READY_M (PCR_INTMTX_CORE1_READY_V << PCR_INTMTX_CORE1_READY_S) +#define PCR_INTMTX_CORE1_READY_V 0x00000001U +#define PCR_INTMTX_CORE1_READY_S 5 + +/** PCR_PCNT_CONF_REG register + * PCNT configuration register + */ +#define PCR_PCNT_CONF_REG (DR_REG_PCR_BASE + 0x9c) +/** PCR_PCNT_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable pcnt clock + */ +#define PCR_PCNT_CLK_EN (BIT(0)) +#define PCR_PCNT_CLK_EN_M (PCR_PCNT_CLK_EN_V << PCR_PCNT_CLK_EN_S) +#define PCR_PCNT_CLK_EN_V 0x00000001U +#define PCR_PCNT_CLK_EN_S 0 +/** PCR_PCNT_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset pcnt module + */ +#define PCR_PCNT_RST_EN (BIT(1)) +#define PCR_PCNT_RST_EN_M (PCR_PCNT_RST_EN_V << PCR_PCNT_RST_EN_S) +#define PCR_PCNT_RST_EN_V 0x00000001U +#define PCR_PCNT_RST_EN_S 1 +/** PCR_PCNT_REG_CLK_EN : R/W; bitpos: [2]; default: 0; + * Set 1 to enable pcnt reg clock + */ +#define PCR_PCNT_REG_CLK_EN (BIT(2)) +#define PCR_PCNT_REG_CLK_EN_M (PCR_PCNT_REG_CLK_EN_V << PCR_PCNT_REG_CLK_EN_S) +#define PCR_PCNT_REG_CLK_EN_V 0x00000001U +#define PCR_PCNT_REG_CLK_EN_S 2 +/** PCR_PCNT_REG_RST_EN : R/W; bitpos: [3]; default: 0; + * Set 1 to reset pcnt reg module + */ +#define PCR_PCNT_REG_RST_EN (BIT(3)) +#define PCR_PCNT_REG_RST_EN_M (PCR_PCNT_REG_RST_EN_V << PCR_PCNT_REG_RST_EN_S) +#define PCR_PCNT_REG_RST_EN_V 0x00000001U +#define PCR_PCNT_REG_RST_EN_S 3 +/** PCR_PCNT_READY : RO; bitpos: [4]; default: 1; + * Query this field after reset pcnt module + */ +#define PCR_PCNT_READY (BIT(4)) +#define PCR_PCNT_READY_M (PCR_PCNT_READY_V << PCR_PCNT_READY_S) +#define PCR_PCNT_READY_V 0x00000001U +#define PCR_PCNT_READY_S 4 +/** PCR_PCNT_CLK_SEL : R/W; bitpos: [6:5]; default: 0; + * Configures the clock source of the pcnt. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F32M_CLK + */ +#define PCR_PCNT_CLK_SEL 0x00000003U +#define PCR_PCNT_CLK_SEL_M (PCR_PCNT_CLK_SEL_V << PCR_PCNT_CLK_SEL_S) +#define PCR_PCNT_CLK_SEL_V 0x00000003U +#define PCR_PCNT_CLK_SEL_S 5 +/** PCR_PCNT_CLK_DIV_NUM : R/W; bitpos: [10:7]; default: 0; + * The integral part of the frequency divider factor of the pcnt function clock. + */ +#define PCR_PCNT_CLK_DIV_NUM 0x0000000FU +#define PCR_PCNT_CLK_DIV_NUM_M (PCR_PCNT_CLK_DIV_NUM_V << PCR_PCNT_CLK_DIV_NUM_S) +#define PCR_PCNT_CLK_DIV_NUM_V 0x0000000FU +#define PCR_PCNT_CLK_DIV_NUM_S 7 + +/** PCR_ETM_CONF_REG register + * ETM configuration register + */ +#define PCR_ETM_CONF_REG (DR_REG_PCR_BASE + 0xa0) +/** PCR_ETM_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable etm clock + */ +#define PCR_ETM_CLK_EN (BIT(0)) +#define PCR_ETM_CLK_EN_M (PCR_ETM_CLK_EN_V << PCR_ETM_CLK_EN_S) +#define PCR_ETM_CLK_EN_V 0x00000001U +#define PCR_ETM_CLK_EN_S 0 +/** PCR_ETM_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset etm module + */ +#define PCR_ETM_RST_EN (BIT(1)) +#define PCR_ETM_RST_EN_M (PCR_ETM_RST_EN_V << PCR_ETM_RST_EN_S) +#define PCR_ETM_RST_EN_V 0x00000001U +#define PCR_ETM_RST_EN_S 1 +/** PCR_ETM_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset etm module + */ +#define PCR_ETM_READY (BIT(2)) +#define PCR_ETM_READY_M (PCR_ETM_READY_V << PCR_ETM_READY_S) +#define PCR_ETM_READY_V 0x00000001U +#define PCR_ETM_READY_S 2 + +/** PCR_PWM0_CONF_REG register + * PWM0 configuration register + */ +#define PCR_PWM0_CONF_REG (DR_REG_PCR_BASE + 0xa4) +/** PCR_PWM0_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable pwm0 clock + */ +#define PCR_PWM0_CLK_EN (BIT(0)) +#define PCR_PWM0_CLK_EN_M (PCR_PWM0_CLK_EN_V << PCR_PWM0_CLK_EN_S) +#define PCR_PWM0_CLK_EN_V 0x00000001U +#define PCR_PWM0_CLK_EN_S 0 +/** PCR_PWM0_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset pwm0 module + */ +#define PCR_PWM0_RST_EN (BIT(1)) +#define PCR_PWM0_RST_EN_M (PCR_PWM0_RST_EN_V << PCR_PWM0_RST_EN_S) +#define PCR_PWM0_RST_EN_V 0x00000001U +#define PCR_PWM0_RST_EN_S 1 +/** PCR_PWM0_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset pwm0 module + */ +#define PCR_PWM0_READY (BIT(2)) +#define PCR_PWM0_READY_M (PCR_PWM0_READY_V << PCR_PWM0_READY_S) +#define PCR_PWM0_READY_V 0x00000001U +#define PCR_PWM0_READY_S 2 + +/** PCR_PWM0_CLK_CONF_REG register + * PWM0_CLK configuration register + */ +#define PCR_PWM0_CLK_CONF_REG (DR_REG_PCR_BASE + 0xa8) +/** PCR_PWM0_DIV_NUM : R/W; bitpos: [19:12]; default: 4; + * The integral part of the frequency divider factor of the pwm0 function clock. + */ +#define PCR_PWM0_DIV_NUM 0x000000FFU +#define PCR_PWM0_DIV_NUM_M (PCR_PWM0_DIV_NUM_V << PCR_PWM0_DIV_NUM_S) +#define PCR_PWM0_DIV_NUM_V 0x000000FFU +#define PCR_PWM0_DIV_NUM_S 12 +/** PCR_PWM0_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of MCPWM0. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F160M_CLK + */ +#define PCR_PWM0_CLKM_SEL 0x00000003U +#define PCR_PWM0_CLKM_SEL_M (PCR_PWM0_CLKM_SEL_V << PCR_PWM0_CLKM_SEL_S) +#define PCR_PWM0_CLKM_SEL_V 0x00000003U +#define PCR_PWM0_CLKM_SEL_S 20 +/** PCR_PWM0_CLKM_EN : R/W; bitpos: [22]; default: 0; + * set this field as 1 to activate pwm0 clkm. + */ +#define PCR_PWM0_CLKM_EN (BIT(22)) +#define PCR_PWM0_CLKM_EN_M (PCR_PWM0_CLKM_EN_V << PCR_PWM0_CLKM_EN_S) +#define PCR_PWM0_CLKM_EN_V 0x00000001U +#define PCR_PWM0_CLKM_EN_S 22 + +/** PCR_PARL_IO_CONF_REG register + * PARL_IO configuration register + */ +#define PCR_PARL_IO_CONF_REG (DR_REG_PCR_BASE + 0xac) +/** PCR_PARL_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable parl apb clock + */ +#define PCR_PARL_CLK_EN (BIT(0)) +#define PCR_PARL_CLK_EN_M (PCR_PARL_CLK_EN_V << PCR_PARL_CLK_EN_S) +#define PCR_PARL_CLK_EN_V 0x00000001U +#define PCR_PARL_CLK_EN_S 0 +/** PCR_PARL_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset parl apb reg + */ +#define PCR_PARL_RST_EN (BIT(1)) +#define PCR_PARL_RST_EN_M (PCR_PARL_RST_EN_V << PCR_PARL_RST_EN_S) +#define PCR_PARL_RST_EN_V 0x00000001U +#define PCR_PARL_RST_EN_S 1 +/** PCR_PARL_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset parl module + */ +#define PCR_PARL_READY (BIT(2)) +#define PCR_PARL_READY_M (PCR_PARL_READY_V << PCR_PARL_READY_S) +#define PCR_PARL_READY_V 0x00000001U +#define PCR_PARL_READY_S 2 + +/** PCR_PARL_CLK_RX_CONF_REG register + * PARL_CLK_RX configuration register + */ +#define PCR_PARL_CLK_RX_CONF_REG (DR_REG_PCR_BASE + 0xb0) +/** PCR_PARL_CLK_RX_DIV_NUM : R/W; bitpos: [15:0]; default: 0; + * The integral part of the frequency divider factor of the parl rx clock. + */ +#define PCR_PARL_CLK_RX_DIV_NUM 0x0000FFFFU +#define PCR_PARL_CLK_RX_DIV_NUM_M (PCR_PARL_CLK_RX_DIV_NUM_V << PCR_PARL_CLK_RX_DIV_NUM_S) +#define PCR_PARL_CLK_RX_DIV_NUM_V 0x0000FFFFU +#define PCR_PARL_CLK_RX_DIV_NUM_S 0 +/** PCR_PARL_CLK_RX_SEL : R/W; bitpos: [17:16]; default: 0; + * Configures the clock source of Paraller IO RX + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F240M_CLK + * 3: Use the clock from chip pin + */ +#define PCR_PARL_CLK_RX_SEL 0x00000003U +#define PCR_PARL_CLK_RX_SEL_M (PCR_PARL_CLK_RX_SEL_V << PCR_PARL_CLK_RX_SEL_S) +#define PCR_PARL_CLK_RX_SEL_V 0x00000003U +#define PCR_PARL_CLK_RX_SEL_S 16 +/** PCR_PARL_CLK_RX_EN : R/W; bitpos: [18]; default: 0; + * Set 1 to enable parl rx clock + */ +#define PCR_PARL_CLK_RX_EN (BIT(18)) +#define PCR_PARL_CLK_RX_EN_M (PCR_PARL_CLK_RX_EN_V << PCR_PARL_CLK_RX_EN_S) +#define PCR_PARL_CLK_RX_EN_V 0x00000001U +#define PCR_PARL_CLK_RX_EN_S 18 +/** PCR_PARL_RX_RST_EN : R/W; bitpos: [19]; default: 0; + * Set 1 to reset parl rx module + */ +#define PCR_PARL_RX_RST_EN (BIT(19)) +#define PCR_PARL_RX_RST_EN_M (PCR_PARL_RX_RST_EN_V << PCR_PARL_RX_RST_EN_S) +#define PCR_PARL_RX_RST_EN_V 0x00000001U +#define PCR_PARL_RX_RST_EN_S 19 + +/** PCR_PARL_CLK_TX_CONF_REG register + * PARL_CLK_TX configuration register + */ +#define PCR_PARL_CLK_TX_CONF_REG (DR_REG_PCR_BASE + 0xb4) +/** PCR_PARL_CLK_TX_DIV_NUM : R/W; bitpos: [15:0]; default: 0; + * The integral part of the frequency divider factor of the parl tx clock. + */ +#define PCR_PARL_CLK_TX_DIV_NUM 0x0000FFFFU +#define PCR_PARL_CLK_TX_DIV_NUM_M (PCR_PARL_CLK_TX_DIV_NUM_V << PCR_PARL_CLK_TX_DIV_NUM_S) +#define PCR_PARL_CLK_TX_DIV_NUM_V 0x0000FFFFU +#define PCR_PARL_CLK_TX_DIV_NUM_S 0 +/** PCR_PARL_CLK_TX_SEL : R/W; bitpos: [17:16]; default: 0; + * Configures the clock source of Paraller IO RX + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F240M_CLK + * 3: Use the clock from chip pin + */ +#define PCR_PARL_CLK_TX_SEL 0x00000003U +#define PCR_PARL_CLK_TX_SEL_M (PCR_PARL_CLK_TX_SEL_V << PCR_PARL_CLK_TX_SEL_S) +#define PCR_PARL_CLK_TX_SEL_V 0x00000003U +#define PCR_PARL_CLK_TX_SEL_S 16 +/** PCR_PARL_CLK_TX_EN : R/W; bitpos: [18]; default: 0; + * Set 1 to enable parl tx clock + */ +#define PCR_PARL_CLK_TX_EN (BIT(18)) +#define PCR_PARL_CLK_TX_EN_M (PCR_PARL_CLK_TX_EN_V << PCR_PARL_CLK_TX_EN_S) +#define PCR_PARL_CLK_TX_EN_V 0x00000001U +#define PCR_PARL_CLK_TX_EN_S 18 +/** PCR_PARL_TX_RST_EN : R/W; bitpos: [19]; default: 0; + * Set 1 to reset parl tx module + */ +#define PCR_PARL_TX_RST_EN (BIT(19)) +#define PCR_PARL_TX_RST_EN_M (PCR_PARL_TX_RST_EN_V << PCR_PARL_TX_RST_EN_S) +#define PCR_PARL_TX_RST_EN_V 0x00000001U +#define PCR_PARL_TX_RST_EN_S 19 + +/** PCR_PVT_MONITOR_CONF_REG register + * PVT_MONITOR configuration register + */ +#define PCR_PVT_MONITOR_CONF_REG (DR_REG_PCR_BASE + 0xb8) +/** PCR_PVT_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable apb clock of pvt module + */ +#define PCR_PVT_MONITOR_CLK_EN (BIT(0)) +#define PCR_PVT_MONITOR_CLK_EN_M (PCR_PVT_MONITOR_CLK_EN_V << PCR_PVT_MONITOR_CLK_EN_S) +#define PCR_PVT_MONITOR_CLK_EN_V 0x00000001U +#define PCR_PVT_MONITOR_CLK_EN_S 0 +/** PCR_PVT_MONITOR_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset all pvt monitor module + */ +#define PCR_PVT_MONITOR_RST_EN (BIT(1)) +#define PCR_PVT_MONITOR_RST_EN_M (PCR_PVT_MONITOR_RST_EN_V << PCR_PVT_MONITOR_RST_EN_S) +#define PCR_PVT_MONITOR_RST_EN_V 0x00000001U +#define PCR_PVT_MONITOR_RST_EN_S 1 +/** PCR_PVT_MONITOR_SITE1_CLK_EN : R/W; bitpos: [2]; default: 1; + * Set 1 to enable function clock of modem pvt module + */ +#define PCR_PVT_MONITOR_SITE1_CLK_EN (BIT(2)) +#define PCR_PVT_MONITOR_SITE1_CLK_EN_M (PCR_PVT_MONITOR_SITE1_CLK_EN_V << PCR_PVT_MONITOR_SITE1_CLK_EN_S) +#define PCR_PVT_MONITOR_SITE1_CLK_EN_V 0x00000001U +#define PCR_PVT_MONITOR_SITE1_CLK_EN_S 2 +/** PCR_PVT_MONITOR_SITE2_CLK_EN : R/W; bitpos: [3]; default: 1; + * Set 1 to enable function clock of cpu pvt module + */ +#define PCR_PVT_MONITOR_SITE2_CLK_EN (BIT(3)) +#define PCR_PVT_MONITOR_SITE2_CLK_EN_M (PCR_PVT_MONITOR_SITE2_CLK_EN_V << PCR_PVT_MONITOR_SITE2_CLK_EN_S) +#define PCR_PVT_MONITOR_SITE2_CLK_EN_V 0x00000001U +#define PCR_PVT_MONITOR_SITE2_CLK_EN_S 3 +/** PCR_PVT_MONITOR_SITE3_CLK_EN : R/W; bitpos: [4]; default: 1; + * Set 1 to enable function clock of hp_peri pvt module + */ +#define PCR_PVT_MONITOR_SITE3_CLK_EN (BIT(4)) +#define PCR_PVT_MONITOR_SITE3_CLK_EN_M (PCR_PVT_MONITOR_SITE3_CLK_EN_V << PCR_PVT_MONITOR_SITE3_CLK_EN_S) +#define PCR_PVT_MONITOR_SITE3_CLK_EN_V 0x00000001U +#define PCR_PVT_MONITOR_SITE3_CLK_EN_S 4 + +/** PCR_PVT_MONITOR_FUNC_CLK_CONF_REG register + * PVT_MONITOR function clock configuration register + */ +#define PCR_PVT_MONITOR_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0xbc) +/** PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM : R/W; bitpos: [3:0]; default: 0; + * The integral part of the frequency divider factor of the pvt_monitor function clock. + */ +#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM 0x0000000FU +#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_M (PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_V << PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_S) +#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_V 0x0000000FU +#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_S 0 +/** PCR_PVT_MONITOR_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 1; + * Configures the clock source of PVT MONITOR. + * 0: XTAL_CLK + * 1(default): PLL_F160M_CLK + */ +#define PCR_PVT_MONITOR_FUNC_CLK_SEL (BIT(20)) +#define PCR_PVT_MONITOR_FUNC_CLK_SEL_M (PCR_PVT_MONITOR_FUNC_CLK_SEL_V << PCR_PVT_MONITOR_FUNC_CLK_SEL_S) +#define PCR_PVT_MONITOR_FUNC_CLK_SEL_V 0x00000001U +#define PCR_PVT_MONITOR_FUNC_CLK_SEL_S 20 +/** PCR_PVT_MONITOR_FUNC_CLK_EN : R/W; bitpos: [22]; default: 0; + * Set 1 to enable source clock of pvt sitex + */ +#define PCR_PVT_MONITOR_FUNC_CLK_EN (BIT(22)) +#define PCR_PVT_MONITOR_FUNC_CLK_EN_M (PCR_PVT_MONITOR_FUNC_CLK_EN_V << PCR_PVT_MONITOR_FUNC_CLK_EN_S) +#define PCR_PVT_MONITOR_FUNC_CLK_EN_V 0x00000001U +#define PCR_PVT_MONITOR_FUNC_CLK_EN_S 22 + +/** PCR_GDMA_CONF_REG register + * GDMA configuration register + */ +#define PCR_GDMA_CONF_REG (DR_REG_PCR_BASE + 0xc0) +/** PCR_GDMA_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable gdma clock + */ +#define PCR_GDMA_CLK_EN (BIT(0)) +#define PCR_GDMA_CLK_EN_M (PCR_GDMA_CLK_EN_V << PCR_GDMA_CLK_EN_S) +#define PCR_GDMA_CLK_EN_V 0x00000001U +#define PCR_GDMA_CLK_EN_S 0 +/** PCR_GDMA_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset gdma module + */ +#define PCR_GDMA_RST_EN (BIT(1)) +#define PCR_GDMA_RST_EN_M (PCR_GDMA_RST_EN_V << PCR_GDMA_RST_EN_S) +#define PCR_GDMA_RST_EN_V 0x00000001U +#define PCR_GDMA_RST_EN_S 1 + +/** PCR_SPI2_CONF_REG register + * SPI2 configuration register + */ +#define PCR_SPI2_CONF_REG (DR_REG_PCR_BASE + 0xc4) +/** PCR_SPI2_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable spi2 apb clock + */ +#define PCR_SPI2_CLK_EN (BIT(0)) +#define PCR_SPI2_CLK_EN_M (PCR_SPI2_CLK_EN_V << PCR_SPI2_CLK_EN_S) +#define PCR_SPI2_CLK_EN_V 0x00000001U +#define PCR_SPI2_CLK_EN_S 0 +/** PCR_SPI2_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset spi2 module + */ +#define PCR_SPI2_RST_EN (BIT(1)) +#define PCR_SPI2_RST_EN_M (PCR_SPI2_RST_EN_V << PCR_SPI2_RST_EN_S) +#define PCR_SPI2_RST_EN_V 0x00000001U +#define PCR_SPI2_RST_EN_S 1 +/** PCR_SPI2_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset spi2 module + */ +#define PCR_SPI2_READY (BIT(2)) +#define PCR_SPI2_READY_M (PCR_SPI2_READY_V << PCR_SPI2_READY_S) +#define PCR_SPI2_READY_V 0x00000001U +#define PCR_SPI2_READY_S 2 + +/** PCR_SPI2_CLKM_CONF_REG register + * SPI2_CLKM configuration register + */ +#define PCR_SPI2_CLKM_CONF_REG (DR_REG_PCR_BASE + 0xc8) +/** PCR_SPI2_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the spi2_mst clock. + */ +#define PCR_SPI2_CLKM_DIV_NUM 0x000000FFU +#define PCR_SPI2_CLKM_DIV_NUM_M (PCR_SPI2_CLKM_DIV_NUM_V << PCR_SPI2_CLKM_DIV_NUM_S) +#define PCR_SPI2_CLKM_DIV_NUM_V 0x000000FFU +#define PCR_SPI2_CLKM_DIV_NUM_S 12 +/** PCR_SPI2_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of SPI2. + * 0 (default): XTAL_CLK + * 1: PLL_F48M_CLK + * 2: RC_FAST_CLK + */ +#define PCR_SPI2_CLKM_SEL 0x00000003U +#define PCR_SPI2_CLKM_SEL_M (PCR_SPI2_CLKM_SEL_V << PCR_SPI2_CLKM_SEL_S) +#define PCR_SPI2_CLKM_SEL_V 0x00000003U +#define PCR_SPI2_CLKM_SEL_S 20 +/** PCR_SPI2_CLKM_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable spi2 function clock + */ +#define PCR_SPI2_CLKM_EN (BIT(22)) +#define PCR_SPI2_CLKM_EN_M (PCR_SPI2_CLKM_EN_V << PCR_SPI2_CLKM_EN_S) +#define PCR_SPI2_CLKM_EN_V 0x00000001U +#define PCR_SPI2_CLKM_EN_S 22 + +/** PCR_AES_CONF_REG register + * AES configuration register + */ +#define PCR_AES_CONF_REG (DR_REG_PCR_BASE + 0xcc) +/** PCR_AES_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable aes clock + */ +#define PCR_AES_CLK_EN (BIT(0)) +#define PCR_AES_CLK_EN_M (PCR_AES_CLK_EN_V << PCR_AES_CLK_EN_S) +#define PCR_AES_CLK_EN_V 0x00000001U +#define PCR_AES_CLK_EN_S 0 +/** PCR_AES_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset aes module + */ +#define PCR_AES_RST_EN (BIT(1)) +#define PCR_AES_RST_EN_M (PCR_AES_RST_EN_V << PCR_AES_RST_EN_S) +#define PCR_AES_RST_EN_V 0x00000001U +#define PCR_AES_RST_EN_S 1 +/** PCR_AES_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset aes module + */ +#define PCR_AES_READY (BIT(2)) +#define PCR_AES_READY_M (PCR_AES_READY_V << PCR_AES_READY_S) +#define PCR_AES_READY_V 0x00000001U +#define PCR_AES_READY_S 2 + +/** PCR_SHA_CONF_REG register + * SHA configuration register + */ +#define PCR_SHA_CONF_REG (DR_REG_PCR_BASE + 0xd0) +/** PCR_SHA_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable sha clock + */ +#define PCR_SHA_CLK_EN (BIT(0)) +#define PCR_SHA_CLK_EN_M (PCR_SHA_CLK_EN_V << PCR_SHA_CLK_EN_S) +#define PCR_SHA_CLK_EN_V 0x00000001U +#define PCR_SHA_CLK_EN_S 0 +/** PCR_SHA_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset sha module + */ +#define PCR_SHA_RST_EN (BIT(1)) +#define PCR_SHA_RST_EN_M (PCR_SHA_RST_EN_V << PCR_SHA_RST_EN_S) +#define PCR_SHA_RST_EN_V 0x00000001U +#define PCR_SHA_RST_EN_S 1 +/** PCR_SHA_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset sha module + */ +#define PCR_SHA_READY (BIT(2)) +#define PCR_SHA_READY_M (PCR_SHA_READY_V << PCR_SHA_READY_S) +#define PCR_SHA_READY_V 0x00000001U +#define PCR_SHA_READY_S 2 + +/** PCR_ECC_CONF_REG register + * ECC configuration register + */ +#define PCR_ECC_CONF_REG (DR_REG_PCR_BASE + 0xdc) +/** PCR_ECC_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable ecc clock + */ +#define PCR_ECC_CLK_EN (BIT(0)) +#define PCR_ECC_CLK_EN_M (PCR_ECC_CLK_EN_V << PCR_ECC_CLK_EN_S) +#define PCR_ECC_CLK_EN_V 0x00000001U +#define PCR_ECC_CLK_EN_S 0 +/** PCR_ECC_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset ecc module + */ +#define PCR_ECC_RST_EN (BIT(1)) +#define PCR_ECC_RST_EN_M (PCR_ECC_RST_EN_V << PCR_ECC_RST_EN_S) +#define PCR_ECC_RST_EN_V 0x00000001U +#define PCR_ECC_RST_EN_S 1 +/** PCR_ECC_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset ecc module + */ +#define PCR_ECC_READY (BIT(2)) +#define PCR_ECC_READY_M (PCR_ECC_READY_V << PCR_ECC_READY_S) +#define PCR_ECC_READY_V 0x00000001U +#define PCR_ECC_READY_S 2 + +/** PCR_ECC_MEM_LP_CTRL_REG register + * HP CORE0 & HP CORE1 memory power control register + */ +#define PCR_ECC_MEM_LP_CTRL_REG (DR_REG_PCR_BASE + 0xe0) +/** PCR_ECC_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 2; + * Configures ecc memory low power mode in low power stage. + * 0: deep sleep + * 1: light sleep + * 2(default): shut down + * 3: disable low power stage + */ +#define PCR_ECC_MEM_LP_MODE 0x00000003U +#define PCR_ECC_MEM_LP_MODE_M (PCR_ECC_MEM_LP_MODE_V << PCR_ECC_MEM_LP_MODE_S) +#define PCR_ECC_MEM_LP_MODE_V 0x00000003U +#define PCR_ECC_MEM_LP_MODE_S 0 +/** PCR_ECC_MEM_LP_EN : R/W; bitpos: [2]; default: 0; + * Set this bit to power down ecc memory. + */ +#define PCR_ECC_MEM_LP_EN (BIT(2)) +#define PCR_ECC_MEM_LP_EN_M (PCR_ECC_MEM_LP_EN_V << PCR_ECC_MEM_LP_EN_S) +#define PCR_ECC_MEM_LP_EN_V 0x00000001U +#define PCR_ECC_MEM_LP_EN_S 2 +/** PCR_ECC_MEM_FORCE_CTRL : R/W; bitpos: [3]; default: 0; + * Set this bit to force software control ecc memory, disable hardware control. + */ +#define PCR_ECC_MEM_FORCE_CTRL (BIT(3)) +#define PCR_ECC_MEM_FORCE_CTRL_M (PCR_ECC_MEM_FORCE_CTRL_V << PCR_ECC_MEM_FORCE_CTRL_S) +#define PCR_ECC_MEM_FORCE_CTRL_V 0x00000001U +#define PCR_ECC_MEM_FORCE_CTRL_S 3 + +/** PCR_HMAC_CONF_REG register + * HMAC configuration register + */ +#define PCR_HMAC_CONF_REG (DR_REG_PCR_BASE + 0xe8) +/** PCR_HMAC_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable hmac clock + */ +#define PCR_HMAC_CLK_EN (BIT(0)) +#define PCR_HMAC_CLK_EN_M (PCR_HMAC_CLK_EN_V << PCR_HMAC_CLK_EN_S) +#define PCR_HMAC_CLK_EN_V 0x00000001U +#define PCR_HMAC_CLK_EN_S 0 +/** PCR_HMAC_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset hmac module + */ +#define PCR_HMAC_RST_EN (BIT(1)) +#define PCR_HMAC_RST_EN_M (PCR_HMAC_RST_EN_V << PCR_HMAC_RST_EN_S) +#define PCR_HMAC_RST_EN_V 0x00000001U +#define PCR_HMAC_RST_EN_S 1 +/** PCR_HMAC_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset hmac module + */ +#define PCR_HMAC_READY (BIT(2)) +#define PCR_HMAC_READY_M (PCR_HMAC_READY_V << PCR_HMAC_READY_S) +#define PCR_HMAC_READY_V 0x00000001U +#define PCR_HMAC_READY_S 2 + +/** PCR_ECDSA_CONF_REG register + * ECDSA configuration register + */ +#define PCR_ECDSA_CONF_REG (DR_REG_PCR_BASE + 0xec) +/** PCR_ECDSA_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable ecdsa clock + */ +#define PCR_ECDSA_CLK_EN (BIT(0)) +#define PCR_ECDSA_CLK_EN_M (PCR_ECDSA_CLK_EN_V << PCR_ECDSA_CLK_EN_S) +#define PCR_ECDSA_CLK_EN_V 0x00000001U +#define PCR_ECDSA_CLK_EN_S 0 +/** PCR_ECDSA_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset ecdsa module + */ +#define PCR_ECDSA_RST_EN (BIT(1)) +#define PCR_ECDSA_RST_EN_M (PCR_ECDSA_RST_EN_V << PCR_ECDSA_RST_EN_S) +#define PCR_ECDSA_RST_EN_V 0x00000001U +#define PCR_ECDSA_RST_EN_S 1 +/** PCR_ECDSA_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset ecdsa module + */ +#define PCR_ECDSA_READY (BIT(2)) +#define PCR_ECDSA_READY_M (PCR_ECDSA_READY_V << PCR_ECDSA_READY_S) +#define PCR_ECDSA_READY_V 0x00000001U +#define PCR_ECDSA_READY_S 2 + +/** PCR_IOMUX_CONF_REG register + * IOMUX configuration register + */ +#define PCR_IOMUX_CONF_REG (DR_REG_PCR_BASE + 0xf0) +/** PCR_IOMUX_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable iomux apb clock + */ +#define PCR_IOMUX_CLK_EN (BIT(0)) +#define PCR_IOMUX_CLK_EN_M (PCR_IOMUX_CLK_EN_V << PCR_IOMUX_CLK_EN_S) +#define PCR_IOMUX_CLK_EN_V 0x00000001U +#define PCR_IOMUX_CLK_EN_S 0 +/** PCR_IOMUX_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset iomux module + */ +#define PCR_IOMUX_RST_EN (BIT(1)) +#define PCR_IOMUX_RST_EN_M (PCR_IOMUX_RST_EN_V << PCR_IOMUX_RST_EN_S) +#define PCR_IOMUX_RST_EN_V 0x00000001U +#define PCR_IOMUX_RST_EN_S 1 + +/** PCR_IOMUX_CLK_CONF_REG register + * IOMUX_CLK configuration register + */ +#define PCR_IOMUX_CLK_CONF_REG (DR_REG_PCR_BASE + 0xf4) +/** PCR_IOMUX_FUNC_CLK_SEL : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of IO MUX. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK + */ +#define PCR_IOMUX_FUNC_CLK_SEL 0x00000003U +#define PCR_IOMUX_FUNC_CLK_SEL_M (PCR_IOMUX_FUNC_CLK_SEL_V << PCR_IOMUX_FUNC_CLK_SEL_S) +#define PCR_IOMUX_FUNC_CLK_SEL_V 0x00000003U +#define PCR_IOMUX_FUNC_CLK_SEL_S 20 +/** PCR_IOMUX_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable iomux function clock + */ +#define PCR_IOMUX_FUNC_CLK_EN (BIT(22)) +#define PCR_IOMUX_FUNC_CLK_EN_M (PCR_IOMUX_FUNC_CLK_EN_V << PCR_IOMUX_FUNC_CLK_EN_S) +#define PCR_IOMUX_FUNC_CLK_EN_V 0x00000001U +#define PCR_IOMUX_FUNC_CLK_EN_S 22 + +/** PCR_REGDMA_CONF_REG register + * REGDMA configuration register + */ +#define PCR_REGDMA_CONF_REG (DR_REG_PCR_BASE + 0xf8) +/** PCR_REGDMA_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable regdma clock + */ +#define PCR_REGDMA_CLK_EN (BIT(0)) +#define PCR_REGDMA_CLK_EN_M (PCR_REGDMA_CLK_EN_V << PCR_REGDMA_CLK_EN_S) +#define PCR_REGDMA_CLK_EN_V 0x00000001U +#define PCR_REGDMA_CLK_EN_S 0 +/** PCR_REGDMA_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset regdma module + */ +#define PCR_REGDMA_RST_EN (BIT(1)) +#define PCR_REGDMA_RST_EN_M (PCR_REGDMA_RST_EN_V << PCR_REGDMA_RST_EN_S) +#define PCR_REGDMA_RST_EN_V 0x00000001U +#define PCR_REGDMA_RST_EN_S 1 +/** PCR_REGDMA_MAC_CLK_EN : R/W; bitpos: [2]; default: 1; + * Set 1 to enable modem control regdma clock relate logic clock + */ +#define PCR_REGDMA_MAC_CLK_EN (BIT(2)) +#define PCR_REGDMA_MAC_CLK_EN_M (PCR_REGDMA_MAC_CLK_EN_V << PCR_REGDMA_MAC_CLK_EN_S) +#define PCR_REGDMA_MAC_CLK_EN_V 0x00000001U +#define PCR_REGDMA_MAC_CLK_EN_S 2 + +/** PCR_TRACE_CONF_REG register + * TRACE configuration register + */ +#define PCR_TRACE_CONF_REG (DR_REG_PCR_BASE + 0xfc) +/** PCR_TRACE_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable core0 trace clock + */ +#define PCR_TRACE_CLK_EN (BIT(0)) +#define PCR_TRACE_CLK_EN_M (PCR_TRACE_CLK_EN_V << PCR_TRACE_CLK_EN_S) +#define PCR_TRACE_CLK_EN_V 0x00000001U +#define PCR_TRACE_CLK_EN_S 0 +/** PCR_TRACE_RST_EN : R/W; bitpos: [1]; default: 1; + * Set 1 to reset core0 trace module + */ +#define PCR_TRACE_RST_EN (BIT(1)) +#define PCR_TRACE_RST_EN_M (PCR_TRACE_RST_EN_V << PCR_TRACE_RST_EN_S) +#define PCR_TRACE_RST_EN_V 0x00000001U +#define PCR_TRACE_RST_EN_S 1 +/** PCR_TRACE1_CLK_EN : R/W; bitpos: [2]; default: 0; + * Set 1 to enable core1 trace clock + */ +#define PCR_TRACE1_CLK_EN (BIT(2)) +#define PCR_TRACE1_CLK_EN_M (PCR_TRACE1_CLK_EN_V << PCR_TRACE1_CLK_EN_S) +#define PCR_TRACE1_CLK_EN_V 0x00000001U +#define PCR_TRACE1_CLK_EN_S 2 +/** PCR_TRACE1_RST_EN : R/W; bitpos: [3]; default: 1; + * Set 1 to reset core1 trace module + */ +#define PCR_TRACE1_RST_EN (BIT(3)) +#define PCR_TRACE1_RST_EN_M (PCR_TRACE1_RST_EN_V << PCR_TRACE1_RST_EN_S) +#define PCR_TRACE1_RST_EN_V 0x00000001U +#define PCR_TRACE1_RST_EN_S 3 + +/** PCR_ASSIST_CONF_REG register + * ASSIST configuration register + */ +#define PCR_ASSIST_CONF_REG (DR_REG_PCR_BASE + 0x100) +/** PCR_ASSIST_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable core0 assist clock + */ +#define PCR_ASSIST_CLK_EN (BIT(0)) +#define PCR_ASSIST_CLK_EN_M (PCR_ASSIST_CLK_EN_V << PCR_ASSIST_CLK_EN_S) +#define PCR_ASSIST_CLK_EN_V 0x00000001U +#define PCR_ASSIST_CLK_EN_S 0 +/** PCR_ASSIST_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset core0 assist module + */ +#define PCR_ASSIST_RST_EN (BIT(1)) +#define PCR_ASSIST_RST_EN_M (PCR_ASSIST_RST_EN_V << PCR_ASSIST_RST_EN_S) +#define PCR_ASSIST_RST_EN_V 0x00000001U +#define PCR_ASSIST_RST_EN_S 1 +/** PCR_ASSIST1_CLK_EN : R/W; bitpos: [2]; default: 0; + * Set 1 to enable core1 assist clock + */ +#define PCR_ASSIST1_CLK_EN (BIT(2)) +#define PCR_ASSIST1_CLK_EN_M (PCR_ASSIST1_CLK_EN_V << PCR_ASSIST1_CLK_EN_S) +#define PCR_ASSIST1_CLK_EN_V 0x00000001U +#define PCR_ASSIST1_CLK_EN_S 2 +/** PCR_ASSIST1_RST_EN : R/W; bitpos: [3]; default: 1; + * Set 1 to reset core1 assist module + */ +#define PCR_ASSIST1_RST_EN (BIT(3)) +#define PCR_ASSIST1_RST_EN_M (PCR_ASSIST1_RST_EN_V << PCR_ASSIST1_RST_EN_S) +#define PCR_ASSIST1_RST_EN_V 0x00000001U +#define PCR_ASSIST1_RST_EN_S 3 + +/** PCR_CACHE_CONF_REG register + * CACHE configuration register + */ +#define PCR_CACHE_CONF_REG (DR_REG_PCR_BASE + 0x104) +/** PCR_ICACHE0_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable icache0 clock + */ +#define PCR_ICACHE0_CLK_EN (BIT(0)) +#define PCR_ICACHE0_CLK_EN_M (PCR_ICACHE0_CLK_EN_V << PCR_ICACHE0_CLK_EN_S) +#define PCR_ICACHE0_CLK_EN_V 0x00000001U +#define PCR_ICACHE0_CLK_EN_S 0 +/** PCR_ICACHE1_CLK_EN : R/W; bitpos: [1]; default: 1; + * Set 1 to enable icache1 clock + */ +#define PCR_ICACHE1_CLK_EN (BIT(1)) +#define PCR_ICACHE1_CLK_EN_M (PCR_ICACHE1_CLK_EN_V << PCR_ICACHE1_CLK_EN_S) +#define PCR_ICACHE1_CLK_EN_V 0x00000001U +#define PCR_ICACHE1_CLK_EN_S 1 +/** PCR_DCACHE_CLK_EN : R/W; bitpos: [2]; default: 1; + * Set 1 to enable dcache clock + */ +#define PCR_DCACHE_CLK_EN (BIT(2)) +#define PCR_DCACHE_CLK_EN_M (PCR_DCACHE_CLK_EN_V << PCR_DCACHE_CLK_EN_S) +#define PCR_DCACHE_CLK_EN_V 0x00000001U +#define PCR_DCACHE_CLK_EN_S 2 +/** PCR_ICACHE0_RST_EN : R/W; bitpos: [3]; default: 0; + * Set 1 to reset icache0 module + */ +#define PCR_ICACHE0_RST_EN (BIT(3)) +#define PCR_ICACHE0_RST_EN_M (PCR_ICACHE0_RST_EN_V << PCR_ICACHE0_RST_EN_S) +#define PCR_ICACHE0_RST_EN_V 0x00000001U +#define PCR_ICACHE0_RST_EN_S 3 +/** PCR_ICACHE1_RST_EN : R/W; bitpos: [4]; default: 0; + * Set 1 to reset icache1 module + */ +#define PCR_ICACHE1_RST_EN (BIT(4)) +#define PCR_ICACHE1_RST_EN_M (PCR_ICACHE1_RST_EN_V << PCR_ICACHE1_RST_EN_S) +#define PCR_ICACHE1_RST_EN_V 0x00000001U +#define PCR_ICACHE1_RST_EN_S 4 +/** PCR_DCACHE_RST_EN : R/W; bitpos: [5]; default: 0; + * Set 1 to reset dcache module + */ +#define PCR_DCACHE_RST_EN (BIT(5)) +#define PCR_DCACHE_RST_EN_M (PCR_DCACHE_RST_EN_V << PCR_DCACHE_RST_EN_S) +#define PCR_DCACHE_RST_EN_V 0x00000001U +#define PCR_DCACHE_RST_EN_S 5 +/** PCR_CACHE_RST_EN : R/W; bitpos: [8]; default: 0; + * Set 1 to reset total cache module + */ +#define PCR_CACHE_RST_EN (BIT(8)) +#define PCR_CACHE_RST_EN_M (PCR_CACHE_RST_EN_V << PCR_CACHE_RST_EN_S) +#define PCR_CACHE_RST_EN_V 0x00000001U +#define PCR_CACHE_RST_EN_S 8 + +/** PCR_CACHE_MEM_LP_CTRL_REG register + * HP CORE0 & HP CORE1 memory power control register + */ +#define PCR_CACHE_MEM_LP_CTRL_REG (DR_REG_PCR_BASE + 0x108) +/** PCR_L1_CACHE_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures l1_cache memory low power mode in low power stage. + * 0(default): deep sleep + * 1: light sleep + * 2: shut down + * 3: disable low power stage + */ +#define PCR_L1_CACHE_MEM_LP_MODE 0x00000003U +#define PCR_L1_CACHE_MEM_LP_MODE_M (PCR_L1_CACHE_MEM_LP_MODE_V << PCR_L1_CACHE_MEM_LP_MODE_S) +#define PCR_L1_CACHE_MEM_LP_MODE_V 0x00000003U +#define PCR_L1_CACHE_MEM_LP_MODE_S 0 +/** PCR_L1_CACHE_MEM_LP_EN : R/W; bitpos: [2]; default: 0; + * Set this bit to power down l1_cache memory. + */ +#define PCR_L1_CACHE_MEM_LP_EN (BIT(2)) +#define PCR_L1_CACHE_MEM_LP_EN_M (PCR_L1_CACHE_MEM_LP_EN_V << PCR_L1_CACHE_MEM_LP_EN_S) +#define PCR_L1_CACHE_MEM_LP_EN_V 0x00000001U +#define PCR_L1_CACHE_MEM_LP_EN_S 2 +/** PCR_L1_CACHE_MEM_FORCE_CTRL : R/W; bitpos: [3]; default: 0; + * Set this bit to force software control l1_cache memory, disable hardware control. + */ +#define PCR_L1_CACHE_MEM_FORCE_CTRL (BIT(3)) +#define PCR_L1_CACHE_MEM_FORCE_CTRL_M (PCR_L1_CACHE_MEM_FORCE_CTRL_V << PCR_L1_CACHE_MEM_FORCE_CTRL_S) +#define PCR_L1_CACHE_MEM_FORCE_CTRL_V 0x00000001U +#define PCR_L1_CACHE_MEM_FORCE_CTRL_S 3 + +/** PCR_MODEM_CONF_REG register + * MODEM_APB configuration register + */ +#define PCR_MODEM_CONF_REG (DR_REG_PCR_BASE + 0x10c) +/** PCR_MODEM_CLK_SEL : R/W; bitpos: [0]; default: 0; + * xxxx + */ +#define PCR_MODEM_CLK_SEL (BIT(0)) +#define PCR_MODEM_CLK_SEL_M (PCR_MODEM_CLK_SEL_V << PCR_MODEM_CLK_SEL_S) +#define PCR_MODEM_CLK_SEL_V 0x00000001U +#define PCR_MODEM_CLK_SEL_S 0 +/** PCR_MODEM_CLK_EN : R/W; bitpos: [1]; default: 1; + * xxxx + */ +#define PCR_MODEM_CLK_EN (BIT(1)) +#define PCR_MODEM_CLK_EN_M (PCR_MODEM_CLK_EN_V << PCR_MODEM_CLK_EN_S) +#define PCR_MODEM_CLK_EN_V 0x00000001U +#define PCR_MODEM_CLK_EN_S 1 +/** PCR_MODEM_RST_EN : R/W; bitpos: [2]; default: 0; + * Set this file as 1 to reset modem-subsystem. + */ +#define PCR_MODEM_RST_EN (BIT(2)) +#define PCR_MODEM_RST_EN_M (PCR_MODEM_RST_EN_V << PCR_MODEM_RST_EN_S) +#define PCR_MODEM_RST_EN_V 0x00000001U +#define PCR_MODEM_RST_EN_S 2 + +/** PCR_TIMEOUT_CONF_REG register + * TIMEOUT configuration register + */ +#define PCR_TIMEOUT_CONF_REG (DR_REG_PCR_BASE + 0x110) +/** PCR_CPU_TIMEOUT_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset cpu_peri timeout module + */ +#define PCR_CPU_TIMEOUT_RST_EN (BIT(1)) +#define PCR_CPU_TIMEOUT_RST_EN_M (PCR_CPU_TIMEOUT_RST_EN_V << PCR_CPU_TIMEOUT_RST_EN_S) +#define PCR_CPU_TIMEOUT_RST_EN_V 0x00000001U +#define PCR_CPU_TIMEOUT_RST_EN_S 1 +/** PCR_HP_TIMEOUT_RST_EN : R/W; bitpos: [2]; default: 0; + * Set 1 to reset hp_peri timeout module and hp_modem timeout module + */ +#define PCR_HP_TIMEOUT_RST_EN (BIT(2)) +#define PCR_HP_TIMEOUT_RST_EN_M (PCR_HP_TIMEOUT_RST_EN_V << PCR_HP_TIMEOUT_RST_EN_S) +#define PCR_HP_TIMEOUT_RST_EN_V 0x00000001U +#define PCR_HP_TIMEOUT_RST_EN_S 2 + +/** PCR_SYSCLK_CONF_REG register + * SYSCLK configuration register + */ +#define PCR_SYSCLK_CONF_REG (DR_REG_PCR_BASE + 0x114) +/** PCR_SOC_CLK_SEL : R/W; bitpos: [17:16]; default: 0; + * Configures to select the clock source of HP_ROOT_CLK. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F160M_CLK + * 2: PLL_F240M_CLK + */ +#define PCR_SOC_CLK_SEL 0x00000003U +#define PCR_SOC_CLK_SEL_M (PCR_SOC_CLK_SEL_V << PCR_SOC_CLK_SEL_S) +#define PCR_SOC_CLK_SEL_V 0x00000003U +#define PCR_SOC_CLK_SEL_S 16 +/** PCR_CLK_XTAL_FREQ : HRO; bitpos: [30:24]; default: 32; + * This field indicates the frequency(MHz) of XTAL. + */ +#define PCR_CLK_XTAL_FREQ 0x0000007FU +#define PCR_CLK_XTAL_FREQ_M (PCR_CLK_XTAL_FREQ_V << PCR_CLK_XTAL_FREQ_S) +#define PCR_CLK_XTAL_FREQ_V 0x0000007FU +#define PCR_CLK_XTAL_FREQ_S 24 +/** PCR_CPU_DBGMD_CLK_EN : R/W; bitpos: [31]; default: 1; + * This field indicates if cpu debug mode clock is enable. 0: disable, 1: + * enable(default). + */ +#define PCR_CPU_DBGMD_CLK_EN (BIT(31)) +#define PCR_CPU_DBGMD_CLK_EN_M (PCR_CPU_DBGMD_CLK_EN_V << PCR_CPU_DBGMD_CLK_EN_S) +#define PCR_CPU_DBGMD_CLK_EN_V 0x00000001U +#define PCR_CPU_DBGMD_CLK_EN_S 31 + +/** PCR_CPU_WAITI_CONF_REG register + * CPU_WAITI configuration register + */ +#define PCR_CPU_WAITI_CONF_REG (DR_REG_PCR_BASE + 0x118) +/** PCR_CPU1_WAIT_MODE_FORCE_ON : R/W; bitpos: [3]; default: 1; + * Set 1 to force cpu1_waiti_clk enable. + */ +#define PCR_CPU1_WAIT_MODE_FORCE_ON (BIT(3)) +#define PCR_CPU1_WAIT_MODE_FORCE_ON_M (PCR_CPU1_WAIT_MODE_FORCE_ON_V << PCR_CPU1_WAIT_MODE_FORCE_ON_S) +#define PCR_CPU1_WAIT_MODE_FORCE_ON_V 0x00000001U +#define PCR_CPU1_WAIT_MODE_FORCE_ON_S 3 +/** PCR_CPU0_WAIT_MODE_FORCE_ON : R/W; bitpos: [4]; default: 1; + * Set 1 to force cpu0_waiti_clk enable. + */ +#define PCR_CPU0_WAIT_MODE_FORCE_ON (BIT(4)) +#define PCR_CPU0_WAIT_MODE_FORCE_ON_M (PCR_CPU0_WAIT_MODE_FORCE_ON_V << PCR_CPU0_WAIT_MODE_FORCE_ON_S) +#define PCR_CPU0_WAIT_MODE_FORCE_ON_V 0x00000001U +#define PCR_CPU0_WAIT_MODE_FORCE_ON_S 4 +/** PCR_CPU_WAITI_DELAY_NUM : R/W; bitpos: [8:5]; default: 0; + * This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk + * will close + */ +#define PCR_CPU_WAITI_DELAY_NUM 0x0000000FU +#define PCR_CPU_WAITI_DELAY_NUM_M (PCR_CPU_WAITI_DELAY_NUM_V << PCR_CPU_WAITI_DELAY_NUM_S) +#define PCR_CPU_WAITI_DELAY_NUM_V 0x0000000FU +#define PCR_CPU_WAITI_DELAY_NUM_S 5 +/** PCR_CPU_WFI_DECREASE_EN : R/W; bitpos: [9]; default: 0; + * Set 1 to enable cpu freq decrease to ahb freq when cpu enter waiti mode + */ +#define PCR_CPU_WFI_DECREASE_EN (BIT(9)) +#define PCR_CPU_WFI_DECREASE_EN_M (PCR_CPU_WFI_DECREASE_EN_V << PCR_CPU_WFI_DECREASE_EN_S) +#define PCR_CPU_WFI_DECREASE_EN_V 0x00000001U +#define PCR_CPU_WFI_DECREASE_EN_S 9 + +/** PCR_CPU_FREQ_CONF_REG register + * CPU_FREQ configuration register + */ +#define PCR_CPU_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x11c) +/** PCR_CPU_DIV_NUM : R/W; bitpos: [7:0]; default: 0; + * Set this field to generate clk_cpu derived by clk_hproot. The clk_cpu is + * div1(default)/div2/div4 of clk_hproot. This field is only available for low-speed + * clock-source such as XTAL/FOSC, and should be used together with PCR_AHB_DIV_NUM. + */ +#define PCR_CPU_DIV_NUM 0x000000FFU +#define PCR_CPU_DIV_NUM_M (PCR_CPU_DIV_NUM_V << PCR_CPU_DIV_NUM_S) +#define PCR_CPU_DIV_NUM_V 0x000000FFU +#define PCR_CPU_DIV_NUM_S 0 + +/** PCR_AHB_FREQ_CONF_REG register + * AHB_FREQ configuration register + */ +#define PCR_AHB_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x120) +/** PCR_AHB_DIV_NUM : R/W; bitpos: [7:0]; default: 0; + * Set this field to generate clk_ahb derived by clk_hproot. The clk_ahb is + * div1(default)/div2/div4/div8 of clk_hproot. This field is only available for + * low-speed clock-source such as XTAL/FOSC, and should be used together with + * PCR_CPU_DIV_NUM. + */ +#define PCR_AHB_DIV_NUM 0x000000FFU +#define PCR_AHB_DIV_NUM_M (PCR_AHB_DIV_NUM_V << PCR_AHB_DIV_NUM_S) +#define PCR_AHB_DIV_NUM_V 0x000000FFU +#define PCR_AHB_DIV_NUM_S 0 + +/** PCR_APB_FREQ_CONF_REG register + * APB_FREQ configuration register + */ +#define PCR_APB_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x124) +/** PCR_APB_DECREASE_DIV_NUM : R/W; bitpos: [7:0]; default: 0; + * If this field's value is grater than PCR_APB_DIV_NUM, the clk_apb will be + * automatically down to clk_apb_decrease only when no access is on apb-bus, and will + * recover to the previous frequency when a new access appears on apb-bus. Set as one + * within (0,1,3) to set clk_apb_decrease as div1/div2/div4(default) of clk_ahb. Note + * that enable this function will reduce performance. Users can set this field as zero + * to disable the auto-decrease-apb-freq function. By default, this function is + * disable. + */ +#define PCR_APB_DECREASE_DIV_NUM 0x000000FFU +#define PCR_APB_DECREASE_DIV_NUM_M (PCR_APB_DECREASE_DIV_NUM_V << PCR_APB_DECREASE_DIV_NUM_S) +#define PCR_APB_DECREASE_DIV_NUM_V 0x000000FFU +#define PCR_APB_DECREASE_DIV_NUM_S 0 +/** PCR_APB_DIV_NUM : R/W; bitpos: [15:8]; default: 0; + * Set as one within (0,1,3) to generate clk_apb derived by clk_ahb. The clk_apb is + * div1(default)/div2/div4 of clk_ahb. + */ +#define PCR_APB_DIV_NUM 0x000000FFU +#define PCR_APB_DIV_NUM_M (PCR_APB_DIV_NUM_V << PCR_APB_DIV_NUM_S) +#define PCR_APB_DIV_NUM_V 0x000000FFU +#define PCR_APB_DIV_NUM_S 8 + +/** PCR_SYSCLK_FREQ_QUERY_0_REG register + * SYSCLK frequency query 0 register + */ +#define PCR_SYSCLK_FREQ_QUERY_0_REG (DR_REG_PCR_BASE + 0x128) +/** PCR_FOSC_FREQ : HRO; bitpos: [7:0]; default: 8; + * This field indicates the frequency(MHz) of FOSC. + */ +#define PCR_FOSC_FREQ 0x000000FFU +#define PCR_FOSC_FREQ_M (PCR_FOSC_FREQ_V << PCR_FOSC_FREQ_S) +#define PCR_FOSC_FREQ_V 0x000000FFU +#define PCR_FOSC_FREQ_S 0 +/** PCR_PLL_FREQ : HRO; bitpos: [17:8]; default: 96; + * This field indicates the frequency(MHz) of SPLL. + */ +#define PCR_PLL_FREQ 0x000003FFU +#define PCR_PLL_FREQ_M (PCR_PLL_FREQ_V << PCR_PLL_FREQ_S) +#define PCR_PLL_FREQ_V 0x000003FFU +#define PCR_PLL_FREQ_S 8 + +/** PCR_PLL_DIV_CLK_EN_REG register + * SPLL DIV clock-gating configuration register + */ +#define PCR_PLL_DIV_CLK_EN_REG (DR_REG_PCR_BASE + 0x12c) +/** PCR_PLL_96M_CLK_EN : R/W; bitpos: [0]; default: 1; + * This field is used to open 96 MHz clock derived from SPLL 96M. 0: close, 1: + * open(default). Only available when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_96M_CLK_EN (BIT(0)) +#define PCR_PLL_96M_CLK_EN_M (PCR_PLL_96M_CLK_EN_V << PCR_PLL_96M_CLK_EN_S) +#define PCR_PLL_96M_CLK_EN_V 0x00000001U +#define PCR_PLL_96M_CLK_EN_S 0 +/** PCR_PLL_64M_CLK_EN : R/W; bitpos: [1]; default: 1; + * This field is used to open 64 MHz clock derived from SPLL 64M. 0: close, 1: + * open(default). Only available when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_64M_CLK_EN (BIT(1)) +#define PCR_PLL_64M_CLK_EN_M (PCR_PLL_64M_CLK_EN_V << PCR_PLL_64M_CLK_EN_S) +#define PCR_PLL_64M_CLK_EN_V 0x00000001U +#define PCR_PLL_64M_CLK_EN_S 1 +/** PCR_PLL_48M_CLK_EN : R/W; bitpos: [2]; default: 1; + * This field is used to open 48 MHz clock (div2 of SPLL) derived from SPLL 96M. 0: + * close, 1: open(default). Only available when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_48M_CLK_EN (BIT(2)) +#define PCR_PLL_48M_CLK_EN_M (PCR_PLL_48M_CLK_EN_V << PCR_PLL_48M_CLK_EN_S) +#define PCR_PLL_48M_CLK_EN_V 0x00000001U +#define PCR_PLL_48M_CLK_EN_S 2 +/** PCR_PLL_32M_CLK_EN : R/W; bitpos: [3]; default: 1; + * This field is used to open 32 MHz clock (div2 of SPLL) derived from SPLL 64M. 0: + * close, 1: open(default). Only available when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_32M_CLK_EN (BIT(3)) +#define PCR_PLL_32M_CLK_EN_M (PCR_PLL_32M_CLK_EN_V << PCR_PLL_32M_CLK_EN_S) +#define PCR_PLL_32M_CLK_EN_V 0x00000001U +#define PCR_PLL_32M_CLK_EN_S 3 +/** PCR_PLL_16M_CLK_EN : R/W; bitpos: [4]; default: 1; + * This field is used to open 16 MHz clock (div6 of SPLL) derived from SPLL 96M. 0: + * close, 1: open(default). Only available when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_16M_CLK_EN (BIT(4)) +#define PCR_PLL_16M_CLK_EN_M (PCR_PLL_16M_CLK_EN_V << PCR_PLL_16M_CLK_EN_S) +#define PCR_PLL_16M_CLK_EN_V 0x00000001U +#define PCR_PLL_16M_CLK_EN_S 4 +/** PCR_PLL_8M_CLK_EN : R/W; bitpos: [5]; default: 1; + * This field is used to open 8 MHz clock (div12 of SPLL) derived from SPLL 96M. 0: + * close, 1: open(default). Only available when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_8M_CLK_EN (BIT(5)) +#define PCR_PLL_8M_CLK_EN_M (PCR_PLL_8M_CLK_EN_V << PCR_PLL_8M_CLK_EN_S) +#define PCR_PLL_8M_CLK_EN_V 0x00000001U +#define PCR_PLL_8M_CLK_EN_S 5 + +/** PCR_CTRL_CLK_OUT_EN_REG register + * CLK_OUT_EN configuration register + */ +#define PCR_CTRL_CLK_OUT_EN_REG (DR_REG_PCR_BASE + 0x130) +/** PCR_CLK8_OEN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable 8m clock + */ +#define PCR_CLK8_OEN (BIT(0)) +#define PCR_CLK8_OEN_M (PCR_CLK8_OEN_V << PCR_CLK8_OEN_S) +#define PCR_CLK8_OEN_V 0x00000001U +#define PCR_CLK8_OEN_S 0 +/** PCR_CLK16_OEN : R/W; bitpos: [1]; default: 1; + * Set 1 to enable 16m clock + */ +#define PCR_CLK16_OEN (BIT(1)) +#define PCR_CLK16_OEN_M (PCR_CLK16_OEN_V << PCR_CLK16_OEN_S) +#define PCR_CLK16_OEN_V 0x00000001U +#define PCR_CLK16_OEN_S 1 +/** PCR_CLK32_OEN : R/W; bitpos: [2]; default: 1; + * Set 1 to enable 32m clock + */ +#define PCR_CLK32_OEN (BIT(2)) +#define PCR_CLK32_OEN_M (PCR_CLK32_OEN_V << PCR_CLK32_OEN_S) +#define PCR_CLK32_OEN_V 0x00000001U +#define PCR_CLK32_OEN_S 2 +/** PCR_CLK_ADC_INF_OEN : R/W; bitpos: [3]; default: 1; + * Reserved + */ +#define PCR_CLK_ADC_INF_OEN (BIT(3)) +#define PCR_CLK_ADC_INF_OEN_M (PCR_CLK_ADC_INF_OEN_V << PCR_CLK_ADC_INF_OEN_S) +#define PCR_CLK_ADC_INF_OEN_V 0x00000001U +#define PCR_CLK_ADC_INF_OEN_S 3 +/** PCR_CLK_DFM_INF_OEN : R/W; bitpos: [4]; default: 1; + * Reserved + */ +#define PCR_CLK_DFM_INF_OEN (BIT(4)) +#define PCR_CLK_DFM_INF_OEN_M (PCR_CLK_DFM_INF_OEN_V << PCR_CLK_DFM_INF_OEN_S) +#define PCR_CLK_DFM_INF_OEN_V 0x00000001U +#define PCR_CLK_DFM_INF_OEN_S 4 +/** PCR_CLK_SDM_MOD_OEN : R/W; bitpos: [5]; default: 1; + * Reserved + */ +#define PCR_CLK_SDM_MOD_OEN (BIT(5)) +#define PCR_CLK_SDM_MOD_OEN_M (PCR_CLK_SDM_MOD_OEN_V << PCR_CLK_SDM_MOD_OEN_S) +#define PCR_CLK_SDM_MOD_OEN_V 0x00000001U +#define PCR_CLK_SDM_MOD_OEN_S 5 +/** PCR_CLK_XTAL_OEN : R/W; bitpos: [6]; default: 1; + * Set 1 to enable xtal clock + */ +#define PCR_CLK_XTAL_OEN (BIT(6)) +#define PCR_CLK_XTAL_OEN_M (PCR_CLK_XTAL_OEN_V << PCR_CLK_XTAL_OEN_S) +#define PCR_CLK_XTAL_OEN_V 0x00000001U +#define PCR_CLK_XTAL_OEN_S 6 + +/** PCR_TIMG_CALI_CLK_CONF_REG register + * timergrout calibrate clock configuration register + */ +#define PCR_TIMG_CALI_CLK_CONF_REG (DR_REG_PCR_BASE + 0x134) +/** PCR_TIMG_CALI_CLK_SEL : R/W; bitpos: [2:0]; default: 0; + * Configures the 32KHz clock for TIMER_GROUP. + * 0 (default): RC32K_CLK + * 1: XTAL32K_CLK + * 2: OSC_SLOW_CLK + * 3: RC_SLOW_CLK + * 4: TIMG_SECURE_CLK + */ +#define PCR_TIMG_CALI_CLK_SEL 0x00000007U +#define PCR_TIMG_CALI_CLK_SEL_M (PCR_TIMG_CALI_CLK_SEL_V << PCR_TIMG_CALI_CLK_SEL_S) +#define PCR_TIMG_CALI_CLK_SEL_V 0x00000007U +#define PCR_TIMG_CALI_CLK_SEL_S 0 +/** PCR_TIMG_SECURE_CLK_SEL : R/W; bitpos: [7:4]; default: 7; + * Configures the clock source for the TIMG_SECURE_CLK. + * 0: EXT_IO_CLK + * 1: CPU_CLK + * 2: AHB_CLK + * 3: APB_CLK + * 4: sec function clock + * 5: mspi function clock + * 6: iomux function clock + * 7: parl io rx function clock + * 8: parl io tx function clock + * 9: spi3 function clock + * 10: spi2 function clock + * 11: RC_FAST_CLK + */ +#define PCR_TIMG_SECURE_CLK_SEL 0x0000000FU +#define PCR_TIMG_SECURE_CLK_SEL_M (PCR_TIMG_SECURE_CLK_SEL_V << PCR_TIMG_SECURE_CLK_SEL_S) +#define PCR_TIMG_SECURE_CLK_SEL_V 0x0000000FU +#define PCR_TIMG_SECURE_CLK_SEL_S 4 +/** PCR_TIMG_SECURE_CLK_DIV_NUM : R/W; bitpos: [15:8]; default: 7; + * When PCR_TIMG_CALI_CLK_SEL set as 4, This field PCR_TIMG_SECURE_CLK_DIV_NUM is used + * to set the divider number of TIMG_SECURE_CLK. + */ +#define PCR_TIMG_SECURE_CLK_DIV_NUM 0x000000FFU +#define PCR_TIMG_SECURE_CLK_DIV_NUM_M (PCR_TIMG_SECURE_CLK_DIV_NUM_V << PCR_TIMG_SECURE_CLK_DIV_NUM_S) +#define PCR_TIMG_SECURE_CLK_DIV_NUM_V 0x000000FFU +#define PCR_TIMG_SECURE_CLK_DIV_NUM_S 8 + +/** PCR_ROM_MEM_LP_CTRL_REG register + * rom power control register + */ +#define PCR_ROM_MEM_LP_CTRL_REG (DR_REG_PCR_BASE + 0x138) +/** PCR_INTERNAL_ROM_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures rom low power mode in low power stage. + * 0(default): deep sleep + * 1: light sleep + * 2: shut down + * 3: disable low power stage + */ +#define PCR_INTERNAL_ROM_MEM_LP_MODE 0x00000003U +#define PCR_INTERNAL_ROM_MEM_LP_MODE_M (PCR_INTERNAL_ROM_MEM_LP_MODE_V << PCR_INTERNAL_ROM_MEM_LP_MODE_S) +#define PCR_INTERNAL_ROM_MEM_LP_MODE_V 0x00000003U +#define PCR_INTERNAL_ROM_MEM_LP_MODE_S 0 +/** PCR_INTERNAL_ROM_MEM_LP_EN : R/W; bitpos: [3:2]; default: 0; + * Set this bit to power down rom. + */ +#define PCR_INTERNAL_ROM_MEM_LP_EN 0x00000003U +#define PCR_INTERNAL_ROM_MEM_LP_EN_M (PCR_INTERNAL_ROM_MEM_LP_EN_V << PCR_INTERNAL_ROM_MEM_LP_EN_S) +#define PCR_INTERNAL_ROM_MEM_LP_EN_V 0x00000003U +#define PCR_INTERNAL_ROM_MEM_LP_EN_S 2 +/** PCR_INTERNAL_ROM_MEM_FORCE_CTRL : R/W; bitpos: [5:4]; default: 0; + * Set this bit to force software control rom, disable hardware control. + */ +#define PCR_INTERNAL_ROM_MEM_FORCE_CTRL 0x00000003U +#define PCR_INTERNAL_ROM_MEM_FORCE_CTRL_M (PCR_INTERNAL_ROM_MEM_FORCE_CTRL_V << PCR_INTERNAL_ROM_MEM_FORCE_CTRL_S) +#define PCR_INTERNAL_ROM_MEM_FORCE_CTRL_V 0x00000003U +#define PCR_INTERNAL_ROM_MEM_FORCE_CTRL_S 4 + +/** PCR_SRAM_POWER_CONF_1_REG register + * HP SRAM/ROM configuration register + */ +#define PCR_SRAM_POWER_CONF_1_REG (DR_REG_PCR_BASE + 0x13c) +/** PCR_SRAM_CLKGATE_FORCE_ON : R/W; bitpos: [26:20]; default: 0; + * 1: Force to open the clock and bypass the gate-clock when accessing the SRAM. 0: A + * gate-clock will be used when accessing the SRAM. + */ +#define PCR_SRAM_CLKGATE_FORCE_ON 0x0000007FU +#define PCR_SRAM_CLKGATE_FORCE_ON_M (PCR_SRAM_CLKGATE_FORCE_ON_V << PCR_SRAM_CLKGATE_FORCE_ON_S) +#define PCR_SRAM_CLKGATE_FORCE_ON_V 0x0000007FU +#define PCR_SRAM_CLKGATE_FORCE_ON_S 20 + +/** PCR_SEC_CONF_REG register + * Clock source configuration register for External Memory Encryption and Decryption + */ +#define PCR_SEC_CONF_REG (DR_REG_PCR_BASE + 0x140) +/** PCR_SEC_CLK_SEL : R/W; bitpos: [1:0]; default: 0; + * Configures the clock source for the External Memory Encryption and Decryption + * module. + * 0(default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F64M_CLK + * 3: PLL_F96M_CLK + */ +#define PCR_SEC_CLK_SEL 0x00000003U +#define PCR_SEC_CLK_SEL_M (PCR_SEC_CLK_SEL_V << PCR_SEC_CLK_SEL_S) +#define PCR_SEC_CLK_SEL_V 0x00000003U +#define PCR_SEC_CLK_SEL_S 0 +/** PCR_SEC_RST_EN : R/W; bitpos: [2]; default: 0; + * Set 1 to reset sec module + */ +#define PCR_SEC_RST_EN (BIT(2)) +#define PCR_SEC_RST_EN_M (PCR_SEC_RST_EN_V << PCR_SEC_RST_EN_S) +#define PCR_SEC_RST_EN_V 0x00000001U +#define PCR_SEC_RST_EN_S 2 +/** PCR_SEC_DIV_NUMINATOR : R/W; bitpos: [6:3]; default: 0; + * The denominator of the frequency divider factor of the sec function clock. + */ +#define PCR_SEC_DIV_NUMINATOR 0x0000000FU +#define PCR_SEC_DIV_NUMINATOR_M (PCR_SEC_DIV_NUMINATOR_V << PCR_SEC_DIV_NUMINATOR_S) +#define PCR_SEC_DIV_NUMINATOR_V 0x0000000FU +#define PCR_SEC_DIV_NUMINATOR_S 3 +/** PCR_SEC_DIV_DENOMINATOR : R/W; bitpos: [10:7]; default: 0; + * The numerator of the frequency divider factor of the sec function clock. + */ +#define PCR_SEC_DIV_DENOMINATOR 0x0000000FU +#define PCR_SEC_DIV_DENOMINATOR_M (PCR_SEC_DIV_DENOMINATOR_V << PCR_SEC_DIV_DENOMINATOR_S) +#define PCR_SEC_DIV_DENOMINATOR_V 0x0000000FU +#define PCR_SEC_DIV_DENOMINATOR_S 7 +/** PCR_SEC_DIV_NUM : R/W; bitpos: [14:11]; default: 0; + * The integral part of the frequency divider factor of the sec function clock. + */ +#define PCR_SEC_DIV_NUM 0x0000000FU +#define PCR_SEC_DIV_NUM_M (PCR_SEC_DIV_NUM_V << PCR_SEC_DIV_NUM_S) +#define PCR_SEC_DIV_NUM_V 0x0000000FU +#define PCR_SEC_DIV_NUM_S 11 + +/** PCR_BUS_CLK_UPDATE_REG register + * Configuration register for applying updated high-performance system clock sources + */ +#define PCR_BUS_CLK_UPDATE_REG (DR_REG_PCR_BASE + 0x148) +/** PCR_BUS_CLOCK_UPDATE : R/W/WTC; bitpos: [0]; default: 0; + * Configures whether or not to update configurations for CPU_CLK division, AHB_CLK + * division and HP_ROOT_CLK clock source selection. + * 0: Not update configurations + * 1: Update configurations + * This bit is automatically cleared when configurations have been updated. + */ +#define PCR_BUS_CLOCK_UPDATE (BIT(0)) +#define PCR_BUS_CLOCK_UPDATE_M (PCR_BUS_CLOCK_UPDATE_V << PCR_BUS_CLOCK_UPDATE_S) +#define PCR_BUS_CLOCK_UPDATE_V 0x00000001U +#define PCR_BUS_CLOCK_UPDATE_S 0 + +/** PCR_SAR_CLK_DIV_REG register + * SAR ADC clock divisor configuration register + */ +#define PCR_SAR_CLK_DIV_REG (DR_REG_PCR_BASE + 0x14c) +/** PCR_SAR2_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 15; + * Configures the divisor for SAR ADC 2 clock to generate ADC analog control signals. + */ +#define PCR_SAR2_CLK_DIV_NUM 0x000000FFU +#define PCR_SAR2_CLK_DIV_NUM_M (PCR_SAR2_CLK_DIV_NUM_V << PCR_SAR2_CLK_DIV_NUM_S) +#define PCR_SAR2_CLK_DIV_NUM_V 0x000000FFU +#define PCR_SAR2_CLK_DIV_NUM_S 0 +/** PCR_SAR1_CLK_DIV_NUM : R/W; bitpos: [15:8]; default: 15; + * Configures the divisor for SAR ADC 1 clock to generate ADC analog control signals. + */ +#define PCR_SAR1_CLK_DIV_NUM 0x000000FFU +#define PCR_SAR1_CLK_DIV_NUM_M (PCR_SAR1_CLK_DIV_NUM_V << PCR_SAR1_CLK_DIV_NUM_S) +#define PCR_SAR1_CLK_DIV_NUM_V 0x000000FFU +#define PCR_SAR1_CLK_DIV_NUM_S 8 + +/** PCR_PWDET_SAR_CLK_CONF_REG register + * xxxx + */ +#define PCR_PWDET_SAR_CLK_CONF_REG (DR_REG_PCR_BASE + 0x150) +/** PCR_PWDET_SAR_READER_EN : R/W; bitpos: [8]; default: 1; + * xxxx + */ +#define PCR_PWDET_SAR_READER_EN (BIT(8)) +#define PCR_PWDET_SAR_READER_EN_M (PCR_PWDET_SAR_READER_EN_V << PCR_PWDET_SAR_READER_EN_S) +#define PCR_PWDET_SAR_READER_EN_V 0x00000001U +#define PCR_PWDET_SAR_READER_EN_S 8 + +/** PCR_TIMERGROUP_WDT_CONF_REG register + * TIMERGROUP_WDT configuration register + */ +#define PCR_TIMERGROUP_WDT_CONF_REG (DR_REG_PCR_BASE + 0x154) +/** PCR_TG0_WDT_RST_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to reset timer_group0 wdt module + */ +#define PCR_TG0_WDT_RST_EN (BIT(0)) +#define PCR_TG0_WDT_RST_EN_M (PCR_TG0_WDT_RST_EN_V << PCR_TG0_WDT_RST_EN_S) +#define PCR_TG0_WDT_RST_EN_V 0x00000001U +#define PCR_TG0_WDT_RST_EN_S 0 +/** PCR_TG1_WDT_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset timer_group1 wdt module + */ +#define PCR_TG1_WDT_RST_EN (BIT(1)) +#define PCR_TG1_WDT_RST_EN_M (PCR_TG1_WDT_RST_EN_V << PCR_TG1_WDT_RST_EN_S) +#define PCR_TG1_WDT_RST_EN_V 0x00000001U +#define PCR_TG1_WDT_RST_EN_S 1 + +/** PCR_TIMERGROUP_XTAL_CONF_REG register + * TIMERGROUP1 configuration register + */ +#define PCR_TIMERGROUP_XTAL_CONF_REG (DR_REG_PCR_BASE + 0x160) +/** PCR_TG0_XTAL_RST_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to reset timer_group0 xtal clock domain + */ +#define PCR_TG0_XTAL_RST_EN (BIT(0)) +#define PCR_TG0_XTAL_RST_EN_M (PCR_TG0_XTAL_RST_EN_V << PCR_TG0_XTAL_RST_EN_S) +#define PCR_TG0_XTAL_RST_EN_V 0x00000001U +#define PCR_TG0_XTAL_RST_EN_S 0 +/** PCR_TG1_XTAL_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset timer_group1 xtal clock domain + */ +#define PCR_TG1_XTAL_RST_EN (BIT(1)) +#define PCR_TG1_XTAL_RST_EN_M (PCR_TG1_XTAL_RST_EN_V << PCR_TG1_XTAL_RST_EN_S) +#define PCR_TG1_XTAL_RST_EN_V 0x00000001U +#define PCR_TG1_XTAL_RST_EN_S 1 +/** PCR_TG0_XTAL_CLK_EN : R/W; bitpos: [2]; default: 1; + * Set 1 to enable tg0 xtal clock + */ +#define PCR_TG0_XTAL_CLK_EN (BIT(2)) +#define PCR_TG0_XTAL_CLK_EN_M (PCR_TG0_XTAL_CLK_EN_V << PCR_TG0_XTAL_CLK_EN_S) +#define PCR_TG0_XTAL_CLK_EN_V 0x00000001U +#define PCR_TG0_XTAL_CLK_EN_S 2 + +/** PCR_KM_CONF_REG register + * Key Manager configuration register + */ +#define PCR_KM_CONF_REG (DR_REG_PCR_BASE + 0x164) +/** PCR_KM_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable km clock + */ +#define PCR_KM_CLK_EN (BIT(0)) +#define PCR_KM_CLK_EN_M (PCR_KM_CLK_EN_V << PCR_KM_CLK_EN_S) +#define PCR_KM_CLK_EN_V 0x00000001U +#define PCR_KM_CLK_EN_S 0 +/** PCR_KM_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset km module + */ +#define PCR_KM_RST_EN (BIT(1)) +#define PCR_KM_RST_EN_M (PCR_KM_RST_EN_V << PCR_KM_RST_EN_S) +#define PCR_KM_RST_EN_V 0x00000001U +#define PCR_KM_RST_EN_S 1 +/** PCR_KM_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset km module + */ +#define PCR_KM_READY (BIT(2)) +#define PCR_KM_READY_M (PCR_KM_READY_V << PCR_KM_READY_S) +#define PCR_KM_READY_V 0x00000001U +#define PCR_KM_READY_S 2 + +/** PCR_KM_MEM_LP_CTRL_REG register + * KM memory power control register + */ +#define PCR_KM_MEM_LP_CTRL_REG (DR_REG_PCR_BASE + 0x168) +/** PCR_KM_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 2; + * Configures km memory low power mode in low power stage. + * 0: deep sleep + * 1: light sleep + * 2(default): shut down + * 3: disable low power stage + */ +#define PCR_KM_MEM_LP_MODE 0x00000003U +#define PCR_KM_MEM_LP_MODE_M (PCR_KM_MEM_LP_MODE_V << PCR_KM_MEM_LP_MODE_S) +#define PCR_KM_MEM_LP_MODE_V 0x00000003U +#define PCR_KM_MEM_LP_MODE_S 0 +/** PCR_KM_MEM_LP_EN : R/W; bitpos: [2]; default: 1; + * Set this bit to power down km memory. + */ +#define PCR_KM_MEM_LP_EN (BIT(2)) +#define PCR_KM_MEM_LP_EN_M (PCR_KM_MEM_LP_EN_V << PCR_KM_MEM_LP_EN_S) +#define PCR_KM_MEM_LP_EN_V 0x00000001U +#define PCR_KM_MEM_LP_EN_S 2 +/** PCR_KM_MEM_FORCE_CTRL : R/W; bitpos: [3]; default: 0; + * Set this bit to force software control km memory, disable hardware control. + */ +#define PCR_KM_MEM_FORCE_CTRL (BIT(3)) +#define PCR_KM_MEM_FORCE_CTRL_M (PCR_KM_MEM_FORCE_CTRL_V << PCR_KM_MEM_FORCE_CTRL_S) +#define PCR_KM_MEM_FORCE_CTRL_V 0x00000001U +#define PCR_KM_MEM_FORCE_CTRL_S 3 + +/** PCR_TCM_MEM_MONITOR_CONF_REG register + * TCM_MEM_MONITOR configuration register + */ +#define PCR_TCM_MEM_MONITOR_CONF_REG (DR_REG_PCR_BASE + 0x16c) +/** PCR_TCM_MEM_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable tcm_mem_monitor clock + */ +#define PCR_TCM_MEM_MONITOR_CLK_EN (BIT(0)) +#define PCR_TCM_MEM_MONITOR_CLK_EN_M (PCR_TCM_MEM_MONITOR_CLK_EN_V << PCR_TCM_MEM_MONITOR_CLK_EN_S) +#define PCR_TCM_MEM_MONITOR_CLK_EN_V 0x00000001U +#define PCR_TCM_MEM_MONITOR_CLK_EN_S 0 +/** PCR_TCM_MEM_MONITOR_RST_EN : R/W; bitpos: [1]; default: 1; + * Set 1 to reset tcm_mem_monitor module + */ +#define PCR_TCM_MEM_MONITOR_RST_EN (BIT(1)) +#define PCR_TCM_MEM_MONITOR_RST_EN_M (PCR_TCM_MEM_MONITOR_RST_EN_V << PCR_TCM_MEM_MONITOR_RST_EN_S) +#define PCR_TCM_MEM_MONITOR_RST_EN_V 0x00000001U +#define PCR_TCM_MEM_MONITOR_RST_EN_S 1 +/** PCR_TCM_MEM_MONITOR_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset tcm_mem_monitor module + */ +#define PCR_TCM_MEM_MONITOR_READY (BIT(2)) +#define PCR_TCM_MEM_MONITOR_READY_M (PCR_TCM_MEM_MONITOR_READY_V << PCR_TCM_MEM_MONITOR_READY_S) +#define PCR_TCM_MEM_MONITOR_READY_V 0x00000001U +#define PCR_TCM_MEM_MONITOR_READY_S 2 + +/** PCR_PSRAM_MEM_MONITOR_CONF_REG register + * PSRAM_MEM_MONITOR configuration register + */ +#define PCR_PSRAM_MEM_MONITOR_CONF_REG (DR_REG_PCR_BASE + 0x170) +/** PCR_PSRAM_MEM_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable psram_mem_monitor clock + */ +#define PCR_PSRAM_MEM_MONITOR_CLK_EN (BIT(0)) +#define PCR_PSRAM_MEM_MONITOR_CLK_EN_M (PCR_PSRAM_MEM_MONITOR_CLK_EN_V << PCR_PSRAM_MEM_MONITOR_CLK_EN_S) +#define PCR_PSRAM_MEM_MONITOR_CLK_EN_V 0x00000001U +#define PCR_PSRAM_MEM_MONITOR_CLK_EN_S 0 +/** PCR_PSRAM_MEM_MONITOR_RST_EN : R/W; bitpos: [1]; default: 1; + * Set 1 to reset psram_mem_monitor module + */ +#define PCR_PSRAM_MEM_MONITOR_RST_EN (BIT(1)) +#define PCR_PSRAM_MEM_MONITOR_RST_EN_M (PCR_PSRAM_MEM_MONITOR_RST_EN_V << PCR_PSRAM_MEM_MONITOR_RST_EN_S) +#define PCR_PSRAM_MEM_MONITOR_RST_EN_V 0x00000001U +#define PCR_PSRAM_MEM_MONITOR_RST_EN_S 1 +/** PCR_PSRAM_MEM_MONITOR_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset psram_mem_monitor module + */ +#define PCR_PSRAM_MEM_MONITOR_READY (BIT(2)) +#define PCR_PSRAM_MEM_MONITOR_READY_M (PCR_PSRAM_MEM_MONITOR_READY_V << PCR_PSRAM_MEM_MONITOR_READY_S) +#define PCR_PSRAM_MEM_MONITOR_READY_V 0x00000001U +#define PCR_PSRAM_MEM_MONITOR_READY_S 2 + +/** PCR_RESET_EVENT_BYPASS_REG register + * reset event bypass backdoor configuration register + */ +#define PCR_RESET_EVENT_BYPASS_REG (DR_REG_PCR_BASE + 0x174) +/** PCR_RESET_EVENT_BYPASS_TEE_APM : R/W; bitpos: [0]; default: 0; + * This field is used to control reset event relationship for tee_apm. 1: tee_apm will + * only be reset by power-reset. some reset event will be bypass. 0:tee_apm will not + * only be reset by power-reset, but also some reset event. + */ +#define PCR_RESET_EVENT_BYPASS_TEE_APM (BIT(0)) +#define PCR_RESET_EVENT_BYPASS_TEE_APM_M (PCR_RESET_EVENT_BYPASS_TEE_APM_V << PCR_RESET_EVENT_BYPASS_TEE_APM_S) +#define PCR_RESET_EVENT_BYPASS_TEE_APM_V 0x00000001U +#define PCR_RESET_EVENT_BYPASS_TEE_APM_S 0 +/** PCR_RESET_EVENT_BYPASS_PCR : R/W; bitpos: [1]; default: 0; + * This field is used to control reset event relationship for pcr. 1: pcr will only be + * reset by power-reset. some reset event will be bypass. 0:pcr will not only be reset + * by power-reset, but also some reset event. + */ +#define PCR_RESET_EVENT_BYPASS_PCR (BIT(1)) +#define PCR_RESET_EVENT_BYPASS_PCR_M (PCR_RESET_EVENT_BYPASS_PCR_V << PCR_RESET_EVENT_BYPASS_PCR_S) +#define PCR_RESET_EVENT_BYPASS_PCR_V 0x00000001U +#define PCR_RESET_EVENT_BYPASS_PCR_S 1 +/** PCR_RESET_EVENT_BYPASS_HPSYSREG : R/W; bitpos: [2]; default: 0; + * This field is used to control reset event relationship for hpsysreg. 1: hpsysreg + * will only be reset by power-reset. some reset event will be bypass. 0:hpsysreg will + * not only be reset by power-reset, but also some reset event. + */ +#define PCR_RESET_EVENT_BYPASS_HPSYSREG (BIT(2)) +#define PCR_RESET_EVENT_BYPASS_HPSYSREG_M (PCR_RESET_EVENT_BYPASS_HPSYSREG_V << PCR_RESET_EVENT_BYPASS_HPSYSREG_S) +#define PCR_RESET_EVENT_BYPASS_HPSYSREG_V 0x00000001U +#define PCR_RESET_EVENT_BYPASS_HPSYSREG_S 2 +/** PCR_RESET_EVENT_BYPASS_IOMUX : R/W; bitpos: [3]; default: 0; + * This field is used to control reset event relationship for iomux. 1: iomux will + * only be reset by power-reset. some reset event will be bypass. 0:iomux will not + * only be reset by power-reset, but also some reset event. + */ +#define PCR_RESET_EVENT_BYPASS_IOMUX (BIT(3)) +#define PCR_RESET_EVENT_BYPASS_IOMUX_M (PCR_RESET_EVENT_BYPASS_IOMUX_V << PCR_RESET_EVENT_BYPASS_IOMUX_S) +#define PCR_RESET_EVENT_BYPASS_IOMUX_V 0x00000001U +#define PCR_RESET_EVENT_BYPASS_IOMUX_S 3 +/** PCR_RESET_EVENT_BYPASS_INTMTX0 : R/W; bitpos: [4]; default: 0; + * This field is used to control reset event relationship for intmtx0. 1: intmtx0 will + * only be reset by power-reset. some reset event will be bypass. 0:intmtx0 will not + * only be reset by power-reset, but also some reset event. + */ +#define PCR_RESET_EVENT_BYPASS_INTMTX0 (BIT(4)) +#define PCR_RESET_EVENT_BYPASS_INTMTX0_M (PCR_RESET_EVENT_BYPASS_INTMTX0_V << PCR_RESET_EVENT_BYPASS_INTMTX0_S) +#define PCR_RESET_EVENT_BYPASS_INTMTX0_V 0x00000001U +#define PCR_RESET_EVENT_BYPASS_INTMTX0_S 4 +/** PCR_RESET_EVENT_BYPASS_INTMTX1 : R/W; bitpos: [5]; default: 0; + * This field is used to control reset event relationship for intmtx1. 1: intmtx1 will + * only be reset by power-reset. some reset event will be bypass. 0:intmtx1 will not + * only be reset by power-reset, but also some reset event. + */ +#define PCR_RESET_EVENT_BYPASS_INTMTX1 (BIT(5)) +#define PCR_RESET_EVENT_BYPASS_INTMTX1_M (PCR_RESET_EVENT_BYPASS_INTMTX1_V << PCR_RESET_EVENT_BYPASS_INTMTX1_S) +#define PCR_RESET_EVENT_BYPASS_INTMTX1_V 0x00000001U +#define PCR_RESET_EVENT_BYPASS_INTMTX1_S 5 +/** PCR_RESET_EVENT_BYPASS_MODEM : R/W; bitpos: [6]; default: 0; + * This field is used to control reset event relationship for modem. 1: modem will + * only be reset by power-reset. some reset event will be bypass. 0:modem will not + * only be reset by power-reset, but also some reset event. + */ +#define PCR_RESET_EVENT_BYPASS_MODEM (BIT(6)) +#define PCR_RESET_EVENT_BYPASS_MODEM_M (PCR_RESET_EVENT_BYPASS_MODEM_V << PCR_RESET_EVENT_BYPASS_MODEM_S) +#define PCR_RESET_EVENT_BYPASS_MODEM_V 0x00000001U +#define PCR_RESET_EVENT_BYPASS_MODEM_S 6 +/** PCR_RESET_EVENT_BYPASS_BUS_MODEM : R/W; bitpos: [7]; default: 0; + * This field is used to control reset event relationship for bus_modem. 1: bus_modem + * will only be reset by power-reset. some reset event will be bypass. 0:bus_modem + * will not only be reset by power-reset, but also some reset event. + */ +#define PCR_RESET_EVENT_BYPASS_BUS_MODEM (BIT(7)) +#define PCR_RESET_EVENT_BYPASS_BUS_MODEM_M (PCR_RESET_EVENT_BYPASS_BUS_MODEM_V << PCR_RESET_EVENT_BYPASS_BUS_MODEM_S) +#define PCR_RESET_EVENT_BYPASS_BUS_MODEM_V 0x00000001U +#define PCR_RESET_EVENT_BYPASS_BUS_MODEM_S 7 + +/** PCR_HPCORE_MEM_LP_CTRL_REG register + * HP CORE0 & HP CORE1 memory power control register + */ +#define PCR_HPCORE_MEM_LP_CTRL_REG (DR_REG_PCR_BASE + 0x178) +/** PCR_HPCORE_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures memory low power mode in low power stage. + * 0(default): deep sleep + * 1: light sleep + * 2: shut down + * 3: disable low power stage + */ +#define PCR_HPCORE_MEM_LP_MODE 0x00000003U +#define PCR_HPCORE_MEM_LP_MODE_M (PCR_HPCORE_MEM_LP_MODE_V << PCR_HPCORE_MEM_LP_MODE_S) +#define PCR_HPCORE_MEM_LP_MODE_V 0x00000003U +#define PCR_HPCORE_MEM_LP_MODE_S 0 +/** PCR_HPCORE_MEM_LP_EN : R/W; bitpos: [2]; default: 0; + * Set this bit to power down HP CORE0 & HP CORE1 memory. + */ +#define PCR_HPCORE_MEM_LP_EN (BIT(2)) +#define PCR_HPCORE_MEM_LP_EN_M (PCR_HPCORE_MEM_LP_EN_V << PCR_HPCORE_MEM_LP_EN_S) +#define PCR_HPCORE_MEM_LP_EN_V 0x00000001U +#define PCR_HPCORE_MEM_LP_EN_S 2 +/** PCR_HPCORE_MEM_FORCE_CTRL : R/W; bitpos: [3]; default: 0; + * Set this bit to force software control HP CORE0 & HP CORE1 memory, disable hardware + * control. + */ +#define PCR_HPCORE_MEM_FORCE_CTRL (BIT(3)) +#define PCR_HPCORE_MEM_FORCE_CTRL_M (PCR_HPCORE_MEM_FORCE_CTRL_V << PCR_HPCORE_MEM_FORCE_CTRL_S) +#define PCR_HPCORE_MEM_FORCE_CTRL_V 0x00000001U +#define PCR_HPCORE_MEM_FORCE_CTRL_S 3 + +/** PCR_USB_OTG11_CONF_REG register + * USB_OTG configuration register + */ +#define PCR_USB_OTG11_CONF_REG (DR_REG_PCR_BASE + 0x17c) +/** PCR_USB_OTG11_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable usb_otg11 clock + */ +#define PCR_USB_OTG11_CLK_EN (BIT(0)) +#define PCR_USB_OTG11_CLK_EN_M (PCR_USB_OTG11_CLK_EN_V << PCR_USB_OTG11_CLK_EN_S) +#define PCR_USB_OTG11_CLK_EN_V 0x00000001U +#define PCR_USB_OTG11_CLK_EN_S 0 +/** PCR_USB_OTG11_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset usb_otg11 module + */ +#define PCR_USB_OTG11_RST_EN (BIT(1)) +#define PCR_USB_OTG11_RST_EN_M (PCR_USB_OTG11_RST_EN_V << PCR_USB_OTG11_RST_EN_S) +#define PCR_USB_OTG11_RST_EN_V 0x00000001U +#define PCR_USB_OTG11_RST_EN_S 1 +/** PCR_USB_OTG11_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset usb_otg11 module + */ +#define PCR_USB_OTG11_READY (BIT(2)) +#define PCR_USB_OTG11_READY_M (PCR_USB_OTG11_READY_V << PCR_USB_OTG11_READY_S) +#define PCR_USB_OTG11_READY_V 0x00000001U +#define PCR_USB_OTG11_READY_S 2 + +/** PCR_USB_OTG11_MEM_LP_CTRL_REG register + * USB_OTG11 memory power control register + */ +#define PCR_USB_OTG11_MEM_LP_CTRL_REG (DR_REG_PCR_BASE + 0x180) +/** PCR_USB_OTG11_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures usb_otg11 memory low power mode in low power stage. + * 0(default): deep sleep + * 1: light sleep + * 2: shut down + * 3: disable low power stage + */ +#define PCR_USB_OTG11_MEM_LP_MODE 0x00000003U +#define PCR_USB_OTG11_MEM_LP_MODE_M (PCR_USB_OTG11_MEM_LP_MODE_V << PCR_USB_OTG11_MEM_LP_MODE_S) +#define PCR_USB_OTG11_MEM_LP_MODE_V 0x00000003U +#define PCR_USB_OTG11_MEM_LP_MODE_S 0 +/** PCR_USB_OTG11_MEM_LP_EN : R/W; bitpos: [2]; default: 0; + * Set this bit to power down usb_otg11 memory. + */ +#define PCR_USB_OTG11_MEM_LP_EN (BIT(2)) +#define PCR_USB_OTG11_MEM_LP_EN_M (PCR_USB_OTG11_MEM_LP_EN_V << PCR_USB_OTG11_MEM_LP_EN_S) +#define PCR_USB_OTG11_MEM_LP_EN_V 0x00000001U +#define PCR_USB_OTG11_MEM_LP_EN_S 2 +/** PCR_USB_OTG11_MEM_FORCE_CTRL : R/W; bitpos: [3]; default: 0; + * Set this bit to force software control usb_otg11 memory, disable hardware control. + */ +#define PCR_USB_OTG11_MEM_FORCE_CTRL (BIT(3)) +#define PCR_USB_OTG11_MEM_FORCE_CTRL_M (PCR_USB_OTG11_MEM_FORCE_CTRL_V << PCR_USB_OTG11_MEM_FORCE_CTRL_S) +#define PCR_USB_OTG11_MEM_FORCE_CTRL_V 0x00000001U +#define PCR_USB_OTG11_MEM_FORCE_CTRL_S 3 + +/** PCR_CORE1_CONF_REG register + * USB_OTG configuration register + */ +#define PCR_CORE1_CONF_REG (DR_REG_PCR_BASE + 0x188) +/** PCR_CORE1_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable core1 clock + */ +#define PCR_CORE1_CLK_EN (BIT(0)) +#define PCR_CORE1_CLK_EN_M (PCR_CORE1_CLK_EN_V << PCR_CORE1_CLK_EN_S) +#define PCR_CORE1_CLK_EN_V 0x00000001U +#define PCR_CORE1_CLK_EN_S 0 +/** PCR_CORE1_RST_EN : R/W; bitpos: [1]; default: 1; + * Set 1 to reset core1 module + */ +#define PCR_CORE1_RST_EN (BIT(1)) +#define PCR_CORE1_RST_EN_M (PCR_CORE1_RST_EN_V << PCR_CORE1_RST_EN_S) +#define PCR_CORE1_RST_EN_V 0x00000001U +#define PCR_CORE1_RST_EN_S 1 + +/** PCR_I2C1_CONF_REG register + * I2C configuration register + */ +#define PCR_I2C1_CONF_REG (DR_REG_PCR_BASE + 0x18c) +/** PCR_I2C1_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable i2c1 apb clock + */ +#define PCR_I2C1_CLK_EN (BIT(0)) +#define PCR_I2C1_CLK_EN_M (PCR_I2C1_CLK_EN_V << PCR_I2C1_CLK_EN_S) +#define PCR_I2C1_CLK_EN_V 0x00000001U +#define PCR_I2C1_CLK_EN_S 0 +/** PCR_I2C1_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset i2c1 module + */ +#define PCR_I2C1_RST_EN (BIT(1)) +#define PCR_I2C1_RST_EN_M (PCR_I2C1_RST_EN_V << PCR_I2C1_RST_EN_S) +#define PCR_I2C1_RST_EN_V 0x00000001U +#define PCR_I2C1_RST_EN_S 1 + +/** PCR_I2C1_SCLK_CONF_REG register + * I2C_SCLK configuration register + */ +#define PCR_I2C1_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x190) +/** PCR_I2C1_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the i2c1 function clock. + */ +#define PCR_I2C1_SCLK_DIV_A 0x0000003FU +#define PCR_I2C1_SCLK_DIV_A_M (PCR_I2C1_SCLK_DIV_A_V << PCR_I2C1_SCLK_DIV_A_S) +#define PCR_I2C1_SCLK_DIV_A_V 0x0000003FU +#define PCR_I2C1_SCLK_DIV_A_S 0 +/** PCR_I2C1_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the i2c1 function clock. + */ +#define PCR_I2C1_SCLK_DIV_B 0x0000003FU +#define PCR_I2C1_SCLK_DIV_B_M (PCR_I2C1_SCLK_DIV_B_V << PCR_I2C1_SCLK_DIV_B_S) +#define PCR_I2C1_SCLK_DIV_B_V 0x0000003FU +#define PCR_I2C1_SCLK_DIV_B_S 6 +/** PCR_I2C1_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the i2c1 function clock. + */ +#define PCR_I2C1_SCLK_DIV_NUM 0x000000FFU +#define PCR_I2C1_SCLK_DIV_NUM_M (PCR_I2C1_SCLK_DIV_NUM_V << PCR_I2C1_SCLK_DIV_NUM_S) +#define PCR_I2C1_SCLK_DIV_NUM_V 0x000000FFU +#define PCR_I2C1_SCLK_DIV_NUM_S 12 +/** PCR_I2C1_SCLK_SEL : R/W; bitpos: [20]; default: 0; + * Configures the clock source of I2C. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + */ +#define PCR_I2C1_SCLK_SEL (BIT(20)) +#define PCR_I2C1_SCLK_SEL_M (PCR_I2C1_SCLK_SEL_V << PCR_I2C1_SCLK_SEL_S) +#define PCR_I2C1_SCLK_SEL_V 0x00000001U +#define PCR_I2C1_SCLK_SEL_S 20 +/** PCR_I2C1_SCLK_EN : R/W; bitpos: [22]; default: 0; + * Set 1 to enable i2c function clock + */ +#define PCR_I2C1_SCLK_EN (BIT(22)) +#define PCR_I2C1_SCLK_EN_M (PCR_I2C1_SCLK_EN_V << PCR_I2C1_SCLK_EN_S) +#define PCR_I2C1_SCLK_EN_V 0x00000001U +#define PCR_I2C1_SCLK_EN_S 22 + +/** PCR_PWM1_CONF_REG register + * PWM1 configuration register + */ +#define PCR_PWM1_CONF_REG (DR_REG_PCR_BASE + 0x194) +/** PCR_PWM1_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable pwm1 clock + */ +#define PCR_PWM1_CLK_EN (BIT(0)) +#define PCR_PWM1_CLK_EN_M (PCR_PWM1_CLK_EN_V << PCR_PWM1_CLK_EN_S) +#define PCR_PWM1_CLK_EN_V 0x00000001U +#define PCR_PWM1_CLK_EN_S 0 +/** PCR_PWM1_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset pwm1 module + */ +#define PCR_PWM1_RST_EN (BIT(1)) +#define PCR_PWM1_RST_EN_M (PCR_PWM1_RST_EN_V << PCR_PWM1_RST_EN_S) +#define PCR_PWM1_RST_EN_V 0x00000001U +#define PCR_PWM1_RST_EN_S 1 +/** PCR_PWM1_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset pwm1 module + */ +#define PCR_PWM1_READY (BIT(2)) +#define PCR_PWM1_READY_M (PCR_PWM1_READY_V << PCR_PWM1_READY_S) +#define PCR_PWM1_READY_V 0x00000001U +#define PCR_PWM1_READY_S 2 + +/** PCR_PWM1_CLK_CONF_REG register + * PWM1_CLK configuration register + */ +#define PCR_PWM1_CLK_CONF_REG (DR_REG_PCR_BASE + 0x198) +/** PCR_PWM1_DIV_NUM : R/W; bitpos: [19:12]; default: 4; + * The integral part of the frequency divider factor of the pwm1 function clock. + */ +#define PCR_PWM1_DIV_NUM 0x000000FFU +#define PCR_PWM1_DIV_NUM_M (PCR_PWM1_DIV_NUM_V << PCR_PWM1_DIV_NUM_S) +#define PCR_PWM1_DIV_NUM_V 0x000000FFU +#define PCR_PWM1_DIV_NUM_S 12 +/** PCR_PWM1_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of MCPWM1. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F160M_CLK + */ +#define PCR_PWM1_CLKM_SEL 0x00000003U +#define PCR_PWM1_CLKM_SEL_M (PCR_PWM1_CLKM_SEL_V << PCR_PWM1_CLKM_SEL_S) +#define PCR_PWM1_CLKM_SEL_V 0x00000003U +#define PCR_PWM1_CLKM_SEL_S 20 +/** PCR_PWM1_CLKM_EN : R/W; bitpos: [22]; default: 0; + * set this field as 1 to activate pwm1 clkm. + */ +#define PCR_PWM1_CLKM_EN (BIT(22)) +#define PCR_PWM1_CLKM_EN_M (PCR_PWM1_CLKM_EN_V << PCR_PWM1_CLKM_EN_S) +#define PCR_PWM1_CLKM_EN_V 0x00000001U +#define PCR_PWM1_CLKM_EN_S 22 + +/** PCR_SPI3_CONF_REG register + * SPI3 configuration register + */ +#define PCR_SPI3_CONF_REG (DR_REG_PCR_BASE + 0x19c) +/** PCR_SPI3_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable spi3 apb clock + */ +#define PCR_SPI3_CLK_EN (BIT(0)) +#define PCR_SPI3_CLK_EN_M (PCR_SPI3_CLK_EN_V << PCR_SPI3_CLK_EN_S) +#define PCR_SPI3_CLK_EN_V 0x00000001U +#define PCR_SPI3_CLK_EN_S 0 +/** PCR_SPI3_RST_EN : R/W; bitpos: [1]; default: 1; + * Set 1 to reset spi3 module + */ +#define PCR_SPI3_RST_EN (BIT(1)) +#define PCR_SPI3_RST_EN_M (PCR_SPI3_RST_EN_V << PCR_SPI3_RST_EN_S) +#define PCR_SPI3_RST_EN_V 0x00000001U +#define PCR_SPI3_RST_EN_S 1 +/** PCR_SPI3_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset spi3 module + */ +#define PCR_SPI3_READY (BIT(2)) +#define PCR_SPI3_READY_M (PCR_SPI3_READY_V << PCR_SPI3_READY_S) +#define PCR_SPI3_READY_V 0x00000001U +#define PCR_SPI3_READY_S 2 + +/** PCR_SPI3_CLKM_CONF_REG register + * SPI3_CLKM configuration register + */ +#define PCR_SPI3_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x1a0) +/** PCR_SPI3_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the spi3_mst clock. + */ +#define PCR_SPI3_CLKM_DIV_NUM 0x000000FFU +#define PCR_SPI3_CLKM_DIV_NUM_M (PCR_SPI3_CLKM_DIV_NUM_V << PCR_SPI3_CLKM_DIV_NUM_S) +#define PCR_SPI3_CLKM_DIV_NUM_V 0x000000FFU +#define PCR_SPI3_CLKM_DIV_NUM_S 12 +/** PCR_SPI3_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of SPI3. + * 0 (default): XTAL_CLK + * 1: PLL_F48M_CLK + * 2: RC_FAST_CLK + */ +#define PCR_SPI3_CLKM_SEL 0x00000003U +#define PCR_SPI3_CLKM_SEL_M (PCR_SPI3_CLKM_SEL_V << PCR_SPI3_CLKM_SEL_S) +#define PCR_SPI3_CLKM_SEL_V 0x00000003U +#define PCR_SPI3_CLKM_SEL_S 20 +/** PCR_SPI3_CLKM_EN : R/W; bitpos: [22]; default: 0; + * Set 1 to enable spi3 function clock + */ +#define PCR_SPI3_CLKM_EN (BIT(22)) +#define PCR_SPI3_CLKM_EN_M (PCR_SPI3_CLKM_EN_V << PCR_SPI3_CLKM_EN_S) +#define PCR_SPI3_CLKM_EN_V 0x00000001U +#define PCR_SPI3_CLKM_EN_S 22 + +/** PCR_ASRC_FUNC_CLK_CONF_REG register + * AUDIO_SAMPLE_RATE_FUNC_CLK configuration register + */ +#define PCR_ASRC_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x1a8) +/** PCR_ASRC_APB_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable audio_sample rate converter apb clock + */ +#define PCR_ASRC_APB_CLK_EN (BIT(22)) +#define PCR_ASRC_APB_CLK_EN_M (PCR_ASRC_APB_CLK_EN_V << PCR_ASRC_APB_CLK_EN_S) +#define PCR_ASRC_APB_CLK_EN_V 0x00000001U +#define PCR_ASRC_APB_CLK_EN_S 22 +/** PCR_ASRC_FUNC_CLK_EN : R/W; bitpos: [23]; default: 1; + * Set 1 to enable audio_sample rate converter function clock + */ +#define PCR_ASRC_FUNC_CLK_EN (BIT(23)) +#define PCR_ASRC_FUNC_CLK_EN_M (PCR_ASRC_FUNC_CLK_EN_V << PCR_ASRC_FUNC_CLK_EN_S) +#define PCR_ASRC_FUNC_CLK_EN_V 0x00000001U +#define PCR_ASRC_FUNC_CLK_EN_S 23 +/** PCR_ASRC_RST_EN : R/W; bitpos: [24]; default: 0; + * Set 1 to reset audio_sample_rate_converter module + */ +#define PCR_ASRC_RST_EN (BIT(24)) +#define PCR_ASRC_RST_EN_M (PCR_ASRC_RST_EN_V << PCR_ASRC_RST_EN_S) +#define PCR_ASRC_RST_EN_V 0x00000001U +#define PCR_ASRC_RST_EN_S 24 + +/** PCR_BUS_CLOCK_GATE_BYPASS_REG register + * bus clock gating bypass configuration register + */ +#define PCR_BUS_CLOCK_GATE_BYPASS_REG (DR_REG_PCR_BASE + 0x1ac) +/** PCR_AHB_CLK_GATING_BYPASS : R/W; bitpos: [0]; default: 1; + * Set 1 to bypass the clock gating for ahb bus + */ +#define PCR_AHB_CLK_GATING_BYPASS (BIT(0)) +#define PCR_AHB_CLK_GATING_BYPASS_M (PCR_AHB_CLK_GATING_BYPASS_V << PCR_AHB_CLK_GATING_BYPASS_S) +#define PCR_AHB_CLK_GATING_BYPASS_V 0x00000001U +#define PCR_AHB_CLK_GATING_BYPASS_S 0 +/** PCR_APB_CLK_GATING_BYPASS : R/W; bitpos: [1]; default: 1; + * Set 1 to bypass the clock gating for apb bus + */ +#define PCR_APB_CLK_GATING_BYPASS (BIT(1)) +#define PCR_APB_CLK_GATING_BYPASS_M (PCR_APB_CLK_GATING_BYPASS_V << PCR_APB_CLK_GATING_BYPASS_S) +#define PCR_APB_CLK_GATING_BYPASS_V 0x00000001U +#define PCR_APB_CLK_GATING_BYPASS_S 1 +/** PCR_AXI_CLK_GATING_BYPASS : R/W; bitpos: [2]; default: 1; + * Set 1 to bypass the clock gating for axi bus + */ +#define PCR_AXI_CLK_GATING_BYPASS (BIT(2)) +#define PCR_AXI_CLK_GATING_BYPASS_M (PCR_AXI_CLK_GATING_BYPASS_V << PCR_AXI_CLK_GATING_BYPASS_S) +#define PCR_AXI_CLK_GATING_BYPASS_V 0x00000001U +#define PCR_AXI_CLK_GATING_BYPASS_S 2 +/** PCR_MEM_CLK_GATING_BYPASS : R/W; bitpos: [3]; default: 1; + * Set 1 to bypass the clock gating for mem bus + */ +#define PCR_MEM_CLK_GATING_BYPASS (BIT(3)) +#define PCR_MEM_CLK_GATING_BYPASS_M (PCR_MEM_CLK_GATING_BYPASS_V << PCR_MEM_CLK_GATING_BYPASS_S) +#define PCR_MEM_CLK_GATING_BYPASS_V 0x00000001U +#define PCR_MEM_CLK_GATING_BYPASS_S 3 + +/** PCR_ZERO_DET_CONF_REG register + * ZERO_DET configuration register + */ +#define PCR_ZERO_DET_CONF_REG (DR_REG_PCR_BASE + 0x1b0) +/** PCR_ZERO_DET_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable zero_det apb clock + */ +#define PCR_ZERO_DET_CLK_EN (BIT(0)) +#define PCR_ZERO_DET_CLK_EN_M (PCR_ZERO_DET_CLK_EN_V << PCR_ZERO_DET_CLK_EN_S) +#define PCR_ZERO_DET_CLK_EN_V 0x00000001U +#define PCR_ZERO_DET_CLK_EN_S 0 +/** PCR_ZERO_DET_RST_EN : R/W; bitpos: [1]; default: 1; + * Set 1 to reset zero_det module + */ +#define PCR_ZERO_DET_RST_EN (BIT(1)) +#define PCR_ZERO_DET_RST_EN_M (PCR_ZERO_DET_RST_EN_V << PCR_ZERO_DET_RST_EN_S) +#define PCR_ZERO_DET_RST_EN_V 0x00000001U +#define PCR_ZERO_DET_RST_EN_S 1 + +/** PCR_ZERO_DET_CLK_CONF_REG register + * ZERO_DET_CLK configuration register + */ +#define PCR_ZERO_DET_CLK_CONF_REG (DR_REG_PCR_BASE + 0x1b4) +/** PCR_ZERO_DET_FUNC_CLK_SEL : R/W; bitpos: [21:20]; default: 0; + * Configures the clock source of ZERO DETECT. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK + */ +#define PCR_ZERO_DET_FUNC_CLK_SEL 0x00000003U +#define PCR_ZERO_DET_FUNC_CLK_SEL_M (PCR_ZERO_DET_FUNC_CLK_SEL_V << PCR_ZERO_DET_FUNC_CLK_SEL_S) +#define PCR_ZERO_DET_FUNC_CLK_SEL_V 0x00000003U +#define PCR_ZERO_DET_FUNC_CLK_SEL_S 20 +/** PCR_ZERO_DET_FUNC_CLK_EN : R/W; bitpos: [22]; default: 0; + * Set 1 to enable zero_det function clock + */ +#define PCR_ZERO_DET_FUNC_CLK_EN (BIT(22)) +#define PCR_ZERO_DET_FUNC_CLK_EN_M (PCR_ZERO_DET_FUNC_CLK_EN_V << PCR_ZERO_DET_FUNC_CLK_EN_S) +#define PCR_ZERO_DET_FUNC_CLK_EN_V 0x00000001U +#define PCR_ZERO_DET_FUNC_CLK_EN_S 22 + +/** PCR_RST_EN_REG register + * PCR clock gating configure register + */ +#define PCR_RST_EN_REG (DR_REG_PCR_BASE + 0x1b8) +/** PCR_PCR_RST_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to reset pcr module + */ +#define PCR_PCR_RST_EN (BIT(0)) +#define PCR_PCR_RST_EN_M (PCR_PCR_RST_EN_V << PCR_PCR_RST_EN_S) +#define PCR_PCR_RST_EN_V 0x00000001U +#define PCR_PCR_RST_EN_S 0 + +/** PCR_DATE_REG register + * Date register. + */ +#define PCR_DATE_REG (DR_REG_PCR_BASE + 0xffc) +/** PCR_DATE : R/W; bitpos: [27:0]; default: 37823024; + * PCR version information. + */ +#define PCR_DATE 0x0FFFFFFFU +#define PCR_DATE_M (PCR_DATE_V << PCR_DATE_S) +#define PCR_DATE_V 0x0FFFFFFFU +#define PCR_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/src/target/esp32h4/ld/esp32h4.rom.api.ld b/src/target/esp32h4/ld/esp32h4.rom.api.ld index 3c7fb41..af451b0 100644 --- a/src/target/esp32h4/ld/esp32h4.rom.api.ld +++ b/src/target/esp32h4/ld/esp32h4.rom.api.ld @@ -27,7 +27,6 @@ PROVIDE ( esp_rom_uart_putc = ets_write_char_uart ); PROVIDE ( esp_rom_uart_attach = uartAttach ); PROVIDE ( esp_rom_uart_init = Uart_Init ); PROVIDE ( esp_rom_uart_div_modify = uart_div_modify ); -PROVIDE ( esp_rom_get_apb_freq = ets_get_apb_freq ); PROVIDE ( esp_rom_get_cpu_freq = ets_clk_get_cpu_freq ); PROVIDE ( esp_rom_get_uart_device = GetUartDevice ); @@ -57,6 +56,7 @@ PROVIDE ( esp_rom_isr_attach = ets_isr_attach ); PROVIDE ( esp_rom_isr_unmask = ets_isr_unmask ); PROVIDE ( esp_rom_get_cpu_ticks_per_us = ets_get_cpu_frequency ); PROVIDE ( esp_rom_set_cpu_ticks_per_us = ets_update_cpu_frequency ); +PROVIDE ( esp_rom_get_xtal_freq = ets_clk_get_xtal_freq); PROVIDE ( esp_rom_spiflash_attach = spi_flash_attach ); PROVIDE ( esp_rom_spiflash_clear_bp = esp_rom_spiflash_unlock ); diff --git a/src/target/esp32h4/src/clock.c b/src/target/esp32h4/src/clock.c new file mode 100644 index 0000000..1fc11a8 --- /dev/null +++ b/src/target/esp32h4/src/clock.c @@ -0,0 +1,14 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 OR MIT + */ + +#include +#include +#include +#include +#include +#include + +// TRM not ready yet diff --git a/src/target/esp32p4/CMakeLists.txt b/src/target/esp32p4/CMakeLists.txt index 27236f4..9a909c7 100644 --- a/src/target/esp32p4/CMakeLists.txt +++ b/src/target/esp32p4/CMakeLists.txt @@ -1,6 +1,7 @@ set(srcs src/uart.c src/usb_serial_jtag.c + src/clock.c ) add_library(${ESP_TARGET_LIB} STATIC ${srcs}) diff --git a/src/target/esp32p4/include/soc/lp_clkrst_reg.h b/src/target/esp32p4/include/soc/lp_clkrst_reg.h new file mode 100644 index 0000000..f487412 --- /dev/null +++ b/src/target/esp32p4/include/soc/lp_clkrst_reg.h @@ -0,0 +1,1037 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 OR MIT + */ +#pragma once + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_CLKRST_LP_CLK_CONF_REG register + * need_des + */ +#define LP_CLKRST_LP_CLK_CONF_REG (DR_REG_LP_CLKRST_BASE + 0x0) +/** LP_CLKRST_SLOW_CLK_SEL : R/W; bitpos: [1:0]; default: 0; + * need_des + */ +#define LP_CLKRST_SLOW_CLK_SEL 0x00000003U +#define LP_CLKRST_SLOW_CLK_SEL_M (LP_CLKRST_SLOW_CLK_SEL_V << LP_CLKRST_SLOW_CLK_SEL_S) +#define LP_CLKRST_SLOW_CLK_SEL_V 0x00000003U +#define LP_CLKRST_SLOW_CLK_SEL_S 0 +/** LP_CLKRST_FAST_CLK_SEL : R/W; bitpos: [3:2]; default: 1; + * need_des + */ +#define LP_CLKRST_FAST_CLK_SEL 0x00000003U +#define LP_CLKRST_FAST_CLK_SEL_M (LP_CLKRST_FAST_CLK_SEL_V << LP_CLKRST_FAST_CLK_SEL_S) +#define LP_CLKRST_FAST_CLK_SEL_V 0x00000003U +#define LP_CLKRST_FAST_CLK_SEL_S 2 +/** LP_CLKRST_LP_PERI_DIV_NUM : R/W; bitpos: [9:4]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_PERI_DIV_NUM 0x0000003FU +#define LP_CLKRST_LP_PERI_DIV_NUM_M (LP_CLKRST_LP_PERI_DIV_NUM_V << LP_CLKRST_LP_PERI_DIV_NUM_S) +#define LP_CLKRST_LP_PERI_DIV_NUM_V 0x0000003FU +#define LP_CLKRST_LP_PERI_DIV_NUM_S 4 +/** LP_CLKRST_ANA_SEL_REF_PLL8M : R/W; bitpos: [10]; default: 0; + * need_des + */ +#define LP_CLKRST_ANA_SEL_REF_PLL8M (BIT(10)) +#define LP_CLKRST_ANA_SEL_REF_PLL8M_M (LP_CLKRST_ANA_SEL_REF_PLL8M_V << LP_CLKRST_ANA_SEL_REF_PLL8M_S) +#define LP_CLKRST_ANA_SEL_REF_PLL8M_V 0x00000001U +#define LP_CLKRST_ANA_SEL_REF_PLL8M_S 10 + +/** LP_CLKRST_LP_CLK_PO_EN_REG register + * need_des + */ +#define LP_CLKRST_LP_CLK_PO_EN_REG (DR_REG_LP_CLKRST_BASE + 0x4) +/** LP_CLKRST_CLK_CORE_EFUSE_OEN : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define LP_CLKRST_CLK_CORE_EFUSE_OEN (BIT(0)) +#define LP_CLKRST_CLK_CORE_EFUSE_OEN_M (LP_CLKRST_CLK_CORE_EFUSE_OEN_V << LP_CLKRST_CLK_CORE_EFUSE_OEN_S) +#define LP_CLKRST_CLK_CORE_EFUSE_OEN_V 0x00000001U +#define LP_CLKRST_CLK_CORE_EFUSE_OEN_S 0 +/** LP_CLKRST_CLK_LP_BUS_OEN : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define LP_CLKRST_CLK_LP_BUS_OEN (BIT(1)) +#define LP_CLKRST_CLK_LP_BUS_OEN_M (LP_CLKRST_CLK_LP_BUS_OEN_V << LP_CLKRST_CLK_LP_BUS_OEN_S) +#define LP_CLKRST_CLK_LP_BUS_OEN_V 0x00000001U +#define LP_CLKRST_CLK_LP_BUS_OEN_S 1 +/** LP_CLKRST_CLK_AON_SLOW_OEN : R/W; bitpos: [2]; default: 0; + * need_des + */ +#define LP_CLKRST_CLK_AON_SLOW_OEN (BIT(2)) +#define LP_CLKRST_CLK_AON_SLOW_OEN_M (LP_CLKRST_CLK_AON_SLOW_OEN_V << LP_CLKRST_CLK_AON_SLOW_OEN_S) +#define LP_CLKRST_CLK_AON_SLOW_OEN_V 0x00000001U +#define LP_CLKRST_CLK_AON_SLOW_OEN_S 2 +/** LP_CLKRST_CLK_AON_FAST_OEN : R/W; bitpos: [3]; default: 0; + * need_des + */ +#define LP_CLKRST_CLK_AON_FAST_OEN (BIT(3)) +#define LP_CLKRST_CLK_AON_FAST_OEN_M (LP_CLKRST_CLK_AON_FAST_OEN_V << LP_CLKRST_CLK_AON_FAST_OEN_S) +#define LP_CLKRST_CLK_AON_FAST_OEN_V 0x00000001U +#define LP_CLKRST_CLK_AON_FAST_OEN_S 3 +/** LP_CLKRST_CLK_SLOW_OEN : R/W; bitpos: [4]; default: 0; + * need_des + */ +#define LP_CLKRST_CLK_SLOW_OEN (BIT(4)) +#define LP_CLKRST_CLK_SLOW_OEN_M (LP_CLKRST_CLK_SLOW_OEN_V << LP_CLKRST_CLK_SLOW_OEN_S) +#define LP_CLKRST_CLK_SLOW_OEN_V 0x00000001U +#define LP_CLKRST_CLK_SLOW_OEN_S 4 +/** LP_CLKRST_CLK_FAST_OEN : R/W; bitpos: [5]; default: 0; + * need_des + */ +#define LP_CLKRST_CLK_FAST_OEN (BIT(5)) +#define LP_CLKRST_CLK_FAST_OEN_M (LP_CLKRST_CLK_FAST_OEN_V << LP_CLKRST_CLK_FAST_OEN_S) +#define LP_CLKRST_CLK_FAST_OEN_V 0x00000001U +#define LP_CLKRST_CLK_FAST_OEN_S 5 +/** LP_CLKRST_CLK_FOSC_OEN : R/W; bitpos: [6]; default: 0; + * need_des + */ +#define LP_CLKRST_CLK_FOSC_OEN (BIT(6)) +#define LP_CLKRST_CLK_FOSC_OEN_M (LP_CLKRST_CLK_FOSC_OEN_V << LP_CLKRST_CLK_FOSC_OEN_S) +#define LP_CLKRST_CLK_FOSC_OEN_V 0x00000001U +#define LP_CLKRST_CLK_FOSC_OEN_S 6 +/** LP_CLKRST_CLK_RC32K_OEN : R/W; bitpos: [7]; default: 0; + * need_des + */ +#define LP_CLKRST_CLK_RC32K_OEN (BIT(7)) +#define LP_CLKRST_CLK_RC32K_OEN_M (LP_CLKRST_CLK_RC32K_OEN_V << LP_CLKRST_CLK_RC32K_OEN_S) +#define LP_CLKRST_CLK_RC32K_OEN_V 0x00000001U +#define LP_CLKRST_CLK_RC32K_OEN_S 7 +/** LP_CLKRST_CLK_SXTAL_OEN : R/W; bitpos: [8]; default: 0; + * need_des + */ +#define LP_CLKRST_CLK_SXTAL_OEN (BIT(8)) +#define LP_CLKRST_CLK_SXTAL_OEN_M (LP_CLKRST_CLK_SXTAL_OEN_V << LP_CLKRST_CLK_SXTAL_OEN_S) +#define LP_CLKRST_CLK_SXTAL_OEN_V 0x00000001U +#define LP_CLKRST_CLK_SXTAL_OEN_S 8 +/** LP_CLKRST_CLK_SOSC_OEN : R/W; bitpos: [9]; default: 0; + * 1'b1: probe sosc clk on + * 1'b0: probe sosc clk off + */ +#define LP_CLKRST_CLK_SOSC_OEN (BIT(9)) +#define LP_CLKRST_CLK_SOSC_OEN_M (LP_CLKRST_CLK_SOSC_OEN_V << LP_CLKRST_CLK_SOSC_OEN_S) +#define LP_CLKRST_CLK_SOSC_OEN_V 0x00000001U +#define LP_CLKRST_CLK_SOSC_OEN_S 9 + +/** LP_CLKRST_LP_CLK_EN_REG register + * need_des + */ +#define LP_CLKRST_LP_CLK_EN_REG (DR_REG_LP_CLKRST_BASE + 0x8) +/** LP_CLKRST_LP_RTC_XTAL_FORCE_ON : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_RTC_XTAL_FORCE_ON (BIT(26)) +#define LP_CLKRST_LP_RTC_XTAL_FORCE_ON_M (LP_CLKRST_LP_RTC_XTAL_FORCE_ON_V << LP_CLKRST_LP_RTC_XTAL_FORCE_ON_S) +#define LP_CLKRST_LP_RTC_XTAL_FORCE_ON_V 0x00000001U +#define LP_CLKRST_LP_RTC_XTAL_FORCE_ON_S 26 +/** LP_CLKRST_CK_EN_LP_RAM : R/W; bitpos: [27]; default: 1; + * need_des + */ +#define LP_CLKRST_CK_EN_LP_RAM (BIT(27)) +#define LP_CLKRST_CK_EN_LP_RAM_M (LP_CLKRST_CK_EN_LP_RAM_V << LP_CLKRST_CK_EN_LP_RAM_S) +#define LP_CLKRST_CK_EN_LP_RAM_V 0x00000001U +#define LP_CLKRST_CK_EN_LP_RAM_S 27 +/** LP_CLKRST_ETM_EVENT_TICK_EN : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define LP_CLKRST_ETM_EVENT_TICK_EN (BIT(28)) +#define LP_CLKRST_ETM_EVENT_TICK_EN_M (LP_CLKRST_ETM_EVENT_TICK_EN_V << LP_CLKRST_ETM_EVENT_TICK_EN_S) +#define LP_CLKRST_ETM_EVENT_TICK_EN_V 0x00000001U +#define LP_CLKRST_ETM_EVENT_TICK_EN_S 28 +/** LP_CLKRST_PLL8M_CLK_FORCE_ON : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define LP_CLKRST_PLL8M_CLK_FORCE_ON (BIT(29)) +#define LP_CLKRST_PLL8M_CLK_FORCE_ON_M (LP_CLKRST_PLL8M_CLK_FORCE_ON_V << LP_CLKRST_PLL8M_CLK_FORCE_ON_S) +#define LP_CLKRST_PLL8M_CLK_FORCE_ON_V 0x00000001U +#define LP_CLKRST_PLL8M_CLK_FORCE_ON_S 29 +/** LP_CLKRST_XTAL_CLK_FORCE_ON : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_CLKRST_XTAL_CLK_FORCE_ON (BIT(30)) +#define LP_CLKRST_XTAL_CLK_FORCE_ON_M (LP_CLKRST_XTAL_CLK_FORCE_ON_V << LP_CLKRST_XTAL_CLK_FORCE_ON_S) +#define LP_CLKRST_XTAL_CLK_FORCE_ON_V 0x00000001U +#define LP_CLKRST_XTAL_CLK_FORCE_ON_S 30 +/** LP_CLKRST_FOSC_CLK_FORCE_ON : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_CLKRST_FOSC_CLK_FORCE_ON (BIT(31)) +#define LP_CLKRST_FOSC_CLK_FORCE_ON_M (LP_CLKRST_FOSC_CLK_FORCE_ON_V << LP_CLKRST_FOSC_CLK_FORCE_ON_S) +#define LP_CLKRST_FOSC_CLK_FORCE_ON_V 0x00000001U +#define LP_CLKRST_FOSC_CLK_FORCE_ON_S 31 + +/** LP_CLKRST_LP_RST_EN_REG register + * need_des + */ +#define LP_CLKRST_LP_RST_EN_REG (DR_REG_LP_CLKRST_BASE + 0xc) +/** LP_CLKRST_RST_EN_LP_HUK : R/W; bitpos: [24]; default: 0; + * need_des + */ +#define LP_CLKRST_RST_EN_LP_HUK (BIT(24)) +#define LP_CLKRST_RST_EN_LP_HUK_M (LP_CLKRST_RST_EN_LP_HUK_V << LP_CLKRST_RST_EN_LP_HUK_S) +#define LP_CLKRST_RST_EN_LP_HUK_V 0x00000001U +#define LP_CLKRST_RST_EN_LP_HUK_S 24 +/** LP_CLKRST_RST_EN_LP_ANAPERI : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define LP_CLKRST_RST_EN_LP_ANAPERI (BIT(25)) +#define LP_CLKRST_RST_EN_LP_ANAPERI_M (LP_CLKRST_RST_EN_LP_ANAPERI_V << LP_CLKRST_RST_EN_LP_ANAPERI_S) +#define LP_CLKRST_RST_EN_LP_ANAPERI_V 0x00000001U +#define LP_CLKRST_RST_EN_LP_ANAPERI_S 25 +/** LP_CLKRST_RST_EN_LP_WDT : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define LP_CLKRST_RST_EN_LP_WDT (BIT(26)) +#define LP_CLKRST_RST_EN_LP_WDT_M (LP_CLKRST_RST_EN_LP_WDT_V << LP_CLKRST_RST_EN_LP_WDT_S) +#define LP_CLKRST_RST_EN_LP_WDT_V 0x00000001U +#define LP_CLKRST_RST_EN_LP_WDT_S 26 +/** LP_CLKRST_RST_EN_LP_TIMER : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define LP_CLKRST_RST_EN_LP_TIMER (BIT(27)) +#define LP_CLKRST_RST_EN_LP_TIMER_M (LP_CLKRST_RST_EN_LP_TIMER_V << LP_CLKRST_RST_EN_LP_TIMER_S) +#define LP_CLKRST_RST_EN_LP_TIMER_V 0x00000001U +#define LP_CLKRST_RST_EN_LP_TIMER_S 27 +/** LP_CLKRST_RST_EN_LP_RTC : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define LP_CLKRST_RST_EN_LP_RTC (BIT(28)) +#define LP_CLKRST_RST_EN_LP_RTC_M (LP_CLKRST_RST_EN_LP_RTC_V << LP_CLKRST_RST_EN_LP_RTC_S) +#define LP_CLKRST_RST_EN_LP_RTC_V 0x00000001U +#define LP_CLKRST_RST_EN_LP_RTC_S 28 +/** LP_CLKRST_RST_EN_LP_MAILBOX : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define LP_CLKRST_RST_EN_LP_MAILBOX (BIT(29)) +#define LP_CLKRST_RST_EN_LP_MAILBOX_M (LP_CLKRST_RST_EN_LP_MAILBOX_V << LP_CLKRST_RST_EN_LP_MAILBOX_S) +#define LP_CLKRST_RST_EN_LP_MAILBOX_V 0x00000001U +#define LP_CLKRST_RST_EN_LP_MAILBOX_S 29 +/** LP_CLKRST_RST_EN_LP_AONEFUSEREG : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_CLKRST_RST_EN_LP_AONEFUSEREG (BIT(30)) +#define LP_CLKRST_RST_EN_LP_AONEFUSEREG_M (LP_CLKRST_RST_EN_LP_AONEFUSEREG_V << LP_CLKRST_RST_EN_LP_AONEFUSEREG_S) +#define LP_CLKRST_RST_EN_LP_AONEFUSEREG_V 0x00000001U +#define LP_CLKRST_RST_EN_LP_AONEFUSEREG_S 30 +/** LP_CLKRST_RST_EN_LP_RAM : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_CLKRST_RST_EN_LP_RAM (BIT(31)) +#define LP_CLKRST_RST_EN_LP_RAM_M (LP_CLKRST_RST_EN_LP_RAM_V << LP_CLKRST_RST_EN_LP_RAM_S) +#define LP_CLKRST_RST_EN_LP_RAM_V 0x00000001U +#define LP_CLKRST_RST_EN_LP_RAM_S 31 + +/** LP_CLKRST_RESET_CAUSE_REG register + * need_des + */ +#define LP_CLKRST_RESET_CAUSE_REG (DR_REG_LP_CLKRST_BASE + 0x10) +/** LP_CLKRST_LPCORE_RESET_CAUSE : RO; bitpos: [5:0]; default: 0; + * 6'h1: POR reset + * 6'h9: PMU LP PERI power down reset + * 6'ha: PMU LP CPU reset + * 6'hf: brown out reset + * 6'h10: LP watchdog chip reset + * 6'h12: super watch dog reset + * 6'h13: glitch reset + * 6'h14: software reset + */ +#define LP_CLKRST_LPCORE_RESET_CAUSE 0x0000003FU +#define LP_CLKRST_LPCORE_RESET_CAUSE_M (LP_CLKRST_LPCORE_RESET_CAUSE_V << LP_CLKRST_LPCORE_RESET_CAUSE_S) +#define LP_CLKRST_LPCORE_RESET_CAUSE_V 0x0000003FU +#define LP_CLKRST_LPCORE_RESET_CAUSE_S 0 +/** LP_CLKRST_LPCORE_RESET_FLAG : RO; bitpos: [6]; default: 0; + * need_des + */ +#define LP_CLKRST_LPCORE_RESET_FLAG (BIT(6)) +#define LP_CLKRST_LPCORE_RESET_FLAG_M (LP_CLKRST_LPCORE_RESET_FLAG_V << LP_CLKRST_LPCORE_RESET_FLAG_S) +#define LP_CLKRST_LPCORE_RESET_FLAG_V 0x00000001U +#define LP_CLKRST_LPCORE_RESET_FLAG_S 6 +/** LP_CLKRST_HPCORE0_RESET_CAUSE : RO; bitpos: [12:7]; default: 0; + * 6'h1: POR reset + * 6'h3: digital system software reset + * 6'h5: PMU HP system power down reset + * 6'h7: HP system reset from HP watchdog + * 6'h9: HP system reset from LP watchdog + * 6'hb: HP core reset from HP watchdog + * 6'hc: HP core software reset + * 6'hd: HP core reset from LP watchdog + * 6'hf: brown out reset + * 6'h10: LP watchdog chip reset + * 6'h12: super watch dog reset + * 6'h13: glitch reset + * 6'h14: efuse crc error reset + * 6'h16: HP usb jtag chip reset + * 6'h17: HP usb uart chip reset + * 6'h18: HP jtag reset + * 6'h1a: HP core lockup + */ +#define LP_CLKRST_HPCORE0_RESET_CAUSE 0x0000003FU +#define LP_CLKRST_HPCORE0_RESET_CAUSE_M (LP_CLKRST_HPCORE0_RESET_CAUSE_V << LP_CLKRST_HPCORE0_RESET_CAUSE_S) +#define LP_CLKRST_HPCORE0_RESET_CAUSE_V 0x0000003FU +#define LP_CLKRST_HPCORE0_RESET_CAUSE_S 7 +/** LP_CLKRST_HPCORE0_RESET_FLAG : RO; bitpos: [13]; default: 0; + * need_des + */ +#define LP_CLKRST_HPCORE0_RESET_FLAG (BIT(13)) +#define LP_CLKRST_HPCORE0_RESET_FLAG_M (LP_CLKRST_HPCORE0_RESET_FLAG_V << LP_CLKRST_HPCORE0_RESET_FLAG_S) +#define LP_CLKRST_HPCORE0_RESET_FLAG_V 0x00000001U +#define LP_CLKRST_HPCORE0_RESET_FLAG_S 13 +/** LP_CLKRST_HPCORE1_RESET_CAUSE : RO; bitpos: [19:14]; default: 0; + * 6'h1: POR reset + * 6'h3: digital system software reset + * 6'h5: PMU HP system power down reset + * 6'h7: HP system reset from HP watchdog + * 6'h9: HP system reset from LP watchdog + * 6'hb: HP core reset from HP watchdog + * 6'hc: HP core software reset + * 6'hd: HP core reset from LP watchdog + * 6'hf: brown out reset + * 6'h10: LP watchdog chip reset + * 6'h12: super watch dog reset + * 6'h13: glitch reset + * 6'h14: efuse crc error reset + * 6'h16: HP usb jtag chip reset + * 6'h17: HP usb uart chip reset + * 6'h18: HP jtag reset + * 6'h1a: HP core lockup + */ +#define LP_CLKRST_HPCORE1_RESET_CAUSE 0x0000003FU +#define LP_CLKRST_HPCORE1_RESET_CAUSE_M (LP_CLKRST_HPCORE1_RESET_CAUSE_V << LP_CLKRST_HPCORE1_RESET_CAUSE_S) +#define LP_CLKRST_HPCORE1_RESET_CAUSE_V 0x0000003FU +#define LP_CLKRST_HPCORE1_RESET_CAUSE_S 14 +/** LP_CLKRST_HPCORE1_RESET_FLAG : RO; bitpos: [20]; default: 0; + * need_des + */ +#define LP_CLKRST_HPCORE1_RESET_FLAG (BIT(20)) +#define LP_CLKRST_HPCORE1_RESET_FLAG_M (LP_CLKRST_HPCORE1_RESET_FLAG_V << LP_CLKRST_HPCORE1_RESET_FLAG_S) +#define LP_CLKRST_HPCORE1_RESET_FLAG_V 0x00000001U +#define LP_CLKRST_HPCORE1_RESET_FLAG_S 20 +/** LP_CLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK : R/W; bitpos: [25]; default: 1; + * 1'b0: enable lpcore pmu_lp_cpu_reset reset_cause, 1'b1: disable lpcore + * pmu_lp_cpu_reset reset_cause + */ +#define LP_CLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK (BIT(25)) +#define LP_CLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_M (LP_CLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_V << LP_CLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_S) +#define LP_CLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_V 0x00000001U +#define LP_CLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_S 25 +/** LP_CLKRST_LPCORE_RESET_CAUSE_CLR : WT; bitpos: [26]; default: 0; + * need_des + */ +#define LP_CLKRST_LPCORE_RESET_CAUSE_CLR (BIT(26)) +#define LP_CLKRST_LPCORE_RESET_CAUSE_CLR_M (LP_CLKRST_LPCORE_RESET_CAUSE_CLR_V << LP_CLKRST_LPCORE_RESET_CAUSE_CLR_S) +#define LP_CLKRST_LPCORE_RESET_CAUSE_CLR_V 0x00000001U +#define LP_CLKRST_LPCORE_RESET_CAUSE_CLR_S 26 +/** LP_CLKRST_LPCORE_RESET_FLAG_CLR : WT; bitpos: [27]; default: 0; + * need_des + */ +#define LP_CLKRST_LPCORE_RESET_FLAG_CLR (BIT(27)) +#define LP_CLKRST_LPCORE_RESET_FLAG_CLR_M (LP_CLKRST_LPCORE_RESET_FLAG_CLR_V << LP_CLKRST_LPCORE_RESET_FLAG_CLR_S) +#define LP_CLKRST_LPCORE_RESET_FLAG_CLR_V 0x00000001U +#define LP_CLKRST_LPCORE_RESET_FLAG_CLR_S 27 +/** LP_CLKRST_HPCORE0_RESET_CAUSE_CLR : WT; bitpos: [28]; default: 0; + * need_des + */ +#define LP_CLKRST_HPCORE0_RESET_CAUSE_CLR (BIT(28)) +#define LP_CLKRST_HPCORE0_RESET_CAUSE_CLR_M (LP_CLKRST_HPCORE0_RESET_CAUSE_CLR_V << LP_CLKRST_HPCORE0_RESET_CAUSE_CLR_S) +#define LP_CLKRST_HPCORE0_RESET_CAUSE_CLR_V 0x00000001U +#define LP_CLKRST_HPCORE0_RESET_CAUSE_CLR_S 28 +/** LP_CLKRST_HPCORE0_RESET_FLAG_CLR : WT; bitpos: [29]; default: 0; + * need_des + */ +#define LP_CLKRST_HPCORE0_RESET_FLAG_CLR (BIT(29)) +#define LP_CLKRST_HPCORE0_RESET_FLAG_CLR_M (LP_CLKRST_HPCORE0_RESET_FLAG_CLR_V << LP_CLKRST_HPCORE0_RESET_FLAG_CLR_S) +#define LP_CLKRST_HPCORE0_RESET_FLAG_CLR_V 0x00000001U +#define LP_CLKRST_HPCORE0_RESET_FLAG_CLR_S 29 +/** LP_CLKRST_HPCORE1_RESET_CAUSE_CLR : WT; bitpos: [30]; default: 0; + * need_des + */ +#define LP_CLKRST_HPCORE1_RESET_CAUSE_CLR (BIT(30)) +#define LP_CLKRST_HPCORE1_RESET_CAUSE_CLR_M (LP_CLKRST_HPCORE1_RESET_CAUSE_CLR_V << LP_CLKRST_HPCORE1_RESET_CAUSE_CLR_S) +#define LP_CLKRST_HPCORE1_RESET_CAUSE_CLR_V 0x00000001U +#define LP_CLKRST_HPCORE1_RESET_CAUSE_CLR_S 30 +/** LP_CLKRST_HPCORE1_RESET_FLAG_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_CLKRST_HPCORE1_RESET_FLAG_CLR (BIT(31)) +#define LP_CLKRST_HPCORE1_RESET_FLAG_CLR_M (LP_CLKRST_HPCORE1_RESET_FLAG_CLR_V << LP_CLKRST_HPCORE1_RESET_FLAG_CLR_S) +#define LP_CLKRST_HPCORE1_RESET_FLAG_CLR_V 0x00000001U +#define LP_CLKRST_HPCORE1_RESET_FLAG_CLR_S 31 + +/** LP_CLKRST_HPCPU_RESET_CTRL0_REG register + * need_des + */ +#define LP_CLKRST_HPCPU_RESET_CTRL0_REG (DR_REG_LP_CLKRST_BASE + 0x14) +/** LP_CLKRST_HPCORE0_LOCKUP_RESET_EN : R/W; bitpos: [0]; default: 0; + * write 1 to enable hpcore0 lockup reset feature, write 0 to disable hpcore0 lockup + * reset feature + */ +#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN (BIT(0)) +#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_M (LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_V << LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_S) +#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_V 0x00000001U +#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_S 0 +/** LP_CLKRST_LP_WDT_HPCORE0_RESET_LENGTH : R/W; bitpos: [3:1]; default: 1; + * need_des + */ +#define LP_CLKRST_LP_WDT_HPCORE0_RESET_LENGTH 0x00000007U +#define LP_CLKRST_LP_WDT_HPCORE0_RESET_LENGTH_M (LP_CLKRST_LP_WDT_HPCORE0_RESET_LENGTH_V << LP_CLKRST_LP_WDT_HPCORE0_RESET_LENGTH_S) +#define LP_CLKRST_LP_WDT_HPCORE0_RESET_LENGTH_V 0x00000007U +#define LP_CLKRST_LP_WDT_HPCORE0_RESET_LENGTH_S 1 +/** LP_CLKRST_LP_WDT_HPCORE0_RESET_EN : R/W; bitpos: [4]; default: 0; + * write 1 to enable lp_wdt reset hpcore0 feature, write 0 to disable lp_wdt reset + * hpcore0 feature + */ +#define LP_CLKRST_LP_WDT_HPCORE0_RESET_EN (BIT(4)) +#define LP_CLKRST_LP_WDT_HPCORE0_RESET_EN_M (LP_CLKRST_LP_WDT_HPCORE0_RESET_EN_V << LP_CLKRST_LP_WDT_HPCORE0_RESET_EN_S) +#define LP_CLKRST_LP_WDT_HPCORE0_RESET_EN_V 0x00000001U +#define LP_CLKRST_LP_WDT_HPCORE0_RESET_EN_S 4 +/** LP_CLKRST_HPCORE0_STALL_WAIT : R/W; bitpos: [11:5]; default: 0; + * need_des + */ +#define LP_CLKRST_HPCORE0_STALL_WAIT 0x0000007FU +#define LP_CLKRST_HPCORE0_STALL_WAIT_M (LP_CLKRST_HPCORE0_STALL_WAIT_V << LP_CLKRST_HPCORE0_STALL_WAIT_S) +#define LP_CLKRST_HPCORE0_STALL_WAIT_V 0x0000007FU +#define LP_CLKRST_HPCORE0_STALL_WAIT_S 5 +/** LP_CLKRST_HPCORE0_STALL_EN : R/W; bitpos: [12]; default: 0; + * need_des + */ +#define LP_CLKRST_HPCORE0_STALL_EN (BIT(12)) +#define LP_CLKRST_HPCORE0_STALL_EN_M (LP_CLKRST_HPCORE0_STALL_EN_V << LP_CLKRST_HPCORE0_STALL_EN_S) +#define LP_CLKRST_HPCORE0_STALL_EN_V 0x00000001U +#define LP_CLKRST_HPCORE0_STALL_EN_S 12 +/** LP_CLKRST_HPCORE0_SW_RESET : WT; bitpos: [13]; default: 0; + * need_des + */ +#define LP_CLKRST_HPCORE0_SW_RESET (BIT(13)) +#define LP_CLKRST_HPCORE0_SW_RESET_M (LP_CLKRST_HPCORE0_SW_RESET_V << LP_CLKRST_HPCORE0_SW_RESET_S) +#define LP_CLKRST_HPCORE0_SW_RESET_V 0x00000001U +#define LP_CLKRST_HPCORE0_SW_RESET_S 13 +/** LP_CLKRST_HPCORE0_OCD_HALT_ON_RESET : R/W; bitpos: [14]; default: 0; + * need_des + */ +#define LP_CLKRST_HPCORE0_OCD_HALT_ON_RESET (BIT(14)) +#define LP_CLKRST_HPCORE0_OCD_HALT_ON_RESET_M (LP_CLKRST_HPCORE0_OCD_HALT_ON_RESET_V << LP_CLKRST_HPCORE0_OCD_HALT_ON_RESET_S) +#define LP_CLKRST_HPCORE0_OCD_HALT_ON_RESET_V 0x00000001U +#define LP_CLKRST_HPCORE0_OCD_HALT_ON_RESET_S 14 +/** LP_CLKRST_HPCORE0_STAT_VECTOR_SEL : R/W; bitpos: [15]; default: 1; + * 1'b1: boot from HP TCM ROM: 0x4FC00000 + * 1'b0: boot from LP TCM RAM: 0x50108000 + */ +#define LP_CLKRST_HPCORE0_STAT_VECTOR_SEL (BIT(15)) +#define LP_CLKRST_HPCORE0_STAT_VECTOR_SEL_M (LP_CLKRST_HPCORE0_STAT_VECTOR_SEL_V << LP_CLKRST_HPCORE0_STAT_VECTOR_SEL_S) +#define LP_CLKRST_HPCORE0_STAT_VECTOR_SEL_V 0x00000001U +#define LP_CLKRST_HPCORE0_STAT_VECTOR_SEL_S 15 +/** LP_CLKRST_HPCORE1_LOCKUP_RESET_EN : R/W; bitpos: [16]; default: 0; + * write 1 to enable hpcore1 lockup reset feature, write 0 to disable hpcore1 lockup + * reset feature + */ +#define LP_CLKRST_HPCORE1_LOCKUP_RESET_EN (BIT(16)) +#define LP_CLKRST_HPCORE1_LOCKUP_RESET_EN_M (LP_CLKRST_HPCORE1_LOCKUP_RESET_EN_V << LP_CLKRST_HPCORE1_LOCKUP_RESET_EN_S) +#define LP_CLKRST_HPCORE1_LOCKUP_RESET_EN_V 0x00000001U +#define LP_CLKRST_HPCORE1_LOCKUP_RESET_EN_S 16 +/** LP_CLKRST_LP_WDT_HPCORE1_RESET_LENGTH : R/W; bitpos: [19:17]; default: 1; + * need_des + */ +#define LP_CLKRST_LP_WDT_HPCORE1_RESET_LENGTH 0x00000007U +#define LP_CLKRST_LP_WDT_HPCORE1_RESET_LENGTH_M (LP_CLKRST_LP_WDT_HPCORE1_RESET_LENGTH_V << LP_CLKRST_LP_WDT_HPCORE1_RESET_LENGTH_S) +#define LP_CLKRST_LP_WDT_HPCORE1_RESET_LENGTH_V 0x00000007U +#define LP_CLKRST_LP_WDT_HPCORE1_RESET_LENGTH_S 17 +/** LP_CLKRST_LP_WDT_HPCORE1_RESET_EN : R/W; bitpos: [20]; default: 0; + * write 1 to enable lp_wdt reset hpcore1 feature, write 0 to disable lp_wdt reset + * hpcore1 feature + */ +#define LP_CLKRST_LP_WDT_HPCORE1_RESET_EN (BIT(20)) +#define LP_CLKRST_LP_WDT_HPCORE1_RESET_EN_M (LP_CLKRST_LP_WDT_HPCORE1_RESET_EN_V << LP_CLKRST_LP_WDT_HPCORE1_RESET_EN_S) +#define LP_CLKRST_LP_WDT_HPCORE1_RESET_EN_V 0x00000001U +#define LP_CLKRST_LP_WDT_HPCORE1_RESET_EN_S 20 +/** LP_CLKRST_HPCORE1_STALL_WAIT : R/W; bitpos: [27:21]; default: 0; + * need_des + */ +#define LP_CLKRST_HPCORE1_STALL_WAIT 0x0000007FU +#define LP_CLKRST_HPCORE1_STALL_WAIT_M (LP_CLKRST_HPCORE1_STALL_WAIT_V << LP_CLKRST_HPCORE1_STALL_WAIT_S) +#define LP_CLKRST_HPCORE1_STALL_WAIT_V 0x0000007FU +#define LP_CLKRST_HPCORE1_STALL_WAIT_S 21 +/** LP_CLKRST_HPCORE1_STALL_EN : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define LP_CLKRST_HPCORE1_STALL_EN (BIT(28)) +#define LP_CLKRST_HPCORE1_STALL_EN_M (LP_CLKRST_HPCORE1_STALL_EN_V << LP_CLKRST_HPCORE1_STALL_EN_S) +#define LP_CLKRST_HPCORE1_STALL_EN_V 0x00000001U +#define LP_CLKRST_HPCORE1_STALL_EN_S 28 +/** LP_CLKRST_HPCORE1_SW_RESET : WT; bitpos: [29]; default: 0; + * need_des + */ +#define LP_CLKRST_HPCORE1_SW_RESET (BIT(29)) +#define LP_CLKRST_HPCORE1_SW_RESET_M (LP_CLKRST_HPCORE1_SW_RESET_V << LP_CLKRST_HPCORE1_SW_RESET_S) +#define LP_CLKRST_HPCORE1_SW_RESET_V 0x00000001U +#define LP_CLKRST_HPCORE1_SW_RESET_S 29 +/** LP_CLKRST_HPCORE1_OCD_HALT_ON_RESET : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_CLKRST_HPCORE1_OCD_HALT_ON_RESET (BIT(30)) +#define LP_CLKRST_HPCORE1_OCD_HALT_ON_RESET_M (LP_CLKRST_HPCORE1_OCD_HALT_ON_RESET_V << LP_CLKRST_HPCORE1_OCD_HALT_ON_RESET_S) +#define LP_CLKRST_HPCORE1_OCD_HALT_ON_RESET_V 0x00000001U +#define LP_CLKRST_HPCORE1_OCD_HALT_ON_RESET_S 30 +/** LP_CLKRST_HPCORE1_STAT_VECTOR_SEL : R/W; bitpos: [31]; default: 1; + * 1'b1: boot from HP TCM ROM: 0x4FC00000 + * 1'b0: boot from LP TCM RAM: 0x50108000 + */ +#define LP_CLKRST_HPCORE1_STAT_VECTOR_SEL (BIT(31)) +#define LP_CLKRST_HPCORE1_STAT_VECTOR_SEL_M (LP_CLKRST_HPCORE1_STAT_VECTOR_SEL_V << LP_CLKRST_HPCORE1_STAT_VECTOR_SEL_S) +#define LP_CLKRST_HPCORE1_STAT_VECTOR_SEL_V 0x00000001U +#define LP_CLKRST_HPCORE1_STAT_VECTOR_SEL_S 31 + +/** LP_CLKRST_HPCPU_RESET_CTRL1_REG register + * need_des + */ +#define LP_CLKRST_HPCPU_RESET_CTRL1_REG (DR_REG_LP_CLKRST_BASE + 0x18) +/** LP_CLKRST_HPCORE0_SW_STALL_CODE : R/W; bitpos: [23:16]; default: 0; + * HP core0 software stall when set to 8'h86 + */ +#define LP_CLKRST_HPCORE0_SW_STALL_CODE 0x000000FFU +#define LP_CLKRST_HPCORE0_SW_STALL_CODE_M (LP_CLKRST_HPCORE0_SW_STALL_CODE_V << LP_CLKRST_HPCORE0_SW_STALL_CODE_S) +#define LP_CLKRST_HPCORE0_SW_STALL_CODE_V 0x000000FFU +#define LP_CLKRST_HPCORE0_SW_STALL_CODE_S 16 +/** LP_CLKRST_HPCORE1_SW_STALL_CODE : R/W; bitpos: [31:24]; default: 0; + * HP core1 software stall when set to 8'h86 + */ +#define LP_CLKRST_HPCORE1_SW_STALL_CODE 0x000000FFU +#define LP_CLKRST_HPCORE1_SW_STALL_CODE_M (LP_CLKRST_HPCORE1_SW_STALL_CODE_V << LP_CLKRST_HPCORE1_SW_STALL_CODE_S) +#define LP_CLKRST_HPCORE1_SW_STALL_CODE_V 0x000000FFU +#define LP_CLKRST_HPCORE1_SW_STALL_CODE_S 24 + +/** LP_CLKRST_FOSC_CNTL_REG register + * need_des + */ +#define LP_CLKRST_FOSC_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x1c) +/** LP_CLKRST_FOSC_DFREQ : R/W; bitpos: [31:22]; default: 400; + * need_des + */ +#define LP_CLKRST_FOSC_DFREQ 0x000003FFU +#define LP_CLKRST_FOSC_DFREQ_M (LP_CLKRST_FOSC_DFREQ_V << LP_CLKRST_FOSC_DFREQ_S) +#define LP_CLKRST_FOSC_DFREQ_V 0x000003FFU +#define LP_CLKRST_FOSC_DFREQ_S 22 + +/** LP_CLKRST_RC32K_CNTL_REG register + * need_des + */ +#define LP_CLKRST_RC32K_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x20) +/** LP_CLKRST_RC32K_DFREQ : R/W; bitpos: [31:0]; default: 650; + * need_des + */ +#define LP_CLKRST_RC32K_DFREQ 0xFFFFFFFFU +#define LP_CLKRST_RC32K_DFREQ_M (LP_CLKRST_RC32K_DFREQ_V << LP_CLKRST_RC32K_DFREQ_S) +#define LP_CLKRST_RC32K_DFREQ_V 0xFFFFFFFFU +#define LP_CLKRST_RC32K_DFREQ_S 0 + +/** LP_CLKRST_SOSC_CNTL_REG register + * need_des + */ +#define LP_CLKRST_SOSC_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x24) +/** LP_CLKRST_SOSC_DFREQ : R/W; bitpos: [31:22]; default: 172; + * need_des + */ +#define LP_CLKRST_SOSC_DFREQ 0x000003FFU +#define LP_CLKRST_SOSC_DFREQ_M (LP_CLKRST_SOSC_DFREQ_V << LP_CLKRST_SOSC_DFREQ_S) +#define LP_CLKRST_SOSC_DFREQ_V 0x000003FFU +#define LP_CLKRST_SOSC_DFREQ_S 22 + +/** LP_CLKRST_CLK_TO_HP_REG register + * need_des + */ +#define LP_CLKRST_CLK_TO_HP_REG (DR_REG_LP_CLKRST_BASE + 0x28) +/** LP_CLKRST_ICG_HP_XTAL32K : R/W; bitpos: [28]; default: 1; + * reserved + */ +#define LP_CLKRST_ICG_HP_XTAL32K (BIT(28)) +#define LP_CLKRST_ICG_HP_XTAL32K_M (LP_CLKRST_ICG_HP_XTAL32K_V << LP_CLKRST_ICG_HP_XTAL32K_S) +#define LP_CLKRST_ICG_HP_XTAL32K_V 0x00000001U +#define LP_CLKRST_ICG_HP_XTAL32K_S 28 +/** LP_CLKRST_ICG_HP_SOSC : R/W; bitpos: [29]; default: 1; + * reserved + */ +#define LP_CLKRST_ICG_HP_SOSC (BIT(29)) +#define LP_CLKRST_ICG_HP_SOSC_M (LP_CLKRST_ICG_HP_SOSC_V << LP_CLKRST_ICG_HP_SOSC_S) +#define LP_CLKRST_ICG_HP_SOSC_V 0x00000001U +#define LP_CLKRST_ICG_HP_SOSC_S 29 +/** LP_CLKRST_ICG_HP_OSC32K : R/W; bitpos: [30]; default: 1; + * reserved + */ +#define LP_CLKRST_ICG_HP_OSC32K (BIT(30)) +#define LP_CLKRST_ICG_HP_OSC32K_M (LP_CLKRST_ICG_HP_OSC32K_V << LP_CLKRST_ICG_HP_OSC32K_S) +#define LP_CLKRST_ICG_HP_OSC32K_V 0x00000001U +#define LP_CLKRST_ICG_HP_OSC32K_S 30 +/** LP_CLKRST_ICG_HP_FOSC : R/W; bitpos: [31]; default: 1; + * reserved + */ +#define LP_CLKRST_ICG_HP_FOSC (BIT(31)) +#define LP_CLKRST_ICG_HP_FOSC_M (LP_CLKRST_ICG_HP_FOSC_V << LP_CLKRST_ICG_HP_FOSC_S) +#define LP_CLKRST_ICG_HP_FOSC_V 0x00000001U +#define LP_CLKRST_ICG_HP_FOSC_S 31 + +/** LP_CLKRST_LPMEM_FORCE_REG register + * need_des + */ +#define LP_CLKRST_LPMEM_FORCE_REG (DR_REG_LP_CLKRST_BASE + 0x2c) +/** LP_CLKRST_LPMEM_CLK_FORCE_ON : R/W; bitpos: [31]; default: 0; + * reserved + */ +#define LP_CLKRST_LPMEM_CLK_FORCE_ON (BIT(31)) +#define LP_CLKRST_LPMEM_CLK_FORCE_ON_M (LP_CLKRST_LPMEM_CLK_FORCE_ON_V << LP_CLKRST_LPMEM_CLK_FORCE_ON_S) +#define LP_CLKRST_LPMEM_CLK_FORCE_ON_V 0x00000001U +#define LP_CLKRST_LPMEM_CLK_FORCE_ON_S 31 + +/** LP_CLKRST_XTAL32K_REG register + * need_des + */ +#define LP_CLKRST_XTAL32K_REG (DR_REG_LP_CLKRST_BASE + 0x30) +/** LP_CLKRST_DRES_XTAL32K : R/W; bitpos: [24:22]; default: 3; + * need_des + */ +#define LP_CLKRST_DRES_XTAL32K 0x00000007U +#define LP_CLKRST_DRES_XTAL32K_M (LP_CLKRST_DRES_XTAL32K_V << LP_CLKRST_DRES_XTAL32K_S) +#define LP_CLKRST_DRES_XTAL32K_V 0x00000007U +#define LP_CLKRST_DRES_XTAL32K_S 22 +/** LP_CLKRST_DGM_XTAL32K : R/W; bitpos: [27:25]; default: 3; + * need_des + */ +#define LP_CLKRST_DGM_XTAL32K 0x00000007U +#define LP_CLKRST_DGM_XTAL32K_M (LP_CLKRST_DGM_XTAL32K_V << LP_CLKRST_DGM_XTAL32K_S) +#define LP_CLKRST_DGM_XTAL32K_V 0x00000007U +#define LP_CLKRST_DGM_XTAL32K_S 25 +/** LP_CLKRST_DBUF_XTAL32K : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define LP_CLKRST_DBUF_XTAL32K (BIT(28)) +#define LP_CLKRST_DBUF_XTAL32K_M (LP_CLKRST_DBUF_XTAL32K_V << LP_CLKRST_DBUF_XTAL32K_S) +#define LP_CLKRST_DBUF_XTAL32K_V 0x00000001U +#define LP_CLKRST_DBUF_XTAL32K_S 28 +/** LP_CLKRST_DAC_XTAL32K : R/W; bitpos: [31:29]; default: 3; + * need_des + */ +#define LP_CLKRST_DAC_XTAL32K 0x00000007U +#define LP_CLKRST_DAC_XTAL32K_M (LP_CLKRST_DAC_XTAL32K_V << LP_CLKRST_DAC_XTAL32K_S) +#define LP_CLKRST_DAC_XTAL32K_V 0x00000007U +#define LP_CLKRST_DAC_XTAL32K_S 29 + +/** LP_CLKRST_MUX_HPSYS_RESET_BYPASS_REG register + * need_des + */ +#define LP_CLKRST_MUX_HPSYS_RESET_BYPASS_REG (DR_REG_LP_CLKRST_BASE + 0x34) +/** LP_CLKRST_MUX_HPSYS_RESET_BYPASS : R/W; bitpos: [31:0]; default: 4294967295; + * reserved + */ +#define LP_CLKRST_MUX_HPSYS_RESET_BYPASS 0xFFFFFFFFU +#define LP_CLKRST_MUX_HPSYS_RESET_BYPASS_M (LP_CLKRST_MUX_HPSYS_RESET_BYPASS_V << LP_CLKRST_MUX_HPSYS_RESET_BYPASS_S) +#define LP_CLKRST_MUX_HPSYS_RESET_BYPASS_V 0xFFFFFFFFU +#define LP_CLKRST_MUX_HPSYS_RESET_BYPASS_S 0 + +/** LP_CLKRST_HPSYS_0_RESET_BYPASS_REG register + * need_des + */ +#define LP_CLKRST_HPSYS_0_RESET_BYPASS_REG (DR_REG_LP_CLKRST_BASE + 0x38) +/** LP_CLKRST_HPSYS_0_RESET_BYPASS : R/W; bitpos: [31:0]; default: 4294967295; + * reserved + */ +#define LP_CLKRST_HPSYS_0_RESET_BYPASS 0xFFFFFFFFU +#define LP_CLKRST_HPSYS_0_RESET_BYPASS_M (LP_CLKRST_HPSYS_0_RESET_BYPASS_V << LP_CLKRST_HPSYS_0_RESET_BYPASS_S) +#define LP_CLKRST_HPSYS_0_RESET_BYPASS_V 0xFFFFFFFFU +#define LP_CLKRST_HPSYS_0_RESET_BYPASS_S 0 + +/** LP_CLKRST_HPSYS_APM_RESET_BYPASS_REG register + * need_des + */ +#define LP_CLKRST_HPSYS_APM_RESET_BYPASS_REG (DR_REG_LP_CLKRST_BASE + 0x3c) +/** LP_CLKRST_HPSYS_APM_RESET_BYPASS : R/W; bitpos: [31:0]; default: 4294967295; + * reserved + */ +#define LP_CLKRST_HPSYS_APM_RESET_BYPASS 0xFFFFFFFFU +#define LP_CLKRST_HPSYS_APM_RESET_BYPASS_M (LP_CLKRST_HPSYS_APM_RESET_BYPASS_V << LP_CLKRST_HPSYS_APM_RESET_BYPASS_S) +#define LP_CLKRST_HPSYS_APM_RESET_BYPASS_V 0xFFFFFFFFU +#define LP_CLKRST_HPSYS_APM_RESET_BYPASS_S 0 + +/** LP_CLKRST_HP_CLK_CTRL_REG register + * HP Clock Control Register. + */ +#define LP_CLKRST_HP_CLK_CTRL_REG (DR_REG_LP_CLKRST_BASE + 0x40) +/** LP_CLKRST_HP_ROOT_CLK_SRC_SEL : R/W; bitpos: [1:0]; default: 0; + * HP SoC Root Clock Source Select. 2'd0: xtal_40m, 2'd1: cpll_400m, 2'd2: fosc_20m. + */ +#define LP_CLKRST_HP_ROOT_CLK_SRC_SEL 0x00000003U +#define LP_CLKRST_HP_ROOT_CLK_SRC_SEL_M (LP_CLKRST_HP_ROOT_CLK_SRC_SEL_V << LP_CLKRST_HP_ROOT_CLK_SRC_SEL_S) +#define LP_CLKRST_HP_ROOT_CLK_SRC_SEL_V 0x00000003U +#define LP_CLKRST_HP_ROOT_CLK_SRC_SEL_S 0 +/** LP_CLKRST_HP_ROOT_CLK_EN : R/W; bitpos: [2]; default: 1; + * HP SoC Root Clock Enable. + */ +#define LP_CLKRST_HP_ROOT_CLK_EN (BIT(2)) +#define LP_CLKRST_HP_ROOT_CLK_EN_M (LP_CLKRST_HP_ROOT_CLK_EN_V << LP_CLKRST_HP_ROOT_CLK_EN_S) +#define LP_CLKRST_HP_ROOT_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_ROOT_CLK_EN_S 2 +/** LP_CLKRST_HP_PAD_PARLIO_TX_CLK_EN : R/W; bitpos: [3]; default: 1; + * PARLIO TX Clock From Pad Enable. + */ +#define LP_CLKRST_HP_PAD_PARLIO_TX_CLK_EN (BIT(3)) +#define LP_CLKRST_HP_PAD_PARLIO_TX_CLK_EN_M (LP_CLKRST_HP_PAD_PARLIO_TX_CLK_EN_V << LP_CLKRST_HP_PAD_PARLIO_TX_CLK_EN_S) +#define LP_CLKRST_HP_PAD_PARLIO_TX_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_PAD_PARLIO_TX_CLK_EN_S 3 +/** LP_CLKRST_HP_PAD_PARLIO_RX_CLK_EN : R/W; bitpos: [4]; default: 1; + * PARLIO RX Clock From Pad Enable. + */ +#define LP_CLKRST_HP_PAD_PARLIO_RX_CLK_EN (BIT(4)) +#define LP_CLKRST_HP_PAD_PARLIO_RX_CLK_EN_M (LP_CLKRST_HP_PAD_PARLIO_RX_CLK_EN_V << LP_CLKRST_HP_PAD_PARLIO_RX_CLK_EN_S) +#define LP_CLKRST_HP_PAD_PARLIO_RX_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_PAD_PARLIO_RX_CLK_EN_S 4 +/** LP_CLKRST_HP_PAD_UART4_SLP_CLK_EN : R/W; bitpos: [5]; default: 1; + * UART4 SLP Clock From Pad Enable. + */ +#define LP_CLKRST_HP_PAD_UART4_SLP_CLK_EN (BIT(5)) +#define LP_CLKRST_HP_PAD_UART4_SLP_CLK_EN_M (LP_CLKRST_HP_PAD_UART4_SLP_CLK_EN_V << LP_CLKRST_HP_PAD_UART4_SLP_CLK_EN_S) +#define LP_CLKRST_HP_PAD_UART4_SLP_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_PAD_UART4_SLP_CLK_EN_S 5 +/** LP_CLKRST_HP_PAD_UART3_SLP_CLK_EN : R/W; bitpos: [6]; default: 1; + * UART3 SLP Clock From Pad Enable. + */ +#define LP_CLKRST_HP_PAD_UART3_SLP_CLK_EN (BIT(6)) +#define LP_CLKRST_HP_PAD_UART3_SLP_CLK_EN_M (LP_CLKRST_HP_PAD_UART3_SLP_CLK_EN_V << LP_CLKRST_HP_PAD_UART3_SLP_CLK_EN_S) +#define LP_CLKRST_HP_PAD_UART3_SLP_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_PAD_UART3_SLP_CLK_EN_S 6 +/** LP_CLKRST_HP_PAD_UART2_SLP_CLK_EN : R/W; bitpos: [7]; default: 1; + * UART2 SLP Clock From Pad Enable. + */ +#define LP_CLKRST_HP_PAD_UART2_SLP_CLK_EN (BIT(7)) +#define LP_CLKRST_HP_PAD_UART2_SLP_CLK_EN_M (LP_CLKRST_HP_PAD_UART2_SLP_CLK_EN_V << LP_CLKRST_HP_PAD_UART2_SLP_CLK_EN_S) +#define LP_CLKRST_HP_PAD_UART2_SLP_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_PAD_UART2_SLP_CLK_EN_S 7 +/** LP_CLKRST_HP_PAD_UART1_SLP_CLK_EN : R/W; bitpos: [8]; default: 1; + * UART1 SLP Clock From Pad Enable. + */ +#define LP_CLKRST_HP_PAD_UART1_SLP_CLK_EN (BIT(8)) +#define LP_CLKRST_HP_PAD_UART1_SLP_CLK_EN_M (LP_CLKRST_HP_PAD_UART1_SLP_CLK_EN_V << LP_CLKRST_HP_PAD_UART1_SLP_CLK_EN_S) +#define LP_CLKRST_HP_PAD_UART1_SLP_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_PAD_UART1_SLP_CLK_EN_S 8 +/** LP_CLKRST_HP_PAD_UART0_SLP_CLK_EN : R/W; bitpos: [9]; default: 1; + * UART0 SLP Clock From Pad Enable. + */ +#define LP_CLKRST_HP_PAD_UART0_SLP_CLK_EN (BIT(9)) +#define LP_CLKRST_HP_PAD_UART0_SLP_CLK_EN_M (LP_CLKRST_HP_PAD_UART0_SLP_CLK_EN_V << LP_CLKRST_HP_PAD_UART0_SLP_CLK_EN_S) +#define LP_CLKRST_HP_PAD_UART0_SLP_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_PAD_UART0_SLP_CLK_EN_S 9 +/** LP_CLKRST_HP_PAD_I2S2_MCLK_EN : R/W; bitpos: [10]; default: 1; + * I2S2 MCLK Clock From Pad Enable. + */ +#define LP_CLKRST_HP_PAD_I2S2_MCLK_EN (BIT(10)) +#define LP_CLKRST_HP_PAD_I2S2_MCLK_EN_M (LP_CLKRST_HP_PAD_I2S2_MCLK_EN_V << LP_CLKRST_HP_PAD_I2S2_MCLK_EN_S) +#define LP_CLKRST_HP_PAD_I2S2_MCLK_EN_V 0x00000001U +#define LP_CLKRST_HP_PAD_I2S2_MCLK_EN_S 10 +/** LP_CLKRST_HP_PAD_I2S1_MCLK_EN : R/W; bitpos: [11]; default: 1; + * I2S1 MCLK Clock From Pad Enable. + */ +#define LP_CLKRST_HP_PAD_I2S1_MCLK_EN (BIT(11)) +#define LP_CLKRST_HP_PAD_I2S1_MCLK_EN_M (LP_CLKRST_HP_PAD_I2S1_MCLK_EN_V << LP_CLKRST_HP_PAD_I2S1_MCLK_EN_S) +#define LP_CLKRST_HP_PAD_I2S1_MCLK_EN_V 0x00000001U +#define LP_CLKRST_HP_PAD_I2S1_MCLK_EN_S 11 +/** LP_CLKRST_HP_PAD_I2S0_MCLK_EN : R/W; bitpos: [12]; default: 1; + * I2S0 MCLK Clock From Pad Enable. + */ +#define LP_CLKRST_HP_PAD_I2S0_MCLK_EN (BIT(12)) +#define LP_CLKRST_HP_PAD_I2S0_MCLK_EN_M (LP_CLKRST_HP_PAD_I2S0_MCLK_EN_V << LP_CLKRST_HP_PAD_I2S0_MCLK_EN_S) +#define LP_CLKRST_HP_PAD_I2S0_MCLK_EN_V 0x00000001U +#define LP_CLKRST_HP_PAD_I2S0_MCLK_EN_S 12 +/** LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN : R/W; bitpos: [13]; default: 1; + * EMACS RX Clock From Pad Enable. + */ +#define LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN (BIT(13)) +#define LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN_M (LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN_V << LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN_S) +#define LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN_S 13 +/** LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN : R/W; bitpos: [14]; default: 1; + * EMACS TX Clock From Pad Enable. + */ +#define LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN (BIT(14)) +#define LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN_M (LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN_V << LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN_S) +#define LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN_S 14 +/** LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN : R/W; bitpos: [15]; default: 1; + * EMACS TXRX Clock From Pad Enable. + */ +#define LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN (BIT(15)) +#define LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN_M (LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN_V << LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN_S) +#define LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN_S 15 +/** LP_CLKRST_HP_XTAL_32K_CLK_EN : R/W; bitpos: [16]; default: 1; + * XTAL 32K Clock Enable. + */ +#define LP_CLKRST_HP_XTAL_32K_CLK_EN (BIT(16)) +#define LP_CLKRST_HP_XTAL_32K_CLK_EN_M (LP_CLKRST_HP_XTAL_32K_CLK_EN_V << LP_CLKRST_HP_XTAL_32K_CLK_EN_S) +#define LP_CLKRST_HP_XTAL_32K_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_XTAL_32K_CLK_EN_S 16 +/** LP_CLKRST_HP_RC_32K_CLK_EN : R/W; bitpos: [17]; default: 1; + * RC 32K Clock Enable. + */ +#define LP_CLKRST_HP_RC_32K_CLK_EN (BIT(17)) +#define LP_CLKRST_HP_RC_32K_CLK_EN_M (LP_CLKRST_HP_RC_32K_CLK_EN_V << LP_CLKRST_HP_RC_32K_CLK_EN_S) +#define LP_CLKRST_HP_RC_32K_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_RC_32K_CLK_EN_S 17 +/** LP_CLKRST_HP_SOSC_150K_CLK_EN : R/W; bitpos: [18]; default: 1; + * SOSC 150K Clock Enable. + */ +#define LP_CLKRST_HP_SOSC_150K_CLK_EN (BIT(18)) +#define LP_CLKRST_HP_SOSC_150K_CLK_EN_M (LP_CLKRST_HP_SOSC_150K_CLK_EN_V << LP_CLKRST_HP_SOSC_150K_CLK_EN_S) +#define LP_CLKRST_HP_SOSC_150K_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_SOSC_150K_CLK_EN_S 18 +/** LP_CLKRST_HP_PLL_8M_CLK_EN : R/W; bitpos: [19]; default: 1; + * PLL 8M Clock Enable. + */ +#define LP_CLKRST_HP_PLL_8M_CLK_EN (BIT(19)) +#define LP_CLKRST_HP_PLL_8M_CLK_EN_M (LP_CLKRST_HP_PLL_8M_CLK_EN_V << LP_CLKRST_HP_PLL_8M_CLK_EN_S) +#define LP_CLKRST_HP_PLL_8M_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_PLL_8M_CLK_EN_S 19 +/** LP_CLKRST_HP_AUDIO_PLL_CLK_EN : R/W; bitpos: [20]; default: 1; + * AUDIO PLL Clock Enable. + */ +#define LP_CLKRST_HP_AUDIO_PLL_CLK_EN (BIT(20)) +#define LP_CLKRST_HP_AUDIO_PLL_CLK_EN_M (LP_CLKRST_HP_AUDIO_PLL_CLK_EN_V << LP_CLKRST_HP_AUDIO_PLL_CLK_EN_S) +#define LP_CLKRST_HP_AUDIO_PLL_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_AUDIO_PLL_CLK_EN_S 20 +/** LP_CLKRST_HP_SDIO_PLL2_CLK_EN : R/W; bitpos: [21]; default: 1; + * SDIO PLL2 Clock Enable. + */ +#define LP_CLKRST_HP_SDIO_PLL2_CLK_EN (BIT(21)) +#define LP_CLKRST_HP_SDIO_PLL2_CLK_EN_M (LP_CLKRST_HP_SDIO_PLL2_CLK_EN_V << LP_CLKRST_HP_SDIO_PLL2_CLK_EN_S) +#define LP_CLKRST_HP_SDIO_PLL2_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_SDIO_PLL2_CLK_EN_S 21 +/** LP_CLKRST_HP_SDIO_PLL1_CLK_EN : R/W; bitpos: [22]; default: 1; + * SDIO PLL1 Clock Enable. + */ +#define LP_CLKRST_HP_SDIO_PLL1_CLK_EN (BIT(22)) +#define LP_CLKRST_HP_SDIO_PLL1_CLK_EN_M (LP_CLKRST_HP_SDIO_PLL1_CLK_EN_V << LP_CLKRST_HP_SDIO_PLL1_CLK_EN_S) +#define LP_CLKRST_HP_SDIO_PLL1_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_SDIO_PLL1_CLK_EN_S 22 +/** LP_CLKRST_HP_SDIO_PLL0_CLK_EN : R/W; bitpos: [23]; default: 1; + * SDIO PLL0 Clock Enable. + */ +#define LP_CLKRST_HP_SDIO_PLL0_CLK_EN (BIT(23)) +#define LP_CLKRST_HP_SDIO_PLL0_CLK_EN_M (LP_CLKRST_HP_SDIO_PLL0_CLK_EN_V << LP_CLKRST_HP_SDIO_PLL0_CLK_EN_S) +#define LP_CLKRST_HP_SDIO_PLL0_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_SDIO_PLL0_CLK_EN_S 23 +/** LP_CLKRST_HP_FOSC_20M_CLK_EN : R/W; bitpos: [24]; default: 1; + * FOSC 20M Clock Enable. + */ +#define LP_CLKRST_HP_FOSC_20M_CLK_EN (BIT(24)) +#define LP_CLKRST_HP_FOSC_20M_CLK_EN_M (LP_CLKRST_HP_FOSC_20M_CLK_EN_V << LP_CLKRST_HP_FOSC_20M_CLK_EN_S) +#define LP_CLKRST_HP_FOSC_20M_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_FOSC_20M_CLK_EN_S 24 +/** LP_CLKRST_HP_XTAL_40M_CLK_EN : R/W; bitpos: [25]; default: 1; + * XTAL 40M Clock Enable. + */ +#define LP_CLKRST_HP_XTAL_40M_CLK_EN (BIT(25)) +#define LP_CLKRST_HP_XTAL_40M_CLK_EN_M (LP_CLKRST_HP_XTAL_40M_CLK_EN_V << LP_CLKRST_HP_XTAL_40M_CLK_EN_S) +#define LP_CLKRST_HP_XTAL_40M_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_XTAL_40M_CLK_EN_S 25 +/** LP_CLKRST_HP_CPLL_400M_CLK_EN : R/W; bitpos: [26]; default: 1; + * CPLL 400M Clock Enable. + */ +#define LP_CLKRST_HP_CPLL_400M_CLK_EN (BIT(26)) +#define LP_CLKRST_HP_CPLL_400M_CLK_EN_M (LP_CLKRST_HP_CPLL_400M_CLK_EN_V << LP_CLKRST_HP_CPLL_400M_CLK_EN_S) +#define LP_CLKRST_HP_CPLL_400M_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_CPLL_400M_CLK_EN_S 26 +/** LP_CLKRST_HP_SPLL_480M_CLK_EN : R/W; bitpos: [27]; default: 1; + * SPLL 480M Clock Enable. + */ +#define LP_CLKRST_HP_SPLL_480M_CLK_EN (BIT(27)) +#define LP_CLKRST_HP_SPLL_480M_CLK_EN_M (LP_CLKRST_HP_SPLL_480M_CLK_EN_V << LP_CLKRST_HP_SPLL_480M_CLK_EN_S) +#define LP_CLKRST_HP_SPLL_480M_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_SPLL_480M_CLK_EN_S 27 +/** LP_CLKRST_HP_MPLL_500M_CLK_EN : R/W; bitpos: [28]; default: 1; + * MPLL 500M Clock Enable. + */ +#define LP_CLKRST_HP_MPLL_500M_CLK_EN (BIT(28)) +#define LP_CLKRST_HP_MPLL_500M_CLK_EN_M (LP_CLKRST_HP_MPLL_500M_CLK_EN_V << LP_CLKRST_HP_MPLL_500M_CLK_EN_S) +#define LP_CLKRST_HP_MPLL_500M_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_MPLL_500M_CLK_EN_S 28 + +/** LP_CLKRST_HP_USB_CLKRST_CTRL0_REG register + * HP USB Clock Reset Control Register. + */ +#define LP_CLKRST_HP_USB_CLKRST_CTRL0_REG (DR_REG_LP_CLKRST_BASE + 0x44) +/** LP_CLKRST_USB_OTG20_SLEEP_MODE : R/W; bitpos: [0]; default: 0; + * unused. + */ +#define LP_CLKRST_USB_OTG20_SLEEP_MODE (BIT(0)) +#define LP_CLKRST_USB_OTG20_SLEEP_MODE_M (LP_CLKRST_USB_OTG20_SLEEP_MODE_V << LP_CLKRST_USB_OTG20_SLEEP_MODE_S) +#define LP_CLKRST_USB_OTG20_SLEEP_MODE_V 0x00000001U +#define LP_CLKRST_USB_OTG20_SLEEP_MODE_S 0 +/** LP_CLKRST_USB_OTG20_BK_SYS_CLK_EN : R/W; bitpos: [1]; default: 1; + * unused. + */ +#define LP_CLKRST_USB_OTG20_BK_SYS_CLK_EN (BIT(1)) +#define LP_CLKRST_USB_OTG20_BK_SYS_CLK_EN_M (LP_CLKRST_USB_OTG20_BK_SYS_CLK_EN_V << LP_CLKRST_USB_OTG20_BK_SYS_CLK_EN_S) +#define LP_CLKRST_USB_OTG20_BK_SYS_CLK_EN_V 0x00000001U +#define LP_CLKRST_USB_OTG20_BK_SYS_CLK_EN_S 1 +/** LP_CLKRST_USB_OTG11_SLEEP_MODE : R/W; bitpos: [2]; default: 0; + * unused. + */ +#define LP_CLKRST_USB_OTG11_SLEEP_MODE (BIT(2)) +#define LP_CLKRST_USB_OTG11_SLEEP_MODE_M (LP_CLKRST_USB_OTG11_SLEEP_MODE_V << LP_CLKRST_USB_OTG11_SLEEP_MODE_S) +#define LP_CLKRST_USB_OTG11_SLEEP_MODE_V 0x00000001U +#define LP_CLKRST_USB_OTG11_SLEEP_MODE_S 2 +/** LP_CLKRST_USB_OTG11_BK_SYS_CLK_EN : R/W; bitpos: [3]; default: 1; + * unused. + */ +#define LP_CLKRST_USB_OTG11_BK_SYS_CLK_EN (BIT(3)) +#define LP_CLKRST_USB_OTG11_BK_SYS_CLK_EN_M (LP_CLKRST_USB_OTG11_BK_SYS_CLK_EN_V << LP_CLKRST_USB_OTG11_BK_SYS_CLK_EN_S) +#define LP_CLKRST_USB_OTG11_BK_SYS_CLK_EN_V 0x00000001U +#define LP_CLKRST_USB_OTG11_BK_SYS_CLK_EN_S 3 +/** LP_CLKRST_USB_OTG11_48M_CLK_EN : R/W; bitpos: [4]; default: 1; + * usb otg11 fs phy clock enable. + */ +#define LP_CLKRST_USB_OTG11_48M_CLK_EN (BIT(4)) +#define LP_CLKRST_USB_OTG11_48M_CLK_EN_M (LP_CLKRST_USB_OTG11_48M_CLK_EN_V << LP_CLKRST_USB_OTG11_48M_CLK_EN_S) +#define LP_CLKRST_USB_OTG11_48M_CLK_EN_V 0x00000001U +#define LP_CLKRST_USB_OTG11_48M_CLK_EN_S 4 +/** LP_CLKRST_USB_DEVICE_48M_CLK_EN : R/W; bitpos: [5]; default: 1; + * usb device fs phy clock enable. + */ +#define LP_CLKRST_USB_DEVICE_48M_CLK_EN (BIT(5)) +#define LP_CLKRST_USB_DEVICE_48M_CLK_EN_M (LP_CLKRST_USB_DEVICE_48M_CLK_EN_V << LP_CLKRST_USB_DEVICE_48M_CLK_EN_S) +#define LP_CLKRST_USB_DEVICE_48M_CLK_EN_V 0x00000001U +#define LP_CLKRST_USB_DEVICE_48M_CLK_EN_S 5 +/** LP_CLKRST_USB_48M_DIV_NUM : R/W; bitpos: [13:6]; default: 9; + * usb 480m to 25m divide number. + */ +#define LP_CLKRST_USB_48M_DIV_NUM 0x000000FFU +#define LP_CLKRST_USB_48M_DIV_NUM_M (LP_CLKRST_USB_48M_DIV_NUM_V << LP_CLKRST_USB_48M_DIV_NUM_S) +#define LP_CLKRST_USB_48M_DIV_NUM_V 0x000000FFU +#define LP_CLKRST_USB_48M_DIV_NUM_S 6 +/** LP_CLKRST_USB_25M_DIV_NUM : R/W; bitpos: [21:14]; default: 19; + * usb 500m to 25m divide number. + */ +#define LP_CLKRST_USB_25M_DIV_NUM 0x000000FFU +#define LP_CLKRST_USB_25M_DIV_NUM_M (LP_CLKRST_USB_25M_DIV_NUM_V << LP_CLKRST_USB_25M_DIV_NUM_S) +#define LP_CLKRST_USB_25M_DIV_NUM_V 0x000000FFU +#define LP_CLKRST_USB_25M_DIV_NUM_S 14 +/** LP_CLKRST_USB_12M_DIV_NUM : R/W; bitpos: [29:22]; default: 39; + * usb 480m to 12m divide number. + */ +#define LP_CLKRST_USB_12M_DIV_NUM 0x000000FFU +#define LP_CLKRST_USB_12M_DIV_NUM_M (LP_CLKRST_USB_12M_DIV_NUM_V << LP_CLKRST_USB_12M_DIV_NUM_S) +#define LP_CLKRST_USB_12M_DIV_NUM_V 0x000000FFU +#define LP_CLKRST_USB_12M_DIV_NUM_S 22 + +/** LP_CLKRST_HP_USB_CLKRST_CTRL1_REG register + * HP USB Clock Reset Control Register. + */ +#define LP_CLKRST_HP_USB_CLKRST_CTRL1_REG (DR_REG_LP_CLKRST_BASE + 0x48) +/** LP_CLKRST_RST_EN_USB_OTG20_ADP : R/W; bitpos: [0]; default: 0; + * usb otg20 adp reset en + */ +#define LP_CLKRST_RST_EN_USB_OTG20_ADP (BIT(0)) +#define LP_CLKRST_RST_EN_USB_OTG20_ADP_M (LP_CLKRST_RST_EN_USB_OTG20_ADP_V << LP_CLKRST_RST_EN_USB_OTG20_ADP_S) +#define LP_CLKRST_RST_EN_USB_OTG20_ADP_V 0x00000001U +#define LP_CLKRST_RST_EN_USB_OTG20_ADP_S 0 +/** LP_CLKRST_RST_EN_USB_OTG20_PHY : R/W; bitpos: [1]; default: 0; + * usb otg20 phy reset en + */ +#define LP_CLKRST_RST_EN_USB_OTG20_PHY (BIT(1)) +#define LP_CLKRST_RST_EN_USB_OTG20_PHY_M (LP_CLKRST_RST_EN_USB_OTG20_PHY_V << LP_CLKRST_RST_EN_USB_OTG20_PHY_S) +#define LP_CLKRST_RST_EN_USB_OTG20_PHY_V 0x00000001U +#define LP_CLKRST_RST_EN_USB_OTG20_PHY_S 1 +/** LP_CLKRST_RST_EN_USB_OTG20 : R/W; bitpos: [2]; default: 0; + * usb otg20 reset en + */ +#define LP_CLKRST_RST_EN_USB_OTG20 (BIT(2)) +#define LP_CLKRST_RST_EN_USB_OTG20_M (LP_CLKRST_RST_EN_USB_OTG20_V << LP_CLKRST_RST_EN_USB_OTG20_S) +#define LP_CLKRST_RST_EN_USB_OTG20_V 0x00000001U +#define LP_CLKRST_RST_EN_USB_OTG20_S 2 +/** LP_CLKRST_RST_EN_USB_OTG11 : R/W; bitpos: [3]; default: 0; + * usb org11 reset en + */ +#define LP_CLKRST_RST_EN_USB_OTG11 (BIT(3)) +#define LP_CLKRST_RST_EN_USB_OTG11_M (LP_CLKRST_RST_EN_USB_OTG11_V << LP_CLKRST_RST_EN_USB_OTG11_S) +#define LP_CLKRST_RST_EN_USB_OTG11_V 0x00000001U +#define LP_CLKRST_RST_EN_USB_OTG11_S 3 +/** LP_CLKRST_RST_EN_USB_DEVICE : R/W; bitpos: [4]; default: 0; + * usb device reset en + */ +#define LP_CLKRST_RST_EN_USB_DEVICE (BIT(4)) +#define LP_CLKRST_RST_EN_USB_DEVICE_M (LP_CLKRST_RST_EN_USB_DEVICE_V << LP_CLKRST_RST_EN_USB_DEVICE_S) +#define LP_CLKRST_RST_EN_USB_DEVICE_V 0x00000001U +#define LP_CLKRST_RST_EN_USB_DEVICE_S 4 +/** LP_CLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL : R/W; bitpos: [29:28]; default: 0; + * usb otg20 hs phy src sel. 2'd0: 12m, 2'd1: 25m, 2'd2: pad_hsphy_refclk. + */ +#define LP_CLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL 0x00000003U +#define LP_CLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL_M (LP_CLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL_V << LP_CLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL_S) +#define LP_CLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL_V 0x00000003U +#define LP_CLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL_S 28 +/** LP_CLKRST_USB_OTG20_PHYREF_CLK_EN : R/W; bitpos: [30]; default: 1; + * usb otg20 hs phy refclk enable. + */ +#define LP_CLKRST_USB_OTG20_PHYREF_CLK_EN (BIT(30)) +#define LP_CLKRST_USB_OTG20_PHYREF_CLK_EN_M (LP_CLKRST_USB_OTG20_PHYREF_CLK_EN_V << LP_CLKRST_USB_OTG20_PHYREF_CLK_EN_S) +#define LP_CLKRST_USB_OTG20_PHYREF_CLK_EN_V 0x00000001U +#define LP_CLKRST_USB_OTG20_PHYREF_CLK_EN_S 30 +/** LP_CLKRST_USB_OTG20_ULPI_CLK_EN : R/W; bitpos: [31]; default: 1; + * usb otg20 ulpi clock enable. + */ +#define LP_CLKRST_USB_OTG20_ULPI_CLK_EN (BIT(31)) +#define LP_CLKRST_USB_OTG20_ULPI_CLK_EN_M (LP_CLKRST_USB_OTG20_ULPI_CLK_EN_V << LP_CLKRST_USB_OTG20_ULPI_CLK_EN_S) +#define LP_CLKRST_USB_OTG20_ULPI_CLK_EN_V 0x00000001U +#define LP_CLKRST_USB_OTG20_ULPI_CLK_EN_S 31 + +/** LP_CLKRST_HP_SDMMC_EMAC_RST_CTRL_REG register + * need_des + */ +#define LP_CLKRST_HP_SDMMC_EMAC_RST_CTRL_REG (DR_REG_LP_CLKRST_BASE + 0x4c) +/** LP_CLKRST_RST_EN_SDMMC : R/W; bitpos: [28]; default: 0; + * hp sdmmc reset en + */ +#define LP_CLKRST_RST_EN_SDMMC (BIT(28)) +#define LP_CLKRST_RST_EN_SDMMC_M (LP_CLKRST_RST_EN_SDMMC_V << LP_CLKRST_RST_EN_SDMMC_S) +#define LP_CLKRST_RST_EN_SDMMC_V 0x00000001U +#define LP_CLKRST_RST_EN_SDMMC_S 28 +/** LP_CLKRST_FORCE_NORST_SDMMC : R/W; bitpos: [29]; default: 0; + * hp sdmmc force norst + */ +#define LP_CLKRST_FORCE_NORST_SDMMC (BIT(29)) +#define LP_CLKRST_FORCE_NORST_SDMMC_M (LP_CLKRST_FORCE_NORST_SDMMC_V << LP_CLKRST_FORCE_NORST_SDMMC_S) +#define LP_CLKRST_FORCE_NORST_SDMMC_V 0x00000001U +#define LP_CLKRST_FORCE_NORST_SDMMC_S 29 +/** LP_CLKRST_RST_EN_EMAC : R/W; bitpos: [30]; default: 0; + * hp emacs reset en + */ +#define LP_CLKRST_RST_EN_EMAC (BIT(30)) +#define LP_CLKRST_RST_EN_EMAC_M (LP_CLKRST_RST_EN_EMAC_V << LP_CLKRST_RST_EN_EMAC_S) +#define LP_CLKRST_RST_EN_EMAC_V 0x00000001U +#define LP_CLKRST_RST_EN_EMAC_S 30 +/** LP_CLKRST_FORCE_NORST_EMAC : R/W; bitpos: [31]; default: 0; + * hp emacs force norst + */ +#define LP_CLKRST_FORCE_NORST_EMAC (BIT(31)) +#define LP_CLKRST_FORCE_NORST_EMAC_M (LP_CLKRST_FORCE_NORST_EMAC_V << LP_CLKRST_FORCE_NORST_EMAC_S) +#define LP_CLKRST_FORCE_NORST_EMAC_V 0x00000001U +#define LP_CLKRST_FORCE_NORST_EMAC_S 31 + +/** LP_CLKRST_DATE_REG register + * need_des + */ +#define LP_CLKRST_DATE_REG (DR_REG_LP_CLKRST_BASE + 0x3fc) +/** LP_CLKRST_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_CLKRST_CLK_EN (BIT(31)) +#define LP_CLKRST_CLK_EN_M (LP_CLKRST_CLK_EN_V << LP_CLKRST_CLK_EN_S) +#define LP_CLKRST_CLK_EN_V 0x00000001U +#define LP_CLKRST_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/src/target/esp32p4/ld/esp32p4.rom.api.ld b/src/target/esp32p4/ld/esp32p4.rom.api.ld index dcb922d..7d42086 100644 --- a/src/target/esp32p4/ld/esp32p4.rom.api.ld +++ b/src/target/esp32p4/ld/esp32p4.rom.api.ld @@ -28,8 +28,8 @@ PROVIDE ( esp_rom_uart_putc = ets_write_char_uart ); PROVIDE ( esp_rom_uart_attach = uartAttach ); PROVIDE ( esp_rom_uart_init = Uart_Init ); PROVIDE ( esp_rom_uart_div_modify = uart_div_modify ); -PROVIDE ( esp_rom_get_apb_freq = ets_get_apb_freq ); PROVIDE ( esp_rom_get_cpu_freq = ets_clk_get_cpu_freq ); +PROVIDE ( esp_rom_get_xtal_freq = ets_clk_get_xtal_freq ); PROVIDE ( esp_rom_get_uart_device = GetUartDevice ); PROVIDE ( esp_rom_usb_serial_putc = uart_tx_one_char3 ); diff --git a/src/target/esp32p4/src/clock.c b/src/target/esp32p4/src/clock.c new file mode 100644 index 0000000..e4f6bd6 --- /dev/null +++ b/src/target/esp32p4/src/clock.c @@ -0,0 +1,34 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 OR MIT + */ + +#include +#include +#include +#include +#include +#include + +#define MHZ 1000000 + +extern uint32_t esp_rom_get_cpu_freq(void); +extern void esp_rom_set_cpu_ticks_per_us(uint32_t ticks_per_us); + +static uint32_t s_cpu_freq = 0; + +void stub_target_clock_init(void) +{ + REG_SET_FIELD(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_ROOT_CLK_SRC_SEL, 1); + s_cpu_freq = 320 * MHZ; + esp_rom_set_cpu_ticks_per_us(s_cpu_freq / MHZ); +} + +uint32_t stub_target_get_cpu_freq(void) +{ + if (s_cpu_freq == 0) { + return esp_rom_get_cpu_freq(); + } + return s_cpu_freq; +} diff --git a/src/target/esp32s2/CMakeLists.txt b/src/target/esp32s2/CMakeLists.txt index 6ca5b16..695452c 100644 --- a/src/target/esp32s2/CMakeLists.txt +++ b/src/target/esp32s2/CMakeLists.txt @@ -2,6 +2,7 @@ set(srcs src/trax.c src/uart.c src/security.c + src/clock.c ) add_library(${ESP_TARGET_LIB} STATIC ${srcs}) diff --git a/src/target/esp32s2/include/soc/rtc_cntl_reg.h b/src/target/esp32s2/include/soc/rtc_cntl_reg.h new file mode 100644 index 0000000..9fd452a --- /dev/null +++ b/src/target/esp32s2/include/soc/rtc_cntl_reg.h @@ -0,0 +1,3294 @@ +/* + * SPDX-FileCopyrightText: 2017-2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 OR MIT + */ + +#pragma once + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define RTC_CNTL_TIME0_REG RTC_CNTL_TIME_LOW0_REG +#define RTC_CNTL_TIME1_REG RTC_CNTL_TIME_HIGH0_REG + +#define RTC_CNTL_OPTIONS0_REG (DR_REG_RTCCNTL_BASE + 0x0000) +/* RTC_CNTL_SW_SYS_RST : WO ;bitpos:[31] ;default: 1'd0 ; */ +/*description: SW system reset*/ +#define RTC_CNTL_SW_SYS_RST (BIT(31)) +#define RTC_CNTL_SW_SYS_RST_M (BIT(31)) +#define RTC_CNTL_SW_SYS_RST_V 0x1 +#define RTC_CNTL_SW_SYS_RST_S 31 +/* RTC_CNTL_DG_WRAP_FORCE_NORST : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: digital core force no reset in deep sleep*/ +#define RTC_CNTL_DG_WRAP_FORCE_NORST (BIT(30)) +#define RTC_CNTL_DG_WRAP_FORCE_NORST_M (BIT(30)) +#define RTC_CNTL_DG_WRAP_FORCE_NORST_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_NORST_S 30 +/* RTC_CNTL_DG_WRAP_FORCE_RST : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: digital wrap force reset in deep sleep*/ +#define RTC_CNTL_DG_WRAP_FORCE_RST (BIT(29)) +#define RTC_CNTL_DG_WRAP_FORCE_RST_M (BIT(29)) +#define RTC_CNTL_DG_WRAP_FORCE_RST_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_RST_S 29 +/* RTC_CNTL_ANALOG_FORCE_NOISO : R/W ;bitpos:[28] ;default: 1'd1 ; */ +/*description: */ +#define RTC_CNTL_ANALOG_FORCE_NOISO (BIT(28)) +#define RTC_CNTL_ANALOG_FORCE_NOISO_M (BIT(28)) +#define RTC_CNTL_ANALOG_FORCE_NOISO_V 0x1 +#define RTC_CNTL_ANALOG_FORCE_NOISO_S 28 +/* RTC_CNTL_PLL_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */ +/*description: */ +#define RTC_CNTL_PLL_FORCE_NOISO (BIT(27)) +#define RTC_CNTL_PLL_FORCE_NOISO_M (BIT(27)) +#define RTC_CNTL_PLL_FORCE_NOISO_V 0x1 +#define RTC_CNTL_PLL_FORCE_NOISO_S 27 +/* RTC_CNTL_XTL_FORCE_NOISO : R/W ;bitpos:[26] ;default: 1'd1 ; */ +/*description: */ +#define RTC_CNTL_XTL_FORCE_NOISO (BIT(26)) +#define RTC_CNTL_XTL_FORCE_NOISO_M (BIT(26)) +#define RTC_CNTL_XTL_FORCE_NOISO_V 0x1 +#define RTC_CNTL_XTL_FORCE_NOISO_S 26 +/* RTC_CNTL_ANALOG_FORCE_ISO : R/W ;bitpos:[25] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_ANALOG_FORCE_ISO (BIT(25)) +#define RTC_CNTL_ANALOG_FORCE_ISO_M (BIT(25)) +#define RTC_CNTL_ANALOG_FORCE_ISO_V 0x1 +#define RTC_CNTL_ANALOG_FORCE_ISO_S 25 +/* RTC_CNTL_PLL_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_PLL_FORCE_ISO (BIT(24)) +#define RTC_CNTL_PLL_FORCE_ISO_M (BIT(24)) +#define RTC_CNTL_PLL_FORCE_ISO_V 0x1 +#define RTC_CNTL_PLL_FORCE_ISO_S 24 +/* RTC_CNTL_XTL_FORCE_ISO : R/W ;bitpos:[23] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_XTL_FORCE_ISO (BIT(23)) +#define RTC_CNTL_XTL_FORCE_ISO_M (BIT(23)) +#define RTC_CNTL_XTL_FORCE_ISO_V 0x1 +#define RTC_CNTL_XTL_FORCE_ISO_S 23 +/* RTC_CNTL_XTL_EN_WAIT : R/W ;bitpos:[17:14] ;default: 4'd2 ; */ +/*description: wait bias_sleep and current source wakeup*/ +#define RTC_CNTL_XTL_EN_WAIT 0x0000000F +#define RTC_CNTL_XTL_EN_WAIT_M ((RTC_CNTL_XTL_EN_WAIT_V)<<(RTC_CNTL_XTL_EN_WAIT_S)) +#define RTC_CNTL_XTL_EN_WAIT_V 0xF +#define RTC_CNTL_XTL_EN_WAIT_S 14 +/* RTC_CNTL_XTL_FORCE_PU : R/W ;bitpos:[13] ;default: 1'd1 ; */ +/*description: crystall force power up*/ +#define RTC_CNTL_XTL_FORCE_PU (BIT(13)) +#define RTC_CNTL_XTL_FORCE_PU_M (BIT(13)) +#define RTC_CNTL_XTL_FORCE_PU_V 0x1 +#define RTC_CNTL_XTL_FORCE_PU_S 13 +/* RTC_CNTL_XTL_FORCE_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: crystall force power down*/ +#define RTC_CNTL_XTL_FORCE_PD (BIT(12)) +#define RTC_CNTL_XTL_FORCE_PD_M (BIT(12)) +#define RTC_CNTL_XTL_FORCE_PD_V 0x1 +#define RTC_CNTL_XTL_FORCE_PD_S 12 +/* RTC_CNTL_BBPLL_FORCE_PU : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: BB_PLL force power up*/ +#define RTC_CNTL_BBPLL_FORCE_PU (BIT(11)) +#define RTC_CNTL_BBPLL_FORCE_PU_M (BIT(11)) +#define RTC_CNTL_BBPLL_FORCE_PU_V 0x1 +#define RTC_CNTL_BBPLL_FORCE_PU_S 11 +/* RTC_CNTL_BBPLL_FORCE_PD : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: BB_PLL force power down*/ +#define RTC_CNTL_BBPLL_FORCE_PD (BIT(10)) +#define RTC_CNTL_BBPLL_FORCE_PD_M (BIT(10)) +#define RTC_CNTL_BBPLL_FORCE_PD_V 0x1 +#define RTC_CNTL_BBPLL_FORCE_PD_S 10 +/* RTC_CNTL_BBPLL_I2C_FORCE_PU : R/W ;bitpos:[9] ;default: 1'd0 ; */ +/*description: BB_PLL_I2C force power up*/ +#define RTC_CNTL_BBPLL_I2C_FORCE_PU (BIT(9)) +#define RTC_CNTL_BBPLL_I2C_FORCE_PU_M (BIT(9)) +#define RTC_CNTL_BBPLL_I2C_FORCE_PU_V 0x1 +#define RTC_CNTL_BBPLL_I2C_FORCE_PU_S 9 +/* RTC_CNTL_BBPLL_I2C_FORCE_PD : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: BB_PLL _I2C force power down*/ +#define RTC_CNTL_BBPLL_I2C_FORCE_PD (BIT(8)) +#define RTC_CNTL_BBPLL_I2C_FORCE_PD_M (BIT(8)) +#define RTC_CNTL_BBPLL_I2C_FORCE_PD_V 0x1 +#define RTC_CNTL_BBPLL_I2C_FORCE_PD_S 8 +/* RTC_CNTL_BB_I2C_FORCE_PU : R/W ;bitpos:[7] ;default: 1'd0 ; */ +/*description: BB_I2C force power up*/ +#define RTC_CNTL_BB_I2C_FORCE_PU (BIT(7)) +#define RTC_CNTL_BB_I2C_FORCE_PU_M (BIT(7)) +#define RTC_CNTL_BB_I2C_FORCE_PU_V 0x1 +#define RTC_CNTL_BB_I2C_FORCE_PU_S 7 +/* RTC_CNTL_BB_I2C_FORCE_PD : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: BB_I2C force power down*/ +#define RTC_CNTL_BB_I2C_FORCE_PD (BIT(6)) +#define RTC_CNTL_BB_I2C_FORCE_PD_M (BIT(6)) +#define RTC_CNTL_BB_I2C_FORCE_PD_V 0x1 +#define RTC_CNTL_BB_I2C_FORCE_PD_S 6 +/* RTC_CNTL_SW_PROCPU_RST : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: PRO CPU SW reset*/ +#define RTC_CNTL_SW_PROCPU_RST (BIT(5)) +#define RTC_CNTL_SW_PROCPU_RST_M (BIT(5)) +#define RTC_CNTL_SW_PROCPU_RST_V 0x1 +#define RTC_CNTL_SW_PROCPU_RST_S 5 +/* RTC_CNTL_SW_APPCPU_RST : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: APP CPU SW reset*/ +#define RTC_CNTL_SW_APPCPU_RST (BIT(4)) +#define RTC_CNTL_SW_APPCPU_RST_M (BIT(4)) +#define RTC_CNTL_SW_APPCPU_RST_V 0x1 +#define RTC_CNTL_SW_APPCPU_RST_S 4 +/* RTC_CNTL_SW_STALL_PROCPU_C0 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */ +/*description: {reg_sw_stall_procpu_c1[5:0] reg_sw_stall_procpu_c0[1:0]} == + 0x86 will stall PRO CPU*/ +#define RTC_CNTL_SW_STALL_PROCPU_C0 0x00000003 +#define RTC_CNTL_SW_STALL_PROCPU_C0_M ((RTC_CNTL_SW_STALL_PROCPU_C0_V)<<(RTC_CNTL_SW_STALL_PROCPU_C0_S)) +#define RTC_CNTL_SW_STALL_PROCPU_C0_V 0x3 +#define RTC_CNTL_SW_STALL_PROCPU_C0_S 2 +/* RTC_CNTL_SW_STALL_APPCPU_C0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: {reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == + 0x86 will stall APP CPU*/ +#define RTC_CNTL_SW_STALL_APPCPU_C0 0x00000003 +#define RTC_CNTL_SW_STALL_APPCPU_C0_M ((RTC_CNTL_SW_STALL_APPCPU_C0_V)<<(RTC_CNTL_SW_STALL_APPCPU_C0_S)) +#define RTC_CNTL_SW_STALL_APPCPU_C0_V 0x3 +#define RTC_CNTL_SW_STALL_APPCPU_C0_S 0 + +#define RTC_CNTL_SLP_TIMER0_REG (DR_REG_RTCCNTL_BASE + 0x0004) +/* RTC_CNTL_SLP_VAL_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: RTC sleep timer low 32 bits*/ +#define RTC_CNTL_SLP_VAL_LO 0xFFFFFFFF +#define RTC_CNTL_SLP_VAL_LO_M ((RTC_CNTL_SLP_VAL_LO_V)<<(RTC_CNTL_SLP_VAL_LO_S)) +#define RTC_CNTL_SLP_VAL_LO_V 0xFFFFFFFF +#define RTC_CNTL_SLP_VAL_LO_S 0 + +#define RTC_CNTL_SLP_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x0008) +/* RTC_CNTL_MAIN_TIMER_ALARM_EN : WO ;bitpos:[16] ;default: 1'h0 ; */ +/*description: timer alarm enable bit*/ +#define RTC_CNTL_MAIN_TIMER_ALARM_EN (BIT(16)) +#define RTC_CNTL_MAIN_TIMER_ALARM_EN_M (BIT(16)) +#define RTC_CNTL_MAIN_TIMER_ALARM_EN_V 0x1 +#define RTC_CNTL_MAIN_TIMER_ALARM_EN_S 16 +/* RTC_CNTL_SLP_VAL_HI : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: RTC sleep timer high 16 bits*/ +#define RTC_CNTL_SLP_VAL_HI 0x0000FFFF +#define RTC_CNTL_SLP_VAL_HI_M ((RTC_CNTL_SLP_VAL_HI_V)<<(RTC_CNTL_SLP_VAL_HI_S)) +#define RTC_CNTL_SLP_VAL_HI_V 0xFFFF +#define RTC_CNTL_SLP_VAL_HI_S 0 + +#define RTC_CNTL_TIME_UPDATE_REG (DR_REG_RTCCNTL_BASE + 0x000C) +/* RTC_CNTL_TIME_UPDATE : WO ;bitpos:[31] ;default: 1'h0 ; */ +/*description: Set 1: to update register with RTC timer*/ +#define RTC_CNTL_TIME_UPDATE (BIT(31)) +#define RTC_CNTL_TIME_UPDATE_M (BIT(31)) +#define RTC_CNTL_TIME_UPDATE_V 0x1 +#define RTC_CNTL_TIME_UPDATE_S 31 +/* RTC_CNTL_TIMER_SYS_RST : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: enable to record system reset time*/ +#define RTC_CNTL_TIMER_SYS_RST (BIT(29)) +#define RTC_CNTL_TIMER_SYS_RST_M (BIT(29)) +#define RTC_CNTL_TIMER_SYS_RST_V 0x1 +#define RTC_CNTL_TIMER_SYS_RST_S 29 +/* RTC_CNTL_TIMER_XTL_OFF : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: Enable to record 40M XTAL OFF time*/ +#define RTC_CNTL_TIMER_XTL_OFF (BIT(28)) +#define RTC_CNTL_TIMER_XTL_OFF_M (BIT(28)) +#define RTC_CNTL_TIMER_XTL_OFF_V 0x1 +#define RTC_CNTL_TIMER_XTL_OFF_S 28 +/* RTC_CNTL_TIMER_SYS_STALL : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: Enable to record system stall time*/ +#define RTC_CNTL_TIMER_SYS_STALL (BIT(27)) +#define RTC_CNTL_TIMER_SYS_STALL_M (BIT(27)) +#define RTC_CNTL_TIMER_SYS_STALL_V 0x1 +#define RTC_CNTL_TIMER_SYS_STALL_S 27 + +#define RTC_CNTL_TIME_LOW0_REG (DR_REG_RTCCNTL_BASE + 0x0010) +/* RTC_CNTL_TIMER_VALUE0_LOW : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: RTC timer low 32 bits*/ +#define RTC_CNTL_TIMER_VALUE0_LOW 0xFFFFFFFF +#define RTC_CNTL_TIMER_VALUE0_LOW_M ((RTC_CNTL_TIMER_VALUE0_LOW_V)<<(RTC_CNTL_TIMER_VALUE0_LOW_S)) +#define RTC_CNTL_TIMER_VALUE0_LOW_V 0xFFFFFFFF +#define RTC_CNTL_TIMER_VALUE0_LOW_S 0 + +#define RTC_CNTL_TIME_HIGH0_REG (DR_REG_RTCCNTL_BASE + 0x0014) +/* RTC_CNTL_TIMER_VALUE0_HIGH : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: RTC timer high 16 bits*/ +#define RTC_CNTL_TIMER_VALUE0_HIGH 0x0000FFFF +#define RTC_CNTL_TIMER_VALUE0_HIGH_M ((RTC_CNTL_TIMER_VALUE0_HIGH_V)<<(RTC_CNTL_TIMER_VALUE0_HIGH_S)) +#define RTC_CNTL_TIMER_VALUE0_HIGH_V 0xFFFF +#define RTC_CNTL_TIMER_VALUE0_HIGH_S 0 + +#define RTC_CNTL_STATE0_REG (DR_REG_RTCCNTL_BASE + 0x0018) +/* RTC_CNTL_SLEEP_EN : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: sleep enable bit*/ +#define RTC_CNTL_SLEEP_EN (BIT(31)) +#define RTC_CNTL_SLEEP_EN_M (BIT(31)) +#define RTC_CNTL_SLEEP_EN_V 0x1 +#define RTC_CNTL_SLEEP_EN_S 31 +/* RTC_CNTL_SLP_REJECT : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: leep reject bit*/ +#define RTC_CNTL_SLP_REJECT (BIT(30)) +#define RTC_CNTL_SLP_REJECT_M (BIT(30)) +#define RTC_CNTL_SLP_REJECT_V 0x1 +#define RTC_CNTL_SLP_REJECT_S 30 +/* RTC_CNTL_SLP_WAKEUP : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: leep wakeup bit*/ +#define RTC_CNTL_SLP_WAKEUP (BIT(29)) +#define RTC_CNTL_SLP_WAKEUP_M (BIT(29)) +#define RTC_CNTL_SLP_WAKEUP_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_S 29 +/* RTC_CNTL_SDIO_ACTIVE_IND : RO ;bitpos:[28] ;default: 1'd0 ; */ +/*description: SDIO active indication*/ +#define RTC_CNTL_SDIO_ACTIVE_IND (BIT(28)) +#define RTC_CNTL_SDIO_ACTIVE_IND_M (BIT(28)) +#define RTC_CNTL_SDIO_ACTIVE_IND_V 0x1 +#define RTC_CNTL_SDIO_ACTIVE_IND_S 28 +/* RTC_CNTL_APB2RTC_BRIDGE_SEL : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: 1: APB to RTC using bridge 0: APB to RTC using sync*/ +#define RTC_CNTL_APB2RTC_BRIDGE_SEL (BIT(22)) +#define RTC_CNTL_APB2RTC_BRIDGE_SEL_M (BIT(22)) +#define RTC_CNTL_APB2RTC_BRIDGE_SEL_V 0x1 +#define RTC_CNTL_APB2RTC_BRIDGE_SEL_S 22 +/* RTC_CNTL_SLP_REJECT_CAUSE_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: clear rtc sleep reject cause*/ +#define RTC_CNTL_SLP_REJECT_CAUSE_CLR (BIT(1)) +#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_V 0x1 +#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_S 1 +/* RTC_CNTL_SW_CPU_INT : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: rtc software interrupt to main cpu*/ +#define RTC_CNTL_SW_CPU_INT (BIT(0)) +#define RTC_CNTL_SW_CPU_INT_M (BIT(0)) +#define RTC_CNTL_SW_CPU_INT_V 0x1 +#define RTC_CNTL_SW_CPU_INT_S 0 + +#define RTC_CNTL_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x001C) +/* RTC_CNTL_PLL_BUF_WAIT : R/W ;bitpos:[31:24] ;default: 8'd40 ; */ +/*description: PLL wait cycles in slow_clk_rtc*/ +#define RTC_CNTL_PLL_BUF_WAIT 0x000000FF +#define RTC_CNTL_PLL_BUF_WAIT_M ((RTC_CNTL_PLL_BUF_WAIT_V)<<(RTC_CNTL_PLL_BUF_WAIT_S)) +#define RTC_CNTL_PLL_BUF_WAIT_V 0xFF +#define RTC_CNTL_PLL_BUF_WAIT_S 24 +/* RTC_CNTL_XTL_BUF_WAIT : R/W ;bitpos:[23:14] ;default: 10'd80 ; */ +/*description: XTAL wait cycles in slow_clk_rtc*/ +#define RTC_CNTL_XTL_BUF_WAIT 0x000003FF +#define RTC_CNTL_XTL_BUF_WAIT_M ((RTC_CNTL_XTL_BUF_WAIT_V)<<(RTC_CNTL_XTL_BUF_WAIT_S)) +#define RTC_CNTL_XTL_BUF_WAIT_V 0x3FF +#define RTC_CNTL_XTL_BUF_WAIT_S 14 +/* RTC_CNTL_CK8M_WAIT : R/W ;bitpos:[13:6] ;default: 8'h10 ; */ +/*description: CK8M wait cycles in slow_clk_rtc*/ +#define RTC_CNTL_CK8M_WAIT 0x000000FF +#define RTC_CNTL_CK8M_WAIT_M ((RTC_CNTL_CK8M_WAIT_V)<<(RTC_CNTL_CK8M_WAIT_S)) +#define RTC_CNTL_CK8M_WAIT_V 0xFF +#define RTC_CNTL_CK8M_WAIT_S 6 +/* RTC_CNTL_CPU_STALL_WAIT : R/W ;bitpos:[5:1] ;default: 5'd1 ; */ +/*description: CPU stall wait cycles in fast_clk_rtc*/ +#define RTC_CNTL_CPU_STALL_WAIT 0x0000001F +#define RTC_CNTL_CPU_STALL_WAIT_M ((RTC_CNTL_CPU_STALL_WAIT_V)<<(RTC_CNTL_CPU_STALL_WAIT_S)) +#define RTC_CNTL_CPU_STALL_WAIT_V 0x1F +#define RTC_CNTL_CPU_STALL_WAIT_S 1 +/* RTC_CNTL_CPU_STALL_EN : R/W ;bitpos:[0] ;default: 1'd1 ; */ +/*description: CPU stall enable bit*/ +#define RTC_CNTL_CPU_STALL_EN (BIT(0)) +#define RTC_CNTL_CPU_STALL_EN_M (BIT(0)) +#define RTC_CNTL_CPU_STALL_EN_V 0x1 +#define RTC_CNTL_CPU_STALL_EN_S 0 + +#define RTC_CNTL_TIMER2_REG (DR_REG_RTCCNTL_BASE + 0x0020) +/* RTC_CNTL_MIN_TIME_CK8M_OFF : R/W ;bitpos:[31:24] ;default: 8'h1 ; */ +/*description: minimal cycles in slow_clk_rtc for CK8M in power down state*/ +#define RTC_CNTL_MIN_TIME_CK8M_OFF 0x000000FF +#define RTC_CNTL_MIN_TIME_CK8M_OFF_M ((RTC_CNTL_MIN_TIME_CK8M_OFF_V)<<(RTC_CNTL_MIN_TIME_CK8M_OFF_S)) +#define RTC_CNTL_MIN_TIME_CK8M_OFF_V 0xFF +#define RTC_CNTL_MIN_TIME_CK8M_OFF_S 24 +/* RTC_CNTL_ULPCP_TOUCH_START_WAIT : R/W ;bitpos:[23:15] ;default: 9'h10 ; */ +/*description: wait cycles in slow_clk_rtc before ULP-coprocessor / touch controller + start to work*/ +#define RTC_CNTL_ULPCP_TOUCH_START_WAIT 0x000001FF +#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_M ((RTC_CNTL_ULPCP_TOUCH_START_WAIT_V)<<(RTC_CNTL_ULPCP_TOUCH_START_WAIT_S)) +#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_V 0x1FF +#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_S 15 + +#define RTC_CNTL_TIMER3_REG (DR_REG_RTCCNTL_BASE + 0x0024) +/* RTC_CNTL_ROM_RAM_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'd10 ; */ +/*description: */ +#define RTC_CNTL_ROM_RAM_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_ROM_RAM_POWERUP_TIMER_M ((RTC_CNTL_ROM_RAM_POWERUP_TIMER_V)<<(RTC_CNTL_ROM_RAM_POWERUP_TIMER_S)) +#define RTC_CNTL_ROM_RAM_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_ROM_RAM_POWERUP_TIMER_S 25 +/* RTC_CNTL_ROM_RAM_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h16 ; */ +/*description: */ +#define RTC_CNTL_ROM_RAM_WAIT_TIMER 0x000001FF +#define RTC_CNTL_ROM_RAM_WAIT_TIMER_M ((RTC_CNTL_ROM_RAM_WAIT_TIMER_V)<<(RTC_CNTL_ROM_RAM_WAIT_TIMER_S)) +#define RTC_CNTL_ROM_RAM_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_ROM_RAM_WAIT_TIMER_S 16 +/* RTC_CNTL_WIFI_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */ +/*description: */ +#define RTC_CNTL_WIFI_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_WIFI_POWERUP_TIMER_M ((RTC_CNTL_WIFI_POWERUP_TIMER_V)<<(RTC_CNTL_WIFI_POWERUP_TIMER_S)) +#define RTC_CNTL_WIFI_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_WIFI_POWERUP_TIMER_S 9 +/* RTC_CNTL_WIFI_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */ +/*description: */ +#define RTC_CNTL_WIFI_WAIT_TIMER 0x000001FF +#define RTC_CNTL_WIFI_WAIT_TIMER_M ((RTC_CNTL_WIFI_WAIT_TIMER_V)<<(RTC_CNTL_WIFI_WAIT_TIMER_S)) +#define RTC_CNTL_WIFI_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_WIFI_WAIT_TIMER_S 0 + +#define RTC_CNTL_TIMER4_REG (DR_REG_RTCCNTL_BASE + 0x0028) +/* RTC_CNTL_DG_WRAP_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h8 ; */ +/*description: */ +#define RTC_CNTL_DG_WRAP_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_M ((RTC_CNTL_DG_WRAP_POWERUP_TIMER_V)<<(RTC_CNTL_DG_WRAP_POWERUP_TIMER_S)) +#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_S 25 +/* RTC_CNTL_DG_WRAP_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h20 ; */ +/*description: */ +#define RTC_CNTL_DG_WRAP_WAIT_TIMER 0x000001FF +#define RTC_CNTL_DG_WRAP_WAIT_TIMER_M ((RTC_CNTL_DG_WRAP_WAIT_TIMER_V)<<(RTC_CNTL_DG_WRAP_WAIT_TIMER_S)) +#define RTC_CNTL_DG_WRAP_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_DG_WRAP_WAIT_TIMER_S 16 +/* RTC_CNTL_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */ +/*description: */ +#define RTC_CNTL_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_POWERUP_TIMER_M ((RTC_CNTL_POWERUP_TIMER_V)<<(RTC_CNTL_POWERUP_TIMER_S)) +#define RTC_CNTL_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_POWERUP_TIMER_S 9 +/* RTC_CNTL_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */ +/*description: */ +#define RTC_CNTL_WAIT_TIMER 0x000001FF +#define RTC_CNTL_WAIT_TIMER_M ((RTC_CNTL_WAIT_TIMER_V)<<(RTC_CNTL_WAIT_TIMER_S)) +#define RTC_CNTL_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_WAIT_TIMER_S 0 + +#define RTC_CNTL_TIMER5_REG (DR_REG_RTCCNTL_BASE + 0x002C) +/* RTC_CNTL_RTCMEM_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h9 ; */ +/*description: */ +#define RTC_CNTL_RTCMEM_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_RTCMEM_POWERUP_TIMER_M ((RTC_CNTL_RTCMEM_POWERUP_TIMER_V)<<(RTC_CNTL_RTCMEM_POWERUP_TIMER_S)) +#define RTC_CNTL_RTCMEM_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_RTCMEM_POWERUP_TIMER_S 25 +/* RTC_CNTL_RTCMEM_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h14 ; */ +/*description: */ +#define RTC_CNTL_RTCMEM_WAIT_TIMER 0x000001FF +#define RTC_CNTL_RTCMEM_WAIT_TIMER_M ((RTC_CNTL_RTCMEM_WAIT_TIMER_V)<<(RTC_CNTL_RTCMEM_WAIT_TIMER_S)) +#define RTC_CNTL_RTCMEM_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_RTCMEM_WAIT_TIMER_S 16 +/* RTC_CNTL_MIN_SLP_VAL : R/W ;bitpos:[15:8] ;default: 8'h80 ; */ +/*description: minimal sleep cycles in slow_clk_rtc*/ +#define RTC_CNTL_MIN_SLP_VAL 0x000000FF +#define RTC_CNTL_MIN_SLP_VAL_M ((RTC_CNTL_MIN_SLP_VAL_V)<<(RTC_CNTL_MIN_SLP_VAL_S)) +#define RTC_CNTL_MIN_SLP_VAL_V 0xFF +#define RTC_CNTL_MIN_SLP_VAL_S 8 + +#define RTC_CNTL_TIMER6_REG (DR_REG_RTCCNTL_BASE + 0x0030) +/* RTC_CNTL_DG_DCDC_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h8 ; */ +/*description: */ +#define RTC_CNTL_DG_DCDC_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_DG_DCDC_POWERUP_TIMER_M ((RTC_CNTL_DG_DCDC_POWERUP_TIMER_V)<<(RTC_CNTL_DG_DCDC_POWERUP_TIMER_S)) +#define RTC_CNTL_DG_DCDC_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_DG_DCDC_POWERUP_TIMER_S 25 +/* RTC_CNTL_DG_DCDC_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h20 ; */ +/*description: */ +#define RTC_CNTL_DG_DCDC_WAIT_TIMER 0x000001FF +#define RTC_CNTL_DG_DCDC_WAIT_TIMER_M ((RTC_CNTL_DG_DCDC_WAIT_TIMER_V)<<(RTC_CNTL_DG_DCDC_WAIT_TIMER_S)) +#define RTC_CNTL_DG_DCDC_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_DG_DCDC_WAIT_TIMER_S 16 + +#define RTC_CNTL_ANA_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0034) +/* RTC_CNTL_PLL_I2C_PU : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_PLL_I2C_PU (BIT(31)) +#define RTC_CNTL_PLL_I2C_PU_M (BIT(31)) +#define RTC_CNTL_PLL_I2C_PU_V 0x1 +#define RTC_CNTL_PLL_I2C_PU_S 31 +/* RTC_CNTL_CKGEN_I2C_PU : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: 1: CKGEN_I2C power up otherwise power down*/ +#define RTC_CNTL_CKGEN_I2C_PU (BIT(30)) +#define RTC_CNTL_CKGEN_I2C_PU_M (BIT(30)) +#define RTC_CNTL_CKGEN_I2C_PU_V 0x1 +#define RTC_CNTL_CKGEN_I2C_PU_S 30 +/* RTC_CNTL_RFRX_PBUS_PU : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: 1: RFRX_PBUS power up otherwise power down*/ +#define RTC_CNTL_RFRX_PBUS_PU (BIT(28)) +#define RTC_CNTL_RFRX_PBUS_PU_M (BIT(28)) +#define RTC_CNTL_RFRX_PBUS_PU_V 0x1 +#define RTC_CNTL_RFRX_PBUS_PU_S 28 +/* RTC_CNTL_TXRF_I2C_PU : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: 1: TXRF_I2C power up otherwise power down*/ +#define RTC_CNTL_TXRF_I2C_PU (BIT(27)) +#define RTC_CNTL_TXRF_I2C_PU_M (BIT(27)) +#define RTC_CNTL_TXRF_I2C_PU_V 0x1 +#define RTC_CNTL_TXRF_I2C_PU_S 27 +/* RTC_CNTL_PVTMON_PU : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: 1: PVTMON power up otherwise power down*/ +#define RTC_CNTL_PVTMON_PU (BIT(26)) +#define RTC_CNTL_PVTMON_PU_M (BIT(26)) +#define RTC_CNTL_PVTMON_PU_V 0x1 +#define RTC_CNTL_PVTMON_PU_S 26 +/* RTC_CNTL_BBPLL_CAL_SLP_START : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: start BBPLL calibration during sleep*/ +#define RTC_CNTL_BBPLL_CAL_SLP_START (BIT(25)) +#define RTC_CNTL_BBPLL_CAL_SLP_START_M (BIT(25)) +#define RTC_CNTL_BBPLL_CAL_SLP_START_V 0x1 +#define RTC_CNTL_BBPLL_CAL_SLP_START_S 25 +/* RTC_CNTL_PLLA_FORCE_PU : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: PLLA force power up*/ +#define RTC_CNTL_PLLA_FORCE_PU (BIT(24)) +#define RTC_CNTL_PLLA_FORCE_PU_M (BIT(24)) +#define RTC_CNTL_PLLA_FORCE_PU_V 0x1 +#define RTC_CNTL_PLLA_FORCE_PU_S 24 +/* RTC_CNTL_PLLA_FORCE_PD : R/W ;bitpos:[23] ;default: 1'b1 ; */ +/*description: PLLA force power down*/ +#define RTC_CNTL_PLLA_FORCE_PD (BIT(23)) +#define RTC_CNTL_PLLA_FORCE_PD_M (BIT(23)) +#define RTC_CNTL_PLLA_FORCE_PD_V 0x1 +#define RTC_CNTL_PLLA_FORCE_PD_S 23 +/* RTC_CNTL_SAR_I2C_FORCE_PU : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: PLLA force power up*/ +#define RTC_CNTL_SAR_I2C_FORCE_PU (BIT(22)) +#define RTC_CNTL_SAR_I2C_FORCE_PU_M (BIT(22)) +#define RTC_CNTL_SAR_I2C_FORCE_PU_V 0x1 +#define RTC_CNTL_SAR_I2C_FORCE_PU_S 22 +/* RTC_CNTL_SAR_I2C_FORCE_PD : R/W ;bitpos:[21] ;default: 1'b1 ; */ +/*description: PLLA force power down*/ +#define RTC_CNTL_SAR_I2C_FORCE_PD (BIT(21)) +#define RTC_CNTL_SAR_I2C_FORCE_PD_M (BIT(21)) +#define RTC_CNTL_SAR_I2C_FORCE_PD_V 0x1 +#define RTC_CNTL_SAR_I2C_FORCE_PD_S 21 +/* RTC_CNTL_GLITCH_RST_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_GLITCH_RST_EN (BIT(20)) +#define RTC_CNTL_GLITCH_RST_EN_M (BIT(20)) +#define RTC_CNTL_GLITCH_RST_EN_V 0x1 +#define RTC_CNTL_GLITCH_RST_EN_S 20 +/* RTC_CNTL_I2C_RESET_POR_FORCE_PU : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_I2C_RESET_POR_FORCE_PU (BIT(19)) +#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_M (BIT(19)) +#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_V 0x1 +#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_S 19 +/* RTC_CNTL_I2C_RESET_POR_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b1 ; */ +/*description: */ +#define RTC_CNTL_I2C_RESET_POR_FORCE_PD (BIT(18)) +#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_M (BIT(18)) +#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_V 0x1 +#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_S 18 + +#define RTC_CNTL_RESET_STATE_REG (DR_REG_RTCCNTL_BASE + 0x0038) +/* RTC_CNTL_PROCPU_STAT_VECTOR_SEL : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: PRO CPU state vector sel*/ +#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL (BIT(13)) +#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_M (BIT(13)) +#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_V 0x1 +#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_S 13 +/* RTC_CNTL_APPCPU_STAT_VECTOR_SEL : R/W ;bitpos:[12] ;default: 1'b1 ; */ +/*description: APP CPU state vector sel*/ +#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL (BIT(12)) +#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_M (BIT(12)) +#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_V 0x1 +#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_S 12 +/* RTC_CNTL_RESET_CAUSE_APPCPU : RO ;bitpos:[11:6] ;default: 0 ; */ +/*description: reset cause of APP CPU*/ +#define RTC_CNTL_RESET_CAUSE_APPCPU 0x0000003F +#define RTC_CNTL_RESET_CAUSE_APPCPU_M ((RTC_CNTL_RESET_CAUSE_APPCPU_V)<<(RTC_CNTL_RESET_CAUSE_APPCPU_S)) +#define RTC_CNTL_RESET_CAUSE_APPCPU_V 0x3F +#define RTC_CNTL_RESET_CAUSE_APPCPU_S 6 +/* RTC_CNTL_RESET_CAUSE_PROCPU : RO ;bitpos:[5:0] ;default: 0 ; */ +/*description: reset cause of PRO CPU*/ +#define RTC_CNTL_RESET_CAUSE_PROCPU 0x0000003F +#define RTC_CNTL_RESET_CAUSE_PROCPU_M ((RTC_CNTL_RESET_CAUSE_PROCPU_V)<<(RTC_CNTL_RESET_CAUSE_PROCPU_S)) +#define RTC_CNTL_RESET_CAUSE_PROCPU_V 0x3F +#define RTC_CNTL_RESET_CAUSE_PROCPU_S 0 + +#define RTC_CNTL_WAKEUP_STATE_REG (DR_REG_RTCCNTL_BASE + 0x003C) +/* RTC_CNTL_WAKEUP_ENA : R/W ;bitpos:[31:15] ;default: 17'b1100 ; */ +/*description: wakeup enable bitmap*/ +#define RTC_CNTL_WAKEUP_ENA 0x0001FFFF +#define RTC_CNTL_WAKEUP_ENA_M ((RTC_CNTL_WAKEUP_ENA_V)<<(RTC_CNTL_WAKEUP_ENA_S)) +#define RTC_CNTL_WAKEUP_ENA_V 0x1FFFF +#define RTC_CNTL_WAKEUP_ENA_S 15 + +#define RTC_CNTL_INT_ENA_REG (DR_REG_RTCCNTL_BASE + 0x0040) +/* RTC_CNTL_GLITCH_DET_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: enable gitch det interrupt*/ +#define RTC_CNTL_GLITCH_DET_INT_ENA (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ENA_M (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ENA_V 0x1 +#define RTC_CNTL_GLITCH_DET_INT_ENA_S 19 +/* RTC_CNTL_TOUCH_TIMEOUT_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: enable touch timeout interrupt*/ +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA (BIT(18)) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_M (BIT(18)) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_V 0x1 +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_S 18 +/* RTC_CNTL_COCPU_TRAP_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: enable cocpu trap interrupt*/ +#define RTC_CNTL_COCPU_TRAP_INT_ENA (BIT(17)) +#define RTC_CNTL_COCPU_TRAP_INT_ENA_M (BIT(17)) +#define RTC_CNTL_COCPU_TRAP_INT_ENA_V 0x1 +#define RTC_CNTL_COCPU_TRAP_INT_ENA_S 17 +/* RTC_CNTL_XTAL32K_DEAD_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: enable xtal32k_dead interrupt*/ +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_M (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_V 0x1 +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_S 16 +/* RTC_CNTL_SWD_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: enable super watch dog interrupt*/ +#define RTC_CNTL_SWD_INT_ENA (BIT(15)) +#define RTC_CNTL_SWD_INT_ENA_M (BIT(15)) +#define RTC_CNTL_SWD_INT_ENA_V 0x1 +#define RTC_CNTL_SWD_INT_ENA_S 15 +/* RTC_CNTL_SARADC2_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: enable saradc2 interrupt*/ +#define RTC_CNTL_SARADC2_INT_ENA (BIT(14)) +#define RTC_CNTL_SARADC2_INT_ENA_M (BIT(14)) +#define RTC_CNTL_SARADC2_INT_ENA_V 0x1 +#define RTC_CNTL_SARADC2_INT_ENA_S 14 +/* RTC_CNTL_COCPU_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: enable riscV cocpu interrupt*/ +#define RTC_CNTL_COCPU_INT_ENA (BIT(13)) +#define RTC_CNTL_COCPU_INT_ENA_M (BIT(13)) +#define RTC_CNTL_COCPU_INT_ENA_V 0x1 +#define RTC_CNTL_COCPU_INT_ENA_S 13 +/* RTC_CNTL_TSENS_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: enable tsens interrupt*/ +#define RTC_CNTL_TSENS_INT_ENA (BIT(12)) +#define RTC_CNTL_TSENS_INT_ENA_M (BIT(12)) +#define RTC_CNTL_TSENS_INT_ENA_V 0x1 +#define RTC_CNTL_TSENS_INT_ENA_S 12 +/* RTC_CNTL_SARADC1_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: enable saradc1 interrupt*/ +#define RTC_CNTL_SARADC1_INT_ENA (BIT(11)) +#define RTC_CNTL_SARADC1_INT_ENA_M (BIT(11)) +#define RTC_CNTL_SARADC1_INT_ENA_V 0x1 +#define RTC_CNTL_SARADC1_INT_ENA_S 11 +/* RTC_CNTL_MAIN_TIMER_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: enable RTC main timer interrupt*/ +#define RTC_CNTL_MAIN_TIMER_INT_ENA (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ENA_M (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ENA_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_ENA_S 10 +/* RTC_CNTL_BROWN_OUT_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: enable brown out interrupt*/ +#define RTC_CNTL_BROWN_OUT_INT_ENA (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ENA_M (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_ENA_S 9 +/* RTC_CNTL_TOUCH_INACTIVE_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: enable touch inactive interrupt*/ +#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA (BIT(8)) +#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_M (BIT(8)) +#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_V 0x1 +#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_S 8 +/* RTC_CNTL_TOUCH_ACTIVE_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: enable touch active interrupt*/ +#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA (BIT(7)) +#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_M (BIT(7)) +#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_V 0x1 +#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_S 7 +/* RTC_CNTL_TOUCH_DONE_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: enable touch done interrupt*/ +#define RTC_CNTL_TOUCH_DONE_INT_ENA (BIT(6)) +#define RTC_CNTL_TOUCH_DONE_INT_ENA_M (BIT(6)) +#define RTC_CNTL_TOUCH_DONE_INT_ENA_V 0x1 +#define RTC_CNTL_TOUCH_DONE_INT_ENA_S 6 +/* RTC_CNTL_ULP_CP_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: enable ULP-coprocessor interrupt*/ +#define RTC_CNTL_ULP_CP_INT_ENA (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_ENA_M (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_ENA_V 0x1 +#define RTC_CNTL_ULP_CP_INT_ENA_S 5 +/* RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: enable touch scan done interrupt*/ +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA (BIT(4)) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_M (BIT(4)) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_V 0x1 +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_S 4 +/* RTC_CNTL_WDT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: enable RTC WDT interrupt*/ +#define RTC_CNTL_WDT_INT_ENA (BIT(3)) +#define RTC_CNTL_WDT_INT_ENA_M (BIT(3)) +#define RTC_CNTL_WDT_INT_ENA_V 0x1 +#define RTC_CNTL_WDT_INT_ENA_S 3 +/* RTC_CNTL_SDIO_IDLE_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: enable SDIO idle interrupt*/ +#define RTC_CNTL_SDIO_IDLE_INT_ENA (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_ENA_M (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_ENA_V 0x1 +#define RTC_CNTL_SDIO_IDLE_INT_ENA_S 2 +/* RTC_CNTL_SLP_REJECT_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: enable sleep reject interrupt*/ +#define RTC_CNTL_SLP_REJECT_INT_ENA (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ENA_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ENA_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_ENA_S 1 +/* RTC_CNTL_SLP_WAKEUP_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: enable sleep wakeup interrupt*/ +#define RTC_CNTL_SLP_WAKEUP_INT_ENA (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_S 0 + +#define RTC_CNTL_INT_RAW_REG (DR_REG_RTCCNTL_BASE + 0x0044) +/* RTC_CNTL_GLITCH_DET_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: glitch_det_interrupt_raw*/ +#define RTC_CNTL_GLITCH_DET_INT_RAW (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_RAW_M (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_RAW_V 0x1 +#define RTC_CNTL_GLITCH_DET_INT_RAW_S 19 +/* RTC_CNTL_TOUCH_TIMEOUT_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: touch timeout interrupt raw*/ +#define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW (BIT(18)) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW_M (BIT(18)) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW_V 0x1 +#define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW_S 18 +/* RTC_CNTL_COCPU_TRAP_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: cocpu trap interrupt raw*/ +#define RTC_CNTL_COCPU_TRAP_INT_RAW (BIT(17)) +#define RTC_CNTL_COCPU_TRAP_INT_RAW_M (BIT(17)) +#define RTC_CNTL_COCPU_TRAP_INT_RAW_V 0x1 +#define RTC_CNTL_COCPU_TRAP_INT_RAW_S 17 +/* RTC_CNTL_XTAL32K_DEAD_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: xtal32k dead detection interrupt raw*/ +#define RTC_CNTL_XTAL32K_DEAD_INT_RAW (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_RAW_M (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_RAW_V 0x1 +#define RTC_CNTL_XTAL32K_DEAD_INT_RAW_S 16 +/* RTC_CNTL_SWD_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: super watch dog interrupt raw*/ +#define RTC_CNTL_SWD_INT_RAW (BIT(15)) +#define RTC_CNTL_SWD_INT_RAW_M (BIT(15)) +#define RTC_CNTL_SWD_INT_RAW_V 0x1 +#define RTC_CNTL_SWD_INT_RAW_S 15 +/* RTC_CNTL_SARADC2_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: saradc2 interrupt raw*/ +#define RTC_CNTL_SARADC2_INT_RAW (BIT(14)) +#define RTC_CNTL_SARADC2_INT_RAW_M (BIT(14)) +#define RTC_CNTL_SARADC2_INT_RAW_V 0x1 +#define RTC_CNTL_SARADC2_INT_RAW_S 14 +/* RTC_CNTL_COCPU_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: riscV cocpu interrupt raw*/ +#define RTC_CNTL_COCPU_INT_RAW (BIT(13)) +#define RTC_CNTL_COCPU_INT_RAW_M (BIT(13)) +#define RTC_CNTL_COCPU_INT_RAW_V 0x1 +#define RTC_CNTL_COCPU_INT_RAW_S 13 +/* RTC_CNTL_TSENS_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: tsens interrupt raw*/ +#define RTC_CNTL_TSENS_INT_RAW (BIT(12)) +#define RTC_CNTL_TSENS_INT_RAW_M (BIT(12)) +#define RTC_CNTL_TSENS_INT_RAW_V 0x1 +#define RTC_CNTL_TSENS_INT_RAW_S 12 +/* RTC_CNTL_SARADC1_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: saradc1 interrupt raw*/ +#define RTC_CNTL_SARADC1_INT_RAW (BIT(11)) +#define RTC_CNTL_SARADC1_INT_RAW_M (BIT(11)) +#define RTC_CNTL_SARADC1_INT_RAW_V 0x1 +#define RTC_CNTL_SARADC1_INT_RAW_S 11 +/* RTC_CNTL_MAIN_TIMER_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: RTC main timer interrupt raw*/ +#define RTC_CNTL_MAIN_TIMER_INT_RAW (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_RAW_M (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_RAW_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_RAW_S 10 +/* RTC_CNTL_BROWN_OUT_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: brown out interrupt raw*/ +#define RTC_CNTL_BROWN_OUT_INT_RAW (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_RAW_M (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_RAW_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_RAW_S 9 +/* RTC_CNTL_TOUCH_INACTIVE_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: touch inactive interrupt raw*/ +#define RTC_CNTL_TOUCH_INACTIVE_INT_RAW (BIT(8)) +#define RTC_CNTL_TOUCH_INACTIVE_INT_RAW_M (BIT(8)) +#define RTC_CNTL_TOUCH_INACTIVE_INT_RAW_V 0x1 +#define RTC_CNTL_TOUCH_INACTIVE_INT_RAW_S 8 +/* RTC_CNTL_TOUCH_ACTIVE_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: touch active interrupt raw*/ +#define RTC_CNTL_TOUCH_ACTIVE_INT_RAW (BIT(7)) +#define RTC_CNTL_TOUCH_ACTIVE_INT_RAW_M (BIT(7)) +#define RTC_CNTL_TOUCH_ACTIVE_INT_RAW_V 0x1 +#define RTC_CNTL_TOUCH_ACTIVE_INT_RAW_S 7 +/* RTC_CNTL_TOUCH_DONE_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: touch interrupt raw*/ +#define RTC_CNTL_TOUCH_DONE_INT_RAW (BIT(6)) +#define RTC_CNTL_TOUCH_DONE_INT_RAW_M (BIT(6)) +#define RTC_CNTL_TOUCH_DONE_INT_RAW_V 0x1 +#define RTC_CNTL_TOUCH_DONE_INT_RAW_S 6 +/* RTC_CNTL_ULP_CP_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: ULP-coprocessor interrupt raw*/ +#define RTC_CNTL_ULP_CP_INT_RAW (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_RAW_M (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_RAW_V 0x1 +#define RTC_CNTL_ULP_CP_INT_RAW_S 5 +/* RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW (BIT(4)) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW_M (BIT(4)) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW_V 0x1 +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW_S 4 +/* RTC_CNTL_WDT_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: RTC WDT interrupt raw*/ +#define RTC_CNTL_WDT_INT_RAW (BIT(3)) +#define RTC_CNTL_WDT_INT_RAW_M (BIT(3)) +#define RTC_CNTL_WDT_INT_RAW_V 0x1 +#define RTC_CNTL_WDT_INT_RAW_S 3 +/* RTC_CNTL_SDIO_IDLE_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: SDIO idle interrupt raw*/ +#define RTC_CNTL_SDIO_IDLE_INT_RAW (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_RAW_M (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_RAW_V 0x1 +#define RTC_CNTL_SDIO_IDLE_INT_RAW_S 2 +/* RTC_CNTL_SLP_REJECT_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: sleep reject interrupt raw*/ +#define RTC_CNTL_SLP_REJECT_INT_RAW (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_RAW_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_RAW_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_RAW_S 1 +/* RTC_CNTL_SLP_WAKEUP_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: sleep wakeup interrupt raw*/ +#define RTC_CNTL_SLP_WAKEUP_INT_RAW (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_RAW_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_RAW_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_RAW_S 0 + +#define RTC_CNTL_INT_ST_REG (DR_REG_RTCCNTL_BASE + 0x0048) +/* RTC_CNTL_GLITCH_DET_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: glitch_det_interrupt state*/ +#define RTC_CNTL_GLITCH_DET_INT_ST (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ST_M (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ST_V 0x1 +#define RTC_CNTL_GLITCH_DET_INT_ST_S 19 +/* RTC_CNTL_TOUCH_TIMEOUT_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: Touch timeout interrupt state*/ +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ST (BIT(18)) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ST_M (BIT(18)) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ST_V 0x1 +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ST_S 18 +/* RTC_CNTL_COCPU_TRAP_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: cocpu trap interrupt state*/ +#define RTC_CNTL_COCPU_TRAP_INT_ST (BIT(17)) +#define RTC_CNTL_COCPU_TRAP_INT_ST_M (BIT(17)) +#define RTC_CNTL_COCPU_TRAP_INT_ST_V 0x1 +#define RTC_CNTL_COCPU_TRAP_INT_ST_S 17 +/* RTC_CNTL_XTAL32K_DEAD_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: xtal32k dead detection interrupt state*/ +#define RTC_CNTL_XTAL32K_DEAD_INT_ST (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ST_M (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ST_V 0x1 +#define RTC_CNTL_XTAL32K_DEAD_INT_ST_S 16 +/* RTC_CNTL_SWD_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: super watch dog interrupt state*/ +#define RTC_CNTL_SWD_INT_ST (BIT(15)) +#define RTC_CNTL_SWD_INT_ST_M (BIT(15)) +#define RTC_CNTL_SWD_INT_ST_V 0x1 +#define RTC_CNTL_SWD_INT_ST_S 15 +/* RTC_CNTL_SARADC2_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: saradc2 interrupt state*/ +#define RTC_CNTL_SARADC2_INT_ST (BIT(14)) +#define RTC_CNTL_SARADC2_INT_ST_M (BIT(14)) +#define RTC_CNTL_SARADC2_INT_ST_V 0x1 +#define RTC_CNTL_SARADC2_INT_ST_S 14 +/* RTC_CNTL_COCPU_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: riscV cocpu interrupt state*/ +#define RTC_CNTL_COCPU_INT_ST (BIT(13)) +#define RTC_CNTL_COCPU_INT_ST_M (BIT(13)) +#define RTC_CNTL_COCPU_INT_ST_V 0x1 +#define RTC_CNTL_COCPU_INT_ST_S 13 +/* RTC_CNTL_TSENS_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: tsens interrupt state*/ +#define RTC_CNTL_TSENS_INT_ST (BIT(12)) +#define RTC_CNTL_TSENS_INT_ST_M (BIT(12)) +#define RTC_CNTL_TSENS_INT_ST_V 0x1 +#define RTC_CNTL_TSENS_INT_ST_S 12 +/* RTC_CNTL_SARADC1_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: saradc1 interrupt state*/ +#define RTC_CNTL_SARADC1_INT_ST (BIT(11)) +#define RTC_CNTL_SARADC1_INT_ST_M (BIT(11)) +#define RTC_CNTL_SARADC1_INT_ST_V 0x1 +#define RTC_CNTL_SARADC1_INT_ST_S 11 +/* RTC_CNTL_MAIN_TIMER_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: RTC main timer interrupt state*/ +#define RTC_CNTL_MAIN_TIMER_INT_ST (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ST_M (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ST_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_ST_S 10 +/* RTC_CNTL_BROWN_OUT_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: brown out interrupt state*/ +#define RTC_CNTL_BROWN_OUT_INT_ST (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ST_M (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ST_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_ST_S 9 +/* RTC_CNTL_TOUCH_INACTIVE_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: touch inactive interrupt state*/ +#define RTC_CNTL_TOUCH_INACTIVE_INT_ST (BIT(8)) +#define RTC_CNTL_TOUCH_INACTIVE_INT_ST_M (BIT(8)) +#define RTC_CNTL_TOUCH_INACTIVE_INT_ST_V 0x1 +#define RTC_CNTL_TOUCH_INACTIVE_INT_ST_S 8 +/* RTC_CNTL_TOUCH_ACTIVE_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: touch active interrupt state*/ +#define RTC_CNTL_TOUCH_ACTIVE_INT_ST (BIT(7)) +#define RTC_CNTL_TOUCH_ACTIVE_INT_ST_M (BIT(7)) +#define RTC_CNTL_TOUCH_ACTIVE_INT_ST_V 0x1 +#define RTC_CNTL_TOUCH_ACTIVE_INT_ST_S 7 +/* RTC_CNTL_TOUCH_DONE_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: touch done interrupt state*/ +#define RTC_CNTL_TOUCH_DONE_INT_ST (BIT(6)) +#define RTC_CNTL_TOUCH_DONE_INT_ST_M (BIT(6)) +#define RTC_CNTL_TOUCH_DONE_INT_ST_V 0x1 +#define RTC_CNTL_TOUCH_DONE_INT_ST_S 6 +/* RTC_CNTL_ULP_CP_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: ULP-coprocessor interrupt state*/ +#define RTC_CNTL_ULP_CP_INT_ST (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_ST_M (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_ST_V 0x1 +#define RTC_CNTL_ULP_CP_INT_ST_S 5 +/* RTC_CNTL_TOUCH_SCAN_DONE_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ST (BIT(4)) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ST_M (BIT(4)) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ST_V 0x1 +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ST_S 4 +/* RTC_CNTL_WDT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: RTC WDT interrupt state*/ +#define RTC_CNTL_WDT_INT_ST (BIT(3)) +#define RTC_CNTL_WDT_INT_ST_M (BIT(3)) +#define RTC_CNTL_WDT_INT_ST_V 0x1 +#define RTC_CNTL_WDT_INT_ST_S 3 +/* RTC_CNTL_SDIO_IDLE_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: SDIO idle interrupt state*/ +#define RTC_CNTL_SDIO_IDLE_INT_ST (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_ST_M (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_ST_V 0x1 +#define RTC_CNTL_SDIO_IDLE_INT_ST_S 2 +/* RTC_CNTL_SLP_REJECT_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: sleep reject interrupt state*/ +#define RTC_CNTL_SLP_REJECT_INT_ST (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ST_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ST_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_ST_S 1 +/* RTC_CNTL_SLP_WAKEUP_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: sleep wakeup interrupt state*/ +#define RTC_CNTL_SLP_WAKEUP_INT_ST (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ST_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ST_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_ST_S 0 + +#define RTC_CNTL_INT_CLR_REG (DR_REG_RTCCNTL_BASE + 0x004C) +/* RTC_CNTL_GLITCH_DET_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: Clear glitch det interrupt state*/ +#define RTC_CNTL_GLITCH_DET_INT_CLR (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_CLR_M (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_CLR_V 0x1 +#define RTC_CNTL_GLITCH_DET_INT_CLR_S 19 +/* RTC_CNTL_TOUCH_TIMEOUT_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: Clear touch timeout interrupt state*/ +#define RTC_CNTL_TOUCH_TIMEOUT_INT_CLR (BIT(18)) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_CLR_M (BIT(18)) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_CLR_V 0x1 +#define RTC_CNTL_TOUCH_TIMEOUT_INT_CLR_S 18 +/* RTC_CNTL_COCPU_TRAP_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: Clear cocpu trap interrupt state*/ +#define RTC_CNTL_COCPU_TRAP_INT_CLR (BIT(17)) +#define RTC_CNTL_COCPU_TRAP_INT_CLR_M (BIT(17)) +#define RTC_CNTL_COCPU_TRAP_INT_CLR_V 0x1 +#define RTC_CNTL_COCPU_TRAP_INT_CLR_S 17 +/* RTC_CNTL_XTAL32K_DEAD_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: Clear RTC WDT interrupt state*/ +#define RTC_CNTL_XTAL32K_DEAD_INT_CLR (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_CLR_M (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_CLR_V 0x1 +#define RTC_CNTL_XTAL32K_DEAD_INT_CLR_S 16 +/* RTC_CNTL_SWD_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: Clear super watch dog interrupt state*/ +#define RTC_CNTL_SWD_INT_CLR (BIT(15)) +#define RTC_CNTL_SWD_INT_CLR_M (BIT(15)) +#define RTC_CNTL_SWD_INT_CLR_V 0x1 +#define RTC_CNTL_SWD_INT_CLR_S 15 +/* RTC_CNTL_SARADC2_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: Clear saradc2 interrupt state*/ +#define RTC_CNTL_SARADC2_INT_CLR (BIT(14)) +#define RTC_CNTL_SARADC2_INT_CLR_M (BIT(14)) +#define RTC_CNTL_SARADC2_INT_CLR_V 0x1 +#define RTC_CNTL_SARADC2_INT_CLR_S 14 +/* RTC_CNTL_COCPU_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: Clear riscV cocpu interrupt state*/ +#define RTC_CNTL_COCPU_INT_CLR (BIT(13)) +#define RTC_CNTL_COCPU_INT_CLR_M (BIT(13)) +#define RTC_CNTL_COCPU_INT_CLR_V 0x1 +#define RTC_CNTL_COCPU_INT_CLR_S 13 +/* RTC_CNTL_TSENS_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Clear tsens interrupt state*/ +#define RTC_CNTL_TSENS_INT_CLR (BIT(12)) +#define RTC_CNTL_TSENS_INT_CLR_M (BIT(12)) +#define RTC_CNTL_TSENS_INT_CLR_V 0x1 +#define RTC_CNTL_TSENS_INT_CLR_S 12 +/* RTC_CNTL_SARADC1_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: Clear saradc1 interrupt state*/ +#define RTC_CNTL_SARADC1_INT_CLR (BIT(11)) +#define RTC_CNTL_SARADC1_INT_CLR_M (BIT(11)) +#define RTC_CNTL_SARADC1_INT_CLR_V 0x1 +#define RTC_CNTL_SARADC1_INT_CLR_S 11 +/* RTC_CNTL_MAIN_TIMER_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: Clear RTC main timer interrupt state*/ +#define RTC_CNTL_MAIN_TIMER_INT_CLR (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_CLR_M (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_CLR_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_CLR_S 10 +/* RTC_CNTL_BROWN_OUT_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Clear brown out interrupt state*/ +#define RTC_CNTL_BROWN_OUT_INT_CLR (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_CLR_M (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_CLR_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_CLR_S 9 +/* RTC_CNTL_TOUCH_INACTIVE_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Clear touch inactive interrupt state*/ +#define RTC_CNTL_TOUCH_INACTIVE_INT_CLR (BIT(8)) +#define RTC_CNTL_TOUCH_INACTIVE_INT_CLR_M (BIT(8)) +#define RTC_CNTL_TOUCH_INACTIVE_INT_CLR_V 0x1 +#define RTC_CNTL_TOUCH_INACTIVE_INT_CLR_S 8 +/* RTC_CNTL_TOUCH_ACTIVE_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Clear touch active interrupt state*/ +#define RTC_CNTL_TOUCH_ACTIVE_INT_CLR (BIT(7)) +#define RTC_CNTL_TOUCH_ACTIVE_INT_CLR_M (BIT(7)) +#define RTC_CNTL_TOUCH_ACTIVE_INT_CLR_V 0x1 +#define RTC_CNTL_TOUCH_ACTIVE_INT_CLR_S 7 +/* RTC_CNTL_TOUCH_DONE_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Clear touch done interrupt state*/ +#define RTC_CNTL_TOUCH_DONE_INT_CLR (BIT(6)) +#define RTC_CNTL_TOUCH_DONE_INT_CLR_M (BIT(6)) +#define RTC_CNTL_TOUCH_DONE_INT_CLR_V 0x1 +#define RTC_CNTL_TOUCH_DONE_INT_CLR_S 6 +/* RTC_CNTL_ULP_CP_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Clear ULP-coprocessor interrupt state*/ +#define RTC_CNTL_ULP_CP_INT_CLR (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_CLR_M (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_CLR_V 0x1 +#define RTC_CNTL_ULP_CP_INT_CLR_S 5 +/* RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR (BIT(4)) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR_M (BIT(4)) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR_V 0x1 +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR_S 4 +/* RTC_CNTL_WDT_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Clear RTC WDT interrupt state*/ +#define RTC_CNTL_WDT_INT_CLR (BIT(3)) +#define RTC_CNTL_WDT_INT_CLR_M (BIT(3)) +#define RTC_CNTL_WDT_INT_CLR_V 0x1 +#define RTC_CNTL_WDT_INT_CLR_S 3 +/* RTC_CNTL_SDIO_IDLE_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Clear SDIO idle interrupt state*/ +#define RTC_CNTL_SDIO_IDLE_INT_CLR (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_CLR_M (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_CLR_V 0x1 +#define RTC_CNTL_SDIO_IDLE_INT_CLR_S 2 +/* RTC_CNTL_SLP_REJECT_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Clear sleep reject interrupt state*/ +#define RTC_CNTL_SLP_REJECT_INT_CLR (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_CLR_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_CLR_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_CLR_S 1 +/* RTC_CNTL_SLP_WAKEUP_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Clear sleep wakeup interrupt state*/ +#define RTC_CNTL_SLP_WAKEUP_INT_CLR (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_CLR_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_CLR_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_CLR_S 0 + +#define RTC_CNTL_STORE0_REG (DR_REG_RTCCNTL_BASE + 0x0050) +/* RTC_CNTL_SCRATCH0 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: */ +#define RTC_CNTL_SCRATCH0 0xFFFFFFFF +#define RTC_CNTL_SCRATCH0_M ((RTC_CNTL_SCRATCH0_V)<<(RTC_CNTL_SCRATCH0_S)) +#define RTC_CNTL_SCRATCH0_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH0_S 0 + +#define RTC_CNTL_STORE1_REG (DR_REG_RTCCNTL_BASE + 0x0054) +/* RTC_CNTL_SCRATCH1 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: */ +#define RTC_CNTL_SCRATCH1 0xFFFFFFFF +#define RTC_CNTL_SCRATCH1_M ((RTC_CNTL_SCRATCH1_V)<<(RTC_CNTL_SCRATCH1_S)) +#define RTC_CNTL_SCRATCH1_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH1_S 0 + +#define RTC_CNTL_STORE2_REG (DR_REG_RTCCNTL_BASE + 0x0058) +/* RTC_CNTL_SCRATCH2 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: */ +#define RTC_CNTL_SCRATCH2 0xFFFFFFFF +#define RTC_CNTL_SCRATCH2_M ((RTC_CNTL_SCRATCH2_V)<<(RTC_CNTL_SCRATCH2_S)) +#define RTC_CNTL_SCRATCH2_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH2_S 0 + +#define RTC_CNTL_STORE3_REG (DR_REG_RTCCNTL_BASE + 0x005C) +/* RTC_CNTL_SCRATCH3 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: */ +#define RTC_CNTL_SCRATCH3 0xFFFFFFFF +#define RTC_CNTL_SCRATCH3_M ((RTC_CNTL_SCRATCH3_V)<<(RTC_CNTL_SCRATCH3_S)) +#define RTC_CNTL_SCRATCH3_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH3_S 0 + +#define RTC_CNTL_EXT_XTL_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0060) +/* RTC_CNTL_XTL_EXT_CTR_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_XTL_EXT_CTR_EN (BIT(31)) +#define RTC_CNTL_XTL_EXT_CTR_EN_M (BIT(31)) +#define RTC_CNTL_XTL_EXT_CTR_EN_V 0x1 +#define RTC_CNTL_XTL_EXT_CTR_EN_S 31 +/* RTC_CNTL_XTL_EXT_CTR_LV : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: 0: power down XTAL at high level 1: power down XTAL at low level*/ +#define RTC_CNTL_XTL_EXT_CTR_LV (BIT(30)) +#define RTC_CNTL_XTL_EXT_CTR_LV_M (BIT(30)) +#define RTC_CNTL_XTL_EXT_CTR_LV_V 0x1 +#define RTC_CNTL_XTL_EXT_CTR_LV_S 30 +/* RTC_CNTL_XTAL32K_GPIO_SEL : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: XTAL_32K sel. 0: external XTAL_32K 1: CLK from RTC pad X32P_C*/ +#define RTC_CNTL_XTAL32K_GPIO_SEL (BIT(23)) +#define RTC_CNTL_XTAL32K_GPIO_SEL_M (BIT(23)) +#define RTC_CNTL_XTAL32K_GPIO_SEL_V 0x1 +#define RTC_CNTL_XTAL32K_GPIO_SEL_S 23 +/* RTC_CNTL_WDT_STATE : RO ;bitpos:[22:20] ;default: 3'h0 ; */ +/*description: state of 32k_wdt*/ +#define RTC_CNTL_WDT_STATE 0x00000007 +#define RTC_CNTL_WDT_STATE_M ((RTC_CNTL_WDT_STATE_V)<<(RTC_CNTL_WDT_STATE_S)) +#define RTC_CNTL_WDT_STATE_V 0x7 +#define RTC_CNTL_WDT_STATE_S 20 +/* RTC_CNTL_DAC_XTAL_32K : R/W ;bitpos:[19:17] ;default: 3'd3 ; */ +/*description: DAC_XTAL_32K*/ +#define RTC_CNTL_DAC_XTAL_32K 0x00000007 +#define RTC_CNTL_DAC_XTAL_32K_M ((RTC_CNTL_DAC_XTAL_32K_V)<<(RTC_CNTL_DAC_XTAL_32K_S)) +#define RTC_CNTL_DAC_XTAL_32K_V 0x7 +#define RTC_CNTL_DAC_XTAL_32K_S 17 +/* RTC_CNTL_XPD_XTAL_32K : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: XPD_XTAL_32K*/ +#define RTC_CNTL_XPD_XTAL_32K (BIT(16)) +#define RTC_CNTL_XPD_XTAL_32K_M (BIT(16)) +#define RTC_CNTL_XPD_XTAL_32K_V 0x1 +#define RTC_CNTL_XPD_XTAL_32K_S 16 +/* RTC_CNTL_DRES_XTAL_32K : R/W ;bitpos:[15:13] ;default: 3'd3 ; */ +/*description: DRES_XTAL_32K*/ +#define RTC_CNTL_DRES_XTAL_32K 0x00000007 +#define RTC_CNTL_DRES_XTAL_32K_M ((RTC_CNTL_DRES_XTAL_32K_V)<<(RTC_CNTL_DRES_XTAL_32K_S)) +#define RTC_CNTL_DRES_XTAL_32K_V 0x7 +#define RTC_CNTL_DRES_XTAL_32K_S 13 +/* RTC_CNTL_DGM_XTAL_32K : R/W ;bitpos:[12:10] ;default: 3'd3 ; */ +/*description: xtal_32k gm control*/ +#define RTC_CNTL_DGM_XTAL_32K 0x00000007 +#define RTC_CNTL_DGM_XTAL_32K_M ((RTC_CNTL_DGM_XTAL_32K_V)<<(RTC_CNTL_DGM_XTAL_32K_S)) +#define RTC_CNTL_DGM_XTAL_32K_V 0x7 +#define RTC_CNTL_DGM_XTAL_32K_S 10 +/* RTC_CNTL_DBUF_XTAL_32K : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: 0: single-end buffer 1: differential buffer*/ +#define RTC_CNTL_DBUF_XTAL_32K (BIT(9)) +#define RTC_CNTL_DBUF_XTAL_32K_M (BIT(9)) +#define RTC_CNTL_DBUF_XTAL_32K_V 0x1 +#define RTC_CNTL_DBUF_XTAL_32K_S 9 +/* RTC_CNTL_ENCKINIT_XTAL_32K : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: apply an internal clock to help xtal 32k to start*/ +#define RTC_CNTL_ENCKINIT_XTAL_32K (BIT(8)) +#define RTC_CNTL_ENCKINIT_XTAL_32K_M (BIT(8)) +#define RTC_CNTL_ENCKINIT_XTAL_32K_V 0x1 +#define RTC_CNTL_ENCKINIT_XTAL_32K_S 8 +/* RTC_CNTL_XTAL32K_XPD_FORCE : R/W ;bitpos:[7] ;default: 1'b1 ; */ +/*description: Xtal 32k xpd control by sw or fsm*/ +#define RTC_CNTL_XTAL32K_XPD_FORCE (BIT(7)) +#define RTC_CNTL_XTAL32K_XPD_FORCE_M (BIT(7)) +#define RTC_CNTL_XTAL32K_XPD_FORCE_V 0x1 +#define RTC_CNTL_XTAL32K_XPD_FORCE_S 7 +/* RTC_CNTL_XTAL32K_AUTO_RETURN : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: xtal 32k switch back xtal when xtal is restarted*/ +#define RTC_CNTL_XTAL32K_AUTO_RETURN (BIT(6)) +#define RTC_CNTL_XTAL32K_AUTO_RETURN_M (BIT(6)) +#define RTC_CNTL_XTAL32K_AUTO_RETURN_V 0x1 +#define RTC_CNTL_XTAL32K_AUTO_RETURN_S 6 +/* RTC_CNTL_XTAL32K_AUTO_RESTART : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: xtal 32k restart xtal when xtal is dead*/ +#define RTC_CNTL_XTAL32K_AUTO_RESTART (BIT(5)) +#define RTC_CNTL_XTAL32K_AUTO_RESTART_M (BIT(5)) +#define RTC_CNTL_XTAL32K_AUTO_RESTART_V 0x1 +#define RTC_CNTL_XTAL32K_AUTO_RESTART_S 5 +/* RTC_CNTL_XTAL32K_AUTO_BACKUP : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: xtal 32k switch to back up clock when xtal is dead*/ +#define RTC_CNTL_XTAL32K_AUTO_BACKUP (BIT(4)) +#define RTC_CNTL_XTAL32K_AUTO_BACKUP_M (BIT(4)) +#define RTC_CNTL_XTAL32K_AUTO_BACKUP_V 0x1 +#define RTC_CNTL_XTAL32K_AUTO_BACKUP_S 4 +/* RTC_CNTL_XTAL32K_EXT_CLK_FO : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: xtal 32k external xtal clock force on*/ +#define RTC_CNTL_XTAL32K_EXT_CLK_FO (BIT(3)) +#define RTC_CNTL_XTAL32K_EXT_CLK_FO_M (BIT(3)) +#define RTC_CNTL_XTAL32K_EXT_CLK_FO_V 0x1 +#define RTC_CNTL_XTAL32K_EXT_CLK_FO_S 3 +/* RTC_CNTL_XTAL32K_WDT_RESET : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: xtal 32k watch dog sw reset*/ +#define RTC_CNTL_XTAL32K_WDT_RESET (BIT(2)) +#define RTC_CNTL_XTAL32K_WDT_RESET_M (BIT(2)) +#define RTC_CNTL_XTAL32K_WDT_RESET_V 0x1 +#define RTC_CNTL_XTAL32K_WDT_RESET_S 2 +/* RTC_CNTL_XTAL32K_WDT_CLK_FO : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: xtal 32k watch dog clock force on*/ +#define RTC_CNTL_XTAL32K_WDT_CLK_FO (BIT(1)) +#define RTC_CNTL_XTAL32K_WDT_CLK_FO_M (BIT(1)) +#define RTC_CNTL_XTAL32K_WDT_CLK_FO_V 0x1 +#define RTC_CNTL_XTAL32K_WDT_CLK_FO_S 1 +/* RTC_CNTL_XTAL32K_WDT_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: xtal 32k watch dog enable*/ +#define RTC_CNTL_XTAL32K_WDT_EN (BIT(0)) +#define RTC_CNTL_XTAL32K_WDT_EN_M (BIT(0)) +#define RTC_CNTL_XTAL32K_WDT_EN_V 0x1 +#define RTC_CNTL_XTAL32K_WDT_EN_S 0 + +#define RTC_CNTL_EXT_WAKEUP_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0064) +/* RTC_CNTL_EXT_WAKEUP1_LV : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_EXT_WAKEUP1_LV (BIT(31)) +#define RTC_CNTL_EXT_WAKEUP1_LV_M (BIT(31)) +#define RTC_CNTL_EXT_WAKEUP1_LV_V 0x1 +#define RTC_CNTL_EXT_WAKEUP1_LV_S 31 +/* RTC_CNTL_EXT_WAKEUP0_LV : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: 0: external wakeup at low level 1: external wakeup at high level*/ +#define RTC_CNTL_EXT_WAKEUP0_LV (BIT(30)) +#define RTC_CNTL_EXT_WAKEUP0_LV_M (BIT(30)) +#define RTC_CNTL_EXT_WAKEUP0_LV_V 0x1 +#define RTC_CNTL_EXT_WAKEUP0_LV_S 30 +/* RTC_CNTL_GPIO_WAKEUP_FILTER : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: enable filter for gpio wakeup event*/ +#define RTC_CNTL_GPIO_WAKEUP_FILTER (BIT(29)) +#define RTC_CNTL_GPIO_WAKEUP_FILTER_M (BIT(29)) +#define RTC_CNTL_GPIO_WAKEUP_FILTER_V 0x1 +#define RTC_CNTL_GPIO_WAKEUP_FILTER_S 29 + +#define RTC_CNTL_SLP_REJECT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0068) +/* RTC_CNTL_DEEP_SLP_REJECT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: enable reject for deep sleep*/ +#define RTC_CNTL_DEEP_SLP_REJECT_EN (BIT(31)) +#define RTC_CNTL_DEEP_SLP_REJECT_EN_M (BIT(31)) +#define RTC_CNTL_DEEP_SLP_REJECT_EN_V 0x1 +#define RTC_CNTL_DEEP_SLP_REJECT_EN_S 31 +/* RTC_CNTL_LIGHT_SLP_REJECT_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: enable reject for light sleep*/ +#define RTC_CNTL_LIGHT_SLP_REJECT_EN (BIT(30)) +#define RTC_CNTL_LIGHT_SLP_REJECT_EN_M (BIT(30)) +#define RTC_CNTL_LIGHT_SLP_REJECT_EN_V 0x1 +#define RTC_CNTL_LIGHT_SLP_REJECT_EN_S 30 +/* RTC_CNTL_SLEEP_REJECT_ENA : R/W ;bitpos:[29:13] ;default: 16'd0 ; */ +/*description: sleep reject enable*/ +#define RTC_CNTL_SLEEP_REJECT_ENA 0x0001FFFF +#define RTC_CNTL_SLEEP_REJECT_ENA_M ((RTC_CNTL_SLEEP_REJECT_ENA_V)<<(RTC_CNTL_SLEEP_REJECT_ENA_S)) +#define RTC_CNTL_SLEEP_REJECT_ENA_V 0x1FFFF +#define RTC_CNTL_SLEEP_REJECT_ENA_S 13 + +#define RTC_CNTL_CPU_PERIOD_CONF_REG (DR_REG_RTCCNTL_BASE + 0x006C) +/* RTC_CNTL_CPUPERIOD_SEL : R/W ;bitpos:[31:30] ;default: 2'b00 ; */ +/*description: */ +#define RTC_CNTL_CPUPERIOD_SEL 0x00000003 +#define RTC_CNTL_CPUPERIOD_SEL_M ((RTC_CNTL_CPUPERIOD_SEL_V)<<(RTC_CNTL_CPUPERIOD_SEL_S)) +#define RTC_CNTL_CPUPERIOD_SEL_V 0x3 +#define RTC_CNTL_CPUPERIOD_SEL_S 30 +/* RTC_CNTL_CPUSEL_CONF : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: CPU sel option*/ +#define RTC_CNTL_CPUSEL_CONF (BIT(29)) +#define RTC_CNTL_CPUSEL_CONF_M (BIT(29)) +#define RTC_CNTL_CPUSEL_CONF_V 0x1 +#define RTC_CNTL_CPUSEL_CONF_S 29 + +#define RTC_CNTL_SDIO_ACT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0070) +/* RTC_CNTL_SDIO_ACT_DNUM : R/W ;bitpos:[31:22] ;default: 10'b0 ; */ +/*description: */ +#define RTC_CNTL_SDIO_ACT_DNUM 0x000003FF +#define RTC_CNTL_SDIO_ACT_DNUM_M ((RTC_CNTL_SDIO_ACT_DNUM_V)<<(RTC_CNTL_SDIO_ACT_DNUM_S)) +#define RTC_CNTL_SDIO_ACT_DNUM_V 0x3FF +#define RTC_CNTL_SDIO_ACT_DNUM_S 22 + +#define RTC_CNTL_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0074) +/* RTC_CNTL_ANA_CLK_RTC_SEL : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ +/*description: */ +#define RTC_CNTL_ANA_CLK_RTC_SEL 0x00000003 +#define RTC_CNTL_ANA_CLK_RTC_SEL_M ((RTC_CNTL_ANA_CLK_RTC_SEL_V)<<(RTC_CNTL_ANA_CLK_RTC_SEL_S)) +#define RTC_CNTL_ANA_CLK_RTC_SEL_V 0x3 +#define RTC_CNTL_ANA_CLK_RTC_SEL_S 30 +/* RTC_CNTL_FAST_CLK_RTC_SEL : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: fast_clk_rtc sel. 0: XTAL div 4 1: CK8M*/ +#define RTC_CNTL_FAST_CLK_RTC_SEL (BIT(29)) +#define RTC_CNTL_FAST_CLK_RTC_SEL_M (BIT(29)) +#define RTC_CNTL_FAST_CLK_RTC_SEL_V 0x1 +#define RTC_CNTL_FAST_CLK_RTC_SEL_S 29 +/* RTC_CNTL_CK8M_FORCE_PU : R/W ;bitpos:[26] ;default: 1'd0 ; */ +/*description: CK8M force power up*/ +#define RTC_CNTL_CK8M_FORCE_PU (BIT(26)) +#define RTC_CNTL_CK8M_FORCE_PU_M (BIT(26)) +#define RTC_CNTL_CK8M_FORCE_PU_V 0x1 +#define RTC_CNTL_CK8M_FORCE_PU_S 26 +/* RTC_CNTL_CK8M_FORCE_PD : R/W ;bitpos:[25] ;default: 1'd0 ; */ +/*description: CK8M force power down*/ +#define RTC_CNTL_CK8M_FORCE_PD (BIT(25)) +#define RTC_CNTL_CK8M_FORCE_PD_M (BIT(25)) +#define RTC_CNTL_CK8M_FORCE_PD_V 0x1 +#define RTC_CNTL_CK8M_FORCE_PD_S 25 +/* RTC_CNTL_CK8M_DFREQ : R/W ;bitpos:[24:17] ;default: 8'd172 ; */ +/*description: CK8M_DFREQ*/ +#define RTC_CNTL_CK8M_DFREQ 0x000000FF +#define RTC_CNTL_CK8M_DFREQ_M ((RTC_CNTL_CK8M_DFREQ_V)<<(RTC_CNTL_CK8M_DFREQ_S)) +#define RTC_CNTL_CK8M_DFREQ_V 0xFF +#define RTC_CNTL_CK8M_DFREQ_S 17 +#define RTC_CNTL_CK8M_DFREQ_DEFAULT 172 //TODO, may change in chip7.2.3 +/* RTC_CNTL_CK8M_FORCE_NOGATING : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: CK8M force no gating during sleep*/ +#define RTC_CNTL_CK8M_FORCE_NOGATING (BIT(16)) +#define RTC_CNTL_CK8M_FORCE_NOGATING_M (BIT(16)) +#define RTC_CNTL_CK8M_FORCE_NOGATING_V 0x1 +#define RTC_CNTL_CK8M_FORCE_NOGATING_S 16 +/* RTC_CNTL_XTAL_FORCE_NOGATING : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: XTAL force no gating during sleep*/ +#define RTC_CNTL_XTAL_FORCE_NOGATING (BIT(15)) +#define RTC_CNTL_XTAL_FORCE_NOGATING_M (BIT(15)) +#define RTC_CNTL_XTAL_FORCE_NOGATING_V 0x1 +#define RTC_CNTL_XTAL_FORCE_NOGATING_S 15 +/* RTC_CNTL_CK8M_DIV_SEL : R/W ;bitpos:[14:12] ;default: 3'd3 ; */ +/*description: divider = reg_ck8m_div_sel + 1*/ +#define RTC_CNTL_CK8M_DIV_SEL 0x00000007 +#define RTC_CNTL_CK8M_DIV_SEL_M ((RTC_CNTL_CK8M_DIV_SEL_V)<<(RTC_CNTL_CK8M_DIV_SEL_S)) +#define RTC_CNTL_CK8M_DIV_SEL_V 0x7 +#define RTC_CNTL_CK8M_DIV_SEL_S 12 +/* RTC_CNTL_DIG_CLK8M_EN : R/W ;bitpos:[10] ;default: 1'd0 ; */ +/*description: enable CK8M for digital core (no relationship with RTC core)*/ +#define RTC_CNTL_DIG_CLK8M_EN (BIT(10)) +#define RTC_CNTL_DIG_CLK8M_EN_M (BIT(10)) +#define RTC_CNTL_DIG_CLK8M_EN_V 0x1 +#define RTC_CNTL_DIG_CLK8M_EN_S 10 +/* RTC_CNTL_DIG_CLK8M_D256_EN : R/W ;bitpos:[9] ;default: 1'd1 ; */ +/*description: enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/ +#define RTC_CNTL_DIG_CLK8M_D256_EN (BIT(9)) +#define RTC_CNTL_DIG_CLK8M_D256_EN_M (BIT(9)) +#define RTC_CNTL_DIG_CLK8M_D256_EN_V 0x1 +#define RTC_CNTL_DIG_CLK8M_D256_EN_S 9 +/* RTC_CNTL_DIG_XTAL32K_EN : R/W ;bitpos:[8] ;default: 1'd0 ; */ +/*description: enable CK_XTAL_32K for digital core (no relationship with RTC core)*/ +#define RTC_CNTL_DIG_XTAL32K_EN (BIT(8)) +#define RTC_CNTL_DIG_XTAL32K_EN_M (BIT(8)) +#define RTC_CNTL_DIG_XTAL32K_EN_V 0x1 +#define RTC_CNTL_DIG_XTAL32K_EN_S 8 +/* RTC_CNTL_ENB_CK8M_DIV : R/W ;bitpos:[7] ;default: 1'd0 ; */ +/*description: 1: CK8M_D256_OUT is actually CK8M 0: CK8M_D256_OUT is CK8M divided by 256*/ +#define RTC_CNTL_ENB_CK8M_DIV (BIT(7)) +#define RTC_CNTL_ENB_CK8M_DIV_M (BIT(7)) +#define RTC_CNTL_ENB_CK8M_DIV_V 0x1 +#define RTC_CNTL_ENB_CK8M_DIV_S 7 +/* RTC_CNTL_ENB_CK8M : R/W ;bitpos:[6] ;default: 1'd0 ; */ +/*description: disable CK8M and CK8M_D256_OUT*/ +#define RTC_CNTL_ENB_CK8M (BIT(6)) +#define RTC_CNTL_ENB_CK8M_M (BIT(6)) +#define RTC_CNTL_ENB_CK8M_V 0x1 +#define RTC_CNTL_ENB_CK8M_S 6 +/* RTC_CNTL_CK8M_DIV : R/W ;bitpos:[5:4] ;default: 2'b01 ; */ +/*description: CK8M_D256_OUT divider. 00: div128 01: div256 10: div512 11: div1024.*/ +#define RTC_CNTL_CK8M_DIV 0x00000003 +#define RTC_CNTL_CK8M_DIV_M ((RTC_CNTL_CK8M_DIV_V)<<(RTC_CNTL_CK8M_DIV_S)) +#define RTC_CNTL_CK8M_DIV_V 0x3 +#define RTC_CNTL_CK8M_DIV_S 4 +/* RTC_CNTL_CK8M_DIV_SEL_VLD : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel + then set vld to actually switch the clk*/ +#define RTC_CNTL_CK8M_DIV_SEL_VLD (BIT(3)) +#define RTC_CNTL_CK8M_DIV_SEL_VLD_M (BIT(3)) +#define RTC_CNTL_CK8M_DIV_SEL_VLD_V 0x1 +#define RTC_CNTL_CK8M_DIV_SEL_VLD_S 3 + +#define RTC_CNTL_SLOW_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0078) +/* RTC_CNTL_SLOW_CLK_NEXT_EDGE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_SLOW_CLK_NEXT_EDGE (BIT(31)) +#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_M (BIT(31)) +#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_V 0x1 +#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_S 31 +/* RTC_CNTL_ANA_CLK_DIV : R/W ;bitpos:[30:23] ;default: 8'd0 ; */ +/*description: */ +#define RTC_CNTL_ANA_CLK_DIV 0x000000FF +#define RTC_CNTL_ANA_CLK_DIV_M ((RTC_CNTL_ANA_CLK_DIV_V)<<(RTC_CNTL_ANA_CLK_DIV_S)) +#define RTC_CNTL_ANA_CLK_DIV_V 0xFF +#define RTC_CNTL_ANA_CLK_DIV_S 23 +/* RTC_CNTL_ANA_CLK_DIV_VLD : R/W ;bitpos:[22] ;default: 1'b1 ; */ +/*description: used to sync div bus. clear vld before set reg_rtc_ana_clk_div + then set vld to actually switch the clk*/ +#define RTC_CNTL_ANA_CLK_DIV_VLD (BIT(22)) +#define RTC_CNTL_ANA_CLK_DIV_VLD_M (BIT(22)) +#define RTC_CNTL_ANA_CLK_DIV_VLD_V 0x1 +#define RTC_CNTL_ANA_CLK_DIV_VLD_S 22 + +#define RTC_CNTL_SDIO_CONF_REG (DR_REG_RTCCNTL_BASE + 0x007C) +/* RTC_CNTL_XPD_SDIO_REG : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_XPD_SDIO_REG (BIT(31)) +#define RTC_CNTL_XPD_SDIO_REG_M (BIT(31)) +#define RTC_CNTL_XPD_SDIO_REG_V 0x1 +#define RTC_CNTL_XPD_SDIO_REG_S 31 +/* RTC_CNTL_DREFH_SDIO : R/W ;bitpos:[30:29] ;default: 2'b00 ; */ +/*description: SW option for DREFH_SDIO. Only active when reg_sdio_force = 1*/ +#define RTC_CNTL_DREFH_SDIO 0x00000003 +#define RTC_CNTL_DREFH_SDIO_M ((RTC_CNTL_DREFH_SDIO_V)<<(RTC_CNTL_DREFH_SDIO_S)) +#define RTC_CNTL_DREFH_SDIO_V 0x3 +#define RTC_CNTL_DREFH_SDIO_S 29 +/* RTC_CNTL_DREFM_SDIO : R/W ;bitpos:[28:27] ;default: 2'b00 ; */ +/*description: SW option for DREFM_SDIO. Only active when reg_sdio_force = 1*/ +#define RTC_CNTL_DREFM_SDIO 0x00000003 +#define RTC_CNTL_DREFM_SDIO_M ((RTC_CNTL_DREFM_SDIO_V)<<(RTC_CNTL_DREFM_SDIO_S)) +#define RTC_CNTL_DREFM_SDIO_V 0x3 +#define RTC_CNTL_DREFM_SDIO_S 27 +/* RTC_CNTL_DREFL_SDIO : R/W ;bitpos:[26:25] ;default: 2'b01 ; */ +/*description: SW option for DREFL_SDIO. Only active when reg_sdio_force = 1*/ +#define RTC_CNTL_DREFL_SDIO 0x00000003 +#define RTC_CNTL_DREFL_SDIO_M ((RTC_CNTL_DREFL_SDIO_V)<<(RTC_CNTL_DREFL_SDIO_S)) +#define RTC_CNTL_DREFL_SDIO_V 0x3 +#define RTC_CNTL_DREFL_SDIO_S 25 +/* RTC_CNTL_REG1P8_READY : RO ;bitpos:[24] ;default: 1'd0 ; */ +/*description: read only register for REG1P8_READY*/ +#define RTC_CNTL_REG1P8_READY (BIT(24)) +#define RTC_CNTL_REG1P8_READY_M (BIT(24)) +#define RTC_CNTL_REG1P8_READY_V 0x1 +#define RTC_CNTL_REG1P8_READY_S 24 +/* RTC_CNTL_SDIO_TIEH : R/W ;bitpos:[23] ;default: 1'd1 ; */ +/*description: SW option for SDIO_TIEH. Only active when reg_sdio_force = 1*/ +#define RTC_CNTL_SDIO_TIEH (BIT(23)) +#define RTC_CNTL_SDIO_TIEH_M (BIT(23)) +#define RTC_CNTL_SDIO_TIEH_V 0x1 +#define RTC_CNTL_SDIO_TIEH_S 23 +/* RTC_CNTL_SDIO_FORCE : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: 1: use SW option to control SDIO_REG 0: use state machine*/ +#define RTC_CNTL_SDIO_FORCE (BIT(22)) +#define RTC_CNTL_SDIO_FORCE_M (BIT(22)) +#define RTC_CNTL_SDIO_FORCE_V 0x1 +#define RTC_CNTL_SDIO_FORCE_S 22 +/* RTC_CNTL_SDIO_PD_EN : R/W ;bitpos:[21] ;default: 1'd1 ; */ +/*description: power down SDIO_REG in sleep. Only active when reg_sdio_force = 0*/ +#define RTC_CNTL_SDIO_PD_EN (BIT(21)) +#define RTC_CNTL_SDIO_PD_EN_M (BIT(21)) +#define RTC_CNTL_SDIO_PD_EN_V 0x1 +#define RTC_CNTL_SDIO_PD_EN_S 21 +/* RTC_CNTL_SDIO_ENCURLIM : R/W ;bitpos:[20] ;default: 1'd1 ; */ +/*description: enable current limit*/ +#define RTC_CNTL_SDIO_ENCURLIM (BIT(20)) +#define RTC_CNTL_SDIO_ENCURLIM_M (BIT(20)) +#define RTC_CNTL_SDIO_ENCURLIM_V 0x1 +#define RTC_CNTL_SDIO_ENCURLIM_S 20 +/* RTC_CNTL_SDIO_MODECURLIM : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: select current limit mode*/ +#define RTC_CNTL_SDIO_MODECURLIM (BIT(19)) +#define RTC_CNTL_SDIO_MODECURLIM_M (BIT(19)) +#define RTC_CNTL_SDIO_MODECURLIM_V 0x1 +#define RTC_CNTL_SDIO_MODECURLIM_S 19 +/* RTC_CNTL_SDIO_DCURLIM : R/W ;bitpos:[18:16] ;default: 3'd0 ; */ +/*description: tune current limit threshold when tieh = 0. About 800mA/(8+d)*/ +#define RTC_CNTL_SDIO_DCURLIM 0x00000007 +#define RTC_CNTL_SDIO_DCURLIM_M ((RTC_CNTL_SDIO_DCURLIM_V)<<(RTC_CNTL_SDIO_DCURLIM_S)) +#define RTC_CNTL_SDIO_DCURLIM_V 0x7 +#define RTC_CNTL_SDIO_DCURLIM_S 16 +/* RTC_CNTL_SDIO_EN_INITI : R/W ;bitpos:[15] ;default: 1'd1 ; */ +/*description: 0 to set init[1:0]=0*/ +#define RTC_CNTL_SDIO_EN_INITI (BIT(15)) +#define RTC_CNTL_SDIO_EN_INITI_M (BIT(15)) +#define RTC_CNTL_SDIO_EN_INITI_V 0x1 +#define RTC_CNTL_SDIO_EN_INITI_S 15 +/* RTC_CNTL_SDIO_INITI : R/W ;bitpos:[14:13] ;default: 2'd1 ; */ +/*description: add resistor from ldo output to ground. 0: no res 1: 6k 2: 4k 3: 2k*/ +#define RTC_CNTL_SDIO_INITI 0x00000003 +#define RTC_CNTL_SDIO_INITI_M ((RTC_CNTL_SDIO_INITI_V)<<(RTC_CNTL_SDIO_INITI_S)) +#define RTC_CNTL_SDIO_INITI_V 0x3 +#define RTC_CNTL_SDIO_INITI_S 13 +/* RTC_CNTL_SDIO_DCAP : R/W ;bitpos:[12:11] ;default: 2'b11 ; */ +/*description: ability to prevent LDO from overshoot*/ +#define RTC_CNTL_SDIO_DCAP 0x00000003 +#define RTC_CNTL_SDIO_DCAP_M ((RTC_CNTL_SDIO_DCAP_V)<<(RTC_CNTL_SDIO_DCAP_S)) +#define RTC_CNTL_SDIO_DCAP_V 0x3 +#define RTC_CNTL_SDIO_DCAP_S 11 +/* RTC_CNTL_SDIO_DTHDRV : R/W ;bitpos:[10:9] ;default: 2'b11 ; */ +/*description: Tieh = 1 mode drive ability. Initially set to 0 to limit charge + current set to 3 after several us.*/ +#define RTC_CNTL_SDIO_DTHDRV 0x00000003 +#define RTC_CNTL_SDIO_DTHDRV_M ((RTC_CNTL_SDIO_DTHDRV_V)<<(RTC_CNTL_SDIO_DTHDRV_S)) +#define RTC_CNTL_SDIO_DTHDRV_V 0x3 +#define RTC_CNTL_SDIO_DTHDRV_S 9 +/* RTC_CNTL_SDIO_TIMER_TARGET : R/W ;bitpos:[7:0] ;default: 8'd10 ; */ +/*description: timer count to apply reg_sdio_dcap after sdio power on*/ +#define RTC_CNTL_SDIO_TIMER_TARGET 0x000000FF +#define RTC_CNTL_SDIO_TIMER_TARGET_M ((RTC_CNTL_SDIO_TIMER_TARGET_V)<<(RTC_CNTL_SDIO_TIMER_TARGET_S)) +#define RTC_CNTL_SDIO_TIMER_TARGET_V 0xFF +#define RTC_CNTL_SDIO_TIMER_TARGET_S 0 + +#define RTC_CNTL_BIAS_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0080) +/* RTC_CNTL_RST_BIAS_I2C : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_RST_BIAS_I2C (BIT(31)) +#define RTC_CNTL_RST_BIAS_I2C_M (BIT(31)) +#define RTC_CNTL_RST_BIAS_I2C_V 0x1 +#define RTC_CNTL_RST_BIAS_I2C_S 31 +/* RTC_CNTL_DEC_HEARTBEAT_WIDTH : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: DEC_HEARTBEAT_WIDTH*/ +#define RTC_CNTL_DEC_HEARTBEAT_WIDTH (BIT(30)) +#define RTC_CNTL_DEC_HEARTBEAT_WIDTH_M (BIT(30)) +#define RTC_CNTL_DEC_HEARTBEAT_WIDTH_V 0x1 +#define RTC_CNTL_DEC_HEARTBEAT_WIDTH_S 30 +/* RTC_CNTL_INC_HEARTBEAT_PERIOD : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: INC_HEARTBEAT_PERIOD*/ +#define RTC_CNTL_INC_HEARTBEAT_PERIOD (BIT(29)) +#define RTC_CNTL_INC_HEARTBEAT_PERIOD_M (BIT(29)) +#define RTC_CNTL_INC_HEARTBEAT_PERIOD_V 0x1 +#define RTC_CNTL_INC_HEARTBEAT_PERIOD_S 29 +/* RTC_CNTL_DEC_HEARTBEAT_PERIOD : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: DEC_HEARTBEAT_PERIOD*/ +#define RTC_CNTL_DEC_HEARTBEAT_PERIOD (BIT(28)) +#define RTC_CNTL_DEC_HEARTBEAT_PERIOD_M (BIT(28)) +#define RTC_CNTL_DEC_HEARTBEAT_PERIOD_V 0x1 +#define RTC_CNTL_DEC_HEARTBEAT_PERIOD_S 28 +/* RTC_CNTL_INC_HEARTBEAT_REFRESH : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: INC_HEARTBEAT_REFRESH*/ +#define RTC_CNTL_INC_HEARTBEAT_REFRESH (BIT(27)) +#define RTC_CNTL_INC_HEARTBEAT_REFRESH_M (BIT(27)) +#define RTC_CNTL_INC_HEARTBEAT_REFRESH_V 0x1 +#define RTC_CNTL_INC_HEARTBEAT_REFRESH_S 27 +/* RTC_CNTL_ENB_SCK_XTAL : R/W ;bitpos:[26] ;default: 1'd0 ; */ +/*description: ENB_SCK_XTAL*/ +#define RTC_CNTL_ENB_SCK_XTAL (BIT(26)) +#define RTC_CNTL_ENB_SCK_XTAL_M (BIT(26)) +#define RTC_CNTL_ENB_SCK_XTAL_V 0x1 +#define RTC_CNTL_ENB_SCK_XTAL_S 26 +/* RTC_CNTL_DBG_ATTEN_MONITOR : R/W ;bitpos:[25:22] ;default: 4'd0 ; */ +/*description: DBG_ATTEN when rtc in monitor state*/ +#define RTC_CNTL_DBG_ATTEN_MONITOR 0x0000000F +#define RTC_CNTL_DBG_ATTEN_MONITOR_M ((RTC_CNTL_DBG_ATTEN_MONITOR_V)<<(RTC_CNTL_DBG_ATTEN_MONITOR_S)) +#define RTC_CNTL_DBG_ATTEN_MONITOR_V 0xF +#define RTC_CNTL_DBG_ATTEN_MONITOR_S 22 +/* RTC_CNTL_DBG_ATTEN_DEEP_SLP : R/W ;bitpos:[21:18] ;default: 4'd0 ; */ +/*description: DBG_ATTEN when rtc in sleep state*/ +#define RTC_CNTL_DBG_ATTEN_DEEP_SLP 0x0000000F +#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_M ((RTC_CNTL_DBG_ATTEN_DEEP_SLP_V)<<(RTC_CNTL_DBG_ATTEN_DEEP_SLP_S)) +#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_V 0xF +#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_S 18 +/* RTC_CNTL_BIAS_SLEEP_MONITOR : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: bias_sleep when rtc in monitor state*/ +#define RTC_CNTL_BIAS_SLEEP_MONITOR (BIT(17)) +#define RTC_CNTL_BIAS_SLEEP_MONITOR_M (BIT(17)) +#define RTC_CNTL_BIAS_SLEEP_MONITOR_V 0x1 +#define RTC_CNTL_BIAS_SLEEP_MONITOR_S 17 +/* RTC_CNTL_BIAS_SLEEP_DEEP_SLP : R/W ;bitpos:[16] ;default: 1'b1 ; */ +/*description: bias_sleep when rtc in sleep_state*/ +#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP (BIT(16)) +#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_M (BIT(16)) +#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_V 0x1 +#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_S 16 +/* RTC_CNTL_PD_CUR_MONITOR : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: xpd cur when rtc in monitor state*/ +#define RTC_CNTL_PD_CUR_MONITOR (BIT(15)) +#define RTC_CNTL_PD_CUR_MONITOR_M (BIT(15)) +#define RTC_CNTL_PD_CUR_MONITOR_V 0x1 +#define RTC_CNTL_PD_CUR_MONITOR_S 15 +/* RTC_CNTL_PD_CUR_DEEP_SLP : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: xpd cur when rtc in sleep_state*/ +#define RTC_CNTL_PD_CUR_DEEP_SLP (BIT(14)) +#define RTC_CNTL_PD_CUR_DEEP_SLP_M (BIT(14)) +#define RTC_CNTL_PD_CUR_DEEP_SLP_V 0x1 +#define RTC_CNTL_PD_CUR_DEEP_SLP_S 14 +/* RTC_CNTL_BIAS_BUF_MONITOR : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_BIAS_BUF_MONITOR (BIT(13)) +#define RTC_CNTL_BIAS_BUF_MONITOR_M (BIT(13)) +#define RTC_CNTL_BIAS_BUF_MONITOR_V 0x1 +#define RTC_CNTL_BIAS_BUF_MONITOR_S 13 +/* RTC_CNTL_BIAS_BUF_DEEP_SLP : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_BIAS_BUF_DEEP_SLP (BIT(12)) +#define RTC_CNTL_BIAS_BUF_DEEP_SLP_M (BIT(12)) +#define RTC_CNTL_BIAS_BUF_DEEP_SLP_V 0x1 +#define RTC_CNTL_BIAS_BUF_DEEP_SLP_S 12 +/* RTC_CNTL_BIAS_BUF_WAKE : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: */ +#define RTC_CNTL_BIAS_BUF_WAKE (BIT(11)) +#define RTC_CNTL_BIAS_BUF_WAKE_M (BIT(11)) +#define RTC_CNTL_BIAS_BUF_WAKE_V 0x1 +#define RTC_CNTL_BIAS_BUF_WAKE_S 11 +/* RTC_CNTL_BIAS_BUF_IDLE : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_BIAS_BUF_IDLE (BIT(10)) +#define RTC_CNTL_BIAS_BUF_IDLE_M (BIT(10)) +#define RTC_CNTL_BIAS_BUF_IDLE_V 0x1 +#define RTC_CNTL_BIAS_BUF_IDLE_S 10 + +#define RTC_CNTL_REG (DR_REG_RTCCNTL_BASE + 0x0084) +/* RTC_CNTL_REGULATOR_FORCE_PU : R/W ;bitpos:[31] ;default: 1'd1 ; */ +/*description: */ +#define RTC_CNTL_REGULATOR_FORCE_PU (BIT(31)) +#define RTC_CNTL_REGULATOR_FORCE_PU_M (BIT(31)) +#define RTC_CNTL_REGULATOR_FORCE_PU_V 0x1 +#define RTC_CNTL_REGULATOR_FORCE_PU_S 31 +/* RTC_CNTL_REGULATOR_FORCE_PD : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: RTC_REG force power down (for RTC_REG power down means decrease + the voltage to 0.8v or lower )*/ +#define RTC_CNTL_REGULATOR_FORCE_PD (BIT(30)) +#define RTC_CNTL_REGULATOR_FORCE_PD_M (BIT(30)) +#define RTC_CNTL_REGULATOR_FORCE_PD_V 0x1 +#define RTC_CNTL_REGULATOR_FORCE_PD_S 30 +/* RTC_CNTL_DBOOST_FORCE_PU : R/W ;bitpos:[29] ;default: 1'd1 ; */ +/*description: RTC_DBOOST force power up*/ +#define RTC_CNTL_DBOOST_FORCE_PU (BIT(29)) +#define RTC_CNTL_DBOOST_FORCE_PU_M (BIT(29)) +#define RTC_CNTL_DBOOST_FORCE_PU_V 0x1 +#define RTC_CNTL_DBOOST_FORCE_PU_S 29 +/* RTC_CNTL_DBOOST_FORCE_PD : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: RTC_DBOOST force power down*/ +#define RTC_CNTL_DBOOST_FORCE_PD (BIT(28)) +#define RTC_CNTL_DBOOST_FORCE_PD_M (BIT(28)) +#define RTC_CNTL_DBOOST_FORCE_PD_V 0x1 +#define RTC_CNTL_DBOOST_FORCE_PD_S 28 +/* RTC_CNTL_DBIAS_WAK : R/W ;bitpos:[27:25] ;default: 3'd4 ; */ +/*description: RTC_DBIAS during wakeup*/ +#define RTC_CNTL_DBIAS_WAK 0x00000007 +#define RTC_CNTL_DBIAS_WAK_M ((RTC_CNTL_DBIAS_WAK_V)<<(RTC_CNTL_DBIAS_WAK_S)) +#define RTC_CNTL_DBIAS_WAK_V 0x7 +#define RTC_CNTL_DBIAS_WAK_S 25 +/* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP, + * RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values. + * Valid if RTC_CNTL_DBG_ATTEN is 0. + */ +#define RTC_CNTL_DIG_DBIAS_0V85 0 +#define RTC_CNTL_DIG_DBIAS_0V90 1 +#define RTC_CNTL_DIG_DBIAS_0V95 2 +#define RTC_CNTL_DIG_DBIAS_1V00 3 +#define RTC_CNTL_DIG_DBIAS_1V05 4 +#define RTC_CNTL_DIG_DBIAS_1V10 5 +#define RTC_CNTL_DIG_DBIAS_1V15 6 +#define RTC_CNTL_DIG_DBIAS_1V20 7 + +/* RTC_CNTL_DBIAS_SLP : R/W ;bitpos:[24:22] ;default: 3'd4 ; */ +/*description: RTC_DBIAS during sleep*/ +#define RTC_CNTL_DBIAS_SLP 0x00000007 +#define RTC_CNTL_DBIAS_SLP_M ((RTC_CNTL_DBIAS_SLP_V)<<(RTC_CNTL_DBIAS_SLP_S)) +#define RTC_CNTL_DBIAS_SLP_V 0x7 +#define RTC_CNTL_DBIAS_SLP_S 22 +/* RTC_CNTL_SCK_DCAP : R/W ;bitpos:[21:14] ;default: 8'd0 ; */ +/*description: SCK_DCAP*/ +#define RTC_CNTL_SCK_DCAP 0x000000FF +#define RTC_CNTL_SCK_DCAP_M ((RTC_CNTL_SCK_DCAP_V)<<(RTC_CNTL_SCK_DCAP_S)) +#define RTC_CNTL_SCK_DCAP_V 0xFF +#define RTC_CNTL_SCK_DCAP_S 14 +/* RTC_CNTL_DIG_DBIAS_WAK : R/W ;bitpos:[13:11] ;default: 3'd4 ; */ +/*description: DIG_REG_DBIAS during wakeup*/ +#define RTC_CNTL_DIG_DBIAS_WAK 0x00000007 +#define RTC_CNTL_DIG_DBIAS_WAK_M ((RTC_CNTL_DIG_DBIAS_WAK_V)<<(RTC_CNTL_DIG_DBIAS_WAK_S)) +#define RTC_CNTL_DIG_DBIAS_WAK_V 0x7 +#define RTC_CNTL_DIG_DBIAS_WAK_S 11 +/* RTC_CNTL_DIG_DBIAS_SLP : R/W ;bitpos:[10:8] ;default: 3'd4 ; */ +/*description: DIG_REG_DBIAS during sleep*/ +#define RTC_CNTL_DIG_DBIAS_SLP 0x00000007 +#define RTC_CNTL_DIG_DBIAS_SLP_M ((RTC_CNTL_DIG_DBIAS_SLP_V)<<(RTC_CNTL_DIG_DBIAS_SLP_S)) +#define RTC_CNTL_DIG_DBIAS_SLP_V 0x7 +#define RTC_CNTL_DIG_DBIAS_SLP_S 8 + +#define RTC_CNTL_PWC_REG (DR_REG_RTCCNTL_BASE + 0x0088) +/* RTC_CNTL_PAD_FORCE_HOLD : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: rtc pad force hold*/ +#define RTC_CNTL_PAD_FORCE_HOLD (BIT(21)) +#define RTC_CNTL_PAD_FORCE_HOLD_M (BIT(21)) +#define RTC_CNTL_PAD_FORCE_HOLD_V 0x1 +#define RTC_CNTL_PAD_FORCE_HOLD_S 21 +/* RTC_CNTL_PD_EN : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: enable power down rtc_peri in sleep*/ +#define RTC_CNTL_PD_EN (BIT(20)) +#define RTC_CNTL_PD_EN_M (BIT(20)) +#define RTC_CNTL_PD_EN_V 0x1 +#define RTC_CNTL_PD_EN_S 20 +/* RTC_CNTL_FORCE_PU : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: rtc_peri force power up*/ +#define RTC_CNTL_FORCE_PU (BIT(19)) +#define RTC_CNTL_FORCE_PU_M (BIT(19)) +#define RTC_CNTL_FORCE_PU_V 0x1 +#define RTC_CNTL_FORCE_PU_S 19 +/* RTC_CNTL_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: rtc_peri force power down*/ +#define RTC_CNTL_FORCE_PD (BIT(18)) +#define RTC_CNTL_FORCE_PD_M (BIT(18)) +#define RTC_CNTL_FORCE_PD_V 0x1 +#define RTC_CNTL_FORCE_PD_S 18 +/* RTC_CNTL_SLOWMEM_PD_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: enable power down RTC memory in sleep*/ +#define RTC_CNTL_SLOWMEM_PD_EN (BIT(17)) +#define RTC_CNTL_SLOWMEM_PD_EN_M (BIT(17)) +#define RTC_CNTL_SLOWMEM_PD_EN_V 0x1 +#define RTC_CNTL_SLOWMEM_PD_EN_S 17 +/* RTC_CNTL_SLOWMEM_FORCE_PU : R/W ;bitpos:[16] ;default: 1'b1 ; */ +/*description: RTC memory force power up*/ +#define RTC_CNTL_SLOWMEM_FORCE_PU (BIT(16)) +#define RTC_CNTL_SLOWMEM_FORCE_PU_M (BIT(16)) +#define RTC_CNTL_SLOWMEM_FORCE_PU_V 0x1 +#define RTC_CNTL_SLOWMEM_FORCE_PU_S 16 +/* RTC_CNTL_SLOWMEM_FORCE_PD : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: RTC memory force power down*/ +#define RTC_CNTL_SLOWMEM_FORCE_PD (BIT(15)) +#define RTC_CNTL_SLOWMEM_FORCE_PD_M (BIT(15)) +#define RTC_CNTL_SLOWMEM_FORCE_PD_V 0x1 +#define RTC_CNTL_SLOWMEM_FORCE_PD_S 15 +/* RTC_CNTL_FASTMEM_PD_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: enable power down fast RTC memory in sleep*/ +#define RTC_CNTL_FASTMEM_PD_EN (BIT(14)) +#define RTC_CNTL_FASTMEM_PD_EN_M (BIT(14)) +#define RTC_CNTL_FASTMEM_PD_EN_V 0x1 +#define RTC_CNTL_FASTMEM_PD_EN_S 14 +/* RTC_CNTL_FASTMEM_FORCE_PU : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: Fast RTC memory force power up*/ +#define RTC_CNTL_FASTMEM_FORCE_PU (BIT(13)) +#define RTC_CNTL_FASTMEM_FORCE_PU_M (BIT(13)) +#define RTC_CNTL_FASTMEM_FORCE_PU_V 0x1 +#define RTC_CNTL_FASTMEM_FORCE_PU_S 13 +/* RTC_CNTL_FASTMEM_FORCE_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Fast RTC memory force power down*/ +#define RTC_CNTL_FASTMEM_FORCE_PD (BIT(12)) +#define RTC_CNTL_FASTMEM_FORCE_PD_M (BIT(12)) +#define RTC_CNTL_FASTMEM_FORCE_PD_V 0x1 +#define RTC_CNTL_FASTMEM_FORCE_PD_S 12 +/* RTC_CNTL_SLOWMEM_FORCE_LPU : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: RTC memory force no PD*/ +#define RTC_CNTL_SLOWMEM_FORCE_LPU (BIT(11)) +#define RTC_CNTL_SLOWMEM_FORCE_LPU_M (BIT(11)) +#define RTC_CNTL_SLOWMEM_FORCE_LPU_V 0x1 +#define RTC_CNTL_SLOWMEM_FORCE_LPU_S 11 +/* RTC_CNTL_SLOWMEM_FORCE_LPD : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: RTC memory force PD*/ +#define RTC_CNTL_SLOWMEM_FORCE_LPD (BIT(10)) +#define RTC_CNTL_SLOWMEM_FORCE_LPD_M (BIT(10)) +#define RTC_CNTL_SLOWMEM_FORCE_LPD_V 0x1 +#define RTC_CNTL_SLOWMEM_FORCE_LPD_S 10 +/* RTC_CNTL_SLOWMEM_FOLW_CPU : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: 1: RTC memory PD following CPU 0: RTC memory PD following RTC state machine*/ +#define RTC_CNTL_SLOWMEM_FOLW_CPU (BIT(9)) +#define RTC_CNTL_SLOWMEM_FOLW_CPU_M (BIT(9)) +#define RTC_CNTL_SLOWMEM_FOLW_CPU_V 0x1 +#define RTC_CNTL_SLOWMEM_FOLW_CPU_S 9 +/* RTC_CNTL_FASTMEM_FORCE_LPU : R/W ;bitpos:[8] ;default: 1'b1 ; */ +/*description: Fast RTC memory force no PD*/ +#define RTC_CNTL_FASTMEM_FORCE_LPU (BIT(8)) +#define RTC_CNTL_FASTMEM_FORCE_LPU_M (BIT(8)) +#define RTC_CNTL_FASTMEM_FORCE_LPU_V 0x1 +#define RTC_CNTL_FASTMEM_FORCE_LPU_S 8 +/* RTC_CNTL_FASTMEM_FORCE_LPD : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Fast RTC memory force PD*/ +#define RTC_CNTL_FASTMEM_FORCE_LPD (BIT(7)) +#define RTC_CNTL_FASTMEM_FORCE_LPD_M (BIT(7)) +#define RTC_CNTL_FASTMEM_FORCE_LPD_V 0x1 +#define RTC_CNTL_FASTMEM_FORCE_LPD_S 7 +/* RTC_CNTL_FASTMEM_FOLW_CPU : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: 1: Fast RTC memory PD following CPU 0: fast RTC memory PD following + RTC state machine*/ +#define RTC_CNTL_FASTMEM_FOLW_CPU (BIT(6)) +#define RTC_CNTL_FASTMEM_FOLW_CPU_M (BIT(6)) +#define RTC_CNTL_FASTMEM_FOLW_CPU_V 0x1 +#define RTC_CNTL_FASTMEM_FOLW_CPU_S 6 +/* RTC_CNTL_FORCE_NOISO : R/W ;bitpos:[5] ;default: 1'd1 ; */ +/*description: rtc_peri force no ISO*/ +#define RTC_CNTL_FORCE_NOISO (BIT(5)) +#define RTC_CNTL_FORCE_NOISO_M (BIT(5)) +#define RTC_CNTL_FORCE_NOISO_V 0x1 +#define RTC_CNTL_FORCE_NOISO_S 5 +/* RTC_CNTL_FORCE_ISO : R/W ;bitpos:[4] ;default: 1'd0 ; */ +/*description: rtc_peri force ISO*/ +#define RTC_CNTL_FORCE_ISO (BIT(4)) +#define RTC_CNTL_FORCE_ISO_M (BIT(4)) +#define RTC_CNTL_FORCE_ISO_V 0x1 +#define RTC_CNTL_FORCE_ISO_S 4 +/* RTC_CNTL_SLOWMEM_FORCE_ISO : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: RTC memory force ISO*/ +#define RTC_CNTL_SLOWMEM_FORCE_ISO (BIT(3)) +#define RTC_CNTL_SLOWMEM_FORCE_ISO_M (BIT(3)) +#define RTC_CNTL_SLOWMEM_FORCE_ISO_V 0x1 +#define RTC_CNTL_SLOWMEM_FORCE_ISO_S 3 +/* RTC_CNTL_SLOWMEM_FORCE_NOISO : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: RTC memory force no ISO*/ +#define RTC_CNTL_SLOWMEM_FORCE_NOISO (BIT(2)) +#define RTC_CNTL_SLOWMEM_FORCE_NOISO_M (BIT(2)) +#define RTC_CNTL_SLOWMEM_FORCE_NOISO_V 0x1 +#define RTC_CNTL_SLOWMEM_FORCE_NOISO_S 2 +/* RTC_CNTL_FASTMEM_FORCE_ISO : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Fast RTC memory force ISO*/ +#define RTC_CNTL_FASTMEM_FORCE_ISO (BIT(1)) +#define RTC_CNTL_FASTMEM_FORCE_ISO_M (BIT(1)) +#define RTC_CNTL_FASTMEM_FORCE_ISO_V 0x1 +#define RTC_CNTL_FASTMEM_FORCE_ISO_S 1 +/* RTC_CNTL_FASTMEM_FORCE_NOISO : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: Fast RTC memory force no ISO*/ +#define RTC_CNTL_FASTMEM_FORCE_NOISO (BIT(0)) +#define RTC_CNTL_FASTMEM_FORCE_NOISO_M (BIT(0)) +#define RTC_CNTL_FASTMEM_FORCE_NOISO_V 0x1 +#define RTC_CNTL_FASTMEM_FORCE_NOISO_S 0 +/* Useful groups of RTC_CNTL_PWC_REG bits */ +#define RTC_CNTL_MEM_FORCE_ISO \ + (RTC_CNTL_SLOWMEM_FORCE_ISO | RTC_CNTL_FASTMEM_FORCE_ISO) +#define RTC_CNTL_MEM_FORCE_NOISO \ + (RTC_CNTL_SLOWMEM_FORCE_NOISO | RTC_CNTL_FASTMEM_FORCE_NOISO) +#define RTC_CNTL_MEM_PD_EN \ + (RTC_CNTL_SLOWMEM_PD_EN | RTC_CNTL_FASTMEM_PD_EN) +#define RTC_CNTL_MEM_FORCE_PU \ + (RTC_CNTL_SLOWMEM_FORCE_PU | RTC_CNTL_FASTMEM_FORCE_PU) +#define RTC_CNTL_MEM_FORCE_PD \ + (RTC_CNTL_SLOWMEM_FORCE_PD | RTC_CNTL_FASTMEM_FORCE_PD) +#define RTC_CNTL_MEM_FOLW_CPU \ + (RTC_CNTL_SLOWMEM_FOLW_CPU | RTC_CNTL_FASTMEM_FOLW_CPU) +#define RTC_CNTL_MEM_FORCE_LPU \ + (RTC_CNTL_SLOWMEM_FORCE_LPU | RTC_CNTL_FASTMEM_FORCE_LPU) +#define RTC_CNTL_MEM_FORCE_LPD \ + (RTC_CNTL_SLOWMEM_FORCE_LPD | RTC_CNTL_FASTMEM_FORCE_LPD) + +#define RTC_CNTL_DIG_PWC_REG (DR_REG_RTCCNTL_BASE + 0x008C) +/* RTC_CNTL_DG_WRAP_PD_EN : R/W ;bitpos:[31] ;default: 0 ; */ +/*description: */ +#define RTC_CNTL_DG_WRAP_PD_EN (BIT(31)) +#define RTC_CNTL_DG_WRAP_PD_EN_M (BIT(31)) +#define RTC_CNTL_DG_WRAP_PD_EN_V 0x1 +#define RTC_CNTL_DG_WRAP_PD_EN_S 31 +/* RTC_CNTL_WIFI_PD_EN : R/W ;bitpos:[30] ;default: 0 ; */ +/*description: enable power down wifi in sleep*/ +#define RTC_CNTL_WIFI_PD_EN (BIT(30)) +#define RTC_CNTL_WIFI_PD_EN_M (BIT(30)) +#define RTC_CNTL_WIFI_PD_EN_V 0x1 +#define RTC_CNTL_WIFI_PD_EN_S 30 +/* RTC_CNTL_INTER_RAM4_PD_EN : R/W ;bitpos:[29] ;default: 0 ; */ +/*description: enable power down internal SRAM 4 in sleep*/ +#define RTC_CNTL_INTER_RAM4_PD_EN (BIT(29)) +#define RTC_CNTL_INTER_RAM4_PD_EN_M (BIT(29)) +#define RTC_CNTL_INTER_RAM4_PD_EN_V 0x1 +#define RTC_CNTL_INTER_RAM4_PD_EN_S 29 +/* RTC_CNTL_INTER_RAM3_PD_EN : R/W ;bitpos:[28] ;default: 0 ; */ +/*description: enable power down internal SRAM 3 in sleep*/ +#define RTC_CNTL_INTER_RAM3_PD_EN (BIT(28)) +#define RTC_CNTL_INTER_RAM3_PD_EN_M (BIT(28)) +#define RTC_CNTL_INTER_RAM3_PD_EN_V 0x1 +#define RTC_CNTL_INTER_RAM3_PD_EN_S 28 +/* RTC_CNTL_INTER_RAM2_PD_EN : R/W ;bitpos:[27] ;default: 0 ; */ +/*description: enable power down internal SRAM 2 in sleep*/ +#define RTC_CNTL_INTER_RAM2_PD_EN (BIT(27)) +#define RTC_CNTL_INTER_RAM2_PD_EN_M (BIT(27)) +#define RTC_CNTL_INTER_RAM2_PD_EN_V 0x1 +#define RTC_CNTL_INTER_RAM2_PD_EN_S 27 +/* RTC_CNTL_INTER_RAM1_PD_EN : R/W ;bitpos:[26] ;default: 0 ; */ +/*description: enable power down internal SRAM 1 in sleep*/ +#define RTC_CNTL_INTER_RAM1_PD_EN (BIT(26)) +#define RTC_CNTL_INTER_RAM1_PD_EN_M (BIT(26)) +#define RTC_CNTL_INTER_RAM1_PD_EN_V 0x1 +#define RTC_CNTL_INTER_RAM1_PD_EN_S 26 +/* RTC_CNTL_INTER_RAM0_PD_EN : R/W ;bitpos:[25] ;default: 0 ; */ +/*description: enable power down internal SRAM 0 in sleep*/ +#define RTC_CNTL_INTER_RAM0_PD_EN (BIT(25)) +#define RTC_CNTL_INTER_RAM0_PD_EN_M (BIT(25)) +#define RTC_CNTL_INTER_RAM0_PD_EN_V 0x1 +#define RTC_CNTL_INTER_RAM0_PD_EN_S 25 +/* RTC_CNTL_ROM0_PD_EN : R/W ;bitpos:[24] ;default: 0 ; */ +/*description: enable power down ROM in sleep*/ +#define RTC_CNTL_ROM0_PD_EN (BIT(24)) +#define RTC_CNTL_ROM0_PD_EN_M (BIT(24)) +#define RTC_CNTL_ROM0_PD_EN_V 0x1 +#define RTC_CNTL_ROM0_PD_EN_S 24 +/* RTC_CNTL_DG_DCDC_PD_EN : R/W ;bitpos:[23] ;default: 0 ; */ +/*description: enable power down digital dcdc in sleep*/ +#define RTC_CNTL_DG_DCDC_PD_EN (BIT(23)) +#define RTC_CNTL_DG_DCDC_PD_EN_M (BIT(23)) +#define RTC_CNTL_DG_DCDC_PD_EN_V 0x1 +#define RTC_CNTL_DG_DCDC_PD_EN_S 23 +/* RTC_CNTL_DG_DCDC_FORCE_PU : R/W ;bitpos:[22] ;default: 1'd1 ; */ +/*description: digital dcdc force power up*/ +#define RTC_CNTL_DG_DCDC_FORCE_PU (BIT(22)) +#define RTC_CNTL_DG_DCDC_FORCE_PU_M (BIT(22)) +#define RTC_CNTL_DG_DCDC_FORCE_PU_V 0x1 +#define RTC_CNTL_DG_DCDC_FORCE_PU_S 22 +/* RTC_CNTL_DG_DCDC_FORCE_PD : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: digital dcdc force power down*/ +#define RTC_CNTL_DG_DCDC_FORCE_PD (BIT(21)) +#define RTC_CNTL_DG_DCDC_FORCE_PD_M (BIT(21)) +#define RTC_CNTL_DG_DCDC_FORCE_PD_V 0x1 +#define RTC_CNTL_DG_DCDC_FORCE_PD_S 21 +/* RTC_CNTL_DG_WRAP_FORCE_PU : R/W ;bitpos:[20] ;default: 1'd1 ; */ +/*description: digital core force power up*/ +#define RTC_CNTL_DG_WRAP_FORCE_PU (BIT(20)) +#define RTC_CNTL_DG_WRAP_FORCE_PU_M (BIT(20)) +#define RTC_CNTL_DG_WRAP_FORCE_PU_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_PU_S 20 +/* RTC_CNTL_DG_WRAP_FORCE_PD : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: digital core force power down*/ +#define RTC_CNTL_DG_WRAP_FORCE_PD (BIT(19)) +#define RTC_CNTL_DG_WRAP_FORCE_PD_M (BIT(19)) +#define RTC_CNTL_DG_WRAP_FORCE_PD_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_PD_S 19 +/* RTC_CNTL_WIFI_FORCE_PU : R/W ;bitpos:[18] ;default: 1'd1 ; */ +/*description: wifi force power up*/ +#define RTC_CNTL_WIFI_FORCE_PU (BIT(18)) +#define RTC_CNTL_WIFI_FORCE_PU_M (BIT(18)) +#define RTC_CNTL_WIFI_FORCE_PU_V 0x1 +#define RTC_CNTL_WIFI_FORCE_PU_S 18 +/* RTC_CNTL_WIFI_FORCE_PD : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: wifi force power down*/ +#define RTC_CNTL_WIFI_FORCE_PD (BIT(17)) +#define RTC_CNTL_WIFI_FORCE_PD_M (BIT(17)) +#define RTC_CNTL_WIFI_FORCE_PD_V 0x1 +#define RTC_CNTL_WIFI_FORCE_PD_S 17 +/* RTC_CNTL_INTER_RAM4_FORCE_PU : R/W ;bitpos:[16] ;default: 1'd1 ; */ +/*description: internal SRAM 4 force power up*/ +#define RTC_CNTL_INTER_RAM4_FORCE_PU (BIT(16)) +#define RTC_CNTL_INTER_RAM4_FORCE_PU_M (BIT(16)) +#define RTC_CNTL_INTER_RAM4_FORCE_PU_V 0x1 +#define RTC_CNTL_INTER_RAM4_FORCE_PU_S 16 +/* RTC_CNTL_INTER_RAM4_FORCE_PD : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: internal SRAM 4 force power down*/ +#define RTC_CNTL_INTER_RAM4_FORCE_PD (BIT(15)) +#define RTC_CNTL_INTER_RAM4_FORCE_PD_M (BIT(15)) +#define RTC_CNTL_INTER_RAM4_FORCE_PD_V 0x1 +#define RTC_CNTL_INTER_RAM4_FORCE_PD_S 15 +/* RTC_CNTL_INTER_RAM3_FORCE_PU : R/W ;bitpos:[14] ;default: 1'd1 ; */ +/*description: internal SRAM 3 force power up*/ +#define RTC_CNTL_INTER_RAM3_FORCE_PU (BIT(14)) +#define RTC_CNTL_INTER_RAM3_FORCE_PU_M (BIT(14)) +#define RTC_CNTL_INTER_RAM3_FORCE_PU_V 0x1 +#define RTC_CNTL_INTER_RAM3_FORCE_PU_S 14 +/* RTC_CNTL_INTER_RAM3_FORCE_PD : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: internal SRAM 3 force power down*/ +#define RTC_CNTL_INTER_RAM3_FORCE_PD (BIT(13)) +#define RTC_CNTL_INTER_RAM3_FORCE_PD_M (BIT(13)) +#define RTC_CNTL_INTER_RAM3_FORCE_PD_V 0x1 +#define RTC_CNTL_INTER_RAM3_FORCE_PD_S 13 +/* RTC_CNTL_INTER_RAM2_FORCE_PU : R/W ;bitpos:[12] ;default: 1'd1 ; */ +/*description: internal SRAM 2 force power up*/ +#define RTC_CNTL_INTER_RAM2_FORCE_PU (BIT(12)) +#define RTC_CNTL_INTER_RAM2_FORCE_PU_M (BIT(12)) +#define RTC_CNTL_INTER_RAM2_FORCE_PU_V 0x1 +#define RTC_CNTL_INTER_RAM2_FORCE_PU_S 12 +/* RTC_CNTL_INTER_RAM2_FORCE_PD : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: internal SRAM 2 force power down*/ +#define RTC_CNTL_INTER_RAM2_FORCE_PD (BIT(11)) +#define RTC_CNTL_INTER_RAM2_FORCE_PD_M (BIT(11)) +#define RTC_CNTL_INTER_RAM2_FORCE_PD_V 0x1 +#define RTC_CNTL_INTER_RAM2_FORCE_PD_S 11 +/* RTC_CNTL_INTER_RAM1_FORCE_PU : R/W ;bitpos:[10] ;default: 1'd1 ; */ +/*description: internal SRAM 1 force power up*/ +#define RTC_CNTL_INTER_RAM1_FORCE_PU (BIT(10)) +#define RTC_CNTL_INTER_RAM1_FORCE_PU_M (BIT(10)) +#define RTC_CNTL_INTER_RAM1_FORCE_PU_V 0x1 +#define RTC_CNTL_INTER_RAM1_FORCE_PU_S 10 +/* RTC_CNTL_INTER_RAM1_FORCE_PD : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: internal SRAM 1 force power down*/ +#define RTC_CNTL_INTER_RAM1_FORCE_PD (BIT(9)) +#define RTC_CNTL_INTER_RAM1_FORCE_PD_M (BIT(9)) +#define RTC_CNTL_INTER_RAM1_FORCE_PD_V 0x1 +#define RTC_CNTL_INTER_RAM1_FORCE_PD_S 9 +/* RTC_CNTL_INTER_RAM0_FORCE_PU : R/W ;bitpos:[8] ;default: 1'd1 ; */ +/*description: internal SRAM 0 force power up*/ +#define RTC_CNTL_INTER_RAM0_FORCE_PU (BIT(8)) +#define RTC_CNTL_INTER_RAM0_FORCE_PU_M (BIT(8)) +#define RTC_CNTL_INTER_RAM0_FORCE_PU_V 0x1 +#define RTC_CNTL_INTER_RAM0_FORCE_PU_S 8 +/* RTC_CNTL_INTER_RAM0_FORCE_PD : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: internal SRAM 0 force power down*/ +#define RTC_CNTL_INTER_RAM0_FORCE_PD (BIT(7)) +#define RTC_CNTL_INTER_RAM0_FORCE_PD_M (BIT(7)) +#define RTC_CNTL_INTER_RAM0_FORCE_PD_V 0x1 +#define RTC_CNTL_INTER_RAM0_FORCE_PD_S 7 +/* RTC_CNTL_ROM0_FORCE_PU : R/W ;bitpos:[6] ;default: 1'd1 ; */ +/*description: ROM force power up*/ +#define RTC_CNTL_ROM0_FORCE_PU (BIT(6)) +#define RTC_CNTL_ROM0_FORCE_PU_M (BIT(6)) +#define RTC_CNTL_ROM0_FORCE_PU_V 0x1 +#define RTC_CNTL_ROM0_FORCE_PU_S 6 +/* RTC_CNTL_ROM0_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: ROM force power down*/ +#define RTC_CNTL_ROM0_FORCE_PD (BIT(5)) +#define RTC_CNTL_ROM0_FORCE_PD_M (BIT(5)) +#define RTC_CNTL_ROM0_FORCE_PD_V 0x1 +#define RTC_CNTL_ROM0_FORCE_PD_S 5 +/* RTC_CNTL_LSLP_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: memories in digital core force no PD in sleep*/ +#define RTC_CNTL_LSLP_MEM_FORCE_PU (BIT(4)) +#define RTC_CNTL_LSLP_MEM_FORCE_PU_M (BIT(4)) +#define RTC_CNTL_LSLP_MEM_FORCE_PU_V 0x1 +#define RTC_CNTL_LSLP_MEM_FORCE_PU_S 4 +/* RTC_CNTL_LSLP_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: memories in digital core force PD in sleep*/ +#define RTC_CNTL_LSLP_MEM_FORCE_PD (BIT(3)) +#define RTC_CNTL_LSLP_MEM_FORCE_PD_M (BIT(3)) +#define RTC_CNTL_LSLP_MEM_FORCE_PD_V 0x1 +#define RTC_CNTL_LSLP_MEM_FORCE_PD_S 3 + +#define RTC_CNTL_DIG_ISO_REG (DR_REG_RTCCNTL_BASE + 0x0090) +/* RTC_CNTL_DG_WRAP_FORCE_NOISO : R/W ;bitpos:[31] ;default: 1'd1 ; */ +/*description: */ +#define RTC_CNTL_DG_WRAP_FORCE_NOISO (BIT(31)) +#define RTC_CNTL_DG_WRAP_FORCE_NOISO_M (BIT(31)) +#define RTC_CNTL_DG_WRAP_FORCE_NOISO_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_NOISO_S 31 +/* RTC_CNTL_DG_WRAP_FORCE_ISO : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: digital core force ISO*/ +#define RTC_CNTL_DG_WRAP_FORCE_ISO (BIT(30)) +#define RTC_CNTL_DG_WRAP_FORCE_ISO_M (BIT(30)) +#define RTC_CNTL_DG_WRAP_FORCE_ISO_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_ISO_S 30 +/* RTC_CNTL_WIFI_FORCE_NOISO : R/W ;bitpos:[29] ;default: 1'd1 ; */ +/*description: wifi force no ISO*/ +#define RTC_CNTL_WIFI_FORCE_NOISO (BIT(29)) +#define RTC_CNTL_WIFI_FORCE_NOISO_M (BIT(29)) +#define RTC_CNTL_WIFI_FORCE_NOISO_V 0x1 +#define RTC_CNTL_WIFI_FORCE_NOISO_S 29 +/* RTC_CNTL_WIFI_FORCE_ISO : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: wifi force ISO*/ +#define RTC_CNTL_WIFI_FORCE_ISO (BIT(28)) +#define RTC_CNTL_WIFI_FORCE_ISO_M (BIT(28)) +#define RTC_CNTL_WIFI_FORCE_ISO_V 0x1 +#define RTC_CNTL_WIFI_FORCE_ISO_S 28 +/* RTC_CNTL_INTER_RAM4_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */ +/*description: internal SRAM 4 force no ISO*/ +#define RTC_CNTL_INTER_RAM4_FORCE_NOISO (BIT(27)) +#define RTC_CNTL_INTER_RAM4_FORCE_NOISO_M (BIT(27)) +#define RTC_CNTL_INTER_RAM4_FORCE_NOISO_V 0x1 +#define RTC_CNTL_INTER_RAM4_FORCE_NOISO_S 27 +/* RTC_CNTL_INTER_RAM4_FORCE_ISO : R/W ;bitpos:[26] ;default: 1'd0 ; */ +/*description: internal SRAM 4 force ISO*/ +#define RTC_CNTL_INTER_RAM4_FORCE_ISO (BIT(26)) +#define RTC_CNTL_INTER_RAM4_FORCE_ISO_M (BIT(26)) +#define RTC_CNTL_INTER_RAM4_FORCE_ISO_V 0x1 +#define RTC_CNTL_INTER_RAM4_FORCE_ISO_S 26 +/* RTC_CNTL_INTER_RAM3_FORCE_NOISO : R/W ;bitpos:[25] ;default: 1'd1 ; */ +/*description: internal SRAM 3 force no ISO*/ +#define RTC_CNTL_INTER_RAM3_FORCE_NOISO (BIT(25)) +#define RTC_CNTL_INTER_RAM3_FORCE_NOISO_M (BIT(25)) +#define RTC_CNTL_INTER_RAM3_FORCE_NOISO_V 0x1 +#define RTC_CNTL_INTER_RAM3_FORCE_NOISO_S 25 +/* RTC_CNTL_INTER_RAM3_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */ +/*description: internal SRAM 3 force ISO*/ +#define RTC_CNTL_INTER_RAM3_FORCE_ISO (BIT(24)) +#define RTC_CNTL_INTER_RAM3_FORCE_ISO_M (BIT(24)) +#define RTC_CNTL_INTER_RAM3_FORCE_ISO_V 0x1 +#define RTC_CNTL_INTER_RAM3_FORCE_ISO_S 24 +/* RTC_CNTL_INTER_RAM2_FORCE_NOISO : R/W ;bitpos:[23] ;default: 1'd1 ; */ +/*description: internal SRAM 2 force no ISO*/ +#define RTC_CNTL_INTER_RAM2_FORCE_NOISO (BIT(23)) +#define RTC_CNTL_INTER_RAM2_FORCE_NOISO_M (BIT(23)) +#define RTC_CNTL_INTER_RAM2_FORCE_NOISO_V 0x1 +#define RTC_CNTL_INTER_RAM2_FORCE_NOISO_S 23 +/* RTC_CNTL_INTER_RAM2_FORCE_ISO : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: internal SRAM 2 force ISO*/ +#define RTC_CNTL_INTER_RAM2_FORCE_ISO (BIT(22)) +#define RTC_CNTL_INTER_RAM2_FORCE_ISO_M (BIT(22)) +#define RTC_CNTL_INTER_RAM2_FORCE_ISO_V 0x1 +#define RTC_CNTL_INTER_RAM2_FORCE_ISO_S 22 +/* RTC_CNTL_INTER_RAM1_FORCE_NOISO : R/W ;bitpos:[21] ;default: 1'd1 ; */ +/*description: internal SRAM 1 force no ISO*/ +#define RTC_CNTL_INTER_RAM1_FORCE_NOISO (BIT(21)) +#define RTC_CNTL_INTER_RAM1_FORCE_NOISO_M (BIT(21)) +#define RTC_CNTL_INTER_RAM1_FORCE_NOISO_V 0x1 +#define RTC_CNTL_INTER_RAM1_FORCE_NOISO_S 21 +/* RTC_CNTL_INTER_RAM1_FORCE_ISO : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: internal SRAM 1 force ISO*/ +#define RTC_CNTL_INTER_RAM1_FORCE_ISO (BIT(20)) +#define RTC_CNTL_INTER_RAM1_FORCE_ISO_M (BIT(20)) +#define RTC_CNTL_INTER_RAM1_FORCE_ISO_V 0x1 +#define RTC_CNTL_INTER_RAM1_FORCE_ISO_S 20 +/* RTC_CNTL_INTER_RAM0_FORCE_NOISO : R/W ;bitpos:[19] ;default: 1'd1 ; */ +/*description: internal SRAM 0 force no ISO*/ +#define RTC_CNTL_INTER_RAM0_FORCE_NOISO (BIT(19)) +#define RTC_CNTL_INTER_RAM0_FORCE_NOISO_M (BIT(19)) +#define RTC_CNTL_INTER_RAM0_FORCE_NOISO_V 0x1 +#define RTC_CNTL_INTER_RAM0_FORCE_NOISO_S 19 +/* RTC_CNTL_INTER_RAM0_FORCE_ISO : R/W ;bitpos:[18] ;default: 1'd0 ; */ +/*description: internal SRAM 0 force ISO*/ +#define RTC_CNTL_INTER_RAM0_FORCE_ISO (BIT(18)) +#define RTC_CNTL_INTER_RAM0_FORCE_ISO_M (BIT(18)) +#define RTC_CNTL_INTER_RAM0_FORCE_ISO_V 0x1 +#define RTC_CNTL_INTER_RAM0_FORCE_ISO_S 18 +/* RTC_CNTL_ROM0_FORCE_NOISO : R/W ;bitpos:[17] ;default: 1'd1 ; */ +/*description: ROM force no ISO*/ +#define RTC_CNTL_ROM0_FORCE_NOISO (BIT(17)) +#define RTC_CNTL_ROM0_FORCE_NOISO_M (BIT(17)) +#define RTC_CNTL_ROM0_FORCE_NOISO_V 0x1 +#define RTC_CNTL_ROM0_FORCE_NOISO_S 17 +/* RTC_CNTL_ROM0_FORCE_ISO : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: ROM force ISO*/ +#define RTC_CNTL_ROM0_FORCE_ISO (BIT(16)) +#define RTC_CNTL_ROM0_FORCE_ISO_M (BIT(16)) +#define RTC_CNTL_ROM0_FORCE_ISO_V 0x1 +#define RTC_CNTL_ROM0_FORCE_ISO_S 16 +/* RTC_CNTL_DG_PAD_FORCE_HOLD : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: digital pad force hold*/ +#define RTC_CNTL_DG_PAD_FORCE_HOLD (BIT(15)) +#define RTC_CNTL_DG_PAD_FORCE_HOLD_M (BIT(15)) +#define RTC_CNTL_DG_PAD_FORCE_HOLD_V 0x1 +#define RTC_CNTL_DG_PAD_FORCE_HOLD_S 15 +/* RTC_CNTL_DG_PAD_FORCE_UNHOLD : R/W ;bitpos:[14] ;default: 1'd1 ; */ +/*description: digital pad force un-hold*/ +#define RTC_CNTL_DG_PAD_FORCE_UNHOLD (BIT(14)) +#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_M (BIT(14)) +#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_V 0x1 +#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_S 14 +/* RTC_CNTL_DG_PAD_FORCE_ISO : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: digital pad force ISO*/ +#define RTC_CNTL_DG_PAD_FORCE_ISO (BIT(13)) +#define RTC_CNTL_DG_PAD_FORCE_ISO_M (BIT(13)) +#define RTC_CNTL_DG_PAD_FORCE_ISO_V 0x1 +#define RTC_CNTL_DG_PAD_FORCE_ISO_S 13 +/* RTC_CNTL_DG_PAD_FORCE_NOISO : R/W ;bitpos:[12] ;default: 1'd1 ; */ +/*description: digital pad force no ISO*/ +#define RTC_CNTL_DG_PAD_FORCE_NOISO (BIT(12)) +#define RTC_CNTL_DG_PAD_FORCE_NOISO_M (BIT(12)) +#define RTC_CNTL_DG_PAD_FORCE_NOISO_V 0x1 +#define RTC_CNTL_DG_PAD_FORCE_NOISO_S 12 +/* RTC_CNTL_DG_PAD_AUTOHOLD_EN : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: digital pad enable auto-hold*/ +#define RTC_CNTL_DG_PAD_AUTOHOLD_EN (BIT(11)) +#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_M (BIT(11)) +#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_V 0x1 +#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_S 11 +/* RTC_CNTL_CLR_DG_PAD_AUTOHOLD : WO ;bitpos:[10] ;default: 1'd0 ; */ +/*description: wtite only register to clear digital pad auto-hold*/ +#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD (BIT(10)) +#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_M (BIT(10)) +#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_V 0x1 +#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_S 10 +/* RTC_CNTL_DG_PAD_AUTOHOLD : RO ;bitpos:[9] ;default: 1'd0 ; */ +/*description: read only register to indicate digital pad auto-hold status*/ +#define RTC_CNTL_DG_PAD_AUTOHOLD (BIT(9)) +#define RTC_CNTL_DG_PAD_AUTOHOLD_M (BIT(9)) +#define RTC_CNTL_DG_PAD_AUTOHOLD_V 0x1 +#define RTC_CNTL_DG_PAD_AUTOHOLD_S 9 +/* RTC_CNTL_DIG_ISO_FORCE_ON : R/W ;bitpos:[8] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_DIG_ISO_FORCE_ON (BIT(8)) +#define RTC_CNTL_DIG_ISO_FORCE_ON_M (BIT(8)) +#define RTC_CNTL_DIG_ISO_FORCE_ON_V 0x1 +#define RTC_CNTL_DIG_ISO_FORCE_ON_S 8 +/* RTC_CNTL_DIG_ISO_FORCE_OFF : R/W ;bitpos:[7] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_DIG_ISO_FORCE_OFF (BIT(7)) +#define RTC_CNTL_DIG_ISO_FORCE_OFF_M (BIT(7)) +#define RTC_CNTL_DIG_ISO_FORCE_OFF_V 0x1 +#define RTC_CNTL_DIG_ISO_FORCE_OFF_S 7 + +#define RTC_CNTL_WDTCONFIG0_REG (DR_REG_RTCCNTL_BASE + 0x0094) +/* RTC_CNTL_WDT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: */ +#define RTC_CNTL_WDT_EN (BIT(31)) +#define RTC_CNTL_WDT_EN_M (BIT(31)) +#define RTC_CNTL_WDT_EN_V 0x1 +#define RTC_CNTL_WDT_EN_S 31 +/* RTC_CNTL_WDT_STG0 : R/W ;bitpos:[30:28] ;default: 3'h0 ; */ +/*description: 1: interrupt stage en 2: CPU reset stage en 3: system reset + stage en 4: RTC reset stage en*/ +#define RTC_CNTL_WDT_STG0 0x00000007 +#define RTC_CNTL_WDT_STG0_M ((RTC_CNTL_WDT_STG0_V)<<(RTC_CNTL_WDT_STG0_S)) +#define RTC_CNTL_WDT_STG0_V 0x7 +#define RTC_CNTL_WDT_STG0_S 28 +/* RTC_CNTL_WDT_STG1 : R/W ;bitpos:[27:25] ;default: 3'h0 ; */ +/*description: 1: interrupt stage en 2: CPU reset stage en 3: system reset + stage en 4: RTC reset stage en*/ +#define RTC_CNTL_WDT_STG1 0x00000007 +#define RTC_CNTL_WDT_STG1_M ((RTC_CNTL_WDT_STG1_V)<<(RTC_CNTL_WDT_STG1_S)) +#define RTC_CNTL_WDT_STG1_V 0x7 +#define RTC_CNTL_WDT_STG1_S 25 +/* RTC_CNTL_WDT_STG2 : R/W ;bitpos:[24:22] ;default: 3'h0 ; */ +/*description: 1: interrupt stage en 2: CPU reset stage en 3: system reset + stage en 4: RTC reset stage en*/ +#define RTC_CNTL_WDT_STG2 0x00000007 +#define RTC_CNTL_WDT_STG2_M ((RTC_CNTL_WDT_STG2_V)<<(RTC_CNTL_WDT_STG2_S)) +#define RTC_CNTL_WDT_STG2_V 0x7 +#define RTC_CNTL_WDT_STG2_S 22 +/* RTC_CNTL_WDT_STG3 : R/W ;bitpos:[21:19] ;default: 3'h0 ; */ +/*description: 1: interrupt stage en 2: CPU reset stage en 3: system reset + stage en 4: RTC reset stage en*/ +#define RTC_CNTL_WDT_STG3 0x00000007 +#define RTC_CNTL_WDT_STG3_M ((RTC_CNTL_WDT_STG3_V)<<(RTC_CNTL_WDT_STG3_S)) +#define RTC_CNTL_WDT_STG3_V 0x7 +#define RTC_CNTL_WDT_STG3_S 19 +/* RTC_CNTL_WDT_STGX : */ +/*description: stage action selection values */ +#define RTC_WDT_STG_SEL_OFF 0 +#define RTC_WDT_STG_SEL_INT 1 +#define RTC_WDT_STG_SEL_RESET_CPU 2 +#define RTC_WDT_STG_SEL_RESET_SYSTEM 3 +#define RTC_WDT_STG_SEL_RESET_RTC 4 + +/* RTC_CNTL_WDT_CPU_RESET_LENGTH : R/W ;bitpos:[18:16] ;default: 3'h1 ; */ +/*description: CPU reset counter length*/ +#define RTC_CNTL_WDT_CPU_RESET_LENGTH 0x00000007 +#define RTC_CNTL_WDT_CPU_RESET_LENGTH_M ((RTC_CNTL_WDT_CPU_RESET_LENGTH_V)<<(RTC_CNTL_WDT_CPU_RESET_LENGTH_S)) +#define RTC_CNTL_WDT_CPU_RESET_LENGTH_V 0x7 +#define RTC_CNTL_WDT_CPU_RESET_LENGTH_S 16 +/* RTC_CNTL_WDT_SYS_RESET_LENGTH : R/W ;bitpos:[15:13] ;default: 3'h1 ; */ +/*description: system reset counter length*/ +#define RTC_CNTL_WDT_SYS_RESET_LENGTH 0x00000007 +#define RTC_CNTL_WDT_SYS_RESET_LENGTH_M ((RTC_CNTL_WDT_SYS_RESET_LENGTH_V)<<(RTC_CNTL_WDT_SYS_RESET_LENGTH_S)) +#define RTC_CNTL_WDT_SYS_RESET_LENGTH_V 0x7 +#define RTC_CNTL_WDT_SYS_RESET_LENGTH_S 13 +/* RTC_CNTL_WDT_FLASHBOOT_MOD_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */ +/*description: enable WDT in flash boot*/ +#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN (BIT(12)) +#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_M (BIT(12)) +#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_V 0x1 +#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_S 12 +/* RTC_CNTL_WDT_PROCPU_RESET_EN : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: enable WDT reset PRO CPU*/ +#define RTC_CNTL_WDT_PROCPU_RESET_EN (BIT(11)) +#define RTC_CNTL_WDT_PROCPU_RESET_EN_M (BIT(11)) +#define RTC_CNTL_WDT_PROCPU_RESET_EN_V 0x1 +#define RTC_CNTL_WDT_PROCPU_RESET_EN_S 11 +/* RTC_CNTL_WDT_APPCPU_RESET_EN : R/W ;bitpos:[10] ;default: 1'd0 ; */ +/*description: enable WDT reset APP CPU*/ +#define RTC_CNTL_WDT_APPCPU_RESET_EN (BIT(10)) +#define RTC_CNTL_WDT_APPCPU_RESET_EN_M (BIT(10)) +#define RTC_CNTL_WDT_APPCPU_RESET_EN_V 0x1 +#define RTC_CNTL_WDT_APPCPU_RESET_EN_S 10 +/* RTC_CNTL_WDT_PAUSE_IN_SLP : R/W ;bitpos:[9] ;default: 1'd1 ; */ +/*description: pause WDT in sleep*/ +#define RTC_CNTL_WDT_PAUSE_IN_SLP (BIT(9)) +#define RTC_CNTL_WDT_PAUSE_IN_SLP_M (BIT(9)) +#define RTC_CNTL_WDT_PAUSE_IN_SLP_V 0x1 +#define RTC_CNTL_WDT_PAUSE_IN_SLP_S 9 +/* RTC_CNTL_WDT_CHIP_RESET_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: wdt reset whole chip enable*/ +#define RTC_CNTL_WDT_CHIP_RESET_EN (BIT(8)) +#define RTC_CNTL_WDT_CHIP_RESET_EN_M (BIT(8)) +#define RTC_CNTL_WDT_CHIP_RESET_EN_V 0x1 +#define RTC_CNTL_WDT_CHIP_RESET_EN_S 8 +/* RTC_CNTL_WDT_CHIP_RESET_WIDTH : R/W ;bitpos:[7:0] ;default: 8'd20 ; */ +/*description: chip reset siginal pulse width*/ +#define RTC_CNTL_WDT_CHIP_RESET_WIDTH 0x000000FF +#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_M ((RTC_CNTL_WDT_CHIP_RESET_WIDTH_V)<<(RTC_CNTL_WDT_CHIP_RESET_WIDTH_S)) +#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_V 0xFF +#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_S 0 + +#define RTC_CNTL_WDTCONFIG1_REG (DR_REG_RTCCNTL_BASE + 0x0098) +/* RTC_CNTL_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd200000 ; */ +/*description: */ +#define RTC_CNTL_WDT_STG0_HOLD 0xFFFFFFFF +#define RTC_CNTL_WDT_STG0_HOLD_M ((RTC_CNTL_WDT_STG0_HOLD_V)<<(RTC_CNTL_WDT_STG0_HOLD_S)) +#define RTC_CNTL_WDT_STG0_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_WDT_STG0_HOLD_S 0 + +#define RTC_CNTL_WDTCONFIG2_REG (DR_REG_RTCCNTL_BASE + 0x009C) +/* RTC_CNTL_WDT_STG1_HOLD : R/W ;bitpos:[31:0] ;default: 32'd80000 ; */ +/*description: */ +#define RTC_CNTL_WDT_STG1_HOLD 0xFFFFFFFF +#define RTC_CNTL_WDT_STG1_HOLD_M ((RTC_CNTL_WDT_STG1_HOLD_V)<<(RTC_CNTL_WDT_STG1_HOLD_S)) +#define RTC_CNTL_WDT_STG1_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_WDT_STG1_HOLD_S 0 + +#define RTC_CNTL_WDTCONFIG3_REG (DR_REG_RTCCNTL_BASE + 0x00A0) +/* RTC_CNTL_WDT_STG2_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */ +/*description: */ +#define RTC_CNTL_WDT_STG2_HOLD 0xFFFFFFFF +#define RTC_CNTL_WDT_STG2_HOLD_M ((RTC_CNTL_WDT_STG2_HOLD_V)<<(RTC_CNTL_WDT_STG2_HOLD_S)) +#define RTC_CNTL_WDT_STG2_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_WDT_STG2_HOLD_S 0 + +#define RTC_CNTL_WDTCONFIG4_REG (DR_REG_RTCCNTL_BASE + 0x00A4) +/* RTC_CNTL_WDT_STG3_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */ +/*description: */ +#define RTC_CNTL_WDT_STG3_HOLD 0xFFFFFFFF +#define RTC_CNTL_WDT_STG3_HOLD_M ((RTC_CNTL_WDT_STG3_HOLD_V)<<(RTC_CNTL_WDT_STG3_HOLD_S)) +#define RTC_CNTL_WDT_STG3_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_WDT_STG3_HOLD_S 0 + +#define RTC_CNTL_WDTFEED_REG (DR_REG_RTCCNTL_BASE + 0x00A8) +/* RTC_CNTL_WDT_FEED : WO ;bitpos:[31] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_WDT_FEED (BIT(31)) +#define RTC_CNTL_WDT_FEED_M (BIT(31)) +#define RTC_CNTL_WDT_FEED_V 0x1 +#define RTC_CNTL_WDT_FEED_S 31 + +#define RTC_CNTL_WDTWPROTECT_REG (DR_REG_RTCCNTL_BASE + 0x00AC) +/* RTC_CNTL_WDT_WKEY : R/W ;bitpos:[31:0] ;default: 32'h50d83aa1 ; */ +/*description: */ +#define RTC_CNTL_WDT_WKEY 0xFFFFFFFF +#define RTC_CNTL_WDT_WKEY_M ((RTC_CNTL_WDT_WKEY_V)<<(RTC_CNTL_WDT_WKEY_S)) +#define RTC_CNTL_WDT_WKEY_V 0xFFFFFFFF +#define RTC_CNTL_WDT_WKEY_S 0 + +#define RTC_CNTL_SWD_CONF_REG (DR_REG_RTCCNTL_BASE + 0x00B0) +/* RTC_CNTL_SWD_AUTO_FEED_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: automatically feed swd when int comes*/ +#define RTC_CNTL_SWD_AUTO_FEED_EN (BIT(31)) +#define RTC_CNTL_SWD_AUTO_FEED_EN_M (BIT(31)) +#define RTC_CNTL_SWD_AUTO_FEED_EN_V 0x1 +#define RTC_CNTL_SWD_AUTO_FEED_EN_S 31 +/* RTC_CNTL_SWD_DISABLE : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: disable SWD*/ +#define RTC_CNTL_SWD_DISABLE (BIT(30)) +#define RTC_CNTL_SWD_DISABLE_M (BIT(30)) +#define RTC_CNTL_SWD_DISABLE_V 0x1 +#define RTC_CNTL_SWD_DISABLE_S 30 +/* RTC_CNTL_SWD_FEED : WO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: Sw feed swd*/ +#define RTC_CNTL_SWD_FEED (BIT(29)) +#define RTC_CNTL_SWD_FEED_M (BIT(29)) +#define RTC_CNTL_SWD_FEED_V 0x1 +#define RTC_CNTL_SWD_FEED_S 29 +/* RTC_CNTL_SWD_RST_FLAG_CLR : WO ;bitpos:[28] ;default: 1'b0 ; */ +/*description: reset swd reset flag*/ +#define RTC_CNTL_SWD_RST_FLAG_CLR (BIT(28)) +#define RTC_CNTL_SWD_RST_FLAG_CLR_M (BIT(28)) +#define RTC_CNTL_SWD_RST_FLAG_CLR_V 0x1 +#define RTC_CNTL_SWD_RST_FLAG_CLR_S 28 +/* RTC_CNTL_SWD_SIGNAL_WIDTH : R/W ;bitpos:[27:18] ;default: 10'd300 ; */ +/*description: adjust signal width send to swd*/ +#define RTC_CNTL_SWD_SIGNAL_WIDTH 0x000003FF +#define RTC_CNTL_SWD_SIGNAL_WIDTH_M ((RTC_CNTL_SWD_SIGNAL_WIDTH_V)<<(RTC_CNTL_SWD_SIGNAL_WIDTH_S)) +#define RTC_CNTL_SWD_SIGNAL_WIDTH_V 0x3FF +#define RTC_CNTL_SWD_SIGNAL_WIDTH_S 18 +/* RTC_CNTL_SWD_FEED_INT : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: swd interrupt for feeding*/ +#define RTC_CNTL_SWD_FEED_INT (BIT(1)) +#define RTC_CNTL_SWD_FEED_INT_M (BIT(1)) +#define RTC_CNTL_SWD_FEED_INT_V 0x1 +#define RTC_CNTL_SWD_FEED_INT_S 1 +/* RTC_CNTL_SWD_RESET_FLAG : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: swd reset flag*/ +#define RTC_CNTL_SWD_RESET_FLAG (BIT(0)) +#define RTC_CNTL_SWD_RESET_FLAG_M (BIT(0)) +#define RTC_CNTL_SWD_RESET_FLAG_V 0x1 +#define RTC_CNTL_SWD_RESET_FLAG_S 0 + +#define RTC_CNTL_SWD_WPROTECT_REG (DR_REG_RTCCNTL_BASE + 0x00B4) +/* RTC_CNTL_SWD_WKEY : R/W ;bitpos:[31:0] ;default: 32'h8f1d312a ; */ +/*description: swd write protect*/ +#define RTC_CNTL_SWD_WKEY 0xFFFFFFFF +#define RTC_CNTL_SWD_WKEY_M ((RTC_CNTL_SWD_WKEY_V)<<(RTC_CNTL_SWD_WKEY_S)) +#define RTC_CNTL_SWD_WKEY_V 0xFFFFFFFF +#define RTC_CNTL_SWD_WKEY_S 0 + +#define RTC_CNTL_SW_CPU_STALL_REG (DR_REG_RTCCNTL_BASE + 0x00B8) +/* RTC_CNTL_SW_STALL_PROCPU_C1 : R/W ;bitpos:[31:26] ;default: 6'b0 ; */ +/*description: */ +#define RTC_CNTL_SW_STALL_PROCPU_C1 0x0000003F +#define RTC_CNTL_SW_STALL_PROCPU_C1_M ((RTC_CNTL_SW_STALL_PROCPU_C1_V)<<(RTC_CNTL_SW_STALL_PROCPU_C1_S)) +#define RTC_CNTL_SW_STALL_PROCPU_C1_V 0x3F +#define RTC_CNTL_SW_STALL_PROCPU_C1_S 26 +/* RTC_CNTL_SW_STALL_APPCPU_C1 : R/W ;bitpos:[25:20] ;default: 6'b0 ; */ +/*description: {reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == + 0x86 will stall APP CPU*/ +#define RTC_CNTL_SW_STALL_APPCPU_C1 0x0000003F +#define RTC_CNTL_SW_STALL_APPCPU_C1_M ((RTC_CNTL_SW_STALL_APPCPU_C1_V)<<(RTC_CNTL_SW_STALL_APPCPU_C1_S)) +#define RTC_CNTL_SW_STALL_APPCPU_C1_V 0x3F +#define RTC_CNTL_SW_STALL_APPCPU_C1_S 20 + +#define RTC_CNTL_STORE4_REG (DR_REG_RTCCNTL_BASE + 0x00BC) +/* RTC_CNTL_SCRATCH4 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: */ +#define RTC_CNTL_SCRATCH4 0xFFFFFFFF +#define RTC_CNTL_SCRATCH4_M ((RTC_CNTL_SCRATCH4_V)<<(RTC_CNTL_SCRATCH4_S)) +#define RTC_CNTL_SCRATCH4_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH4_S 0 + +#define RTC_CNTL_STORE5_REG (DR_REG_RTCCNTL_BASE + 0x00C0) +/* RTC_CNTL_SCRATCH5 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: */ +#define RTC_CNTL_SCRATCH5 0xFFFFFFFF +#define RTC_CNTL_SCRATCH5_M ((RTC_CNTL_SCRATCH5_V)<<(RTC_CNTL_SCRATCH5_S)) +#define RTC_CNTL_SCRATCH5_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH5_S 0 + +#define RTC_CNTL_STORE6_REG (DR_REG_RTCCNTL_BASE + 0x00C4) +/* RTC_CNTL_SCRATCH6 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: */ +#define RTC_CNTL_SCRATCH6 0xFFFFFFFF +#define RTC_CNTL_SCRATCH6_M ((RTC_CNTL_SCRATCH6_V)<<(RTC_CNTL_SCRATCH6_S)) +#define RTC_CNTL_SCRATCH6_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH6_S 0 + +#define RTC_CNTL_STORE7_REG (DR_REG_RTCCNTL_BASE + 0x00C8) +/* RTC_CNTL_SCRATCH7 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: */ +#define RTC_CNTL_SCRATCH7 0xFFFFFFFF +#define RTC_CNTL_SCRATCH7_M ((RTC_CNTL_SCRATCH7_V)<<(RTC_CNTL_SCRATCH7_S)) +#define RTC_CNTL_SCRATCH7_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH7_S 0 + +#define RTC_CNTL_LOW_POWER_ST_REG (DR_REG_RTCCNTL_BASE + 0x00CC) +/* RTC_CNTL_MAIN_STATE : RO ;bitpos:[31:28] ;default: 4'd0 ; */ +/*description: rtc main state machine status*/ +#define RTC_CNTL_MAIN_STATE 0x0000000F +#define RTC_CNTL_MAIN_STATE_M ((RTC_CNTL_MAIN_STATE_V)<<(RTC_CNTL_MAIN_STATE_S)) +#define RTC_CNTL_MAIN_STATE_V 0xF +#define RTC_CNTL_MAIN_STATE_S 28 +/* RTC_CNTL_MAIN_STATE_IN_IDLE : RO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: rtc main state machine is in idle state*/ +#define RTC_CNTL_MAIN_STATE_IN_IDLE (BIT(27)) +#define RTC_CNTL_MAIN_STATE_IN_IDLE_M (BIT(27)) +#define RTC_CNTL_MAIN_STATE_IN_IDLE_V 0x1 +#define RTC_CNTL_MAIN_STATE_IN_IDLE_S 27 +/* RTC_CNTL_MAIN_STATE_IN_SLP : RO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: rtc main state machine is in sleep state*/ +#define RTC_CNTL_MAIN_STATE_IN_SLP (BIT(26)) +#define RTC_CNTL_MAIN_STATE_IN_SLP_M (BIT(26)) +#define RTC_CNTL_MAIN_STATE_IN_SLP_V 0x1 +#define RTC_CNTL_MAIN_STATE_IN_SLP_S 26 +/* RTC_CNTL_MAIN_STATE_IN_WAIT_XTL : RO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: rtc main state machine is in wait xtal state*/ +#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL (BIT(25)) +#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_M (BIT(25)) +#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_V 0x1 +#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_S 25 +/* RTC_CNTL_MAIN_STATE_IN_WAIT_PLL : RO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: rtc main state machine is in wait pll state*/ +#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL (BIT(24)) +#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_M (BIT(24)) +#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_V 0x1 +#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_S 24 +/* RTC_CNTL_MAIN_STATE_IN_WAIT_8M : RO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: rtc main state machine is in wait 8m state*/ +#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M (BIT(23)) +#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_M (BIT(23)) +#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_V 0x1 +#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_S 23 +/* RTC_CNTL_IN_LOW_POWER_STATE : RO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: rtc main state machine is in the states of low power*/ +#define RTC_CNTL_IN_LOW_POWER_STATE (BIT(22)) +#define RTC_CNTL_IN_LOW_POWER_STATE_M (BIT(22)) +#define RTC_CNTL_IN_LOW_POWER_STATE_V 0x1 +#define RTC_CNTL_IN_LOW_POWER_STATE_S 22 +/* RTC_CNTL_IN_WAKEUP_STATE : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: rtc main state machine is in the states of wakeup process*/ +#define RTC_CNTL_IN_WAKEUP_STATE (BIT(21)) +#define RTC_CNTL_IN_WAKEUP_STATE_M (BIT(21)) +#define RTC_CNTL_IN_WAKEUP_STATE_V 0x1 +#define RTC_CNTL_IN_WAKEUP_STATE_S 21 +/* RTC_CNTL_MAIN_STATE_WAIT_END : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: rtc main state machine has been waited for some cycles*/ +#define RTC_CNTL_MAIN_STATE_WAIT_END (BIT(20)) +#define RTC_CNTL_MAIN_STATE_WAIT_END_M (BIT(20)) +#define RTC_CNTL_MAIN_STATE_WAIT_END_V 0x1 +#define RTC_CNTL_MAIN_STATE_WAIT_END_S 20 +/* RTC_CNTL_RDY_FOR_WAKEUP : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: rtc is ready to receive wake up trigger from wake up source*/ +#define RTC_CNTL_RDY_FOR_WAKEUP (BIT(19)) +#define RTC_CNTL_RDY_FOR_WAKEUP_M (BIT(19)) +#define RTC_CNTL_RDY_FOR_WAKEUP_V 0x1 +#define RTC_CNTL_RDY_FOR_WAKEUP_S 19 +/* RTC_CNTL_MAIN_STATE_PLL_ON : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: rtc main state machine is in states that pll should be running*/ +#define RTC_CNTL_MAIN_STATE_PLL_ON (BIT(18)) +#define RTC_CNTL_MAIN_STATE_PLL_ON_M (BIT(18)) +#define RTC_CNTL_MAIN_STATE_PLL_ON_V 0x1 +#define RTC_CNTL_MAIN_STATE_PLL_ON_S 18 +/* RTC_CNTL_MAIN_STATE_XTAL_ISO : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: no use any more*/ +#define RTC_CNTL_MAIN_STATE_XTAL_ISO (BIT(17)) +#define RTC_CNTL_MAIN_STATE_XTAL_ISO_M (BIT(17)) +#define RTC_CNTL_MAIN_STATE_XTAL_ISO_V 0x1 +#define RTC_CNTL_MAIN_STATE_XTAL_ISO_S 17 +/* RTC_CNTL_COCPU_STATE_DONE : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: ulp/cocpu is done*/ +#define RTC_CNTL_COCPU_STATE_DONE (BIT(16)) +#define RTC_CNTL_COCPU_STATE_DONE_M (BIT(16)) +#define RTC_CNTL_COCPU_STATE_DONE_V 0x1 +#define RTC_CNTL_COCPU_STATE_DONE_S 16 +/* RTC_CNTL_COCPU_STATE_SLP : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: ulp/cocpu is in sleep state*/ +#define RTC_CNTL_COCPU_STATE_SLP (BIT(15)) +#define RTC_CNTL_COCPU_STATE_SLP_M (BIT(15)) +#define RTC_CNTL_COCPU_STATE_SLP_V 0x1 +#define RTC_CNTL_COCPU_STATE_SLP_S 15 +/* RTC_CNTL_COCPU_STATE_SWITCH : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: ulp/cocpu is about to working. Switch rtc main state*/ +#define RTC_CNTL_COCPU_STATE_SWITCH (BIT(14)) +#define RTC_CNTL_COCPU_STATE_SWITCH_M (BIT(14)) +#define RTC_CNTL_COCPU_STATE_SWITCH_V 0x1 +#define RTC_CNTL_COCPU_STATE_SWITCH_S 14 +/* RTC_CNTL_COCPU_STATE_START : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: ulp/cocpu should start to work*/ +#define RTC_CNTL_COCPU_STATE_START (BIT(13)) +#define RTC_CNTL_COCPU_STATE_START_M (BIT(13)) +#define RTC_CNTL_COCPU_STATE_START_V 0x1 +#define RTC_CNTL_COCPU_STATE_START_S 13 +/* RTC_CNTL_TOUCH_STATE_DONE : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: touch is done*/ +#define RTC_CNTL_TOUCH_STATE_DONE (BIT(12)) +#define RTC_CNTL_TOUCH_STATE_DONE_M (BIT(12)) +#define RTC_CNTL_TOUCH_STATE_DONE_V 0x1 +#define RTC_CNTL_TOUCH_STATE_DONE_S 12 +/* RTC_CNTL_TOUCH_STATE_SLP : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: touch is in sleep state*/ +#define RTC_CNTL_TOUCH_STATE_SLP (BIT(11)) +#define RTC_CNTL_TOUCH_STATE_SLP_M (BIT(11)) +#define RTC_CNTL_TOUCH_STATE_SLP_V 0x1 +#define RTC_CNTL_TOUCH_STATE_SLP_S 11 +/* RTC_CNTL_TOUCH_STATE_SWITCH : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: touch is about to working. Switch rtc main state*/ +#define RTC_CNTL_TOUCH_STATE_SWITCH (BIT(10)) +#define RTC_CNTL_TOUCH_STATE_SWITCH_M (BIT(10)) +#define RTC_CNTL_TOUCH_STATE_SWITCH_V 0x1 +#define RTC_CNTL_TOUCH_STATE_SWITCH_S 10 +/* RTC_CNTL_TOUCH_STATE_START : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: touch should start to work*/ +#define RTC_CNTL_TOUCH_STATE_START (BIT(9)) +#define RTC_CNTL_TOUCH_STATE_START_M (BIT(9)) +#define RTC_CNTL_TOUCH_STATE_START_V 0x1 +#define RTC_CNTL_TOUCH_STATE_START_S 9 +/* RTC_CNTL_XPD_DIG : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: digital wrap power down*/ +#define RTC_CNTL_XPD_DIG (BIT(8)) +#define RTC_CNTL_XPD_DIG_M (BIT(8)) +#define RTC_CNTL_XPD_DIG_V 0x1 +#define RTC_CNTL_XPD_DIG_S 8 +/* RTC_CNTL_DIG_ISO : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: digital wrap iso*/ +#define RTC_CNTL_DIG_ISO (BIT(7)) +#define RTC_CNTL_DIG_ISO_M (BIT(7)) +#define RTC_CNTL_DIG_ISO_V 0x1 +#define RTC_CNTL_DIG_ISO_S 7 +/* RTC_CNTL_XPD_WIFI : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: wifi wrap power down*/ +#define RTC_CNTL_XPD_WIFI (BIT(6)) +#define RTC_CNTL_XPD_WIFI_M (BIT(6)) +#define RTC_CNTL_XPD_WIFI_V 0x1 +#define RTC_CNTL_XPD_WIFI_S 6 +/* RTC_CNTL_WIFI_ISO : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: wifi iso*/ +#define RTC_CNTL_WIFI_ISO (BIT(5)) +#define RTC_CNTL_WIFI_ISO_M (BIT(5)) +#define RTC_CNTL_WIFI_ISO_V 0x1 +#define RTC_CNTL_WIFI_ISO_S 5 +/* RTC_CNTL_XPD_RTC_PERI : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: rtc peripheral power down*/ +#define RTC_CNTL_XPD_RTC_PERI (BIT(4)) +#define RTC_CNTL_XPD_RTC_PERI_M (BIT(4)) +#define RTC_CNTL_XPD_RTC_PERI_V 0x1 +#define RTC_CNTL_XPD_RTC_PERI_S 4 +/* RTC_CNTL_PERI_ISO : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: rtc peripheral iso*/ +#define RTC_CNTL_PERI_ISO (BIT(3)) +#define RTC_CNTL_PERI_ISO_M (BIT(3)) +#define RTC_CNTL_PERI_ISO_V 0x1 +#define RTC_CNTL_PERI_ISO_S 3 +/* RTC_CNTL_XPD_DIG_DCDC : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: External DCDC power down*/ +#define RTC_CNTL_XPD_DIG_DCDC (BIT(2)) +#define RTC_CNTL_XPD_DIG_DCDC_M (BIT(2)) +#define RTC_CNTL_XPD_DIG_DCDC_V 0x1 +#define RTC_CNTL_XPD_DIG_DCDC_S 2 +/* RTC_CNTL_XPD_ROM0 : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: rom0 power down*/ +#define RTC_CNTL_XPD_ROM0 (BIT(0)) +#define RTC_CNTL_XPD_ROM0_M (BIT(0)) +#define RTC_CNTL_XPD_ROM0_V 0x1 +#define RTC_CNTL_XPD_ROM0_S 0 + +#define RTC_CNTL_DIAG0_REG (DR_REG_RTCCNTL_BASE + 0x00D0) +/* RTC_CNTL_LOW_POWER_DIAG1 : RO ;bitpos:[31:0] ;default: 0 ; */ +/*description: */ +#define RTC_CNTL_LOW_POWER_DIAG1 0xFFFFFFFF +#define RTC_CNTL_LOW_POWER_DIAG1_M ((RTC_CNTL_LOW_POWER_DIAG1_V)<<(RTC_CNTL_LOW_POWER_DIAG1_S)) +#define RTC_CNTL_LOW_POWER_DIAG1_V 0xFFFFFFFF +#define RTC_CNTL_LOW_POWER_DIAG1_S 0 + +#define RTC_CNTL_PAD_HOLD_REG (DR_REG_RTCCNTL_BASE + 0x00D4) +/* RTC_CNTL_PAD21_HOLD : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_PAD21_HOLD (BIT(21)) +#define RTC_CNTL_PAD21_HOLD_M (BIT(21)) +#define RTC_CNTL_PAD21_HOLD_V 0x1 +#define RTC_CNTL_PAD21_HOLD_S 21 +/* RTC_CNTL_PAD20_HOLD : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_PAD20_HOLD (BIT(20)) +#define RTC_CNTL_PAD20_HOLD_M (BIT(20)) +#define RTC_CNTL_PAD20_HOLD_V 0x1 +#define RTC_CNTL_PAD20_HOLD_S 20 +/* RTC_CNTL_PAD19_HOLD : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_PAD19_HOLD (BIT(19)) +#define RTC_CNTL_PAD19_HOLD_M (BIT(19)) +#define RTC_CNTL_PAD19_HOLD_V 0x1 +#define RTC_CNTL_PAD19_HOLD_S 19 +/* RTC_CNTL_PDAC2_HOLD : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_PDAC2_HOLD (BIT(18)) +#define RTC_CNTL_PDAC2_HOLD_M (BIT(18)) +#define RTC_CNTL_PDAC2_HOLD_V 0x1 +#define RTC_CNTL_PDAC2_HOLD_S 18 +/* RTC_CNTL_PDAC1_HOLD : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_PDAC1_HOLD (BIT(17)) +#define RTC_CNTL_PDAC1_HOLD_M (BIT(17)) +#define RTC_CNTL_PDAC1_HOLD_V 0x1 +#define RTC_CNTL_PDAC1_HOLD_S 17 +/* RTC_CNTL_X32N_HOLD : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_X32N_HOLD (BIT(16)) +#define RTC_CNTL_X32N_HOLD_M (BIT(16)) +#define RTC_CNTL_X32N_HOLD_V 0x1 +#define RTC_CNTL_X32N_HOLD_S 16 +/* RTC_CNTL_X32P_HOLD : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_X32P_HOLD (BIT(15)) +#define RTC_CNTL_X32P_HOLD_M (BIT(15)) +#define RTC_CNTL_X32P_HOLD_V 0x1 +#define RTC_CNTL_X32P_HOLD_S 15 +/* RTC_CNTL_TOUCH_PAD14_HOLD : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD14_HOLD (BIT(14)) +#define RTC_CNTL_TOUCH_PAD14_HOLD_M (BIT(14)) +#define RTC_CNTL_TOUCH_PAD14_HOLD_V 0x1 +#define RTC_CNTL_TOUCH_PAD14_HOLD_S 14 +/* RTC_CNTL_TOUCH_PAD13_HOLD : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD13_HOLD (BIT(13)) +#define RTC_CNTL_TOUCH_PAD13_HOLD_M (BIT(13)) +#define RTC_CNTL_TOUCH_PAD13_HOLD_V 0x1 +#define RTC_CNTL_TOUCH_PAD13_HOLD_S 13 +/* RTC_CNTL_TOUCH_PAD12_HOLD : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD12_HOLD (BIT(12)) +#define RTC_CNTL_TOUCH_PAD12_HOLD_M (BIT(12)) +#define RTC_CNTL_TOUCH_PAD12_HOLD_V 0x1 +#define RTC_CNTL_TOUCH_PAD12_HOLD_S 12 +/* RTC_CNTL_TOUCH_PAD11_HOLD : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD11_HOLD (BIT(11)) +#define RTC_CNTL_TOUCH_PAD11_HOLD_M (BIT(11)) +#define RTC_CNTL_TOUCH_PAD11_HOLD_V 0x1 +#define RTC_CNTL_TOUCH_PAD11_HOLD_S 11 +/* RTC_CNTL_TOUCH_PAD10_HOLD : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD10_HOLD (BIT(10)) +#define RTC_CNTL_TOUCH_PAD10_HOLD_M (BIT(10)) +#define RTC_CNTL_TOUCH_PAD10_HOLD_V 0x1 +#define RTC_CNTL_TOUCH_PAD10_HOLD_S 10 +/* RTC_CNTL_TOUCH_PAD9_HOLD : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD9_HOLD (BIT(9)) +#define RTC_CNTL_TOUCH_PAD9_HOLD_M (BIT(9)) +#define RTC_CNTL_TOUCH_PAD9_HOLD_V 0x1 +#define RTC_CNTL_TOUCH_PAD9_HOLD_S 9 +/* RTC_CNTL_TOUCH_PAD8_HOLD : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD8_HOLD (BIT(8)) +#define RTC_CNTL_TOUCH_PAD8_HOLD_M (BIT(8)) +#define RTC_CNTL_TOUCH_PAD8_HOLD_V 0x1 +#define RTC_CNTL_TOUCH_PAD8_HOLD_S 8 +/* RTC_CNTL_TOUCH_PAD7_HOLD : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD7_HOLD (BIT(7)) +#define RTC_CNTL_TOUCH_PAD7_HOLD_M (BIT(7)) +#define RTC_CNTL_TOUCH_PAD7_HOLD_V 0x1 +#define RTC_CNTL_TOUCH_PAD7_HOLD_S 7 +/* RTC_CNTL_TOUCH_PAD6_HOLD : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD6_HOLD (BIT(6)) +#define RTC_CNTL_TOUCH_PAD6_HOLD_M (BIT(6)) +#define RTC_CNTL_TOUCH_PAD6_HOLD_V 0x1 +#define RTC_CNTL_TOUCH_PAD6_HOLD_S 6 +/* RTC_CNTL_TOUCH_PAD5_HOLD : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD5_HOLD (BIT(5)) +#define RTC_CNTL_TOUCH_PAD5_HOLD_M (BIT(5)) +#define RTC_CNTL_TOUCH_PAD5_HOLD_V 0x1 +#define RTC_CNTL_TOUCH_PAD5_HOLD_S 5 +/* RTC_CNTL_TOUCH_PAD4_HOLD : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD4_HOLD (BIT(4)) +#define RTC_CNTL_TOUCH_PAD4_HOLD_M (BIT(4)) +#define RTC_CNTL_TOUCH_PAD4_HOLD_V 0x1 +#define RTC_CNTL_TOUCH_PAD4_HOLD_S 4 +/* RTC_CNTL_TOUCH_PAD3_HOLD : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD3_HOLD (BIT(3)) +#define RTC_CNTL_TOUCH_PAD3_HOLD_M (BIT(3)) +#define RTC_CNTL_TOUCH_PAD3_HOLD_V 0x1 +#define RTC_CNTL_TOUCH_PAD3_HOLD_S 3 +/* RTC_CNTL_TOUCH_PAD2_HOLD : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD2_HOLD (BIT(2)) +#define RTC_CNTL_TOUCH_PAD2_HOLD_M (BIT(2)) +#define RTC_CNTL_TOUCH_PAD2_HOLD_V 0x1 +#define RTC_CNTL_TOUCH_PAD2_HOLD_S 2 +/* RTC_CNTL_TOUCH_PAD1_HOLD : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD1_HOLD (BIT(1)) +#define RTC_CNTL_TOUCH_PAD1_HOLD_M (BIT(1)) +#define RTC_CNTL_TOUCH_PAD1_HOLD_V 0x1 +#define RTC_CNTL_TOUCH_PAD1_HOLD_S 1 +/* RTC_CNTL_TOUCH_PAD0_HOLD : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD0_HOLD (BIT(0)) +#define RTC_CNTL_TOUCH_PAD0_HOLD_M (BIT(0)) +#define RTC_CNTL_TOUCH_PAD0_HOLD_V 0x1 +#define RTC_CNTL_TOUCH_PAD0_HOLD_S 0 + +#define RTC_CNTL_DIG_PAD_HOLD_REG (DR_REG_RTCCNTL_BASE + 0x00D8) +/* RTC_CNTL_DIG_PAD_HOLD : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define RTC_CNTL_DIG_PAD_HOLD 0xFFFFFFFF +#define RTC_CNTL_DIG_PAD_HOLD_M ((RTC_CNTL_DIG_PAD_HOLD_V)<<(RTC_CNTL_DIG_PAD_HOLD_S)) +#define RTC_CNTL_DIG_PAD_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_DIG_PAD_HOLD_S 0 + +#define RTC_CNTL_EXT_WAKEUP1_REG (DR_REG_RTCCNTL_BASE + 0x00DC) +/* RTC_CNTL_EXT_WAKEUP1_STATUS_CLR : WO ;bitpos:[22] ;default: 1'd0 ; */ +/*description: clear ext wakeup1 status*/ +#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR (BIT(22)) +#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_M (BIT(22)) +#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_V 0x1 +#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_S 22 +/* RTC_CNTL_EXT_WAKEUP1_SEL : R/W ;bitpos:[21:0] ;default: 22'd0 ; */ +/*description: Bitmap to select RTC pads for ext wakeup1*/ +#define RTC_CNTL_EXT_WAKEUP1_SEL 0x003FFFFF +#define RTC_CNTL_EXT_WAKEUP1_SEL_M ((RTC_CNTL_EXT_WAKEUP1_SEL_V)<<(RTC_CNTL_EXT_WAKEUP1_SEL_S)) +#define RTC_CNTL_EXT_WAKEUP1_SEL_V 0x3FFFFF +#define RTC_CNTL_EXT_WAKEUP1_SEL_S 0 + +#define RTC_CNTL_EXT_WAKEUP1_STATUS_REG (DR_REG_RTCCNTL_BASE + 0x00E0) +/* RTC_CNTL_EXT_WAKEUP1_STATUS : RO ;bitpos:[21:0] ;default: 22'd0 ; */ +/*description: ext wakeup1 status*/ +#define RTC_CNTL_EXT_WAKEUP1_STATUS 0x003FFFFF +#define RTC_CNTL_EXT_WAKEUP1_STATUS_M ((RTC_CNTL_EXT_WAKEUP1_STATUS_V)<<(RTC_CNTL_EXT_WAKEUP1_STATUS_S)) +#define RTC_CNTL_EXT_WAKEUP1_STATUS_V 0x3FFFFF +#define RTC_CNTL_EXT_WAKEUP1_STATUS_S 0 + +#define RTC_CNTL_BROWN_OUT_REG (DR_REG_RTCCNTL_BASE + 0x00E4) +/* RTC_CNTL_BROWN_OUT_DET : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_BROWN_OUT_DET (BIT(31)) +#define RTC_CNTL_BROWN_OUT_DET_M (BIT(31)) +#define RTC_CNTL_BROWN_OUT_DET_V 0x1 +#define RTC_CNTL_BROWN_OUT_DET_S 31 +/* RTC_CNTL_BROWN_OUT_ENA : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: enable brown out*/ +#define RTC_CNTL_BROWN_OUT_ENA (BIT(30)) +#define RTC_CNTL_BROWN_OUT_ENA_M (BIT(30)) +#define RTC_CNTL_BROWN_OUT_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_ENA_S 30 +/* RTC_CNTL_BROWN_OUT_CNT_CLR : WO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: clear brown out counter*/ +#define RTC_CNTL_BROWN_OUT_CNT_CLR (BIT(29)) +#define RTC_CNTL_BROWN_OUT_CNT_CLR_M (BIT(29)) +#define RTC_CNTL_BROWN_OUT_CNT_CLR_V 0x1 +#define RTC_CNTL_BROWN_OUT_CNT_CLR_S 29 +/* RTC_CNTL_BROWN_OUT_RST_SEL : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: 1: 4-pos reset*/ +#define RTC_CNTL_BROWN_OUT_RST_SEL (BIT(27)) +#define RTC_CNTL_BROWN_OUT_RST_SEL_M (BIT(27)) +#define RTC_CNTL_BROWN_OUT_RST_SEL_V 0x1 +#define RTC_CNTL_BROWN_OUT_RST_SEL_S 27 +/* RTC_CNTL_BROWN_OUT_RST_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: enable brown out reset*/ +#define RTC_CNTL_BROWN_OUT_RST_ENA (BIT(26)) +#define RTC_CNTL_BROWN_OUT_RST_ENA_M (BIT(26)) +#define RTC_CNTL_BROWN_OUT_RST_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_RST_ENA_S 26 +/* RTC_CNTL_BROWN_OUT_RST_WAIT : R/W ;bitpos:[25:16] ;default: 10'h3ff ; */ +/*description: brown out reset wait cycles*/ +#define RTC_CNTL_BROWN_OUT_RST_WAIT 0x000003FF +#define RTC_CNTL_BROWN_OUT_RST_WAIT_M ((RTC_CNTL_BROWN_OUT_RST_WAIT_V)<<(RTC_CNTL_BROWN_OUT_RST_WAIT_S)) +#define RTC_CNTL_BROWN_OUT_RST_WAIT_V 0x3FF +#define RTC_CNTL_BROWN_OUT_RST_WAIT_S 16 +/* RTC_CNTL_BROWN_OUT_PD_RF_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: enable power down RF when brown out happens*/ +#define RTC_CNTL_BROWN_OUT_PD_RF_ENA (BIT(15)) +#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_M (BIT(15)) +#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_S 15 +/* RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: enable close flash when brown out happens*/ +#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA (BIT(14)) +#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_M (BIT(14)) +#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_S 14 +/* RTC_CNTL_BROWN_OUT_INT_WAIT : R/W ;bitpos:[13:4] ;default: 10'h2ff ; */ +/*description: brown out interrupt wait cycles*/ +#define RTC_CNTL_BROWN_OUT_INT_WAIT 0x000003FF +#define RTC_CNTL_BROWN_OUT_INT_WAIT_M ((RTC_CNTL_BROWN_OUT_INT_WAIT_V)<<(RTC_CNTL_BROWN_OUT_INT_WAIT_S)) +#define RTC_CNTL_BROWN_OUT_INT_WAIT_V 0x3FF +#define RTC_CNTL_BROWN_OUT_INT_WAIT_S 4 +/* RTC_CNTL_BROWN_OUT2_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: enable brown_out2 to start chip reset*/ +#define RTC_CNTL_BROWN_OUT2_ENA (BIT(0)) +#define RTC_CNTL_BROWN_OUT2_ENA_M (BIT(0)) +#define RTC_CNTL_BROWN_OUT2_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT2_ENA_S 0 + +#define RTC_CNTL_TIME_LOW1_REG (DR_REG_RTCCNTL_BASE + 0x00E8) +/* RTC_CNTL_TIMER_VALUE1_LOW : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: RTC timer low 32 bits*/ +#define RTC_CNTL_TIMER_VALUE1_LOW 0xFFFFFFFF +#define RTC_CNTL_TIMER_VALUE1_LOW_M ((RTC_CNTL_TIMER_VALUE1_LOW_V)<<(RTC_CNTL_TIMER_VALUE1_LOW_S)) +#define RTC_CNTL_TIMER_VALUE1_LOW_V 0xFFFFFFFF +#define RTC_CNTL_TIMER_VALUE1_LOW_S 0 + +#define RTC_CNTL_TIME_HIGH1_REG (DR_REG_RTCCNTL_BASE + 0x00EC) +/* RTC_CNTL_TIMER_VALUE1_HIGH : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: RTC timer high 16 bits*/ +#define RTC_CNTL_TIMER_VALUE1_HIGH 0x0000FFFF +#define RTC_CNTL_TIMER_VALUE1_HIGH_M ((RTC_CNTL_TIMER_VALUE1_HIGH_V)<<(RTC_CNTL_TIMER_VALUE1_HIGH_S)) +#define RTC_CNTL_TIMER_VALUE1_HIGH_V 0xFFFF +#define RTC_CNTL_TIMER_VALUE1_HIGH_S 0 + +#define RTC_CNTL_XTAL32K_CLK_FACTOR_REG (DR_REG_RTCCNTL_BASE + 0x00F0) +/* RTC_CNTL_XTAL32K_CLK_FACTOR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: xtal 32k watch dog backup clock factor*/ +#define RTC_CNTL_XTAL32K_CLK_FACTOR 0xFFFFFFFF +#define RTC_CNTL_XTAL32K_CLK_FACTOR_M ((RTC_CNTL_XTAL32K_CLK_FACTOR_V)<<(RTC_CNTL_XTAL32K_CLK_FACTOR_S)) +#define RTC_CNTL_XTAL32K_CLK_FACTOR_V 0xFFFFFFFF +#define RTC_CNTL_XTAL32K_CLK_FACTOR_S 0 + +#define RTC_CNTL_XTAL32K_CONF_REG (DR_REG_RTCCNTL_BASE + 0x00F4) +/* RTC_CNTL_XTAL32K_STABLE_THRES : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ +/*description: if restarted xtal32k period is smaller than this it is regarded as stable*/ +#define RTC_CNTL_XTAL32K_STABLE_THRES 0x0000000F +#define RTC_CNTL_XTAL32K_STABLE_THRES_M ((RTC_CNTL_XTAL32K_STABLE_THRES_V)<<(RTC_CNTL_XTAL32K_STABLE_THRES_S)) +#define RTC_CNTL_XTAL32K_STABLE_THRES_V 0xF +#define RTC_CNTL_XTAL32K_STABLE_THRES_S 28 +/* RTC_CNTL_XTAL32K_WDT_TIMEOUT : R/W ;bitpos:[27:20] ;default: 8'hff ; */ +/*description: If no clock detected for this amount of time 32k is regarded as dead*/ +#define RTC_CNTL_XTAL32K_WDT_TIMEOUT 0x000000FF +#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_M ((RTC_CNTL_XTAL32K_WDT_TIMEOUT_V)<<(RTC_CNTL_XTAL32K_WDT_TIMEOUT_S)) +#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_V 0xFF +#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_S 20 +/* RTC_CNTL_XTAL32K_RESTART_WAIT : R/W ;bitpos:[19:4] ;default: 16'h0 ; */ +/*description: cycles to wait to repower on xtal 32k*/ +#define RTC_CNTL_XTAL32K_RESTART_WAIT 0x0000FFFF +#define RTC_CNTL_XTAL32K_RESTART_WAIT_M ((RTC_CNTL_XTAL32K_RESTART_WAIT_V)<<(RTC_CNTL_XTAL32K_RESTART_WAIT_S)) +#define RTC_CNTL_XTAL32K_RESTART_WAIT_V 0xFFFF +#define RTC_CNTL_XTAL32K_RESTART_WAIT_S 4 +/* RTC_CNTL_XTAL32K_RETURN_WAIT : R/W ;bitpos:[3:0] ;default: 4'h0 ; */ +/*description: cycles to wait to return normal xtal 32k*/ +#define RTC_CNTL_XTAL32K_RETURN_WAIT 0x0000000F +#define RTC_CNTL_XTAL32K_RETURN_WAIT_M ((RTC_CNTL_XTAL32K_RETURN_WAIT_V)<<(RTC_CNTL_XTAL32K_RETURN_WAIT_S)) +#define RTC_CNTL_XTAL32K_RETURN_WAIT_V 0xF +#define RTC_CNTL_XTAL32K_RETURN_WAIT_S 0 + +#define RTC_CNTL_ULP_CP_TIMER_REG (DR_REG_RTCCNTL_BASE + 0x00F8) +/* RTC_CNTL_ULP_CP_SLP_TIMER_EN : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: ULP-coprocessor timer enable bit*/ +#define RTC_CNTL_ULP_CP_SLP_TIMER_EN (BIT(31)) +#define RTC_CNTL_ULP_CP_SLP_TIMER_EN_M (BIT(31)) +#define RTC_CNTL_ULP_CP_SLP_TIMER_EN_V 0x1 +#define RTC_CNTL_ULP_CP_SLP_TIMER_EN_S 31 +/* RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR : WO ;bitpos:[30] ;default: 1'd0 ; */ +/*description: ULP-coprocessor wakeup by GPIO state clear*/ +#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR (BIT(30)) +#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_M (BIT(30)) +#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_V 0x1 +#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_S 30 +/* RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: ULP-coprocessor wakeup by GPIO enable*/ +#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA (BIT(29)) +#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_M (BIT(29)) +#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_V 0x1 +#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_S 29 +/* RTC_CNTL_ULP_CP_PC_INIT : R/W ;bitpos:[10:0] ;default: 11'b0 ; */ +/*description: ULP-coprocessor PC initial address*/ +#define RTC_CNTL_ULP_CP_PC_INIT 0x000007FF +#define RTC_CNTL_ULP_CP_PC_INIT_M ((RTC_CNTL_ULP_CP_PC_INIT_V)<<(RTC_CNTL_ULP_CP_PC_INIT_S)) +#define RTC_CNTL_ULP_CP_PC_INIT_V 0x7FF +#define RTC_CNTL_ULP_CP_PC_INIT_S 0 + +#define RTC_CNTL_ULP_CP_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x00FC) +/* RTC_CNTL_ULP_CP_START_TOP : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: Write 1 to start ULP-coprocessor*/ +#define RTC_CNTL_ULP_CP_START_TOP (BIT(31)) +#define RTC_CNTL_ULP_CP_START_TOP_M (BIT(31)) +#define RTC_CNTL_ULP_CP_START_TOP_V 0x1 +#define RTC_CNTL_ULP_CP_START_TOP_S 31 +/* RTC_CNTL_ULP_CP_FORCE_START_TOP : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: 1: ULP-coprocessor is started by SW*/ +#define RTC_CNTL_ULP_CP_FORCE_START_TOP (BIT(30)) +#define RTC_CNTL_ULP_CP_FORCE_START_TOP_M (BIT(30)) +#define RTC_CNTL_ULP_CP_FORCE_START_TOP_V 0x1 +#define RTC_CNTL_ULP_CP_FORCE_START_TOP_S 30 +/* RTC_CNTL_ULP_CP_RESET : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: ulp coprocessor clk software reset*/ +#define RTC_CNTL_ULP_CP_RESET (BIT(29)) +#define RTC_CNTL_ULP_CP_RESET_M (BIT(29)) +#define RTC_CNTL_ULP_CP_RESET_V 0x1 +#define RTC_CNTL_ULP_CP_RESET_S 29 +/* RTC_CNTL_ULP_CP_CLK_FO : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: ulp coprocessor clk force on*/ +#define RTC_CNTL_ULP_CP_CLK_FO (BIT(28)) +#define RTC_CNTL_ULP_CP_CLK_FO_M (BIT(28)) +#define RTC_CNTL_ULP_CP_CLK_FO_V 0x1 +#define RTC_CNTL_ULP_CP_CLK_FO_S 28 +/* RTC_CNTL_ULP_CP_MEM_OFFST_CLR : WO ;bitpos:[22] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_ULP_CP_MEM_OFFST_CLR (BIT(22)) +#define RTC_CNTL_ULP_CP_MEM_OFFST_CLR_M (BIT(22)) +#define RTC_CNTL_ULP_CP_MEM_OFFST_CLR_V 0x1 +#define RTC_CNTL_ULP_CP_MEM_OFFST_CLR_S 22 +/* RTC_CNTL_ULP_CP_MEM_ADDR_SIZE : R/W ;bitpos:[21:11] ;default: 11'd512 ; */ +/*description: */ +#define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE 0x000007FF +#define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_M ((RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_V)<<(RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_S)) +#define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_V 0x7FF +#define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_S 11 +/* RTC_CNTL_ULP_CP_MEM_ADDR_INIT : R/W ;bitpos:[10:0] ;default: 11'd512 ; */ +/*description: */ +#define RTC_CNTL_ULP_CP_MEM_ADDR_INIT 0x000007FF +#define RTC_CNTL_ULP_CP_MEM_ADDR_INIT_M ((RTC_CNTL_ULP_CP_MEM_ADDR_INIT_V)<<(RTC_CNTL_ULP_CP_MEM_ADDR_INIT_S)) +#define RTC_CNTL_ULP_CP_MEM_ADDR_INIT_V 0x7FF +#define RTC_CNTL_ULP_CP_MEM_ADDR_INIT_S 0 + +#define RTC_CNTL_COCPU_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x0100) +/* RTC_CNTL_COCPU_SW_INT_TRIGGER : WO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: trigger cocpu register interrupt*/ +#define RTC_CNTL_COCPU_SW_INT_TRIGGER (BIT(26)) +#define RTC_CNTL_COCPU_SW_INT_TRIGGER_M (BIT(26)) +#define RTC_CNTL_COCPU_SW_INT_TRIGGER_V 0x1 +#define RTC_CNTL_COCPU_SW_INT_TRIGGER_S 26 +/* RTC_CNTL_COCPU_DONE : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: done signal used by riscv to control timer.*/ +#define RTC_CNTL_COCPU_DONE (BIT(25)) +#define RTC_CNTL_COCPU_DONE_M (BIT(25)) +#define RTC_CNTL_COCPU_DONE_V 0x1 +#define RTC_CNTL_COCPU_DONE_S 25 +/* RTC_CNTL_COCPU_DONE_FORCE : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: 1: select riscv done 0: select ulp done*/ +#define RTC_CNTL_COCPU_DONE_FORCE (BIT(24)) +#define RTC_CNTL_COCPU_DONE_FORCE_M (BIT(24)) +#define RTC_CNTL_COCPU_DONE_FORCE_V 0x1 +#define RTC_CNTL_COCPU_DONE_FORCE_S 24 +/* RTC_CNTL_COCPU_SEL : R/W ;bitpos:[23] ;default: 1'b1 ; */ +/*description: 1: old ULP 0: new riscV*/ +#define RTC_CNTL_COCPU_SEL (BIT(23)) +#define RTC_CNTL_COCPU_SEL_M (BIT(23)) +#define RTC_CNTL_COCPU_SEL_V 0x1 +#define RTC_CNTL_COCPU_SEL_S 23 +/* RTC_CNTL_COCPU_SHUT_RESET_EN : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: to reset cocpu*/ +#define RTC_CNTL_COCPU_SHUT_RESET_EN (BIT(22)) +#define RTC_CNTL_COCPU_SHUT_RESET_EN_M (BIT(22)) +#define RTC_CNTL_COCPU_SHUT_RESET_EN_V 0x1 +#define RTC_CNTL_COCPU_SHUT_RESET_EN_S 22 +/* RTC_CNTL_COCPU_SHUT_2_CLK_DIS : R/W ;bitpos:[21:14] ;default: 8'd40 ; */ +/*description: time from shut cocpu to disable clk*/ +#define RTC_CNTL_COCPU_SHUT_2_CLK_DIS 0x000000FF +#define RTC_CNTL_COCPU_SHUT_2_CLK_DIS_M ((RTC_CNTL_COCPU_SHUT_2_CLK_DIS_V)<<(RTC_CNTL_COCPU_SHUT_2_CLK_DIS_S)) +#define RTC_CNTL_COCPU_SHUT_2_CLK_DIS_V 0xFF +#define RTC_CNTL_COCPU_SHUT_2_CLK_DIS_S 14 +/* RTC_CNTL_COCPU_SHUT : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: to shut cocpu*/ +#define RTC_CNTL_COCPU_SHUT (BIT(13)) +#define RTC_CNTL_COCPU_SHUT_M (BIT(13)) +#define RTC_CNTL_COCPU_SHUT_V 0x1 +#define RTC_CNTL_COCPU_SHUT_S 13 +/* RTC_CNTL_COCPU_START_2_INTR_EN : R/W ;bitpos:[12:7] ;default: 6'd16 ; */ +/*description: time from start cocpu to give start interrupt*/ +#define RTC_CNTL_COCPU_START_2_INTR_EN 0x0000003F +#define RTC_CNTL_COCPU_START_2_INTR_EN_M ((RTC_CNTL_COCPU_START_2_INTR_EN_V)<<(RTC_CNTL_COCPU_START_2_INTR_EN_S)) +#define RTC_CNTL_COCPU_START_2_INTR_EN_V 0x3F +#define RTC_CNTL_COCPU_START_2_INTR_EN_S 7 +/* RTC_CNTL_COCPU_START_2_RESET_DIS : R/W ;bitpos:[6:1] ;default: 6'd8 ; */ +/*description: time from start cocpu to pull down reset*/ +#define RTC_CNTL_COCPU_START_2_RESET_DIS 0x0000003F +#define RTC_CNTL_COCPU_START_2_RESET_DIS_M ((RTC_CNTL_COCPU_START_2_RESET_DIS_V)<<(RTC_CNTL_COCPU_START_2_RESET_DIS_S)) +#define RTC_CNTL_COCPU_START_2_RESET_DIS_V 0x3F +#define RTC_CNTL_COCPU_START_2_RESET_DIS_S 1 +/* RTC_CNTL_COCPU_CLK_FO : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: cocpu clk force on*/ +#define RTC_CNTL_COCPU_CLK_FO (BIT(0)) +#define RTC_CNTL_COCPU_CLK_FO_M (BIT(0)) +#define RTC_CNTL_COCPU_CLK_FO_V 0x1 +#define RTC_CNTL_COCPU_CLK_FO_S 0 + +#define RTC_CNTL_TOUCH_CTRL1_REG (DR_REG_RTCCNTL_BASE + 0x0104) +/* RTC_CNTL_TOUCH_MEAS_NUM : R/W ;bitpos:[31:16] ;default: 16'h1000 ; */ +/*description: the meas length (in 8MHz)*/ +#define RTC_CNTL_TOUCH_MEAS_NUM 0x0000FFFF +#define RTC_CNTL_TOUCH_MEAS_NUM_M ((RTC_CNTL_TOUCH_MEAS_NUM_V)<<(RTC_CNTL_TOUCH_MEAS_NUM_S)) +#define RTC_CNTL_TOUCH_MEAS_NUM_V 0xFFFF +#define RTC_CNTL_TOUCH_MEAS_NUM_S 16 +/* RTC_CNTL_TOUCH_SLEEP_CYCLES : R/W ;bitpos:[15:0] ;default: 16'h100 ; */ +/*description: sleep cycles for timer*/ +#define RTC_CNTL_TOUCH_SLEEP_CYCLES 0x0000FFFF +#define RTC_CNTL_TOUCH_SLEEP_CYCLES_M ((RTC_CNTL_TOUCH_SLEEP_CYCLES_V)<<(RTC_CNTL_TOUCH_SLEEP_CYCLES_S)) +#define RTC_CNTL_TOUCH_SLEEP_CYCLES_V 0xFFFF +#define RTC_CNTL_TOUCH_SLEEP_CYCLES_S 0 + +#define RTC_CNTL_TOUCH_CTRL2_REG (DR_REG_RTCCNTL_BASE + 0x0108) +/* RTC_CNTL_TOUCH_CLKGATE_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: touch clock enable*/ +#define RTC_CNTL_TOUCH_CLKGATE_EN (BIT(31)) +#define RTC_CNTL_TOUCH_CLKGATE_EN_M (BIT(31)) +#define RTC_CNTL_TOUCH_CLKGATE_EN_V 0x1 +#define RTC_CNTL_TOUCH_CLKGATE_EN_S 31 +/* RTC_CNTL_TOUCH_CLK_FO : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: touch clock force on*/ +#define RTC_CNTL_TOUCH_CLK_FO (BIT(30)) +#define RTC_CNTL_TOUCH_CLK_FO_M (BIT(30)) +#define RTC_CNTL_TOUCH_CLK_FO_V 0x1 +#define RTC_CNTL_TOUCH_CLK_FO_S 30 +/* RTC_CNTL_TOUCH_RESET : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: reset upgrade touch*/ +#define RTC_CNTL_TOUCH_RESET (BIT(29)) +#define RTC_CNTL_TOUCH_RESET_M (BIT(29)) +#define RTC_CNTL_TOUCH_RESET_V 0x1 +#define RTC_CNTL_TOUCH_RESET_S 29 +/* RTC_CNTL_TOUCH_TIMER_FORCE_DONE : R/W ;bitpos:[28:27] ;default: 2'b0 ; */ +/*description: force touch timer done*/ +#define RTC_CNTL_TOUCH_TIMER_FORCE_DONE 0x00000003 +#define RTC_CNTL_TOUCH_TIMER_FORCE_DONE_M ((RTC_CNTL_TOUCH_TIMER_FORCE_DONE_V)<<(RTC_CNTL_TOUCH_TIMER_FORCE_DONE_S)) +#define RTC_CNTL_TOUCH_TIMER_FORCE_DONE_V 0x3 +#define RTC_CNTL_TOUCH_TIMER_FORCE_DONE_S 27 +/* RTC_CNTL_TOUCH_SLP_CYC_DIV : R/W ;bitpos:[26:25] ;default: 2'd0 ; */ +/*description: when a touch pad is active sleep cycle could be divided by this number*/ +#define RTC_CNTL_TOUCH_SLP_CYC_DIV 0x00000003 +#define RTC_CNTL_TOUCH_SLP_CYC_DIV_M ((RTC_CNTL_TOUCH_SLP_CYC_DIV_V)<<(RTC_CNTL_TOUCH_SLP_CYC_DIV_S)) +#define RTC_CNTL_TOUCH_SLP_CYC_DIV_V 0x3 +#define RTC_CNTL_TOUCH_SLP_CYC_DIV_S 25 +/* RTC_CNTL_TOUCH_XPD_WAIT : R/W ;bitpos:[24:17] ;default: 8'h4 ; */ +/*description: the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD*/ +#define RTC_CNTL_TOUCH_XPD_WAIT 0x000000FF +#define RTC_CNTL_TOUCH_XPD_WAIT_M ((RTC_CNTL_TOUCH_XPD_WAIT_V)<<(RTC_CNTL_TOUCH_XPD_WAIT_S)) +#define RTC_CNTL_TOUCH_XPD_WAIT_V 0xFF +#define RTC_CNTL_TOUCH_XPD_WAIT_S 17 +/* RTC_CNTL_TOUCH_START_FORCE : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: 1: to start touch fsm by SW*/ +#define RTC_CNTL_TOUCH_START_FORCE (BIT(16)) +#define RTC_CNTL_TOUCH_START_FORCE_M (BIT(16)) +#define RTC_CNTL_TOUCH_START_FORCE_V 0x1 +#define RTC_CNTL_TOUCH_START_FORCE_S 16 +/* RTC_CNTL_TOUCH_START_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: 1: start touch fsm*/ +#define RTC_CNTL_TOUCH_START_EN (BIT(15)) +#define RTC_CNTL_TOUCH_START_EN_M (BIT(15)) +#define RTC_CNTL_TOUCH_START_EN_V 0x1 +#define RTC_CNTL_TOUCH_START_EN_S 15 +/* RTC_CNTL_TOUCH_START_FSM_EN : R/W ;bitpos:[14] ;default: 1'b1 ; */ +/*description: 1: TOUCH_START & TOUCH_XPD is controlled by touch fsm*/ +#define RTC_CNTL_TOUCH_START_FSM_EN (BIT(14)) +#define RTC_CNTL_TOUCH_START_FSM_EN_M (BIT(14)) +#define RTC_CNTL_TOUCH_START_FSM_EN_V 0x1 +#define RTC_CNTL_TOUCH_START_FSM_EN_S 14 +/* RTC_CNTL_TOUCH_SLP_TIMER_EN : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: touch timer enable bit*/ +#define RTC_CNTL_TOUCH_SLP_TIMER_EN (BIT(13)) +#define RTC_CNTL_TOUCH_SLP_TIMER_EN_M (BIT(13)) +#define RTC_CNTL_TOUCH_SLP_TIMER_EN_V 0x1 +#define RTC_CNTL_TOUCH_SLP_TIMER_EN_S 13 +/* RTC_CNTL_TOUCH_DBIAS : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: 1:use self bias 0:use bandgap bias*/ +#define RTC_CNTL_TOUCH_DBIAS (BIT(12)) +#define RTC_CNTL_TOUCH_DBIAS_M (BIT(12)) +#define RTC_CNTL_TOUCH_DBIAS_V 0x1 +#define RTC_CNTL_TOUCH_DBIAS_S 12 +/* RTC_CNTL_TOUCH_REFC : R/W ;bitpos:[11:9] ;default: 3'h0 ; */ +/*description: TOUCH pad0 reference cap*/ +#define RTC_CNTL_TOUCH_REFC 0x00000007 +#define RTC_CNTL_TOUCH_REFC_M ((RTC_CNTL_TOUCH_REFC_V)<<(RTC_CNTL_TOUCH_REFC_S)) +#define RTC_CNTL_TOUCH_REFC_V 0x7 +#define RTC_CNTL_TOUCH_REFC_S 9 +/* RTC_CNTL_TOUCH_XPD_BIAS : R/W ;bitpos:[8] ;default: 1'd0 ; */ +/*description: TOUCH_XPD_BIAS*/ +#define RTC_CNTL_TOUCH_XPD_BIAS (BIT(8)) +#define RTC_CNTL_TOUCH_XPD_BIAS_M (BIT(8)) +#define RTC_CNTL_TOUCH_XPD_BIAS_V 0x1 +#define RTC_CNTL_TOUCH_XPD_BIAS_S 8 +/* RTC_CNTL_TOUCH_DREFH : R/W ;bitpos:[7:6] ;default: 2'b11 ; */ +/*description: TOUCH_DREFH*/ +#define RTC_CNTL_TOUCH_DREFH 0x00000003 +#define RTC_CNTL_TOUCH_DREFH_M ((RTC_CNTL_TOUCH_DREFH_V)<<(RTC_CNTL_TOUCH_DREFH_S)) +#define RTC_CNTL_TOUCH_DREFH_V 0x3 +#define RTC_CNTL_TOUCH_DREFH_S 6 +/* RTC_CNTL_TOUCH_DREFL : R/W ;bitpos:[5:4] ;default: 2'b00 ; */ +/*description: TOUCH_DREFL*/ +#define RTC_CNTL_TOUCH_DREFL 0x00000003 +#define RTC_CNTL_TOUCH_DREFL_M ((RTC_CNTL_TOUCH_DREFL_V)<<(RTC_CNTL_TOUCH_DREFL_S)) +#define RTC_CNTL_TOUCH_DREFL_V 0x3 +#define RTC_CNTL_TOUCH_DREFL_S 4 +/* RTC_CNTL_TOUCH_DRANGE : R/W ;bitpos:[3:2] ;default: 2'b11 ; */ +/*description: TOUCH_DRANGE*/ +#define RTC_CNTL_TOUCH_DRANGE 0x00000003 +#define RTC_CNTL_TOUCH_DRANGE_M ((RTC_CNTL_TOUCH_DRANGE_V)<<(RTC_CNTL_TOUCH_DRANGE_S)) +#define RTC_CNTL_TOUCH_DRANGE_V 0x3 +#define RTC_CNTL_TOUCH_DRANGE_S 2 + +#define RTC_CNTL_TOUCH_SCAN_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x010C) +/* RTC_CNTL_TOUCH_OUT_RING : R/W ;bitpos:[31:28] ;default: 4'hf ; */ +/*description: select out ring pad*/ +#define RTC_CNTL_TOUCH_OUT_RING 0x0000000F +#define RTC_CNTL_TOUCH_OUT_RING_M ((RTC_CNTL_TOUCH_OUT_RING_V)<<(RTC_CNTL_TOUCH_OUT_RING_S)) +#define RTC_CNTL_TOUCH_OUT_RING_V 0xF +#define RTC_CNTL_TOUCH_OUT_RING_S 28 +/* RTC_CNTL_TOUCH_BUFDRV : R/W ;bitpos:[27:25] ;default: 3'h0 ; */ +/*description: touch7 buffer driver strength*/ +#define RTC_CNTL_TOUCH_BUFDRV 0x00000007 +#define RTC_CNTL_TOUCH_BUFDRV_M ((RTC_CNTL_TOUCH_BUFDRV_V)<<(RTC_CNTL_TOUCH_BUFDRV_S)) +#define RTC_CNTL_TOUCH_BUFDRV_V 0x7 +#define RTC_CNTL_TOUCH_BUFDRV_S 25 +/* RTC_CNTL_TOUCH_SCAN_PAD_MAP : R/W ;bitpos:[24:10] ;default: 15'h0 ; */ +/*description: touch scan mode pad enable map*/ +#define RTC_CNTL_TOUCH_SCAN_PAD_MAP 0x00007FFF +#define RTC_CNTL_TOUCH_SCAN_PAD_MAP_M ((RTC_CNTL_TOUCH_SCAN_PAD_MAP_V)<<(RTC_CNTL_TOUCH_SCAN_PAD_MAP_S)) +#define RTC_CNTL_TOUCH_SCAN_PAD_MAP_V 0x7FFF +#define RTC_CNTL_TOUCH_SCAN_PAD_MAP_S 10 +/* RTC_CNTL_TOUCH_SHIELD_PAD_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: touch pad14 will be used as shield*/ +#define RTC_CNTL_TOUCH_SHIELD_PAD_EN (BIT(9)) +#define RTC_CNTL_TOUCH_SHIELD_PAD_EN_M (BIT(9)) +#define RTC_CNTL_TOUCH_SHIELD_PAD_EN_V 0x1 +#define RTC_CNTL_TOUCH_SHIELD_PAD_EN_S 9 +/* RTC_CNTL_TOUCH_INACTIVE_CONNECTION : R/W ;bitpos:[8] ;default: 1'b1 ; */ +/*description: inactive touch pads connect to 1: gnd 0: HighZ*/ +#define RTC_CNTL_TOUCH_INACTIVE_CONNECTION (BIT(8)) +#define RTC_CNTL_TOUCH_INACTIVE_CONNECTION_M (BIT(8)) +#define RTC_CNTL_TOUCH_INACTIVE_CONNECTION_V 0x1 +#define RTC_CNTL_TOUCH_INACTIVE_CONNECTION_S 8 +/* RTC_CNTL_TOUCH_DENOISE_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: touch pad0 will be used to de-noise*/ +#define RTC_CNTL_TOUCH_DENOISE_EN (BIT(2)) +#define RTC_CNTL_TOUCH_DENOISE_EN_M (BIT(2)) +#define RTC_CNTL_TOUCH_DENOISE_EN_V 0x1 +#define RTC_CNTL_TOUCH_DENOISE_EN_S 2 +/* RTC_CNTL_TOUCH_DENOISE_RES : R/W ;bitpos:[1:0] ;default: 2'd2 ; */ +/*description: De-noise resolution: 12/10/8/4 bit*/ +#define RTC_CNTL_TOUCH_DENOISE_RES 0x00000003 +#define RTC_CNTL_TOUCH_DENOISE_RES_M ((RTC_CNTL_TOUCH_DENOISE_RES_V)<<(RTC_CNTL_TOUCH_DENOISE_RES_S)) +#define RTC_CNTL_TOUCH_DENOISE_RES_V 0x3 +#define RTC_CNTL_TOUCH_DENOISE_RES_S 0 + +#define RTC_CNTL_TOUCH_SLP_THRES_REG (DR_REG_RTCCNTL_BASE + 0x0110) +/* RTC_CNTL_TOUCH_SLP_PAD : R/W ;bitpos:[31:27] ;default: 4'hF ; */ +/*description: */ +#define RTC_CNTL_TOUCH_SLP_PAD 0x0000001F +#define RTC_CNTL_TOUCH_SLP_PAD_M ((RTC_CNTL_TOUCH_SLP_PAD_V)<<(RTC_CNTL_TOUCH_SLP_PAD_S)) +#define RTC_CNTL_TOUCH_SLP_PAD_V 0x1F +#define RTC_CNTL_TOUCH_SLP_PAD_S 27 +/* RTC_CNTL_TOUCH_SLP_APPROACH_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: sleep pad approach function enable*/ +#define RTC_CNTL_TOUCH_SLP_APPROACH_EN (BIT(26)) +#define RTC_CNTL_TOUCH_SLP_APPROACH_EN_M (BIT(26)) +#define RTC_CNTL_TOUCH_SLP_APPROACH_EN_V 0x1 +#define RTC_CNTL_TOUCH_SLP_APPROACH_EN_S 26 +/* RTC_CNTL_TOUCH_SLP_TH : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: the threshold for sleep touch pad*/ +#define RTC_CNTL_TOUCH_SLP_TH 0x003FFFFF +#define RTC_CNTL_TOUCH_SLP_TH_M ((RTC_CNTL_TOUCH_SLP_TH_V)<<(RTC_CNTL_TOUCH_SLP_TH_S)) +#define RTC_CNTL_TOUCH_SLP_TH_V 0x3FFFFF +#define RTC_CNTL_TOUCH_SLP_TH_S 0 + +#define RTC_CNTL_TOUCH_APPROACH_REG (DR_REG_RTCCNTL_BASE + 0x0114) +/* RTC_CNTL_TOUCH_APPROACH_MEAS_TIME : R/W ;bitpos:[31:24] ;default: 8'd80 ; */ +/*description: approach pads total meas times*/ +#define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME 0x000000FF +#define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_M ((RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_V)<<(RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_S)) +#define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_V 0xFF +#define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_S 24 +/* RTC_CNTL_TOUCH_SLP_CHANNEL_CLR : WO ;bitpos:[23] ;default: 1'd0 ; */ +/*description: clear touch slp channel*/ +#define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR (BIT(23)) +#define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_M (BIT(23)) +#define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_V 0x1 +#define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_S 23 + +#define RTC_CNTL_TOUCH_FILTER_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x0118) +/* RTC_CNTL_TOUCH_FILTER_EN : R/W ;bitpos:[31] ;default: 1'b1 ; */ +/*description: touch filter enable*/ +#define RTC_CNTL_TOUCH_FILTER_EN (BIT(31)) +#define RTC_CNTL_TOUCH_FILTER_EN_M (BIT(31)) +#define RTC_CNTL_TOUCH_FILTER_EN_V 0x1 +#define RTC_CNTL_TOUCH_FILTER_EN_S 31 +/* RTC_CNTL_TOUCH_FILTER_MODE : R/W ;bitpos:[30:28] ;default: 3'd1 ; */ +/*description: 0: IIR ? 1: IIR ? 2: IIR 1/8 3: Jitter*/ +#define RTC_CNTL_TOUCH_FILTER_MODE 0x00000007 +#define RTC_CNTL_TOUCH_FILTER_MODE_M ((RTC_CNTL_TOUCH_FILTER_MODE_V)<<(RTC_CNTL_TOUCH_FILTER_MODE_S)) +#define RTC_CNTL_TOUCH_FILTER_MODE_V 0x7 +#define RTC_CNTL_TOUCH_FILTER_MODE_S 28 +/* RTC_CNTL_TOUCH_DEBOUNCE : R/W ;bitpos:[27:25] ;default: 3'd3 ; */ +/*description: debounce counter*/ +#define RTC_CNTL_TOUCH_DEBOUNCE 0x00000007 +#define RTC_CNTL_TOUCH_DEBOUNCE_M ((RTC_CNTL_TOUCH_DEBOUNCE_V)<<(RTC_CNTL_TOUCH_DEBOUNCE_S)) +#define RTC_CNTL_TOUCH_DEBOUNCE_V 0x7 +#define RTC_CNTL_TOUCH_DEBOUNCE_S 25 +/* RTC_CNTL_TOUCH_CONFIG3 : R/W ;bitpos:[24:23] ;default: 2'd1 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_CONFIG3 0x00000003 +#define RTC_CNTL_TOUCH_CONFIG3_M ((RTC_CNTL_TOUCH_CONFIG3_V)<<(RTC_CNTL_TOUCH_CONFIG3_S)) +#define RTC_CNTL_TOUCH_CONFIG3_V 0x3 +#define RTC_CNTL_TOUCH_CONFIG3_S 23 +/* RTC_CNTL_TOUCH_NOISE_THRES : R/W ;bitpos:[22:21] ;default: 2'd1 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_NOISE_THRES 0x00000003 +#define RTC_CNTL_TOUCH_NOISE_THRES_M ((RTC_CNTL_TOUCH_NOISE_THRES_V)<<(RTC_CNTL_TOUCH_NOISE_THRES_S)) +#define RTC_CNTL_TOUCH_NOISE_THRES_V 0x3 +#define RTC_CNTL_TOUCH_NOISE_THRES_S 21 +/* RTC_CNTL_TOUCH_CONFIG2 : R/W ;bitpos:[20:19] ;default: 2'd1 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_CONFIG2 0x00000003 +#define RTC_CNTL_TOUCH_CONFIG2_M ((RTC_CNTL_TOUCH_CONFIG2_V)<<(RTC_CNTL_TOUCH_CONFIG2_S)) +#define RTC_CNTL_TOUCH_CONFIG2_V 0x3 +#define RTC_CNTL_TOUCH_CONFIG2_S 19 +/* RTC_CNTL_TOUCH_CONFIG1 : R/W ;bitpos:[18:15] ;default: 4'd5 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_CONFIG1 0x0000000F +#define RTC_CNTL_TOUCH_CONFIG1_M ((RTC_CNTL_TOUCH_CONFIG1_V)<<(RTC_CNTL_TOUCH_CONFIG1_S)) +#define RTC_CNTL_TOUCH_CONFIG1_V 0xF +#define RTC_CNTL_TOUCH_CONFIG1_S 15 +/* RTC_CNTL_TOUCH_JITTER_STEP : R/W ;bitpos:[14:11] ;default: 4'd1 ; */ +/*description: touch jitter step*/ +#define RTC_CNTL_TOUCH_JITTER_STEP 0x0000000F +#define RTC_CNTL_TOUCH_JITTER_STEP_M ((RTC_CNTL_TOUCH_JITTER_STEP_V)<<(RTC_CNTL_TOUCH_JITTER_STEP_S)) +#define RTC_CNTL_TOUCH_JITTER_STEP_V 0xF +#define RTC_CNTL_TOUCH_JITTER_STEP_S 11 +/* RTC_CNTL_TOUCH_SMOOTH_LVL : R/W ;bitpos:[10:9] ;default: 2'd0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_SMOOTH_LVL 0x00000003 +#define RTC_CNTL_TOUCH_SMOOTH_LVL_M ((RTC_CNTL_TOUCH_SMOOTH_LVL_V)<<(RTC_CNTL_TOUCH_SMOOTH_LVL_S)) +#define RTC_CNTL_TOUCH_SMOOTH_LVL_V 0x3 +#define RTC_CNTL_TOUCH_SMOOTH_LVL_S 9 + +#define RTC_CNTL_USB_CONF_REG (DR_REG_RTCCNTL_BASE + 0x011C) +/* RTC_CNTL_IO_MUX_RESET_DISABLE : R/W ;bitpos:[18] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_IO_MUX_RESET_DISABLE (BIT(18)) +#define RTC_CNTL_IO_MUX_RESET_DISABLE_M (BIT(18)) +#define RTC_CNTL_IO_MUX_RESET_DISABLE_V 0x1 +#define RTC_CNTL_IO_MUX_RESET_DISABLE_S 18 +/* RTC_CNTL_USB_RESET_DISABLE : R/W ;bitpos:[17] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_USB_RESET_DISABLE (BIT(17)) +#define RTC_CNTL_USB_RESET_DISABLE_M (BIT(17)) +#define RTC_CNTL_USB_RESET_DISABLE_V 0x1 +#define RTC_CNTL_USB_RESET_DISABLE_S 17 +/* RTC_CNTL_USB_TX_EN_OVERRIDE : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_USB_TX_EN_OVERRIDE (BIT(16)) +#define RTC_CNTL_USB_TX_EN_OVERRIDE_M (BIT(16)) +#define RTC_CNTL_USB_TX_EN_OVERRIDE_V 0x1 +#define RTC_CNTL_USB_TX_EN_OVERRIDE_S 16 +/* RTC_CNTL_USB_TX_EN : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_USB_TX_EN (BIT(15)) +#define RTC_CNTL_USB_TX_EN_M (BIT(15)) +#define RTC_CNTL_USB_TX_EN_V 0x1 +#define RTC_CNTL_USB_TX_EN_S 15 +/* RTC_CNTL_USB_TXP : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_USB_TXP (BIT(14)) +#define RTC_CNTL_USB_TXP_M (BIT(14)) +#define RTC_CNTL_USB_TXP_V 0x1 +#define RTC_CNTL_USB_TXP_S 14 +/* RTC_CNTL_USB_TXM : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_USB_TXM (BIT(13)) +#define RTC_CNTL_USB_TXM_M (BIT(13)) +#define RTC_CNTL_USB_TXM_V 0x1 +#define RTC_CNTL_USB_TXM_S 13 +/* RTC_CNTL_USB_PAD_ENABLE : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_USB_PAD_ENABLE (BIT(12)) +#define RTC_CNTL_USB_PAD_ENABLE_M (BIT(12)) +#define RTC_CNTL_USB_PAD_ENABLE_V 0x1 +#define RTC_CNTL_USB_PAD_ENABLE_S 12 +/* RTC_CNTL_USB_PAD_ENABLE_OVERRIDE : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE (BIT(11)) +#define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_M (BIT(11)) +#define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_V 0x1 +#define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_S 11 +/* RTC_CNTL_USB_PULLUP_VALUE : R/W ;bitpos:[10] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_USB_PULLUP_VALUE (BIT(10)) +#define RTC_CNTL_USB_PULLUP_VALUE_M (BIT(10)) +#define RTC_CNTL_USB_PULLUP_VALUE_V 0x1 +#define RTC_CNTL_USB_PULLUP_VALUE_S 10 +/* RTC_CNTL_USB_DM_PULLDOWN : R/W ;bitpos:[9] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_USB_DM_PULLDOWN (BIT(9)) +#define RTC_CNTL_USB_DM_PULLDOWN_M (BIT(9)) +#define RTC_CNTL_USB_DM_PULLDOWN_V 0x1 +#define RTC_CNTL_USB_DM_PULLDOWN_S 9 +/* RTC_CNTL_USB_DM_PULLUP : R/W ;bitpos:[8] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_USB_DM_PULLUP (BIT(8)) +#define RTC_CNTL_USB_DM_PULLUP_M (BIT(8)) +#define RTC_CNTL_USB_DM_PULLUP_V 0x1 +#define RTC_CNTL_USB_DM_PULLUP_S 8 +/* RTC_CNTL_USB_DP_PULLDOWN : R/W ;bitpos:[7] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_USB_DP_PULLDOWN (BIT(7)) +#define RTC_CNTL_USB_DP_PULLDOWN_M (BIT(7)) +#define RTC_CNTL_USB_DP_PULLDOWN_V 0x1 +#define RTC_CNTL_USB_DP_PULLDOWN_S 7 +/* RTC_CNTL_USB_DP_PULLUP : R/W ;bitpos:[6] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_USB_DP_PULLUP (BIT(6)) +#define RTC_CNTL_USB_DP_PULLUP_M (BIT(6)) +#define RTC_CNTL_USB_DP_PULLUP_V 0x1 +#define RTC_CNTL_USB_DP_PULLUP_S 6 +/* RTC_CNTL_USB_PAD_PULL_OVERRIDE : R/W ;bitpos:[5] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_USB_PAD_PULL_OVERRIDE (BIT(5)) +#define RTC_CNTL_USB_PAD_PULL_OVERRIDE_M (BIT(5)) +#define RTC_CNTL_USB_PAD_PULL_OVERRIDE_V 0x1 +#define RTC_CNTL_USB_PAD_PULL_OVERRIDE_S 5 +/* RTC_CNTL_USB_VREF_OVERRIDE : R/W ;bitpos:[4] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_USB_VREF_OVERRIDE (BIT(4)) +#define RTC_CNTL_USB_VREF_OVERRIDE_M (BIT(4)) +#define RTC_CNTL_USB_VREF_OVERRIDE_V 0x1 +#define RTC_CNTL_USB_VREF_OVERRIDE_S 4 +/* RTC_CNTL_USB_VREFL : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ +/*description: */ +#define RTC_CNTL_USB_VREFL 0x00000003 +#define RTC_CNTL_USB_VREFL_M ((RTC_CNTL_USB_VREFL_V)<<(RTC_CNTL_USB_VREFL_S)) +#define RTC_CNTL_USB_VREFL_V 0x3 +#define RTC_CNTL_USB_VREFL_S 2 +/* RTC_CNTL_USB_VREFH : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: */ +#define RTC_CNTL_USB_VREFH 0x00000003 +#define RTC_CNTL_USB_VREFH_M ((RTC_CNTL_USB_VREFH_V)<<(RTC_CNTL_USB_VREFH_S)) +#define RTC_CNTL_USB_VREFH_V 0x3 +#define RTC_CNTL_USB_VREFH_S 0 + +#define RTC_CNTL_TOUCH_TIMEOUT_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x0120) +/* RTC_CNTL_TOUCH_TIMEOUT_EN : R/W ;bitpos:[22] ;default: 1'b1 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_TIMEOUT_EN (BIT(22)) +#define RTC_CNTL_TOUCH_TIMEOUT_EN_M (BIT(22)) +#define RTC_CNTL_TOUCH_TIMEOUT_EN_V 0x1 +#define RTC_CNTL_TOUCH_TIMEOUT_EN_S 22 +/* RTC_CNTL_TOUCH_TIMEOUT_NUM : R/W ;bitpos:[21:0] ;default: 22'h3fffff ; */ +/*description: */ +#define RTC_CNTL_TOUCH_TIMEOUT_NUM 0x003FFFFF +#define RTC_CNTL_TOUCH_TIMEOUT_NUM_M ((RTC_CNTL_TOUCH_TIMEOUT_NUM_V)<<(RTC_CNTL_TOUCH_TIMEOUT_NUM_S)) +#define RTC_CNTL_TOUCH_TIMEOUT_NUM_V 0x3FFFFF +#define RTC_CNTL_TOUCH_TIMEOUT_NUM_S 0 + +#define RTC_CNTL_SLP_REJECT_CAUSE_REG (DR_REG_RTCCNTL_BASE + 0x0124) +/* RTC_CNTL_REJECT_CAUSE : RO ;bitpos:[16:0] ;default: 17'd0 ; */ +/*description: sleep reject cause*/ +#define RTC_CNTL_REJECT_CAUSE 0x0001FFFF +#define RTC_CNTL_REJECT_CAUSE_M ((RTC_CNTL_REJECT_CAUSE_V)<<(RTC_CNTL_REJECT_CAUSE_S)) +#define RTC_CNTL_REJECT_CAUSE_V 0x1FFFF +#define RTC_CNTL_REJECT_CAUSE_S 0 + +#define RTC_CNTL_OPTION1_REG (DR_REG_RTCCNTL_BASE + 0x0128) +/* RTC_CNTL_FORCE_DOWNLOAD_BOOT : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_FORCE_DOWNLOAD_BOOT (BIT(0)) +#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_M (BIT(0)) +#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_V 0x1 +#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_S 0 + +#define RTC_CNTL_SLP_WAKEUP_CAUSE_REG (DR_REG_RTCCNTL_BASE + 0x012C) +/* RTC_CNTL_WAKEUP_CAUSE : RO ;bitpos:[16:0] ;default: 17'd0 ; */ +/*description: sleep wakeup cause*/ +#define RTC_CNTL_WAKEUP_CAUSE 0x0001FFFF +#define RTC_CNTL_WAKEUP_CAUSE_M ((RTC_CNTL_WAKEUP_CAUSE_V)<<(RTC_CNTL_WAKEUP_CAUSE_S)) +#define RTC_CNTL_WAKEUP_CAUSE_V 0x1FFFF +#define RTC_CNTL_WAKEUP_CAUSE_S 0 + +#define RTC_CNTL_ULP_CP_TIMER_1_REG (DR_REG_RTCCNTL_BASE + 0x0130) +/* RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE : R/W ;bitpos:[31:8] ;default: 24'd200 ; */ +/*description: sleep cycles for ULP-coprocessor timer*/ +#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE 0x00FFFFFF +#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_M ((RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V)<<(RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S)) +#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V 0xFFFFFF +#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S 8 + +#define RTC_CNTL_DATE_REG (DR_REG_RTCCNTL_BASE + 0x0138) +/* RTC_CNTL_CNTL_DATE : R/W ;bitpos:[27:0] ;default: 28'h1908130 ; */ +/*description: */ +#define RTC_CNTL_CNTL_DATE 0x0FFFFFFF +#define RTC_CNTL_CNTL_DATE_M ((RTC_CNTL_CNTL_DATE_V)<<(RTC_CNTL_CNTL_DATE_S)) +#define RTC_CNTL_CNTL_DATE_V 0xFFFFFFF +#define RTC_CNTL_CNTL_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/src/target/esp32s2/include/soc/system_reg.h b/src/target/esp32s2/include/soc/system_reg.h new file mode 100644 index 0000000..912629a --- /dev/null +++ b/src/target/esp32s2/include/soc/system_reg.h @@ -0,0 +1,884 @@ +/* + * SPDX-FileCopyrightText: 2017-2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 OR MIT + */ +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif +#include + +#define DPORT_ROM_CTRL_0_REG (DR_REG_SYSTEM_BASE + 0x000) +/* DPORT_ROM_FO : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define DPORT_ROM_FO 0x00000003 +#define DPORT_ROM_FO_M ((DPORT_ROM_FO_V)<<(DPORT_ROM_FO_S)) +#define DPORT_ROM_FO_V 0x3 +#define DPORT_ROM_FO_S 0 + +#define DPORT_ROM_CTRL_1_REG (DR_REG_SYSTEM_BASE + 0x004) +/* DPORT_ROM_FORCE_PU : R/W ;bitpos:[3:2] ;default: 2'b11 ; */ +/*description: */ +#define DPORT_ROM_FORCE_PU 0x00000003 +#define DPORT_ROM_FORCE_PU_M ((DPORT_ROM_FORCE_PU_V)<<(DPORT_ROM_FORCE_PU_S)) +#define DPORT_ROM_FORCE_PU_V 0x3 +#define DPORT_ROM_FORCE_PU_S 2 +/* DPORT_ROM_FORCE_PD : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: */ +#define DPORT_ROM_FORCE_PD 0x00000003 +#define DPORT_ROM_FORCE_PD_M ((DPORT_ROM_FORCE_PD_V)<<(DPORT_ROM_FORCE_PD_S)) +#define DPORT_ROM_FORCE_PD_V 0x3 +#define DPORT_ROM_FORCE_PD_S 0 + +#define DPORT_SRAM_CTRL_0_REG (DR_REG_SYSTEM_BASE + 0x008) +/* DPORT_SRAM_FO : R/W ;bitpos:[21:0] ;default: ~22'b0 ; */ +/*description: */ +#define DPORT_SRAM_FO 0x003FFFFF +#define DPORT_SRAM_FO_M ((DPORT_SRAM_FO_V)<<(DPORT_SRAM_FO_S)) +#define DPORT_SRAM_FO_V 0x3FFFFF +#define DPORT_SRAM_FO_S 0 + +#define DPORT_SRAM_CTRL_1_REG (DR_REG_SYSTEM_BASE + 0x00C) +/* DPORT_SRAM_FORCE_PD : R/W ;bitpos:[21:0] ;default: 22'b0 ; */ +/*description: */ +#define DPORT_SRAM_FORCE_PD 0x003FFFFF +#define DPORT_SRAM_FORCE_PD_M ((DPORT_SRAM_FORCE_PD_V)<<(DPORT_SRAM_FORCE_PD_S)) +#define DPORT_SRAM_FORCE_PD_V 0x3FFFFF +#define DPORT_SRAM_FORCE_PD_S 0 + +#define DPORT_PERI_CLK_EN_REG DPORT_CPU_PERI_CLK_EN_REG +#define DPORT_CPU_PERI_CLK_EN_REG (DR_REG_SYSTEM_BASE + 0x010) +/* DPORT_CLK_EN_DEDICATED_GPIO : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_CLK_EN_DEDICATED_GPIO (BIT(7)) +#define DPORT_CLK_EN_DEDICATED_GPIO_M (BIT(7)) +#define DPORT_CLK_EN_DEDICATED_GPIO_V 0x1 +#define DPORT_CLK_EN_DEDICATED_GPIO_S 7 +/* DPORT_CLK_EN_ASSIST_DEBUG : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_CLK_EN_ASSIST_DEBUG (BIT(6)) +#define DPORT_CLK_EN_ASSIST_DEBUG_M (BIT(6)) +#define DPORT_CLK_EN_ASSIST_DEBUG_V 0x1 +#define DPORT_CLK_EN_ASSIST_DEBUG_S 6 + +/* NB: Digital signature reset will hold AES & RSA in reset */ +#define DPORT_PERI_EN_ASSIST_DEBUG DPORT_CLK_EN_ASSIST_DEBUG + +#define DPORT_PERI_RST_EN_REG DPORT_CPU_PERI_RST_EN_REG +#define DPORT_CPU_PERI_RST_EN_REG (DR_REG_SYSTEM_BASE + 0x014) +/* DPORT_RST_EN_DEDICATED_GPIO : R/W ;bitpos:[7] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_RST_EN_DEDICATED_GPIO (BIT(7)) +#define DPORT_RST_EN_DEDICATED_GPIO_M (BIT(7)) +#define DPORT_RST_EN_DEDICATED_GPIO_V 0x1 +#define DPORT_RST_EN_DEDICATED_GPIO_S 7 +/* DPORT_RST_EN_ASSIST_DEBUG : R/W ;bitpos:[6] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_RST_EN_ASSIST_DEBUG (BIT(6)) +#define DPORT_RST_EN_ASSIST_DEBUG_M (BIT(6)) +#define DPORT_RST_EN_ASSIST_DEBUG_V 0x1 +#define DPORT_RST_EN_ASSIST_DEBUG_S 6 + +#define DPORT_CPU_PER_CONF_REG (DR_REG_SYSTEM_BASE + 0x018) +/* DPORT_CPU_WAITI_DELAY_NUM : R/W ;bitpos:[7:4] ;default: 4'h0 ; */ +/*description: */ +#define DPORT_CPU_WAITI_DELAY_NUM 0x0000000F +#define DPORT_CPU_WAITI_DELAY_NUM_M ((DPORT_CPU_WAITI_DELAY_NUM_V)<<(DPORT_CPU_WAITI_DELAY_NUM_S)) +#define DPORT_CPU_WAITI_DELAY_NUM_V 0xF +#define DPORT_CPU_WAITI_DELAY_NUM_S 4 +/* DPORT_CPU_WAIT_MODE_FORCE_ON : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_CPU_WAIT_MODE_FORCE_ON (BIT(3)) +#define DPORT_CPU_WAIT_MODE_FORCE_ON_M (BIT(3)) +#define DPORT_CPU_WAIT_MODE_FORCE_ON_V 0x1 +#define DPORT_CPU_WAIT_MODE_FORCE_ON_S 3 +/* DPORT_PLL_FREQ_SEL : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_PLL_FREQ_SEL (BIT(2)) +#define DPORT_PLL_FREQ_SEL_M (BIT(2)) +#define DPORT_PLL_FREQ_SEL_V 0x1 +#define DPORT_PLL_FREQ_SEL_S 2 +/* DPORT_CPUPERIOD_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: */ +#define DPORT_CPUPERIOD_SEL 0x00000003 +#define DPORT_CPUPERIOD_SEL_M ((DPORT_CPUPERIOD_SEL_V)<<(DPORT_CPUPERIOD_SEL_S)) +#define DPORT_CPUPERIOD_SEL_V 0x3 +#define DPORT_CPUPERIOD_SEL_S 0 + +#define DPORT_JTAG_CTRL_0_REG (DR_REG_SYSTEM_BASE + 0x01C) +/* DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0 0xFFFFFFFF +#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_M ((DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_V)<<(DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_S)) +#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_V 0xFFFFFFFF +#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_S 0 + +#define DPORT_JTAG_CTRL_1_REG (DR_REG_SYSTEM_BASE + 0x020) +/* DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1 0xFFFFFFFF +#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_M ((DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_V)<<(DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_S)) +#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_V 0xFFFFFFFF +#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_S 0 + +#define DPORT_JTAG_CTRL_2_REG (DR_REG_SYSTEM_BASE + 0x024) +/* DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2 0xFFFFFFFF +#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_M ((DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_V)<<(DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_S)) +#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_V 0xFFFFFFFF +#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_S 0 + +#define DPORT_JTAG_CTRL_3_REG (DR_REG_SYSTEM_BASE + 0x028) +/* DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3 0xFFFFFFFF +#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_M ((DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_V)<<(DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_S)) +#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_V 0xFFFFFFFF +#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_S 0 + +#define DPORT_JTAG_CTRL_4_REG (DR_REG_SYSTEM_BASE + 0x02C) +/* DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4 0xFFFFFFFF +#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_M ((DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_V)<<(DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_S)) +#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_V 0xFFFFFFFF +#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_S 0 + +#define DPORT_JTAG_CTRL_5_REG (DR_REG_SYSTEM_BASE + 0x030) +/* DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5 0xFFFFFFFF +#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_M ((DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_V)<<(DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_S)) +#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_V 0xFFFFFFFF +#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_S 0 + +#define DPORT_JTAG_CTRL_6_REG (DR_REG_SYSTEM_BASE + 0x034) +/* DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6 0xFFFFFFFF +#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_M ((DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_V)<<(DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_S)) +#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_V 0xFFFFFFFF +#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_S 0 + +#define DPORT_JTAG_CTRL_7_REG (DR_REG_SYSTEM_BASE + 0x038) +/* DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7 0xFFFFFFFF +#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_M ((DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_V)<<(DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_S)) +#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_V 0xFFFFFFFF +#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_S 0 + +#define DPORT_MEM_PD_MASK_REG (DR_REG_SYSTEM_BASE + 0x03C) +/* DPORT_LSLP_MEM_PD_MASK : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_LSLP_MEM_PD_MASK (BIT(0)) +#define DPORT_LSLP_MEM_PD_MASK_M (BIT(0)) +#define DPORT_LSLP_MEM_PD_MASK_V 0x1 +#define DPORT_LSLP_MEM_PD_MASK_S 0 + +#define DPORT_PERIP_CLK_EN_REG DPORT_PERIP_CLK_EN0_REG +#define DPORT_PERIP_CLK_EN0_REG (DR_REG_SYSTEM_BASE + 0x040) +/* DPORT_ADC2_ARB_CLK_EN : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_ADC2_ARB_CLK_EN (BIT(30)) +#define DPORT_ADC2_ARB_CLK_EN_M (BIT(30)) +#define DPORT_ADC2_ARB_CLK_EN_V 0x1 +#define DPORT_ADC2_ARB_CLK_EN_S 30 +/* DPORT_SYSTIMER_CLK_EN : R/W ;bitpos:[29] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_SYSTIMER_CLK_EN (BIT(29)) +#define DPORT_SYSTIMER_CLK_EN_M (BIT(29)) +#define DPORT_SYSTIMER_CLK_EN_V 0x1 +#define DPORT_SYSTIMER_CLK_EN_S 29 +/* DPORT_APB_SARADC_CLK_EN : R/W ;bitpos:[28] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_APB_SARADC_CLK_EN (BIT(28)) +#define DPORT_APB_SARADC_CLK_EN_M (BIT(28)) +#define DPORT_APB_SARADC_CLK_EN_V 0x1 +#define DPORT_APB_SARADC_CLK_EN_S 28 +/* DPORT_SPI3_DMA_CLK_EN : R/W ;bitpos:[27] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_SPI3_DMA_CLK_EN (BIT(27)) +#define DPORT_SPI3_DMA_CLK_EN_M (BIT(27)) +#define DPORT_SPI3_DMA_CLK_EN_V 0x1 +#define DPORT_SPI3_DMA_CLK_EN_S 27 +/* DPORT_PWM3_CLK_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PWM3_CLK_EN (BIT(26)) +#define DPORT_PWM3_CLK_EN_M (BIT(26)) +#define DPORT_PWM3_CLK_EN_V 0x1 +#define DPORT_PWM3_CLK_EN_S 26 +/* DPORT_PWM2_CLK_EN : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PWM2_CLK_EN (BIT(25)) +#define DPORT_PWM2_CLK_EN_M (BIT(25)) +#define DPORT_PWM2_CLK_EN_V 0x1 +#define DPORT_PWM2_CLK_EN_S 25 +/* DPORT_UART_MEM_CLK_EN : R/W ;bitpos:[24] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_UART_MEM_CLK_EN (BIT(24)) +#define DPORT_UART_MEM_CLK_EN_M (BIT(24)) +#define DPORT_UART_MEM_CLK_EN_V 0x1 +#define DPORT_UART_MEM_CLK_EN_S 24 +/* DPORT_USB_CLK_EN : R/W ;bitpos:[23] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_USB_CLK_EN (BIT(23)) +#define DPORT_USB_CLK_EN_M (BIT(23)) +#define DPORT_USB_CLK_EN_V 0x1 +#define DPORT_USB_CLK_EN_S 23 +/* DPORT_SPI2_DMA_CLK_EN : R/W ;bitpos:[22] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_SPI2_DMA_CLK_EN (BIT(22)) +#define DPORT_SPI2_DMA_CLK_EN_M (BIT(22)) +#define DPORT_SPI2_DMA_CLK_EN_V 0x1 +#define DPORT_SPI2_DMA_CLK_EN_S 22 +/* DPORT_PWM1_CLK_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PWM1_CLK_EN (BIT(20)) +#define DPORT_PWM1_CLK_EN_M (BIT(20)) +#define DPORT_PWM1_CLK_EN_V 0x1 +#define DPORT_PWM1_CLK_EN_S 20 +/* DPORT_TWAI_CLK_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_TWAI_CLK_EN (BIT(19)) +#define DPORT_TWAI_CLK_EN_M (BIT(19)) +#define DPORT_TWAI_CLK_EN_V 0x1 +#define DPORT_TWAI_CLK_EN_S 19 +/* DPORT_I2C_EXT1_CLK_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_I2C_EXT1_CLK_EN (BIT(18)) +#define DPORT_I2C_EXT1_CLK_EN_M (BIT(18)) +#define DPORT_I2C_EXT1_CLK_EN_V 0x1 +#define DPORT_I2C_EXT1_CLK_EN_S 18 +/* DPORT_PWM0_CLK_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PWM0_CLK_EN (BIT(17)) +#define DPORT_PWM0_CLK_EN_M (BIT(17)) +#define DPORT_PWM0_CLK_EN_V 0x1 +#define DPORT_PWM0_CLK_EN_S 17 +/* DPORT_SPI3_CLK_EN : R/W ;bitpos:[16] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_SPI3_CLK_EN (BIT(16)) +#define DPORT_SPI3_CLK_EN_M (BIT(16)) +#define DPORT_SPI3_CLK_EN_V 0x1 +#define DPORT_SPI3_CLK_EN_S 16 +/* DPORT_TIMERGROUP1_CLK_EN : R/W ;bitpos:[15] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_TIMERGROUP1_CLK_EN (BIT(15)) +#define DPORT_TIMERGROUP1_CLK_EN_M (BIT(15)) +#define DPORT_TIMERGROUP1_CLK_EN_V 0x1 +#define DPORT_TIMERGROUP1_CLK_EN_S 15 +/* DPORT_EFUSE_CLK_EN : R/W ;bitpos:[14] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_EFUSE_CLK_EN (BIT(14)) +#define DPORT_EFUSE_CLK_EN_M (BIT(14)) +#define DPORT_EFUSE_CLK_EN_V 0x1 +#define DPORT_EFUSE_CLK_EN_S 14 +/* DPORT_TIMERGROUP_CLK_EN : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_TIMERGROUP_CLK_EN (BIT(13)) +#define DPORT_TIMERGROUP_CLK_EN_M (BIT(13)) +#define DPORT_TIMERGROUP_CLK_EN_V 0x1 +#define DPORT_TIMERGROUP_CLK_EN_S 13 +/* DPORT_UHCI1_CLK_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_UHCI1_CLK_EN (BIT(12)) +#define DPORT_UHCI1_CLK_EN_M (BIT(12)) +#define DPORT_UHCI1_CLK_EN_V 0x1 +#define DPORT_UHCI1_CLK_EN_S 12 +/* DPORT_LEDC_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_LEDC_CLK_EN (BIT(11)) +#define DPORT_LEDC_CLK_EN_M (BIT(11)) +#define DPORT_LEDC_CLK_EN_V 0x1 +#define DPORT_LEDC_CLK_EN_S 11 +/* DPORT_PCNT_CLK_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PCNT_CLK_EN (BIT(10)) +#define DPORT_PCNT_CLK_EN_M (BIT(10)) +#define DPORT_PCNT_CLK_EN_V 0x1 +#define DPORT_PCNT_CLK_EN_S 10 +/* DPORT_RMT_CLK_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_RMT_CLK_EN (BIT(9)) +#define DPORT_RMT_CLK_EN_M (BIT(9)) +#define DPORT_RMT_CLK_EN_V 0x1 +#define DPORT_RMT_CLK_EN_S 9 +/* DPORT_UHCI0_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_UHCI0_CLK_EN (BIT(8)) +#define DPORT_UHCI0_CLK_EN_M (BIT(8)) +#define DPORT_UHCI0_CLK_EN_V 0x1 +#define DPORT_UHCI0_CLK_EN_S 8 +/* DPORT_I2C_EXT0_CLK_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_I2C_EXT0_CLK_EN (BIT(7)) +#define DPORT_I2C_EXT0_CLK_EN_M (BIT(7)) +#define DPORT_I2C_EXT0_CLK_EN_V 0x1 +#define DPORT_I2C_EXT0_CLK_EN_S 7 +/* DPORT_SPI2_CLK_EN : R/W ;bitpos:[6] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_SPI2_CLK_EN (BIT(6)) +#define DPORT_SPI2_CLK_EN_M (BIT(6)) +#define DPORT_SPI2_CLK_EN_V 0x1 +#define DPORT_SPI2_CLK_EN_S 6 +/* DPORT_UART1_CLK_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_UART1_CLK_EN (BIT(5)) +#define DPORT_UART1_CLK_EN_M (BIT(5)) +#define DPORT_UART1_CLK_EN_V 0x1 +#define DPORT_UART1_CLK_EN_S 5 +/* DPORT_I2S0_CLK_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_I2S0_CLK_EN (BIT(4)) +#define DPORT_I2S0_CLK_EN_M (BIT(4)) +#define DPORT_I2S0_CLK_EN_V 0x1 +#define DPORT_I2S0_CLK_EN_S 4 +/* DPORT_WDG_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_WDG_CLK_EN (BIT(3)) +#define DPORT_WDG_CLK_EN_M (BIT(3)) +#define DPORT_WDG_CLK_EN_V 0x1 +#define DPORT_WDG_CLK_EN_S 3 +/* DPORT_UART_CLK_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_UART_CLK_EN (BIT(2)) +#define DPORT_UART_CLK_EN_M (BIT(2)) +#define DPORT_UART_CLK_EN_V 0x1 +#define DPORT_UART_CLK_EN_S 2 +/* DPORT_SPI01_CLK_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_SPI01_CLK_EN (BIT(1)) +#define DPORT_SPI01_CLK_EN_M (BIT(1)) +#define DPORT_SPI01_CLK_EN_V 0x1 +#define DPORT_SPI01_CLK_EN_S 1 +/* DPORT_TIMERS_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_TIMERS_CLK_EN (BIT(0)) +#define DPORT_TIMERS_CLK_EN_M (BIT(0)) +#define DPORT_TIMERS_CLK_EN_V 0x1 +#define DPORT_TIMERS_CLK_EN_S 0 + +#define DPORT_CPU_PERIP_CLK_EN1_REG DPORT_PERIP_CLK_EN1_REG +#define DPORT_PERIP_CLK_EN1_REG (DR_REG_SYSTEM_BASE + 0x044) +/* DPORT_CRYPTO_DMA_CLK_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_CRYPTO_DMA_CLK_EN (BIT(6)) +#define DPORT_CRYPTO_DMA_CLK_EN_M (BIT(6)) +#define DPORT_CRYPTO_DMA_CLK_EN_V 0x1 +#define DPORT_CRYPTO_DMA_CLK_EN_S 6 +/* DPORT_CRYPTO_HMAC_CLK_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_CRYPTO_HMAC_CLK_EN (BIT(5)) +#define DPORT_CRYPTO_HMAC_CLK_EN_M (BIT(5)) +#define DPORT_CRYPTO_HMAC_CLK_EN_V 0x1 +#define DPORT_CRYPTO_HMAC_CLK_EN_S 5 +/* DPORT_CRYPTO_DS_CLK_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_CRYPTO_DS_CLK_EN (BIT(4)) +#define DPORT_CRYPTO_DS_CLK_EN_M (BIT(4)) +#define DPORT_CRYPTO_DS_CLK_EN_V 0x1 +#define DPORT_CRYPTO_DS_CLK_EN_S 4 +/* DPORT_CRYPTO_RSA_CLK_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_CRYPTO_RSA_CLK_EN (BIT(3)) +#define DPORT_CRYPTO_RSA_CLK_EN_M (BIT(3)) +#define DPORT_CRYPTO_RSA_CLK_EN_V 0x1 +#define DPORT_CRYPTO_RSA_CLK_EN_S 3 +/* DPORT_CRYPTO_SHA_CLK_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_CRYPTO_SHA_CLK_EN (BIT(2)) +#define DPORT_CRYPTO_SHA_CLK_EN_M (BIT(2)) +#define DPORT_CRYPTO_SHA_CLK_EN_V 0x1 +#define DPORT_CRYPTO_SHA_CLK_EN_S 2 +/* DPORT_CRYPTO_AES_CLK_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_CRYPTO_AES_CLK_EN (BIT(1)) +#define DPORT_CRYPTO_AES_CLK_EN_M (BIT(1)) +#define DPORT_CRYPTO_AES_CLK_EN_V 0x1 +#define DPORT_CRYPTO_AES_CLK_EN_S 1 + +#define DPORT_PERIP_RST_EN0_REG (DR_REG_SYSTEM_BASE + 0x048) +/* DPORT_ADC2_ARB_RST : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_ADC2_ARB_RST (BIT(30)) +#define DPORT_ADC2_ARB_RST_M (BIT(30)) +#define DPORT_ADC2_ARB_RST_V 0x1 +#define DPORT_ADC2_ARB_RST_S 30 +/* DPORT_SYSTIMER_RST : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_SYSTIMER_RST (BIT(29)) +#define DPORT_SYSTIMER_RST_M (BIT(29)) +#define DPORT_SYSTIMER_RST_V 0x1 +#define DPORT_SYSTIMER_RST_S 29 +/* DPORT_APB_SARADC_RST : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APB_SARADC_RST (BIT(28)) +#define DPORT_APB_SARADC_RST_M (BIT(28)) +#define DPORT_APB_SARADC_RST_V 0x1 +#define DPORT_APB_SARADC_RST_S 28 +/* DPORT_SPI3_DMA_RST : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_SPI3_DMA_RST (BIT(27)) +#define DPORT_SPI3_DMA_RST_M (BIT(27)) +#define DPORT_SPI3_DMA_RST_V 0x1 +#define DPORT_SPI3_DMA_RST_S 27 +/* DPORT_PWM3_RST : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PWM3_RST (BIT(26)) +#define DPORT_PWM3_RST_M (BIT(26)) +#define DPORT_PWM3_RST_V 0x1 +#define DPORT_PWM3_RST_S 26 +/* DPORT_PWM2_RST : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PWM2_RST (BIT(25)) +#define DPORT_PWM2_RST_M (BIT(25)) +#define DPORT_PWM2_RST_V 0x1 +#define DPORT_PWM2_RST_S 25 +/* DPORT_UART_MEM_RST : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_UART_MEM_RST (BIT(24)) +#define DPORT_UART_MEM_RST_M (BIT(24)) +#define DPORT_UART_MEM_RST_V 0x1 +#define DPORT_UART_MEM_RST_S 24 +/* DPORT_USB_RST : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_USB_RST (BIT(23)) +#define DPORT_USB_RST_M (BIT(23)) +#define DPORT_USB_RST_V 0x1 +#define DPORT_USB_RST_S 23 +/* DPORT_SPI2_DMA_RST : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_SPI2_DMA_RST (BIT(22)) +#define DPORT_SPI2_DMA_RST_M (BIT(22)) +#define DPORT_SPI2_DMA_RST_V 0x1 +#define DPORT_SPI2_DMA_RST_S 22 +/* DPORT_PWM1_RST : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PWM1_RST (BIT(20)) +#define DPORT_PWM1_RST_M (BIT(20)) +#define DPORT_PWM1_RST_V 0x1 +#define DPORT_PWM1_RST_S 20 +/* DPORT_TWAI_RST : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_TWAI_RST (BIT(19)) +#define DPORT_TWAI_RST_M (BIT(19)) +#define DPORT_TWAI_RST_V 0x1 +#define DPORT_TWAI_RST_S 19 +/* DPORT_I2C_EXT1_RST : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_I2C_EXT1_RST (BIT(18)) +#define DPORT_I2C_EXT1_RST_M (BIT(18)) +#define DPORT_I2C_EXT1_RST_V 0x1 +#define DPORT_I2C_EXT1_RST_S 18 +/* DPORT_PWM0_RST : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PWM0_RST (BIT(17)) +#define DPORT_PWM0_RST_M (BIT(17)) +#define DPORT_PWM0_RST_V 0x1 +#define DPORT_PWM0_RST_S 17 +/* DPORT_SPI3_RST : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_SPI3_RST (BIT(16)) +#define DPORT_SPI3_RST_M (BIT(16)) +#define DPORT_SPI3_RST_V 0x1 +#define DPORT_SPI3_RST_S 16 +/* DPORT_TIMERGROUP1_RST : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_TIMERGROUP1_RST (BIT(15)) +#define DPORT_TIMERGROUP1_RST_M (BIT(15)) +#define DPORT_TIMERGROUP1_RST_V 0x1 +#define DPORT_TIMERGROUP1_RST_S 15 +/* DPORT_EFUSE_RST : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_EFUSE_RST (BIT(14)) +#define DPORT_EFUSE_RST_M (BIT(14)) +#define DPORT_EFUSE_RST_V 0x1 +#define DPORT_EFUSE_RST_S 14 +/* DPORT_TIMERGROUP_RST : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_TIMERGROUP_RST (BIT(13)) +#define DPORT_TIMERGROUP_RST_M (BIT(13)) +#define DPORT_TIMERGROUP_RST_V 0x1 +#define DPORT_TIMERGROUP_RST_S 13 +/* DPORT_UHCI1_RST : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_UHCI1_RST (BIT(12)) +#define DPORT_UHCI1_RST_M (BIT(12)) +#define DPORT_UHCI1_RST_V 0x1 +#define DPORT_UHCI1_RST_S 12 +/* DPORT_LEDC_RST : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_LEDC_RST (BIT(11)) +#define DPORT_LEDC_RST_M (BIT(11)) +#define DPORT_LEDC_RST_V 0x1 +#define DPORT_LEDC_RST_S 11 +/* DPORT_PCNT_RST : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PCNT_RST (BIT(10)) +#define DPORT_PCNT_RST_M (BIT(10)) +#define DPORT_PCNT_RST_V 0x1 +#define DPORT_PCNT_RST_S 10 +/* DPORT_RMT_RST : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_RMT_RST (BIT(9)) +#define DPORT_RMT_RST_M (BIT(9)) +#define DPORT_RMT_RST_V 0x1 +#define DPORT_RMT_RST_S 9 +/* DPORT_UHCI0_RST : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_UHCI0_RST (BIT(8)) +#define DPORT_UHCI0_RST_M (BIT(8)) +#define DPORT_UHCI0_RST_V 0x1 +#define DPORT_UHCI0_RST_S 8 +/* DPORT_I2C_EXT0_RST : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_I2C_EXT0_RST (BIT(7)) +#define DPORT_I2C_EXT0_RST_M (BIT(7)) +#define DPORT_I2C_EXT0_RST_V 0x1 +#define DPORT_I2C_EXT0_RST_S 7 +/* DPORT_SPI2_RST : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_SPI2_RST (BIT(6)) +#define DPORT_SPI2_RST_M (BIT(6)) +#define DPORT_SPI2_RST_V 0x1 +#define DPORT_SPI2_RST_S 6 +/* DPORT_UART1_RST : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_UART1_RST (BIT(5)) +#define DPORT_UART1_RST_M (BIT(5)) +#define DPORT_UART1_RST_V 0x1 +#define DPORT_UART1_RST_S 5 +/* DPORT_I2S0_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_I2S0_RST (BIT(4)) +#define DPORT_I2S0_RST_M (BIT(4)) +#define DPORT_I2S0_RST_V 0x1 +#define DPORT_I2S0_RST_S 4 +/* DPORT_WDG_RST : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_WDG_RST (BIT(3)) +#define DPORT_WDG_RST_M (BIT(3)) +#define DPORT_WDG_RST_V 0x1 +#define DPORT_WDG_RST_S 3 +/* DPORT_UART_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_UART_RST (BIT(2)) +#define DPORT_UART_RST_M (BIT(2)) +#define DPORT_UART_RST_V 0x1 +#define DPORT_UART_RST_S 2 +/* DPORT_SPI01_RST : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_SPI01_RST (BIT(1)) +#define DPORT_SPI01_RST_M (BIT(1)) +#define DPORT_SPI01_RST_V 0x1 +#define DPORT_SPI01_RST_S 1 +/* DPORT_TIMERS_RST : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_TIMERS_RST (BIT(0)) +#define DPORT_TIMERS_RST_M (BIT(0)) +#define DPORT_TIMERS_RST_V 0x1 +#define DPORT_TIMERS_RST_S 0 + +#define DPORT_CPU_PERIP_RST_EN1_REG DPORT_PERIP_RST_EN1_REG +#define DPORT_PERIP_RST_EN1_REG (DR_REG_SYSTEM_BASE + 0x04C) +/* DPORT_CRYPTO_DMA_RST : R/W ;bitpos:[6] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_CRYPTO_DMA_RST (BIT(6)) +#define DPORT_CRYPTO_DMA_RST_M (BIT(6)) +#define DPORT_CRYPTO_DMA_RST_V 0x1 +#define DPORT_CRYPTO_DMA_RST_S 6 +/* DPORT_CRYPTO_HMAC_RST : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_CRYPTO_HMAC_RST (BIT(5)) +#define DPORT_CRYPTO_HMAC_RST_M (BIT(5)) +#define DPORT_CRYPTO_HMAC_RST_V 0x1 +#define DPORT_CRYPTO_HMAC_RST_S 5 +/* DPORT_CRYPTO_DS_RST : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_CRYPTO_DS_RST (BIT(4)) +#define DPORT_CRYPTO_DS_RST_M (BIT(4)) +#define DPORT_CRYPTO_DS_RST_V 0x1 +#define DPORT_CRYPTO_DS_RST_S 4 +/* DPORT_CRYPTO_RSA_RST : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_CRYPTO_RSA_RST (BIT(3)) +#define DPORT_CRYPTO_RSA_RST_M (BIT(3)) +#define DPORT_CRYPTO_RSA_RST_V 0x1 +#define DPORT_CRYPTO_RSA_RST_S 3 +/* DPORT_CRYPTO_SHA_RST : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_CRYPTO_SHA_RST (BIT(2)) +#define DPORT_CRYPTO_SHA_RST_M (BIT(2)) +#define DPORT_CRYPTO_SHA_RST_V 0x1 +#define DPORT_CRYPTO_SHA_RST_S 2 +/* DPORT_CRYPTO_AES_RST : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_CRYPTO_AES_RST (BIT(1)) +#define DPORT_CRYPTO_AES_RST_M (BIT(1)) +#define DPORT_CRYPTO_AES_RST_V 0x1 +#define DPORT_CRYPTO_AES_RST_S 1 + +#define DPORT_BT_LPCK_DIV_INT_REG (DR_REG_SYSTEM_BASE + 0x050) +/* DPORT_BT_LPCK_DIV_NUM : R/W ;bitpos:[11:0] ;default: 12'd255 ; */ +/*description: */ +#define DPORT_BT_LPCK_DIV_NUM 0x00000FFF +#define DPORT_BT_LPCK_DIV_NUM_M ((DPORT_BT_LPCK_DIV_NUM_V)<<(DPORT_BT_LPCK_DIV_NUM_S)) +#define DPORT_BT_LPCK_DIV_NUM_V 0xFFF +#define DPORT_BT_LPCK_DIV_NUM_S 0 + +#define DPORT_BT_LPCK_DIV_FRAC_REG (DR_REG_SYSTEM_BASE + 0x054) +/* DPORT_LPCLK_RTC_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_LPCLK_RTC_EN (BIT(28)) +#define DPORT_LPCLK_RTC_EN_M (BIT(28)) +#define DPORT_LPCLK_RTC_EN_V 0x1 +#define DPORT_LPCLK_RTC_EN_S 28 +/* DPORT_LPCLK_SEL_XTAL32K : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_LPCLK_SEL_XTAL32K (BIT(27)) +#define DPORT_LPCLK_SEL_XTAL32K_M (BIT(27)) +#define DPORT_LPCLK_SEL_XTAL32K_V 0x1 +#define DPORT_LPCLK_SEL_XTAL32K_S 27 +/* DPORT_LPCLK_SEL_XTAL : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_LPCLK_SEL_XTAL (BIT(26)) +#define DPORT_LPCLK_SEL_XTAL_M (BIT(26)) +#define DPORT_LPCLK_SEL_XTAL_V 0x1 +#define DPORT_LPCLK_SEL_XTAL_S 26 +/* DPORT_LPCLK_SEL_8M : R/W ;bitpos:[25] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_LPCLK_SEL_8M (BIT(25)) +#define DPORT_LPCLK_SEL_8M_M (BIT(25)) +#define DPORT_LPCLK_SEL_8M_V 0x1 +#define DPORT_LPCLK_SEL_8M_S 25 +/* DPORT_LPCLK_SEL_RTC_SLOW : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_LPCLK_SEL_RTC_SLOW (BIT(24)) +#define DPORT_LPCLK_SEL_RTC_SLOW_M (BIT(24)) +#define DPORT_LPCLK_SEL_RTC_SLOW_V 0x1 +#define DPORT_LPCLK_SEL_RTC_SLOW_S 24 +/* DPORT_BT_LPCK_DIV_A : R/W ;bitpos:[23:12] ;default: 12'd1 ; */ +/*description: */ +#define DPORT_BT_LPCK_DIV_A 0x00000FFF +#define DPORT_BT_LPCK_DIV_A_M ((DPORT_BT_LPCK_DIV_A_V)<<(DPORT_BT_LPCK_DIV_A_S)) +#define DPORT_BT_LPCK_DIV_A_V 0xFFF +#define DPORT_BT_LPCK_DIV_A_S 12 +/* DPORT_BT_LPCK_DIV_B : R/W ;bitpos:[11:0] ;default: 12'd1 ; */ +/*description: */ +#define DPORT_BT_LPCK_DIV_B 0x00000FFF +#define DPORT_BT_LPCK_DIV_B_M ((DPORT_BT_LPCK_DIV_B_V)<<(DPORT_BT_LPCK_DIV_B_S)) +#define DPORT_BT_LPCK_DIV_B_V 0xFFF +#define DPORT_BT_LPCK_DIV_B_S 0 + +#define DPORT_CPU_INTR_FROM_CPU_0_REG (DR_REG_SYSTEM_BASE + 0x058) +/* DPORT_CPU_INTR_FROM_CPU_0 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_CPU_INTR_FROM_CPU_0 (BIT(0)) +#define DPORT_CPU_INTR_FROM_CPU_0_M (BIT(0)) +#define DPORT_CPU_INTR_FROM_CPU_0_V 0x1 +#define DPORT_CPU_INTR_FROM_CPU_0_S 0 + +#define DPORT_CPU_INTR_FROM_CPU_1_REG (DR_REG_SYSTEM_BASE + 0x05C) +/* DPORT_CPU_INTR_FROM_CPU_1 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_CPU_INTR_FROM_CPU_1 (BIT(0)) +#define DPORT_CPU_INTR_FROM_CPU_1_M (BIT(0)) +#define DPORT_CPU_INTR_FROM_CPU_1_V 0x1 +#define DPORT_CPU_INTR_FROM_CPU_1_S 0 + +#define DPORT_CPU_INTR_FROM_CPU_2_REG (DR_REG_SYSTEM_BASE + 0x060) +/* DPORT_CPU_INTR_FROM_CPU_2 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_CPU_INTR_FROM_CPU_2 (BIT(0)) +#define DPORT_CPU_INTR_FROM_CPU_2_M (BIT(0)) +#define DPORT_CPU_INTR_FROM_CPU_2_V 0x1 +#define DPORT_CPU_INTR_FROM_CPU_2_S 0 + +#define DPORT_CPU_INTR_FROM_CPU_3_REG (DR_REG_SYSTEM_BASE + 0x064) +/* DPORT_CPU_INTR_FROM_CPU_3 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_CPU_INTR_FROM_CPU_3 (BIT(0)) +#define DPORT_CPU_INTR_FROM_CPU_3_M (BIT(0)) +#define DPORT_CPU_INTR_FROM_CPU_3_V 0x1 +#define DPORT_CPU_INTR_FROM_CPU_3_S 0 + +#define DPORT_RSA_PD_CTRL_REG (DR_REG_SYSTEM_BASE + 0x068) +/* DPORT_RSA_MEM_FORCE_PD : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_RSA_MEM_FORCE_PD (BIT(2)) +#define DPORT_RSA_MEM_FORCE_PD_M (BIT(2)) +#define DPORT_RSA_MEM_FORCE_PD_V 0x1 +#define DPORT_RSA_MEM_FORCE_PD_S 2 +/* DPORT_RSA_MEM_FORCE_PU : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_RSA_MEM_FORCE_PU (BIT(1)) +#define DPORT_RSA_MEM_FORCE_PU_M (BIT(1)) +#define DPORT_RSA_MEM_FORCE_PU_V 0x1 +#define DPORT_RSA_MEM_FORCE_PU_S 1 +/* DPORT_RSA_MEM_PD : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_RSA_MEM_PD (BIT(0)) +#define DPORT_RSA_MEM_PD_M (BIT(0)) +#define DPORT_RSA_MEM_PD_V 0x1 +#define DPORT_RSA_MEM_PD_S 0 +#define DPORT_RSA_PD DPORT_RSA_MEM_PD + +#define DPORT_BUSTOEXTMEM_ENA_REG (DR_REG_SYSTEM_BASE + 0x06C) +/* DPORT_BUSTOEXTMEM_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_BUSTOEXTMEM_ENA (BIT(0)) +#define DPORT_BUSTOEXTMEM_ENA_M (BIT(0)) +#define DPORT_BUSTOEXTMEM_ENA_V 0x1 +#define DPORT_BUSTOEXTMEM_ENA_S 0 + +#define DPORT_CACHE_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x070) +/* DPORT_PRO_CACHE_RESET : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PRO_CACHE_RESET (BIT(2)) +#define DPORT_PRO_CACHE_RESET_M (BIT(2)) +#define DPORT_PRO_CACHE_RESET_V 0x1 +#define DPORT_PRO_CACHE_RESET_S 2 +/* DPORT_PRO_DCACHE_CLK_ON : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_PRO_DCACHE_CLK_ON (BIT(1)) +#define DPORT_PRO_DCACHE_CLK_ON_M (BIT(1)) +#define DPORT_PRO_DCACHE_CLK_ON_V 0x1 +#define DPORT_PRO_DCACHE_CLK_ON_S 1 +/* DPORT_PRO_ICACHE_CLK_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_PRO_ICACHE_CLK_ON (BIT(0)) +#define DPORT_PRO_ICACHE_CLK_ON_M (BIT(0)) +#define DPORT_PRO_ICACHE_CLK_ON_V 0x1 +#define DPORT_PRO_ICACHE_CLK_ON_S 0 + +#define DPORT_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x074) +/* DPORT_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_ENABLE_DOWNLOAD_MANUAL_ENCRYPT (BIT(3)) +#define DPORT_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_M (BIT(3)) +#define DPORT_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V 0x1 +#define DPORT_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S 3 +/* DPORT_ENABLE_DOWNLOAD_G0CB_DECRYPT : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_ENABLE_DOWNLOAD_G0CB_DECRYPT (BIT(2)) +#define DPORT_ENABLE_DOWNLOAD_G0CB_DECRYPT_M (BIT(2)) +#define DPORT_ENABLE_DOWNLOAD_G0CB_DECRYPT_V 0x1 +#define DPORT_ENABLE_DOWNLOAD_G0CB_DECRYPT_S 2 +/* DPORT_ENABLE_DOWNLOAD_DB_ENCRYPT : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_ENABLE_DOWNLOAD_DB_ENCRYPT (BIT(1)) +#define DPORT_ENABLE_DOWNLOAD_DB_ENCRYPT_M (BIT(1)) +#define DPORT_ENABLE_DOWNLOAD_DB_ENCRYPT_V 0x1 +#define DPORT_ENABLE_DOWNLOAD_DB_ENCRYPT_S 1 +/* DPORT_ENABLE_SPI_MANUAL_ENCRYPT : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_ENABLE_SPI_MANUAL_ENCRYPT (BIT(0)) +#define DPORT_ENABLE_SPI_MANUAL_ENCRYPT_M (BIT(0)) +#define DPORT_ENABLE_SPI_MANUAL_ENCRYPT_V 0x1 +#define DPORT_ENABLE_SPI_MANUAL_ENCRYPT_S 0 + +#define DPORT_RTC_FASTMEM_CONFIG_REG (DR_REG_SYSTEM_BASE + 0x078) +/* DPORT_RTC_MEM_CRC_FINISH : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_RTC_MEM_CRC_FINISH (BIT(31)) +#define DPORT_RTC_MEM_CRC_FINISH_M (BIT(31)) +#define DPORT_RTC_MEM_CRC_FINISH_V 0x1 +#define DPORT_RTC_MEM_CRC_FINISH_S 31 +/* DPORT_RTC_MEM_CRC_LEN : R/W ;bitpos:[30:20] ;default: 11'h7ff ; */ +/*description: */ +#define DPORT_RTC_MEM_CRC_LEN 0x000007FF +#define DPORT_RTC_MEM_CRC_LEN_M ((DPORT_RTC_MEM_CRC_LEN_V)<<(DPORT_RTC_MEM_CRC_LEN_S)) +#define DPORT_RTC_MEM_CRC_LEN_V 0x7FF +#define DPORT_RTC_MEM_CRC_LEN_S 20 +/* DPORT_RTC_MEM_CRC_ADDR : R/W ;bitpos:[19:9] ;default: 11'h0 ; */ +/*description: */ +#define DPORT_RTC_MEM_CRC_ADDR 0x000007FF +#define DPORT_RTC_MEM_CRC_ADDR_M ((DPORT_RTC_MEM_CRC_ADDR_V)<<(DPORT_RTC_MEM_CRC_ADDR_S)) +#define DPORT_RTC_MEM_CRC_ADDR_V 0x7FF +#define DPORT_RTC_MEM_CRC_ADDR_S 9 +/* DPORT_RTC_MEM_CRC_START : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_RTC_MEM_CRC_START (BIT(8)) +#define DPORT_RTC_MEM_CRC_START_M (BIT(8)) +#define DPORT_RTC_MEM_CRC_START_V 0x1 +#define DPORT_RTC_MEM_CRC_START_S 8 + +#define DPORT_RTC_FASTMEM_CRC_REG (DR_REG_SYSTEM_BASE + 0x07C) +/* DPORT_RTC_MEM_CRC_RES : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define DPORT_RTC_MEM_CRC_RES 0xFFFFFFFF +#define DPORT_RTC_MEM_CRC_RES_M ((DPORT_RTC_MEM_CRC_RES_V)<<(DPORT_RTC_MEM_CRC_RES_S)) +#define DPORT_RTC_MEM_CRC_RES_V 0xFFFFFFFF +#define DPORT_RTC_MEM_CRC_RES_S 0 + +#define DPORT_REDUNDANT_ECO_CTRL_REG (DR_REG_SYSTEM_BASE + 0x080) +/* DPORT_REDUNDANT_ECO_RESULT : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_REDUNDANT_ECO_RESULT (BIT(1)) +#define DPORT_REDUNDANT_ECO_RESULT_M (BIT(1)) +#define DPORT_REDUNDANT_ECO_RESULT_V 0x1 +#define DPORT_REDUNDANT_ECO_RESULT_S 1 +/* DPORT_REDUNDANT_ECO_DRIVE : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_REDUNDANT_ECO_DRIVE (BIT(0)) +#define DPORT_REDUNDANT_ECO_DRIVE_M (BIT(0)) +#define DPORT_REDUNDANT_ECO_DRIVE_V 0x1 +#define DPORT_REDUNDANT_ECO_DRIVE_S 0 + +#define SYSTEM_CLOCK_GATE_REG (DR_REG_SYSTEM_BASE + 0x084) +/* SYSTEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_CLK_EN (BIT(0)) +#define SYSTEM_CLK_EN_M (BIT(0)) +#define SYSTEM_CLK_EN_V 0x1 +#define SYSTEM_CLK_EN_S 0 + +#define DPORT_SRAM_CTRL_2_REG (DR_REG_SYSTEM_BASE + 0x088) +/* DPORT_SRAM_FORCE_PU : R/W ;bitpos:[21:0] ;default: 22'h3fffff ; */ +/*description: */ +#define DPORT_SRAM_FORCE_PU 0x003FFFFF +#define DPORT_SRAM_FORCE_PU_M ((DPORT_SRAM_FORCE_PU_V)<<(DPORT_SRAM_FORCE_PU_S)) +#define DPORT_SRAM_FORCE_PU_V 0x3FFFFF +#define DPORT_SRAM_FORCE_PU_S 0 + +#define DPORT_SYSCLK_CONF_REG (DR_REG_SYSTEM_BASE + 0x08C) +/* DPORT_CLK_DIV_EN : RO ;bitpos:[19] ;default: 1'd0 ; */ +/*description: */ +#define DPORT_CLK_DIV_EN (BIT(19)) +#define DPORT_CLK_DIV_EN_M (BIT(19)) +#define DPORT_CLK_DIV_EN_V 0x1 +#define DPORT_CLK_DIV_EN_S 19 +/* DPORT_CLK_XTAL_FREQ : RO ;bitpos:[18:12] ;default: 7'd0 ; */ +/*description: */ +#define DPORT_CLK_XTAL_FREQ 0x0000007F +#define DPORT_CLK_XTAL_FREQ_M ((DPORT_CLK_XTAL_FREQ_V)<<(DPORT_CLK_XTAL_FREQ_S)) +#define DPORT_CLK_XTAL_FREQ_V 0x7F +#define DPORT_CLK_XTAL_FREQ_S 12 +/* DPORT_SOC_CLK_SEL : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ +/*description: */ +#define DPORT_SOC_CLK_SEL 0x00000003 +#define DPORT_SOC_CLK_SEL_M ((DPORT_SOC_CLK_SEL_V)<<(DPORT_SOC_CLK_SEL_S)) +#define DPORT_SOC_CLK_SEL_V 0x3 +#define DPORT_SOC_CLK_SEL_S 10 +/* DPORT_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */ +/*description: */ +#define DPORT_PRE_DIV_CNT 0x000003FF +#define DPORT_PRE_DIV_CNT_M ((DPORT_PRE_DIV_CNT_V)<<(DPORT_PRE_DIV_CNT_S)) +#define DPORT_PRE_DIV_CNT_V 0x3FF +#define DPORT_PRE_DIV_CNT_S 0 + +#define SYSTEM_DATE_REG (DR_REG_SYSTEM_BASE + 0xFFC) +/* SYSTEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h1908020 ; */ +/*description: */ +#define SYSTEM_DATE 0x0FFFFFFF +#define SYSTEM_DATE_M ((SYSTEM_DATE_V)<<(SYSTEM_DATE_S)) +#define SYSTEM_DATE_V 0xFFFFFFF +#define SYSTEM_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/src/target/esp32s2/ld/esp32s2.rom.api.ld b/src/target/esp32s2/ld/esp32s2.rom.api.ld index 42d03b8..dc5e631 100644 --- a/src/target/esp32s2/ld/esp32s2.rom.api.ld +++ b/src/target/esp32s2/ld/esp32s2.rom.api.ld @@ -31,10 +31,11 @@ PROVIDE ( esp_rom_uart_switch_buffer = uart_buff_switch ); PROVIDE ( esp_rom_uart_attach = uartAttach ); PROVIDE ( esp_rom_uart_init = Uart_Init ); PROVIDE ( esp_rom_uart_div_modify = uart_div_modify ); -PROVIDE ( esp_rom_get_apb_freq = ets_get_apb_freq ); PROVIDE ( esp_rom_uart_tx_switch = uart_tx_switch ); PROVIDE ( esp_rom_update_cpu_frequency = ets_update_cpu_frequency ); PROVIDE ( esp_rom_get_uart_device = GetUartDevice ); +PROVIDE ( esp_rom_get_xtal_frequency = ets_get_xtal_freq ); +PROVIDE ( esp_rom_get_apb_frequency = ets_get_apb_freq ); PROVIDE ( esp_rom_output_flush_tx = uart_tx_flush ); PROVIDE ( esp_rom_output_tx_one_char = uart_tx_one_char ); diff --git a/src/target/esp32s2/src/clock.c b/src/target/esp32s2/src/clock.c new file mode 100644 index 0000000..d86e23d --- /dev/null +++ b/src/target/esp32s2/src/clock.c @@ -0,0 +1,47 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 OR MIT + */ + +#include +#include +#include +#include +#include +#include +#include + +#define MHZ 1000000 + +extern void esp_rom_set_cpu_ticks_per_us(uint32_t ticks_per_us); +extern uint32_t esp_rom_get_cpu_ticks_per_us(void); +extern uint32_t esp_rom_get_apb_frequency(void); + +static uint32_t s_cpu_freq = 0; + +void stub_target_clock_init(void) +{ + + REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_1V20); + REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_1V20); + + REG_SET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_SOC_CLK_SEL, 1); + REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_PLL_FREQ_SEL, 1); + REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 2); + s_cpu_freq = 240 * MHZ; + esp_rom_set_cpu_ticks_per_us(s_cpu_freq / MHZ); +} + +uint32_t stub_target_get_cpu_freq(void) +{ + if (s_cpu_freq == 0) { + return esp_rom_get_cpu_ticks_per_us() * MHZ; + } + return s_cpu_freq; +} + +uint32_t stub_target_get_apb_freq(void) +{ + return esp_rom_get_apb_frequency(); +} diff --git a/src/target/esp32s2/src/uart.c b/src/target/esp32s2/src/uart.c index 3168ce2..13f4880 100644 --- a/src/target/esp32s2/src/uart.c +++ b/src/target/esp32s2/src/uart.c @@ -8,13 +8,13 @@ #include #include #include +#include +#include #include #include // These functions are defined in the ROM extern void esp_rom_uart_attach(void *rxBuffer); -extern uint32_t esp_rom_get_apb_freq(void); -extern void esp_rom_update_cpu_frequency(uint32_t ticks_per_us); extern void esp_rom_uart_init(uint8_t uart_no, uint32_t clock); extern void esp_rom_uart_tx_switch(uint8_t uart_no); extern void esp_rom_uart_div_modify(uint8_t uart_no, uint32_t divisor); @@ -33,17 +33,19 @@ void stub_target_rom_uart_init(uint8_t uart_no, uint32_t clock) void stub_target_uart_init(uint8_t uart_num) { - esp_rom_update_cpu_frequency(esp_rom_get_apb_freq() / 1000000); stub_target_rom_uart_attach(NULL); - stub_target_rom_uart_init(uart_num, esp_rom_get_apb_freq()); + uint32_t clock = stub_target_get_apb_freq(); + stub_target_rom_uart_init(uart_num, clock); esp_rom_uart_tx_switch(uart_num); } void stub_target_uart_rominit_set_baudrate(uint8_t uart_num, uint32_t baudrate) { - uint32_t clock = esp_rom_get_apb_freq(); - uint32_t divisor = clock / baudrate; + stub_lib_delay_us(5 * 1000); + + uint32_t clk_div = (stub_target_get_apb_freq() << 4) / baudrate; stub_target_uart_wait_idle(uart_num); - esp_rom_uart_div_modify(uart_num, divisor); - // TODO: Consider decimal part + esp_rom_uart_div_modify(uart_num, clk_div); + + stub_lib_delay_us(5 * 1000); } diff --git a/src/target/esp32s3/CMakeLists.txt b/src/target/esp32s3/CMakeLists.txt index 857528d..654581a 100644 --- a/src/target/esp32s3/CMakeLists.txt +++ b/src/target/esp32s3/CMakeLists.txt @@ -3,6 +3,7 @@ set(srcs src/trax.c src/uart.c src/usb_serial_jtag.c + src/clock.c ) add_library(${ESP_TARGET_LIB} STATIC ${srcs}) diff --git a/src/target/esp32s3/include/soc/rtc_cntl_reg.h b/src/target/esp32s3/include/soc/rtc_cntl_reg.h new file mode 100644 index 0000000..62b67d4 --- /dev/null +++ b/src/target/esp32s3/include/soc/rtc_cntl_reg.h @@ -0,0 +1,3698 @@ +/* + * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 OR MIT + */ + +#ifndef _SOC_RTC_CNTL_REG_H_ +#define _SOC_RTC_CNTL_REG_H_ + +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* The value that needs to be written to RTC_CNTL_SWD_WPROTECT_REG to write-enable the wdt registers */ +#define RTC_CNTL_SWD_WKEY_VALUE 0x8F1D312A + +#define RTC_CNTL_TIME0_REG RTC_CNTL_TIME_LOW0_REG +#define RTC_CNTL_TIME1_REG RTC_CNTL_TIME_HIGH0_REG + +#define RTC_CNTL_OPTIONS0_REG (DR_REG_RTCCNTL_BASE + 0x0) +/* RTC_CNTL_SW_SYS_RST : WO ;bitpos:[31] ;default: 1'd0 ; */ +/*description: SW system reset.*/ +#define RTC_CNTL_SW_SYS_RST (BIT(31)) +#define RTC_CNTL_SW_SYS_RST_M (BIT(31)) +#define RTC_CNTL_SW_SYS_RST_V 0x1 +#define RTC_CNTL_SW_SYS_RST_S 31 +/* RTC_CNTL_DG_WRAP_FORCE_NORST : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: digital core force no reset in deep sleep.*/ +#define RTC_CNTL_DG_WRAP_FORCE_NORST (BIT(30)) +#define RTC_CNTL_DG_WRAP_FORCE_NORST_M (BIT(30)) +#define RTC_CNTL_DG_WRAP_FORCE_NORST_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_NORST_S 30 +/* RTC_CNTL_DG_WRAP_FORCE_RST : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: digital wrap force reset in deep sleep.*/ +#define RTC_CNTL_DG_WRAP_FORCE_RST (BIT(29)) +#define RTC_CNTL_DG_WRAP_FORCE_RST_M (BIT(29)) +#define RTC_CNTL_DG_WRAP_FORCE_RST_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_RST_S 29 +/* RTC_CNTL_ANALOG_FORCE_NOISO : R/W ;bitpos:[28] ;default: 1'd1 ; */ +/*description: .*/ +#define RTC_CNTL_ANALOG_FORCE_NOISO (BIT(28)) +#define RTC_CNTL_ANALOG_FORCE_NOISO_M (BIT(28)) +#define RTC_CNTL_ANALOG_FORCE_NOISO_V 0x1 +#define RTC_CNTL_ANALOG_FORCE_NOISO_S 28 +/* RTC_CNTL_PLL_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */ +/*description: .*/ +#define RTC_CNTL_PLL_FORCE_NOISO (BIT(27)) +#define RTC_CNTL_PLL_FORCE_NOISO_M (BIT(27)) +#define RTC_CNTL_PLL_FORCE_NOISO_V 0x1 +#define RTC_CNTL_PLL_FORCE_NOISO_S 27 +/* RTC_CNTL_XTL_FORCE_NOISO : R/W ;bitpos:[26] ;default: 1'd1 ; */ +/*description: .*/ +#define RTC_CNTL_XTL_FORCE_NOISO (BIT(26)) +#define RTC_CNTL_XTL_FORCE_NOISO_M (BIT(26)) +#define RTC_CNTL_XTL_FORCE_NOISO_V 0x1 +#define RTC_CNTL_XTL_FORCE_NOISO_S 26 +/* RTC_CNTL_ANALOG_FORCE_ISO : R/W ;bitpos:[25] ;default: 1'd0 ; */ +/*description: .*/ +#define RTC_CNTL_ANALOG_FORCE_ISO (BIT(25)) +#define RTC_CNTL_ANALOG_FORCE_ISO_M (BIT(25)) +#define RTC_CNTL_ANALOG_FORCE_ISO_V 0x1 +#define RTC_CNTL_ANALOG_FORCE_ISO_S 25 +/* RTC_CNTL_PLL_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */ +/*description: .*/ +#define RTC_CNTL_PLL_FORCE_ISO (BIT(24)) +#define RTC_CNTL_PLL_FORCE_ISO_M (BIT(24)) +#define RTC_CNTL_PLL_FORCE_ISO_V 0x1 +#define RTC_CNTL_PLL_FORCE_ISO_S 24 +/* RTC_CNTL_XTL_FORCE_ISO : R/W ;bitpos:[23] ;default: 1'd0 ; */ +/*description: .*/ +#define RTC_CNTL_XTL_FORCE_ISO (BIT(23)) +#define RTC_CNTL_XTL_FORCE_ISO_M (BIT(23)) +#define RTC_CNTL_XTL_FORCE_ISO_V 0x1 +#define RTC_CNTL_XTL_FORCE_ISO_S 23 +/* RTC_CNTL_XTL_EN_WAIT : R/W ;bitpos:[17:14] ;default: 4'd2 ; */ +/*description: wait bias_sleep and current source wakeup.*/ +#define RTC_CNTL_XTL_EN_WAIT 0x0000000F +#define RTC_CNTL_XTL_EN_WAIT_M ((RTC_CNTL_XTL_EN_WAIT_V)<<(RTC_CNTL_XTL_EN_WAIT_S)) +#define RTC_CNTL_XTL_EN_WAIT_V 0xF +#define RTC_CNTL_XTL_EN_WAIT_S 14 +/* RTC_CNTL_XTL_FORCE_PU : R/W ;bitpos:[13] ;default: 1'd1 ; */ +/*description: crystall force power up.*/ +#define RTC_CNTL_XTL_FORCE_PU (BIT(13)) +#define RTC_CNTL_XTL_FORCE_PU_M (BIT(13)) +#define RTC_CNTL_XTL_FORCE_PU_V 0x1 +#define RTC_CNTL_XTL_FORCE_PU_S 13 +/* RTC_CNTL_XTL_FORCE_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: crystall force power down.*/ +#define RTC_CNTL_XTL_FORCE_PD (BIT(12)) +#define RTC_CNTL_XTL_FORCE_PD_M (BIT(12)) +#define RTC_CNTL_XTL_FORCE_PD_V 0x1 +#define RTC_CNTL_XTL_FORCE_PD_S 12 +/* RTC_CNTL_BBPLL_FORCE_PU : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: BB_PLL force power up.*/ +#define RTC_CNTL_BBPLL_FORCE_PU (BIT(11)) +#define RTC_CNTL_BBPLL_FORCE_PU_M (BIT(11)) +#define RTC_CNTL_BBPLL_FORCE_PU_V 0x1 +#define RTC_CNTL_BBPLL_FORCE_PU_S 11 +/* RTC_CNTL_BBPLL_FORCE_PD : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: BB_PLL force power down.*/ +#define RTC_CNTL_BBPLL_FORCE_PD (BIT(10)) +#define RTC_CNTL_BBPLL_FORCE_PD_M (BIT(10)) +#define RTC_CNTL_BBPLL_FORCE_PD_V 0x1 +#define RTC_CNTL_BBPLL_FORCE_PD_S 10 +/* RTC_CNTL_BBPLL_I2C_FORCE_PU : R/W ;bitpos:[9] ;default: 1'd0 ; */ +/*description: BB_PLL_I2C force power up.*/ +#define RTC_CNTL_BBPLL_I2C_FORCE_PU (BIT(9)) +#define RTC_CNTL_BBPLL_I2C_FORCE_PU_M (BIT(9)) +#define RTC_CNTL_BBPLL_I2C_FORCE_PU_V 0x1 +#define RTC_CNTL_BBPLL_I2C_FORCE_PU_S 9 +/* RTC_CNTL_BBPLL_I2C_FORCE_PD : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: BB_PLL _I2C force power down.*/ +#define RTC_CNTL_BBPLL_I2C_FORCE_PD (BIT(8)) +#define RTC_CNTL_BBPLL_I2C_FORCE_PD_M (BIT(8)) +#define RTC_CNTL_BBPLL_I2C_FORCE_PD_V 0x1 +#define RTC_CNTL_BBPLL_I2C_FORCE_PD_S 8 +/* RTC_CNTL_BB_I2C_FORCE_PU : R/W ;bitpos:[7] ;default: 1'd0 ; */ +/*description: BB_I2C force power up.*/ +#define RTC_CNTL_BB_I2C_FORCE_PU (BIT(7)) +#define RTC_CNTL_BB_I2C_FORCE_PU_M (BIT(7)) +#define RTC_CNTL_BB_I2C_FORCE_PU_V 0x1 +#define RTC_CNTL_BB_I2C_FORCE_PU_S 7 +/* RTC_CNTL_BB_I2C_FORCE_PD : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: BB_I2C force power down.*/ +#define RTC_CNTL_BB_I2C_FORCE_PD (BIT(6)) +#define RTC_CNTL_BB_I2C_FORCE_PD_M (BIT(6)) +#define RTC_CNTL_BB_I2C_FORCE_PD_V 0x1 +#define RTC_CNTL_BB_I2C_FORCE_PD_S 6 +/* RTC_CNTL_SW_PROCPU_RST : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: PRO CPU SW reset.*/ +#define RTC_CNTL_SW_PROCPU_RST (BIT(5)) +#define RTC_CNTL_SW_PROCPU_RST_M (BIT(5)) +#define RTC_CNTL_SW_PROCPU_RST_V 0x1 +#define RTC_CNTL_SW_PROCPU_RST_S 5 +/* RTC_CNTL_SW_APPCPU_RST : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: APP CPU SW reset.*/ +#define RTC_CNTL_SW_APPCPU_RST (BIT(4)) +#define RTC_CNTL_SW_APPCPU_RST_M (BIT(4)) +#define RTC_CNTL_SW_APPCPU_RST_V 0x1 +#define RTC_CNTL_SW_APPCPU_RST_S 4 +/* RTC_CNTL_SW_STALL_PROCPU_C0 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */ +/*description: {reg_sw_stall_procpu_c1[5:0], reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall P +RO CPU.*/ +#define RTC_CNTL_SW_STALL_PROCPU_C0 0x00000003 +#define RTC_CNTL_SW_STALL_PROCPU_C0_M ((RTC_CNTL_SW_STALL_PROCPU_C0_V)<<(RTC_CNTL_SW_STALL_PROCPU_C0_S)) +#define RTC_CNTL_SW_STALL_PROCPU_C0_V 0x3 +#define RTC_CNTL_SW_STALL_PROCPU_C0_S 2 +/* RTC_CNTL_SW_STALL_APPCPU_C0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: {reg_sw_stall_appcpu_c1[5:0], reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall A +PP CPU.*/ +#define RTC_CNTL_SW_STALL_APPCPU_C0 0x00000003 +#define RTC_CNTL_SW_STALL_APPCPU_C0_M ((RTC_CNTL_SW_STALL_APPCPU_C0_V)<<(RTC_CNTL_SW_STALL_APPCPU_C0_S)) +#define RTC_CNTL_SW_STALL_APPCPU_C0_V 0x3 +#define RTC_CNTL_SW_STALL_APPCPU_C0_S 0 + +#define RTC_CNTL_SLP_TIMER0_REG (DR_REG_RTCCNTL_BASE + 0x4) +/* RTC_CNTL_SLP_VAL_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define RTC_CNTL_SLP_VAL_LO 0xFFFFFFFF +#define RTC_CNTL_SLP_VAL_LO_M ((RTC_CNTL_SLP_VAL_LO_V)<<(RTC_CNTL_SLP_VAL_LO_S)) +#define RTC_CNTL_SLP_VAL_LO_V 0xFFFFFFFF +#define RTC_CNTL_SLP_VAL_LO_S 0 + +#define RTC_CNTL_SLP_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x8) +/* RTC_CNTL_MAIN_TIMER_ALARM_EN : WO ;bitpos:[16] ;default: 1'h0 ; */ +/*description: timer alarm enable bit.*/ +#define RTC_CNTL_MAIN_TIMER_ALARM_EN (BIT(16)) +#define RTC_CNTL_MAIN_TIMER_ALARM_EN_M (BIT(16)) +#define RTC_CNTL_MAIN_TIMER_ALARM_EN_V 0x1 +#define RTC_CNTL_MAIN_TIMER_ALARM_EN_S 16 +/* RTC_CNTL_SLP_VAL_HI : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: RTC sleep timer high 16 bits.*/ +#define RTC_CNTL_SLP_VAL_HI 0x0000FFFF +#define RTC_CNTL_SLP_VAL_HI_M ((RTC_CNTL_SLP_VAL_HI_V)<<(RTC_CNTL_SLP_VAL_HI_S)) +#define RTC_CNTL_SLP_VAL_HI_V 0xFFFF +#define RTC_CNTL_SLP_VAL_HI_S 0 + +#define RTC_CNTL_TIME_UPDATE_REG (DR_REG_RTCCNTL_BASE + 0xC) +/* RTC_CNTL_TIME_UPDATE : WO ;bitpos:[31] ;default: 1'h0 ; */ +/*description: Set 1: to update register with RTC timer.*/ +#define RTC_CNTL_TIME_UPDATE (BIT(31)) +#define RTC_CNTL_TIME_UPDATE_M (BIT(31)) +#define RTC_CNTL_TIME_UPDATE_V 0x1 +#define RTC_CNTL_TIME_UPDATE_S 31 +/* RTC_CNTL_TIMER_SYS_RST : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: enable to record system reset time.*/ +#define RTC_CNTL_TIMER_SYS_RST (BIT(29)) +#define RTC_CNTL_TIMER_SYS_RST_M (BIT(29)) +#define RTC_CNTL_TIMER_SYS_RST_V 0x1 +#define RTC_CNTL_TIMER_SYS_RST_S 29 +/* RTC_CNTL_TIMER_XTL_OFF : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: Enable to record 40M XTAL OFF time.*/ +#define RTC_CNTL_TIMER_XTL_OFF (BIT(28)) +#define RTC_CNTL_TIMER_XTL_OFF_M (BIT(28)) +#define RTC_CNTL_TIMER_XTL_OFF_V 0x1 +#define RTC_CNTL_TIMER_XTL_OFF_S 28 +/* RTC_CNTL_TIMER_SYS_STALL : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: Enable to record system stall time.*/ +#define RTC_CNTL_TIMER_SYS_STALL (BIT(27)) +#define RTC_CNTL_TIMER_SYS_STALL_M (BIT(27)) +#define RTC_CNTL_TIMER_SYS_STALL_V 0x1 +#define RTC_CNTL_TIMER_SYS_STALL_S 27 + +#define RTC_CNTL_TIME_LOW0_REG (DR_REG_RTCCNTL_BASE + 0x10) +/* RTC_CNTL_TIMER_VALUE0_LOW : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: RTC timer low 32 bits.*/ +#define RTC_CNTL_TIMER_VALUE0_LOW 0xFFFFFFFF +#define RTC_CNTL_TIMER_VALUE0_LOW_M ((RTC_CNTL_TIMER_VALUE0_LOW_V)<<(RTC_CNTL_TIMER_VALUE0_LOW_S)) +#define RTC_CNTL_TIMER_VALUE0_LOW_V 0xFFFFFFFF +#define RTC_CNTL_TIMER_VALUE0_LOW_S 0 + +#define RTC_CNTL_TIME_HIGH0_REG (DR_REG_RTCCNTL_BASE + 0x14) +/* RTC_CNTL_TIMER_VALUE0_HIGH : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: RTC timer high 16 bits.*/ +#define RTC_CNTL_TIMER_VALUE0_HIGH 0x0000FFFF +#define RTC_CNTL_TIMER_VALUE0_HIGH_M ((RTC_CNTL_TIMER_VALUE0_HIGH_V)<<(RTC_CNTL_TIMER_VALUE0_HIGH_S)) +#define RTC_CNTL_TIMER_VALUE0_HIGH_V 0xFFFF +#define RTC_CNTL_TIMER_VALUE0_HIGH_S 0 + +#define RTC_CNTL_STATE0_REG (DR_REG_RTCCNTL_BASE + 0x18) +/* RTC_CNTL_SLEEP_EN : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: sleep enable bit.*/ +#define RTC_CNTL_SLEEP_EN (BIT(31)) +#define RTC_CNTL_SLEEP_EN_M (BIT(31)) +#define RTC_CNTL_SLEEP_EN_V 0x1 +#define RTC_CNTL_SLEEP_EN_S 31 +/* RTC_CNTL_SLP_REJECT : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: leep reject bit.*/ +#define RTC_CNTL_SLP_REJECT (BIT(30)) +#define RTC_CNTL_SLP_REJECT_M (BIT(30)) +#define RTC_CNTL_SLP_REJECT_V 0x1 +#define RTC_CNTL_SLP_REJECT_S 30 +/* RTC_CNTL_SLP_WAKEUP : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: leep wakeup bit.*/ +#define RTC_CNTL_SLP_WAKEUP (BIT(29)) +#define RTC_CNTL_SLP_WAKEUP_M (BIT(29)) +#define RTC_CNTL_SLP_WAKEUP_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_S 29 +/* RTC_CNTL_SDIO_ACTIVE_IND : RO ;bitpos:[28] ;default: 1'd0 ; */ +/*description: SDIO active indication.*/ +#define RTC_CNTL_SDIO_ACTIVE_IND (BIT(28)) +#define RTC_CNTL_SDIO_ACTIVE_IND_M (BIT(28)) +#define RTC_CNTL_SDIO_ACTIVE_IND_V 0x1 +#define RTC_CNTL_SDIO_ACTIVE_IND_S 28 +/* RTC_CNTL_APB2RTC_BRIDGE_SEL : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: 1: APB to RTC using bridge.*/ +#define RTC_CNTL_APB2RTC_BRIDGE_SEL (BIT(22)) +#define RTC_CNTL_APB2RTC_BRIDGE_SEL_M (BIT(22)) +#define RTC_CNTL_APB2RTC_BRIDGE_SEL_V 0x1 +#define RTC_CNTL_APB2RTC_BRIDGE_SEL_S 22 +/* RTC_CNTL_SLP_REJECT_CAUSE_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: clear rtc sleep reject cause.*/ +#define RTC_CNTL_SLP_REJECT_CAUSE_CLR (BIT(1)) +#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_V 0x1 +#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_S 1 +/* RTC_CNTL_SW_CPU_INT : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: rtc software interrupt to main cpu.*/ +#define RTC_CNTL_SW_CPU_INT (BIT(0)) +#define RTC_CNTL_SW_CPU_INT_M (BIT(0)) +#define RTC_CNTL_SW_CPU_INT_V 0x1 +#define RTC_CNTL_SW_CPU_INT_S 0 + +#define RTC_CNTL_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x1C) +/* RTC_CNTL_PLL_BUF_WAIT : R/W ;bitpos:[31:24] ;default: 8'd40 ; */ +/*description: PLL wait cycles in slow_clk_rtc.*/ +#define RTC_CNTL_PLL_BUF_WAIT 0x000000FF +#define RTC_CNTL_PLL_BUF_WAIT_M ((RTC_CNTL_PLL_BUF_WAIT_V)<<(RTC_CNTL_PLL_BUF_WAIT_S)) +#define RTC_CNTL_PLL_BUF_WAIT_V 0xFF +#define RTC_CNTL_PLL_BUF_WAIT_S 24 +/* RTC_CNTL_XTL_BUF_WAIT : R/W ;bitpos:[23:14] ;default: 10'd80 ; */ +/*description: XTAL wait cycles in slow_clk_rtc.*/ +#define RTC_CNTL_XTL_BUF_WAIT 0x000003FF +#define RTC_CNTL_XTL_BUF_WAIT_M ((RTC_CNTL_XTL_BUF_WAIT_V)<<(RTC_CNTL_XTL_BUF_WAIT_S)) +#define RTC_CNTL_XTL_BUF_WAIT_V 0x3FF +#define RTC_CNTL_XTL_BUF_WAIT_S 14 +/* RTC_CNTL_CK8M_WAIT : R/W ;bitpos:[13:6] ;default: 8'h10 ; */ +/*description: CK8M wait cycles in slow_clk_rtc.*/ +#define RTC_CNTL_CK8M_WAIT 0x000000FF +#define RTC_CNTL_CK8M_WAIT_M ((RTC_CNTL_CK8M_WAIT_V)<<(RTC_CNTL_CK8M_WAIT_S)) +#define RTC_CNTL_CK8M_WAIT_V 0xFF +#define RTC_CNTL_CK8M_WAIT_S 6 +/* RTC_CNTL_CPU_STALL_WAIT : R/W ;bitpos:[5:1] ;default: 5'd1 ; */ +/*description: CPU stall wait cycles in fast_clk_rtc.*/ +#define RTC_CNTL_CPU_STALL_WAIT 0x0000001F +#define RTC_CNTL_CPU_STALL_WAIT_M ((RTC_CNTL_CPU_STALL_WAIT_V)<<(RTC_CNTL_CPU_STALL_WAIT_S)) +#define RTC_CNTL_CPU_STALL_WAIT_V 0x1F +#define RTC_CNTL_CPU_STALL_WAIT_S 1 +/* RTC_CNTL_CPU_STALL_EN : R/W ;bitpos:[0] ;default: 1'd1 ; */ +/*description: CPU stall enable bit.*/ +#define RTC_CNTL_CPU_STALL_EN (BIT(0)) +#define RTC_CNTL_CPU_STALL_EN_M (BIT(0)) +#define RTC_CNTL_CPU_STALL_EN_V 0x1 +#define RTC_CNTL_CPU_STALL_EN_S 0 + +#define RTC_CNTL_TIMER2_REG (DR_REG_RTCCNTL_BASE + 0x20) +/* RTC_CNTL_MIN_TIME_CK8M_OFF : R/W ;bitpos:[31:24] ;default: 8'h1 ; */ +/*description: minimal cycles in slow_clk_rtc for CK8M in power down state.*/ +#define RTC_CNTL_MIN_TIME_CK8M_OFF 0x000000FF +#define RTC_CNTL_MIN_TIME_CK8M_OFF_M ((RTC_CNTL_MIN_TIME_CK8M_OFF_V)<<(RTC_CNTL_MIN_TIME_CK8M_OFF_S)) +#define RTC_CNTL_MIN_TIME_CK8M_OFF_V 0xFF +#define RTC_CNTL_MIN_TIME_CK8M_OFF_S 24 +/* RTC_CNTL_ULPCP_TOUCH_START_WAIT : R/W ;bitpos:[23:15] ;default: 9'h10 ; */ +/*description: wait cycles in slow_clk_rtc before ULP-coprocessor / touch controller start to w +ork.*/ +#define RTC_CNTL_ULPCP_TOUCH_START_WAIT 0x000001FF +#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_M ((RTC_CNTL_ULPCP_TOUCH_START_WAIT_V)<<(RTC_CNTL_ULPCP_TOUCH_START_WAIT_S)) +#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_V 0x1FF +#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_S 15 + +#define RTC_CNTL_TIMER3_REG (DR_REG_RTCCNTL_BASE + 0x24) +/* RTC_CNTL_BT_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'd10 ; */ +/*description: .*/ +#define RTC_CNTL_BT_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_BT_POWERUP_TIMER_M ((RTC_CNTL_BT_POWERUP_TIMER_V)<<(RTC_CNTL_BT_POWERUP_TIMER_S)) +#define RTC_CNTL_BT_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_BT_POWERUP_TIMER_S 25 +/* RTC_CNTL_BT_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h16 ; */ +/*description: .*/ +#define RTC_CNTL_BT_WAIT_TIMER 0x000001FF +#define RTC_CNTL_BT_WAIT_TIMER_M ((RTC_CNTL_BT_WAIT_TIMER_V)<<(RTC_CNTL_BT_WAIT_TIMER_S)) +#define RTC_CNTL_BT_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_BT_WAIT_TIMER_S 16 +/* RTC_CNTL_WIFI_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */ +/*description: .*/ +#define RTC_CNTL_WIFI_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_WIFI_POWERUP_TIMER_M ((RTC_CNTL_WIFI_POWERUP_TIMER_V)<<(RTC_CNTL_WIFI_POWERUP_TIMER_S)) +#define RTC_CNTL_WIFI_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_WIFI_POWERUP_TIMER_S 9 +/* RTC_CNTL_WIFI_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */ +/*description: .*/ +#define RTC_CNTL_WIFI_WAIT_TIMER 0x000001FF +#define RTC_CNTL_WIFI_WAIT_TIMER_M ((RTC_CNTL_WIFI_WAIT_TIMER_V)<<(RTC_CNTL_WIFI_WAIT_TIMER_S)) +#define RTC_CNTL_WIFI_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_WIFI_WAIT_TIMER_S 0 + +#define RTC_CNTL_TIMER4_REG (DR_REG_RTCCNTL_BASE + 0x28) +/* RTC_CNTL_DG_WRAP_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h8 ; */ +/*description: .*/ +#define RTC_CNTL_DG_WRAP_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_M ((RTC_CNTL_DG_WRAP_POWERUP_TIMER_V)<<(RTC_CNTL_DG_WRAP_POWERUP_TIMER_S)) +#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_S 25 +/* RTC_CNTL_DG_WRAP_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h20 ; */ +/*description: .*/ +#define RTC_CNTL_DG_WRAP_WAIT_TIMER 0x000001FF +#define RTC_CNTL_DG_WRAP_WAIT_TIMER_M ((RTC_CNTL_DG_WRAP_WAIT_TIMER_V)<<(RTC_CNTL_DG_WRAP_WAIT_TIMER_S)) +#define RTC_CNTL_DG_WRAP_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_DG_WRAP_WAIT_TIMER_S 16 +/* RTC_CNTL_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */ +/*description: .*/ +#define RTC_CNTL_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_POWERUP_TIMER_M ((RTC_CNTL_POWERUP_TIMER_V)<<(RTC_CNTL_POWERUP_TIMER_S)) +#define RTC_CNTL_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_POWERUP_TIMER_S 9 +/* RTC_CNTL_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */ +/*description: .*/ +#define RTC_CNTL_WAIT_TIMER 0x000001FF +#define RTC_CNTL_WAIT_TIMER_M ((RTC_CNTL_WAIT_TIMER_V)<<(RTC_CNTL_WAIT_TIMER_S)) +#define RTC_CNTL_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_WAIT_TIMER_S 0 + +#define RTC_CNTL_TIMER5_REG (DR_REG_RTCCNTL_BASE + 0x2C) +/* RTC_CNTL_MIN_SLP_VAL : R/W ;bitpos:[15:8] ;default: 8'h80 ; */ +/*description: minimal sleep cycles in slow_clk_rtc.*/ +#define RTC_CNTL_MIN_SLP_VAL 0x000000FF +#define RTC_CNTL_MIN_SLP_VAL_M ((RTC_CNTL_MIN_SLP_VAL_V)<<(RTC_CNTL_MIN_SLP_VAL_S)) +#define RTC_CNTL_MIN_SLP_VAL_V 0xFF +#define RTC_CNTL_MIN_SLP_VAL_S 8 + +#define RTC_CNTL_TIMER6_REG (DR_REG_RTCCNTL_BASE + 0x30) +/* RTC_CNTL_DG_PERI_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h8 ; */ +/*description: .*/ +#define RTC_CNTL_DG_PERI_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_DG_PERI_POWERUP_TIMER_M ((RTC_CNTL_DG_PERI_POWERUP_TIMER_V)<<(RTC_CNTL_DG_PERI_POWERUP_TIMER_S)) +#define RTC_CNTL_DG_PERI_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_DG_PERI_POWERUP_TIMER_S 25 +/* RTC_CNTL_DG_PERI_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h20 ; */ +/*description: .*/ +#define RTC_CNTL_DG_PERI_WAIT_TIMER 0x000001FF +#define RTC_CNTL_DG_PERI_WAIT_TIMER_M ((RTC_CNTL_DG_PERI_WAIT_TIMER_V)<<(RTC_CNTL_DG_PERI_WAIT_TIMER_S)) +#define RTC_CNTL_DG_PERI_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_DG_PERI_WAIT_TIMER_S 16 +/* RTC_CNTL_CPU_TOP_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */ +/*description: .*/ +#define RTC_CNTL_CPU_TOP_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_CPU_TOP_POWERUP_TIMER_M ((RTC_CNTL_CPU_TOP_POWERUP_TIMER_V)<<(RTC_CNTL_CPU_TOP_POWERUP_TIMER_S)) +#define RTC_CNTL_CPU_TOP_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_CPU_TOP_POWERUP_TIMER_S 9 +/* RTC_CNTL_CPU_TOP_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */ +/*description: .*/ +#define RTC_CNTL_CPU_TOP_WAIT_TIMER 0x000001FF +#define RTC_CNTL_CPU_TOP_WAIT_TIMER_M ((RTC_CNTL_CPU_TOP_WAIT_TIMER_V)<<(RTC_CNTL_CPU_TOP_WAIT_TIMER_S)) +#define RTC_CNTL_CPU_TOP_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_CPU_TOP_WAIT_TIMER_S 0 + +#define RTC_CNTL_ANA_CONF_REG (DR_REG_RTCCNTL_BASE + 0x34) +/* RTC_CNTL_PLL_I2C_PU : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: .*/ +#define RTC_CNTL_PLL_I2C_PU (BIT(31)) +#define RTC_CNTL_PLL_I2C_PU_M (BIT(31)) +#define RTC_CNTL_PLL_I2C_PU_V 0x1 +#define RTC_CNTL_PLL_I2C_PU_S 31 +/* RTC_CNTL_CKGEN_I2C_PU : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: 1: CKGEN_I2C power up.*/ +#define RTC_CNTL_CKGEN_I2C_PU (BIT(30)) +#define RTC_CNTL_CKGEN_I2C_PU_M (BIT(30)) +#define RTC_CNTL_CKGEN_I2C_PU_V 0x1 +#define RTC_CNTL_CKGEN_I2C_PU_S 30 +/* RTC_CNTL_RFRX_PBUS_PU : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: 1: RFRX_PBUS power up.*/ +#define RTC_CNTL_RFRX_PBUS_PU (BIT(28)) +#define RTC_CNTL_RFRX_PBUS_PU_M (BIT(28)) +#define RTC_CNTL_RFRX_PBUS_PU_V 0x1 +#define RTC_CNTL_RFRX_PBUS_PU_S 28 +/* RTC_CNTL_TXRF_I2C_PU : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: 1: TXRF_I2C power up.*/ +#define RTC_CNTL_TXRF_I2C_PU (BIT(27)) +#define RTC_CNTL_TXRF_I2C_PU_M (BIT(27)) +#define RTC_CNTL_TXRF_I2C_PU_V 0x1 +#define RTC_CNTL_TXRF_I2C_PU_S 27 +/* RTC_CNTL_PVTMON_PU : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: 1: PVTMON power up.*/ +#define RTC_CNTL_PVTMON_PU (BIT(26)) +#define RTC_CNTL_PVTMON_PU_M (BIT(26)) +#define RTC_CNTL_PVTMON_PU_V 0x1 +#define RTC_CNTL_PVTMON_PU_S 26 +/* RTC_CNTL_BBPLL_CAL_SLP_START : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: start BBPLL calibration during sleep.*/ +#define RTC_CNTL_BBPLL_CAL_SLP_START (BIT(25)) +#define RTC_CNTL_BBPLL_CAL_SLP_START_M (BIT(25)) +#define RTC_CNTL_BBPLL_CAL_SLP_START_V 0x1 +#define RTC_CNTL_BBPLL_CAL_SLP_START_S 25 +/* RTC_CNTL_ANALOG_TOP_ISO_MONITOR : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: PLLA force power up.*/ +#define RTC_CNTL_ANALOG_TOP_ISO_MONITOR (BIT(24)) +#define RTC_CNTL_ANALOG_TOP_ISO_MONITOR_M (BIT(24)) +#define RTC_CNTL_ANALOG_TOP_ISO_MONITOR_V 0x1 +#define RTC_CNTL_ANALOG_TOP_ISO_MONITOR_S 24 +/* RTC_CNTL_ANALOG_TOP_ISO_SLEEP : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: PLLA force power down.*/ +#define RTC_CNTL_ANALOG_TOP_ISO_SLEEP (BIT(23)) +#define RTC_CNTL_ANALOG_TOP_ISO_SLEEP_M (BIT(23)) +#define RTC_CNTL_ANALOG_TOP_ISO_SLEEP_V 0x1 +#define RTC_CNTL_ANALOG_TOP_ISO_SLEEP_S 23 +/* RTC_CNTL_SAR_I2C_PU : R/W ;bitpos:[22] ;default: 1'b1 ; */ +/*description: PLLA force power up.*/ +#define RTC_CNTL_SAR_I2C_PU (BIT(22)) +#define RTC_CNTL_SAR_I2C_PU_M (BIT(22)) +#define RTC_CNTL_SAR_I2C_PU_V 0x1 +#define RTC_CNTL_SAR_I2C_PU_S 22 +/* RTC_CNTL_GLITCH_RST_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_GLITCH_RST_EN (BIT(20)) +#define RTC_CNTL_GLITCH_RST_EN_M (BIT(20)) +#define RTC_CNTL_GLITCH_RST_EN_V 0x1 +#define RTC_CNTL_GLITCH_RST_EN_S 20 +/* RTC_CNTL_I2C_RESET_POR_FORCE_PU : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_I2C_RESET_POR_FORCE_PU (BIT(19)) +#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_M (BIT(19)) +#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_V 0x1 +#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_S 19 +/* RTC_CNTL_I2C_RESET_POR_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b1 ; */ +/*description: .*/ +#define RTC_CNTL_I2C_RESET_POR_FORCE_PD (BIT(18)) +#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_M (BIT(18)) +#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_V 0x1 +#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_S 18 + +#define RTC_CNTL_RESET_STATE_REG (DR_REG_RTCCNTL_BASE + 0x38) +/* RTC_CNTL_PRO_DRESET_MASK : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_PRO_DRESET_MASK (BIT(25)) +#define RTC_CNTL_PRO_DRESET_MASK_M (BIT(25)) +#define RTC_CNTL_PRO_DRESET_MASK_V 0x1 +#define RTC_CNTL_PRO_DRESET_MASK_S 25 +/* RTC_CNTL_APP_DRESET_MASK : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_APP_DRESET_MASK (BIT(24)) +#define RTC_CNTL_APP_DRESET_MASK_M (BIT(24)) +#define RTC_CNTL_APP_DRESET_MASK_V 0x1 +#define RTC_CNTL_APP_DRESET_MASK_S 24 +/* RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR : WO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR (BIT(23)) +#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR_M (BIT(23)) +#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR_V 0x1 +#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR_S 23 +/* RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR (BIT(22)) +#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR_M (BIT(22)) +#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR_V 0x1 +#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR_S 22 +/* RTC_CNTL_RESET_FLAG_JTAG_APPCPU : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU (BIT(21)) +#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_M (BIT(21)) +#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_V 0x1 +#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_S 21 +/* RTC_CNTL_RESET_FLAG_JTAG_PROCPU : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU (BIT(20)) +#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_M (BIT(20)) +#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_V 0x1 +#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_S 20 +/* RTC_CNTL_PROCPU_OCD_HALT_ON_RESET : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: PROCPU OcdHaltOnReset.*/ +#define RTC_CNTL_PROCPU_OCD_HALT_ON_RESET (BIT(19)) +#define RTC_CNTL_PROCPU_OCD_HALT_ON_RESET_M (BIT(19)) +#define RTC_CNTL_PROCPU_OCD_HALT_ON_RESET_V 0x1 +#define RTC_CNTL_PROCPU_OCD_HALT_ON_RESET_S 19 +/* RTC_CNTL_APPCPU_OCD_HALT_ON_RESET : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: APPCPU OcdHaltOnReset.*/ +#define RTC_CNTL_APPCPU_OCD_HALT_ON_RESET (BIT(18)) +#define RTC_CNTL_APPCPU_OCD_HALT_ON_RESET_M (BIT(18)) +#define RTC_CNTL_APPCPU_OCD_HALT_ON_RESET_V 0x1 +#define RTC_CNTL_APPCPU_OCD_HALT_ON_RESET_S 18 +/* RTC_CNTL_RESET_FLAG_APPCPU_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: clear APP CPU reset flag.*/ +#define RTC_CNTL_RESET_FLAG_APPCPU_CLR (BIT(17)) +#define RTC_CNTL_RESET_FLAG_APPCPU_CLR_M (BIT(17)) +#define RTC_CNTL_RESET_FLAG_APPCPU_CLR_V 0x1 +#define RTC_CNTL_RESET_FLAG_APPCPU_CLR_S 17 +/* RTC_CNTL_RESET_FLAG_PROCPU_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: clear PRO CPU reset_flag.*/ +#define RTC_CNTL_RESET_FLAG_PROCPU_CLR (BIT(16)) +#define RTC_CNTL_RESET_FLAG_PROCPU_CLR_M (BIT(16)) +#define RTC_CNTL_RESET_FLAG_PROCPU_CLR_V 0x1 +#define RTC_CNTL_RESET_FLAG_PROCPU_CLR_S 16 +/* RTC_CNTL_RESET_FLAG_APPCPU : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: APP CPU reset flag.*/ +#define RTC_CNTL_RESET_FLAG_APPCPU (BIT(15)) +#define RTC_CNTL_RESET_FLAG_APPCPU_M (BIT(15)) +#define RTC_CNTL_RESET_FLAG_APPCPU_V 0x1 +#define RTC_CNTL_RESET_FLAG_APPCPU_S 15 +/* RTC_CNTL_RESET_FLAG_PROCPU : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: PRO CPU reset_flag.*/ +#define RTC_CNTL_RESET_FLAG_PROCPU (BIT(14)) +#define RTC_CNTL_RESET_FLAG_PROCPU_M (BIT(14)) +#define RTC_CNTL_RESET_FLAG_PROCPU_V 0x1 +#define RTC_CNTL_RESET_FLAG_PROCPU_S 14 +/* RTC_CNTL_PROCPU_STAT_VECTOR_SEL : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: PRO CPU state vector sel.*/ +#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL (BIT(13)) +#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_M (BIT(13)) +#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_V 0x1 +#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_S 13 +/* RTC_CNTL_APPCPU_STAT_VECTOR_SEL : R/W ;bitpos:[12] ;default: 1'b1 ; */ +/*description: APP CPU state vector sel.*/ +#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL (BIT(12)) +#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_M (BIT(12)) +#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_V 0x1 +#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_S 12 +/* RTC_CNTL_RESET_CAUSE_APPCPU : RO ;bitpos:[11:6] ;default: 0 ; */ +/*description: reset cause of APP CPU.*/ +#define RTC_CNTL_RESET_CAUSE_APPCPU 0x0000003F +#define RTC_CNTL_RESET_CAUSE_APPCPU_M ((RTC_CNTL_RESET_CAUSE_APPCPU_V)<<(RTC_CNTL_RESET_CAUSE_APPCPU_S)) +#define RTC_CNTL_RESET_CAUSE_APPCPU_V 0x3F +#define RTC_CNTL_RESET_CAUSE_APPCPU_S 6 +/* RTC_CNTL_RESET_CAUSE_PROCPU : RO ;bitpos:[5:0] ;default: 0 ; */ +/*description: reset cause of PRO CPU.*/ +#define RTC_CNTL_RESET_CAUSE_PROCPU 0x0000003F +#define RTC_CNTL_RESET_CAUSE_PROCPU_M ((RTC_CNTL_RESET_CAUSE_PROCPU_V)<<(RTC_CNTL_RESET_CAUSE_PROCPU_S)) +#define RTC_CNTL_RESET_CAUSE_PROCPU_V 0x3F +#define RTC_CNTL_RESET_CAUSE_PROCPU_S 0 + +#define RTC_CNTL_WAKEUP_STATE_REG (DR_REG_RTCCNTL_BASE + 0x3C) +/* RTC_CNTL_WAKEUP_ENA : R/W ;bitpos:[31:15] ;default: 17'b1100 ; */ +/*description: wakeup enable bitmap.*/ +#define RTC_CNTL_WAKEUP_ENA 0x0001FFFF +#define RTC_CNTL_WAKEUP_ENA_M ((RTC_CNTL_WAKEUP_ENA_V)<<(RTC_CNTL_WAKEUP_ENA_S)) +#define RTC_CNTL_WAKEUP_ENA_V 0x1FFFF +#define RTC_CNTL_WAKEUP_ENA_S 15 + +#define RTC_CNTL_INT_ENA_REG (DR_REG_RTCCNTL_BASE + 0x40) +/* RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA (BIT(20)) +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_M (BIT(20)) +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_V 0x1 +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_S 20 +/* RTC_CNTL_GLITCH_DET_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: enable gitch det interrupt.*/ +#define RTC_CNTL_GLITCH_DET_INT_ENA (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ENA_M (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ENA_V 0x1 +#define RTC_CNTL_GLITCH_DET_INT_ENA_S 19 +/* RTC_CNTL_TOUCH_TIMEOUT_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: enable touch timeout interrupt.*/ +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA (BIT(18)) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_M (BIT(18)) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_V 0x1 +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_S 18 +/* RTC_CNTL_COCPU_TRAP_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: enable cocpu trap interrupt.*/ +#define RTC_CNTL_COCPU_TRAP_INT_ENA (BIT(17)) +#define RTC_CNTL_COCPU_TRAP_INT_ENA_M (BIT(17)) +#define RTC_CNTL_COCPU_TRAP_INT_ENA_V 0x1 +#define RTC_CNTL_COCPU_TRAP_INT_ENA_S 17 +/* RTC_CNTL_XTAL32K_DEAD_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: enable xtal32k_dead interrupt.*/ +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_M (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_V 0x1 +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_S 16 +/* RTC_CNTL_SWD_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: enable super watch dog interrupt.*/ +#define RTC_CNTL_SWD_INT_ENA (BIT(15)) +#define RTC_CNTL_SWD_INT_ENA_M (BIT(15)) +#define RTC_CNTL_SWD_INT_ENA_V 0x1 +#define RTC_CNTL_SWD_INT_ENA_S 15 +/* RTC_CNTL_SARADC2_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: enable saradc2 interrupt.*/ +#define RTC_CNTL_SARADC2_INT_ENA (BIT(14)) +#define RTC_CNTL_SARADC2_INT_ENA_M (BIT(14)) +#define RTC_CNTL_SARADC2_INT_ENA_V 0x1 +#define RTC_CNTL_SARADC2_INT_ENA_S 14 +/* RTC_CNTL_COCPU_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: enable riscV cocpu interrupt.*/ +#define RTC_CNTL_COCPU_INT_ENA (BIT(13)) +#define RTC_CNTL_COCPU_INT_ENA_M (BIT(13)) +#define RTC_CNTL_COCPU_INT_ENA_V 0x1 +#define RTC_CNTL_COCPU_INT_ENA_S 13 +/* RTC_CNTL_TSENS_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: enable tsens interrupt.*/ +#define RTC_CNTL_TSENS_INT_ENA (BIT(12)) +#define RTC_CNTL_TSENS_INT_ENA_M (BIT(12)) +#define RTC_CNTL_TSENS_INT_ENA_V 0x1 +#define RTC_CNTL_TSENS_INT_ENA_S 12 +/* RTC_CNTL_SARADC1_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: enable saradc1 interrupt.*/ +#define RTC_CNTL_SARADC1_INT_ENA (BIT(11)) +#define RTC_CNTL_SARADC1_INT_ENA_M (BIT(11)) +#define RTC_CNTL_SARADC1_INT_ENA_V 0x1 +#define RTC_CNTL_SARADC1_INT_ENA_S 11 +/* RTC_CNTL_MAIN_TIMER_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: enable RTC main timer interrupt.*/ +#define RTC_CNTL_MAIN_TIMER_INT_ENA (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ENA_M (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ENA_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_ENA_S 10 +/* RTC_CNTL_BROWN_OUT_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: enable brown out interrupt.*/ +#define RTC_CNTL_BROWN_OUT_INT_ENA (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ENA_M (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_ENA_S 9 +/* RTC_CNTL_TOUCH_INACTIVE_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: enable touch inactive interrupt.*/ +#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA (BIT(8)) +#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_M (BIT(8)) +#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_V 0x1 +#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_S 8 +/* RTC_CNTL_TOUCH_ACTIVE_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: enable touch active interrupt.*/ +#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA (BIT(7)) +#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_M (BIT(7)) +#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_V 0x1 +#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_S 7 +/* RTC_CNTL_TOUCH_DONE_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: enable touch done interrupt.*/ +#define RTC_CNTL_TOUCH_DONE_INT_ENA (BIT(6)) +#define RTC_CNTL_TOUCH_DONE_INT_ENA_M (BIT(6)) +#define RTC_CNTL_TOUCH_DONE_INT_ENA_V 0x1 +#define RTC_CNTL_TOUCH_DONE_INT_ENA_S 6 +/* RTC_CNTL_ULP_CP_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: enable ULP-coprocessor interrupt.*/ +#define RTC_CNTL_ULP_CP_INT_ENA (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_ENA_M (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_ENA_V 0x1 +#define RTC_CNTL_ULP_CP_INT_ENA_S 5 +/* RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: enable touch scan done interrupt.*/ +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA (BIT(4)) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_M (BIT(4)) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_V 0x1 +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_S 4 +/* RTC_CNTL_WDT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: enable RTC WDT interrupt.*/ +#define RTC_CNTL_WDT_INT_ENA (BIT(3)) +#define RTC_CNTL_WDT_INT_ENA_M (BIT(3)) +#define RTC_CNTL_WDT_INT_ENA_V 0x1 +#define RTC_CNTL_WDT_INT_ENA_S 3 +/* RTC_CNTL_SDIO_IDLE_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: enable SDIO idle interrupt.*/ +#define RTC_CNTL_SDIO_IDLE_INT_ENA (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_ENA_M (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_ENA_V 0x1 +#define RTC_CNTL_SDIO_IDLE_INT_ENA_S 2 +/* RTC_CNTL_SLP_REJECT_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: enable sleep reject interrupt.*/ +#define RTC_CNTL_SLP_REJECT_INT_ENA (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ENA_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ENA_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_ENA_S 1 +/* RTC_CNTL_SLP_WAKEUP_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: enable sleep wakeup interrupt.*/ +#define RTC_CNTL_SLP_WAKEUP_INT_ENA (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_S 0 + +#define RTC_CNTL_INT_RAW_REG (DR_REG_RTCCNTL_BASE + 0x44) +/* RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_RAW : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_RAW (BIT(20)) +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_RAW_M (BIT(20)) +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_RAW_V 0x1 +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_RAW_S 20 +/* RTC_CNTL_GLITCH_DET_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: glitch_det_interrupt_raw.*/ +#define RTC_CNTL_GLITCH_DET_INT_RAW (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_RAW_M (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_RAW_V 0x1 +#define RTC_CNTL_GLITCH_DET_INT_RAW_S 19 +/* RTC_CNTL_TOUCH_TIMEOUT_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: touch timeout interrupt raw.*/ +#define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW (BIT(18)) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW_M (BIT(18)) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW_V 0x1 +#define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW_S 18 +/* RTC_CNTL_COCPU_TRAP_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: cocpu trap interrupt raw.*/ +#define RTC_CNTL_COCPU_TRAP_INT_RAW (BIT(17)) +#define RTC_CNTL_COCPU_TRAP_INT_RAW_M (BIT(17)) +#define RTC_CNTL_COCPU_TRAP_INT_RAW_V 0x1 +#define RTC_CNTL_COCPU_TRAP_INT_RAW_S 17 +/* RTC_CNTL_XTAL32K_DEAD_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: xtal32k dead detection interrupt raw.*/ +#define RTC_CNTL_XTAL32K_DEAD_INT_RAW (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_RAW_M (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_RAW_V 0x1 +#define RTC_CNTL_XTAL32K_DEAD_INT_RAW_S 16 +/* RTC_CNTL_SWD_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: super watch dog interrupt raw.*/ +#define RTC_CNTL_SWD_INT_RAW (BIT(15)) +#define RTC_CNTL_SWD_INT_RAW_M (BIT(15)) +#define RTC_CNTL_SWD_INT_RAW_V 0x1 +#define RTC_CNTL_SWD_INT_RAW_S 15 +/* RTC_CNTL_SARADC2_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: saradc2 interrupt raw.*/ +#define RTC_CNTL_SARADC2_INT_RAW (BIT(14)) +#define RTC_CNTL_SARADC2_INT_RAW_M (BIT(14)) +#define RTC_CNTL_SARADC2_INT_RAW_V 0x1 +#define RTC_CNTL_SARADC2_INT_RAW_S 14 +/* RTC_CNTL_COCPU_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: riscV cocpu interrupt raw.*/ +#define RTC_CNTL_COCPU_INT_RAW (BIT(13)) +#define RTC_CNTL_COCPU_INT_RAW_M (BIT(13)) +#define RTC_CNTL_COCPU_INT_RAW_V 0x1 +#define RTC_CNTL_COCPU_INT_RAW_S 13 +/* RTC_CNTL_TSENS_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: tsens interrupt raw.*/ +#define RTC_CNTL_TSENS_INT_RAW (BIT(12)) +#define RTC_CNTL_TSENS_INT_RAW_M (BIT(12)) +#define RTC_CNTL_TSENS_INT_RAW_V 0x1 +#define RTC_CNTL_TSENS_INT_RAW_S 12 +/* RTC_CNTL_SARADC1_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: saradc1 interrupt raw.*/ +#define RTC_CNTL_SARADC1_INT_RAW (BIT(11)) +#define RTC_CNTL_SARADC1_INT_RAW_M (BIT(11)) +#define RTC_CNTL_SARADC1_INT_RAW_V 0x1 +#define RTC_CNTL_SARADC1_INT_RAW_S 11 +/* RTC_CNTL_MAIN_TIMER_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: RTC main timer interrupt raw.*/ +#define RTC_CNTL_MAIN_TIMER_INT_RAW (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_RAW_M (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_RAW_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_RAW_S 10 +/* RTC_CNTL_BROWN_OUT_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: brown out interrupt raw.*/ +#define RTC_CNTL_BROWN_OUT_INT_RAW (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_RAW_M (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_RAW_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_RAW_S 9 +/* RTC_CNTL_TOUCH_INACTIVE_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: touch inactive interrupt raw.*/ +#define RTC_CNTL_TOUCH_INACTIVE_INT_RAW (BIT(8)) +#define RTC_CNTL_TOUCH_INACTIVE_INT_RAW_M (BIT(8)) +#define RTC_CNTL_TOUCH_INACTIVE_INT_RAW_V 0x1 +#define RTC_CNTL_TOUCH_INACTIVE_INT_RAW_S 8 +/* RTC_CNTL_TOUCH_ACTIVE_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: touch active interrupt raw.*/ +#define RTC_CNTL_TOUCH_ACTIVE_INT_RAW (BIT(7)) +#define RTC_CNTL_TOUCH_ACTIVE_INT_RAW_M (BIT(7)) +#define RTC_CNTL_TOUCH_ACTIVE_INT_RAW_V 0x1 +#define RTC_CNTL_TOUCH_ACTIVE_INT_RAW_S 7 +/* RTC_CNTL_TOUCH_DONE_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: touch interrupt raw.*/ +#define RTC_CNTL_TOUCH_DONE_INT_RAW (BIT(6)) +#define RTC_CNTL_TOUCH_DONE_INT_RAW_M (BIT(6)) +#define RTC_CNTL_TOUCH_DONE_INT_RAW_V 0x1 +#define RTC_CNTL_TOUCH_DONE_INT_RAW_S 6 +/* RTC_CNTL_ULP_CP_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: ULP-coprocessor interrupt raw.*/ +#define RTC_CNTL_ULP_CP_INT_RAW (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_RAW_M (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_RAW_V 0x1 +#define RTC_CNTL_ULP_CP_INT_RAW_S 5 +/* RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW (BIT(4)) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW_M (BIT(4)) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW_V 0x1 +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW_S 4 +/* RTC_CNTL_WDT_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: RTC WDT interrupt raw.*/ +#define RTC_CNTL_WDT_INT_RAW (BIT(3)) +#define RTC_CNTL_WDT_INT_RAW_M (BIT(3)) +#define RTC_CNTL_WDT_INT_RAW_V 0x1 +#define RTC_CNTL_WDT_INT_RAW_S 3 +/* RTC_CNTL_SDIO_IDLE_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: SDIO idle interrupt raw.*/ +#define RTC_CNTL_SDIO_IDLE_INT_RAW (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_RAW_M (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_RAW_V 0x1 +#define RTC_CNTL_SDIO_IDLE_INT_RAW_S 2 +/* RTC_CNTL_SLP_REJECT_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: sleep reject interrupt raw.*/ +#define RTC_CNTL_SLP_REJECT_INT_RAW (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_RAW_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_RAW_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_RAW_S 1 +/* RTC_CNTL_SLP_WAKEUP_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: sleep wakeup interrupt raw.*/ +#define RTC_CNTL_SLP_WAKEUP_INT_RAW (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_RAW_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_RAW_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_RAW_S 0 + +#define RTC_CNTL_INT_ST_REG (DR_REG_RTCCNTL_BASE + 0x48) +/* RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ST (BIT(20)) +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ST_M (BIT(20)) +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ST_V 0x1 +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ST_S 20 +/* RTC_CNTL_GLITCH_DET_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: glitch_det_interrupt state.*/ +#define RTC_CNTL_GLITCH_DET_INT_ST (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ST_M (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ST_V 0x1 +#define RTC_CNTL_GLITCH_DET_INT_ST_S 19 +/* RTC_CNTL_TOUCH_TIMEOUT_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: Touch timeout interrupt state.*/ +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ST (BIT(18)) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ST_M (BIT(18)) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ST_V 0x1 +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ST_S 18 +/* RTC_CNTL_COCPU_TRAP_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: cocpu trap interrupt state.*/ +#define RTC_CNTL_COCPU_TRAP_INT_ST (BIT(17)) +#define RTC_CNTL_COCPU_TRAP_INT_ST_M (BIT(17)) +#define RTC_CNTL_COCPU_TRAP_INT_ST_V 0x1 +#define RTC_CNTL_COCPU_TRAP_INT_ST_S 17 +/* RTC_CNTL_XTAL32K_DEAD_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: xtal32k dead detection interrupt state.*/ +#define RTC_CNTL_XTAL32K_DEAD_INT_ST (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ST_M (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ST_V 0x1 +#define RTC_CNTL_XTAL32K_DEAD_INT_ST_S 16 +/* RTC_CNTL_SWD_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: super watch dog interrupt state.*/ +#define RTC_CNTL_SWD_INT_ST (BIT(15)) +#define RTC_CNTL_SWD_INT_ST_M (BIT(15)) +#define RTC_CNTL_SWD_INT_ST_V 0x1 +#define RTC_CNTL_SWD_INT_ST_S 15 +/* RTC_CNTL_SARADC2_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: saradc2 interrupt state.*/ +#define RTC_CNTL_SARADC2_INT_ST (BIT(14)) +#define RTC_CNTL_SARADC2_INT_ST_M (BIT(14)) +#define RTC_CNTL_SARADC2_INT_ST_V 0x1 +#define RTC_CNTL_SARADC2_INT_ST_S 14 +/* RTC_CNTL_COCPU_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: riscV cocpu interrupt state.*/ +#define RTC_CNTL_COCPU_INT_ST (BIT(13)) +#define RTC_CNTL_COCPU_INT_ST_M (BIT(13)) +#define RTC_CNTL_COCPU_INT_ST_V 0x1 +#define RTC_CNTL_COCPU_INT_ST_S 13 +/* RTC_CNTL_TSENS_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: tsens interrupt state.*/ +#define RTC_CNTL_TSENS_INT_ST (BIT(12)) +#define RTC_CNTL_TSENS_INT_ST_M (BIT(12)) +#define RTC_CNTL_TSENS_INT_ST_V 0x1 +#define RTC_CNTL_TSENS_INT_ST_S 12 +/* RTC_CNTL_SARADC1_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: saradc1 interrupt state.*/ +#define RTC_CNTL_SARADC1_INT_ST (BIT(11)) +#define RTC_CNTL_SARADC1_INT_ST_M (BIT(11)) +#define RTC_CNTL_SARADC1_INT_ST_V 0x1 +#define RTC_CNTL_SARADC1_INT_ST_S 11 +/* RTC_CNTL_MAIN_TIMER_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: RTC main timer interrupt state.*/ +#define RTC_CNTL_MAIN_TIMER_INT_ST (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ST_M (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ST_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_ST_S 10 +/* RTC_CNTL_BROWN_OUT_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: brown out interrupt state.*/ +#define RTC_CNTL_BROWN_OUT_INT_ST (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ST_M (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ST_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_ST_S 9 +/* RTC_CNTL_TOUCH_INACTIVE_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: touch inactive interrupt state.*/ +#define RTC_CNTL_TOUCH_INACTIVE_INT_ST (BIT(8)) +#define RTC_CNTL_TOUCH_INACTIVE_INT_ST_M (BIT(8)) +#define RTC_CNTL_TOUCH_INACTIVE_INT_ST_V 0x1 +#define RTC_CNTL_TOUCH_INACTIVE_INT_ST_S 8 +/* RTC_CNTL_TOUCH_ACTIVE_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: touch active interrupt state.*/ +#define RTC_CNTL_TOUCH_ACTIVE_INT_ST (BIT(7)) +#define RTC_CNTL_TOUCH_ACTIVE_INT_ST_M (BIT(7)) +#define RTC_CNTL_TOUCH_ACTIVE_INT_ST_V 0x1 +#define RTC_CNTL_TOUCH_ACTIVE_INT_ST_S 7 +/* RTC_CNTL_TOUCH_DONE_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: touch done interrupt state.*/ +#define RTC_CNTL_TOUCH_DONE_INT_ST (BIT(6)) +#define RTC_CNTL_TOUCH_DONE_INT_ST_M (BIT(6)) +#define RTC_CNTL_TOUCH_DONE_INT_ST_V 0x1 +#define RTC_CNTL_TOUCH_DONE_INT_ST_S 6 +/* RTC_CNTL_ULP_CP_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: ULP-coprocessor interrupt state.*/ +#define RTC_CNTL_ULP_CP_INT_ST (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_ST_M (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_ST_V 0x1 +#define RTC_CNTL_ULP_CP_INT_ST_S 5 +/* RTC_CNTL_TOUCH_SCAN_DONE_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ST (BIT(4)) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ST_M (BIT(4)) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ST_V 0x1 +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ST_S 4 +/* RTC_CNTL_WDT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: RTC WDT interrupt state.*/ +#define RTC_CNTL_WDT_INT_ST (BIT(3)) +#define RTC_CNTL_WDT_INT_ST_M (BIT(3)) +#define RTC_CNTL_WDT_INT_ST_V 0x1 +#define RTC_CNTL_WDT_INT_ST_S 3 +/* RTC_CNTL_SDIO_IDLE_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: SDIO idle interrupt state.*/ +#define RTC_CNTL_SDIO_IDLE_INT_ST (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_ST_M (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_ST_V 0x1 +#define RTC_CNTL_SDIO_IDLE_INT_ST_S 2 +/* RTC_CNTL_SLP_REJECT_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: sleep reject interrupt state.*/ +#define RTC_CNTL_SLP_REJECT_INT_ST (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ST_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ST_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_ST_S 1 +/* RTC_CNTL_SLP_WAKEUP_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: sleep wakeup interrupt state.*/ +#define RTC_CNTL_SLP_WAKEUP_INT_ST (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ST_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ST_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_ST_S 0 + +#define RTC_CNTL_INT_CLR_REG (DR_REG_RTCCNTL_BASE + 0x4C) +/* RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_CLR (BIT(20)) +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_CLR_M (BIT(20)) +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_CLR_V 0x1 +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_CLR_S 20 +/* RTC_CNTL_GLITCH_DET_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: Clear glitch det interrupt state.*/ +#define RTC_CNTL_GLITCH_DET_INT_CLR (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_CLR_M (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_CLR_V 0x1 +#define RTC_CNTL_GLITCH_DET_INT_CLR_S 19 +/* RTC_CNTL_TOUCH_TIMEOUT_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: Clear touch timeout interrupt state.*/ +#define RTC_CNTL_TOUCH_TIMEOUT_INT_CLR (BIT(18)) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_CLR_M (BIT(18)) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_CLR_V 0x1 +#define RTC_CNTL_TOUCH_TIMEOUT_INT_CLR_S 18 +/* RTC_CNTL_COCPU_TRAP_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: Clear cocpu trap interrupt state.*/ +#define RTC_CNTL_COCPU_TRAP_INT_CLR (BIT(17)) +#define RTC_CNTL_COCPU_TRAP_INT_CLR_M (BIT(17)) +#define RTC_CNTL_COCPU_TRAP_INT_CLR_V 0x1 +#define RTC_CNTL_COCPU_TRAP_INT_CLR_S 17 +/* RTC_CNTL_XTAL32K_DEAD_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: Clear RTC WDT interrupt state.*/ +#define RTC_CNTL_XTAL32K_DEAD_INT_CLR (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_CLR_M (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_CLR_V 0x1 +#define RTC_CNTL_XTAL32K_DEAD_INT_CLR_S 16 +/* RTC_CNTL_SWD_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: Clear super watch dog interrupt state.*/ +#define RTC_CNTL_SWD_INT_CLR (BIT(15)) +#define RTC_CNTL_SWD_INT_CLR_M (BIT(15)) +#define RTC_CNTL_SWD_INT_CLR_V 0x1 +#define RTC_CNTL_SWD_INT_CLR_S 15 +/* RTC_CNTL_SARADC2_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: Clear saradc2 interrupt state.*/ +#define RTC_CNTL_SARADC2_INT_CLR (BIT(14)) +#define RTC_CNTL_SARADC2_INT_CLR_M (BIT(14)) +#define RTC_CNTL_SARADC2_INT_CLR_V 0x1 +#define RTC_CNTL_SARADC2_INT_CLR_S 14 +/* RTC_CNTL_COCPU_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: Clear riscV cocpu interrupt state.*/ +#define RTC_CNTL_COCPU_INT_CLR (BIT(13)) +#define RTC_CNTL_COCPU_INT_CLR_M (BIT(13)) +#define RTC_CNTL_COCPU_INT_CLR_V 0x1 +#define RTC_CNTL_COCPU_INT_CLR_S 13 +/* RTC_CNTL_TSENS_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Clear tsens interrupt state.*/ +#define RTC_CNTL_TSENS_INT_CLR (BIT(12)) +#define RTC_CNTL_TSENS_INT_CLR_M (BIT(12)) +#define RTC_CNTL_TSENS_INT_CLR_V 0x1 +#define RTC_CNTL_TSENS_INT_CLR_S 12 +/* RTC_CNTL_SARADC1_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: Clear saradc1 interrupt state.*/ +#define RTC_CNTL_SARADC1_INT_CLR (BIT(11)) +#define RTC_CNTL_SARADC1_INT_CLR_M (BIT(11)) +#define RTC_CNTL_SARADC1_INT_CLR_V 0x1 +#define RTC_CNTL_SARADC1_INT_CLR_S 11 +/* RTC_CNTL_MAIN_TIMER_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: Clear RTC main timer interrupt state.*/ +#define RTC_CNTL_MAIN_TIMER_INT_CLR (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_CLR_M (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_CLR_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_CLR_S 10 +/* RTC_CNTL_BROWN_OUT_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Clear brown out interrupt state.*/ +#define RTC_CNTL_BROWN_OUT_INT_CLR (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_CLR_M (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_CLR_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_CLR_S 9 +/* RTC_CNTL_TOUCH_INACTIVE_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Clear touch inactive interrupt state.*/ +#define RTC_CNTL_TOUCH_INACTIVE_INT_CLR (BIT(8)) +#define RTC_CNTL_TOUCH_INACTIVE_INT_CLR_M (BIT(8)) +#define RTC_CNTL_TOUCH_INACTIVE_INT_CLR_V 0x1 +#define RTC_CNTL_TOUCH_INACTIVE_INT_CLR_S 8 +/* RTC_CNTL_TOUCH_ACTIVE_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Clear touch active interrupt state.*/ +#define RTC_CNTL_TOUCH_ACTIVE_INT_CLR (BIT(7)) +#define RTC_CNTL_TOUCH_ACTIVE_INT_CLR_M (BIT(7)) +#define RTC_CNTL_TOUCH_ACTIVE_INT_CLR_V 0x1 +#define RTC_CNTL_TOUCH_ACTIVE_INT_CLR_S 7 +/* RTC_CNTL_TOUCH_DONE_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Clear touch done interrupt state.*/ +#define RTC_CNTL_TOUCH_DONE_INT_CLR (BIT(6)) +#define RTC_CNTL_TOUCH_DONE_INT_CLR_M (BIT(6)) +#define RTC_CNTL_TOUCH_DONE_INT_CLR_V 0x1 +#define RTC_CNTL_TOUCH_DONE_INT_CLR_S 6 +/* RTC_CNTL_ULP_CP_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Clear ULP-coprocessor interrupt state.*/ +#define RTC_CNTL_ULP_CP_INT_CLR (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_CLR_M (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_CLR_V 0x1 +#define RTC_CNTL_ULP_CP_INT_CLR_S 5 +/* RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR (BIT(4)) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR_M (BIT(4)) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR_V 0x1 +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR_S 4 +/* RTC_CNTL_WDT_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Clear RTC WDT interrupt state.*/ +#define RTC_CNTL_WDT_INT_CLR (BIT(3)) +#define RTC_CNTL_WDT_INT_CLR_M (BIT(3)) +#define RTC_CNTL_WDT_INT_CLR_V 0x1 +#define RTC_CNTL_WDT_INT_CLR_S 3 +/* RTC_CNTL_SDIO_IDLE_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Clear SDIO idle interrupt state.*/ +#define RTC_CNTL_SDIO_IDLE_INT_CLR (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_CLR_M (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_CLR_V 0x1 +#define RTC_CNTL_SDIO_IDLE_INT_CLR_S 2 +/* RTC_CNTL_SLP_REJECT_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Clear sleep reject interrupt state.*/ +#define RTC_CNTL_SLP_REJECT_INT_CLR (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_CLR_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_CLR_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_CLR_S 1 +/* RTC_CNTL_SLP_WAKEUP_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Clear sleep wakeup interrupt state.*/ +#define RTC_CNTL_SLP_WAKEUP_INT_CLR (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_CLR_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_CLR_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_CLR_S 0 + +#define RTC_CNTL_STORE0_REG (DR_REG_RTCCNTL_BASE + 0x50) +/* RTC_CNTL_SCRATCH0 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: .*/ +#define RTC_CNTL_SCRATCH0 0xFFFFFFFF +#define RTC_CNTL_SCRATCH0_M ((RTC_CNTL_SCRATCH0_V)<<(RTC_CNTL_SCRATCH0_S)) +#define RTC_CNTL_SCRATCH0_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH0_S 0 + +#define RTC_CNTL_STORE1_REG (DR_REG_RTCCNTL_BASE + 0x54) +/* RTC_CNTL_SCRATCH1 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: .*/ +#define RTC_CNTL_SCRATCH1 0xFFFFFFFF +#define RTC_CNTL_SCRATCH1_M ((RTC_CNTL_SCRATCH1_V)<<(RTC_CNTL_SCRATCH1_S)) +#define RTC_CNTL_SCRATCH1_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH1_S 0 + +#define RTC_CNTL_STORE2_REG (DR_REG_RTCCNTL_BASE + 0x58) +/* RTC_CNTL_SCRATCH2 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: .*/ +#define RTC_CNTL_SCRATCH2 0xFFFFFFFF +#define RTC_CNTL_SCRATCH2_M ((RTC_CNTL_SCRATCH2_V)<<(RTC_CNTL_SCRATCH2_S)) +#define RTC_CNTL_SCRATCH2_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH2_S 0 + +#define RTC_CNTL_STORE3_REG (DR_REG_RTCCNTL_BASE + 0x5C) +/* RTC_CNTL_SCRATCH3 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: .*/ +#define RTC_CNTL_SCRATCH3 0xFFFFFFFF +#define RTC_CNTL_SCRATCH3_M ((RTC_CNTL_SCRATCH3_V)<<(RTC_CNTL_SCRATCH3_S)) +#define RTC_CNTL_SCRATCH3_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH3_S 0 + +#define RTC_CNTL_EXT_XTL_CONF_REG (DR_REG_RTCCNTL_BASE + 0x60) +/* RTC_CNTL_XTL_EXT_CTR_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_XTL_EXT_CTR_EN (BIT(31)) +#define RTC_CNTL_XTL_EXT_CTR_EN_M (BIT(31)) +#define RTC_CNTL_XTL_EXT_CTR_EN_V 0x1 +#define RTC_CNTL_XTL_EXT_CTR_EN_S 31 +/* RTC_CNTL_XTL_EXT_CTR_LV : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: 0: power down XTAL at high level.*/ +#define RTC_CNTL_XTL_EXT_CTR_LV (BIT(30)) +#define RTC_CNTL_XTL_EXT_CTR_LV_M (BIT(30)) +#define RTC_CNTL_XTL_EXT_CTR_LV_V 0x1 +#define RTC_CNTL_XTL_EXT_CTR_LV_S 30 +/* RTC_CNTL_XTAL32K_GPIO_SEL : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: XTAL_32K sel. 0: external XTAL_32K.*/ +#define RTC_CNTL_XTAL32K_GPIO_SEL (BIT(23)) +#define RTC_CNTL_XTAL32K_GPIO_SEL_M (BIT(23)) +#define RTC_CNTL_XTAL32K_GPIO_SEL_V 0x1 +#define RTC_CNTL_XTAL32K_GPIO_SEL_S 23 +/* RTC_CNTL_WDT_STATE : RO ;bitpos:[22:20] ;default: 3'h0 ; */ +/*description: state of 32k_wdt.*/ +#define RTC_CNTL_WDT_STATE 0x00000007 +#define RTC_CNTL_WDT_STATE_M ((RTC_CNTL_WDT_STATE_V)<<(RTC_CNTL_WDT_STATE_S)) +#define RTC_CNTL_WDT_STATE_V 0x7 +#define RTC_CNTL_WDT_STATE_S 20 +/* RTC_CNTL_DAC_XTAL_32K : R/W ;bitpos:[19:17] ;default: 3'd3 ; */ +/*description: DAC_XTAL_32K.*/ +#define RTC_CNTL_DAC_XTAL_32K 0x00000007 +#define RTC_CNTL_DAC_XTAL_32K_M ((RTC_CNTL_DAC_XTAL_32K_V)<<(RTC_CNTL_DAC_XTAL_32K_S)) +#define RTC_CNTL_DAC_XTAL_32K_V 0x7 +#define RTC_CNTL_DAC_XTAL_32K_S 17 +/* RTC_CNTL_XPD_XTAL_32K : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: XPD_XTAL_32K.*/ +#define RTC_CNTL_XPD_XTAL_32K (BIT(16)) +#define RTC_CNTL_XPD_XTAL_32K_M (BIT(16)) +#define RTC_CNTL_XPD_XTAL_32K_V 0x1 +#define RTC_CNTL_XPD_XTAL_32K_S 16 +/* RTC_CNTL_DRES_XTAL_32K : R/W ;bitpos:[15:13] ;default: 3'd3 ; */ +/*description: DRES_XTAL_32K.*/ +#define RTC_CNTL_DRES_XTAL_32K 0x00000007 +#define RTC_CNTL_DRES_XTAL_32K_M ((RTC_CNTL_DRES_XTAL_32K_V)<<(RTC_CNTL_DRES_XTAL_32K_S)) +#define RTC_CNTL_DRES_XTAL_32K_V 0x7 +#define RTC_CNTL_DRES_XTAL_32K_S 13 +/* RTC_CNTL_DGM_XTAL_32K : R/W ;bitpos:[12:10] ;default: 3'd3 ; */ +/*description: xtal_32k gm control.*/ +#define RTC_CNTL_DGM_XTAL_32K 0x00000007 +#define RTC_CNTL_DGM_XTAL_32K_M ((RTC_CNTL_DGM_XTAL_32K_V)<<(RTC_CNTL_DGM_XTAL_32K_S)) +#define RTC_CNTL_DGM_XTAL_32K_V 0x7 +#define RTC_CNTL_DGM_XTAL_32K_S 10 +/* RTC_CNTL_DBUF_XTAL_32K : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: 0: single-end buffer 1: differential buffer.*/ +#define RTC_CNTL_DBUF_XTAL_32K (BIT(9)) +#define RTC_CNTL_DBUF_XTAL_32K_M (BIT(9)) +#define RTC_CNTL_DBUF_XTAL_32K_V 0x1 +#define RTC_CNTL_DBUF_XTAL_32K_S 9 +/* RTC_CNTL_ENCKINIT_XTAL_32K : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: apply an internal clock to help xtal 32k to start.*/ +#define RTC_CNTL_ENCKINIT_XTAL_32K (BIT(8)) +#define RTC_CNTL_ENCKINIT_XTAL_32K_M (BIT(8)) +#define RTC_CNTL_ENCKINIT_XTAL_32K_V 0x1 +#define RTC_CNTL_ENCKINIT_XTAL_32K_S 8 +/* RTC_CNTL_XTAL32K_XPD_FORCE : R/W ;bitpos:[7] ;default: 1'b1 ; */ +/*description: Xtal 32k xpd control by sw or fsm.*/ +#define RTC_CNTL_XTAL32K_XPD_FORCE (BIT(7)) +#define RTC_CNTL_XTAL32K_XPD_FORCE_M (BIT(7)) +#define RTC_CNTL_XTAL32K_XPD_FORCE_V 0x1 +#define RTC_CNTL_XTAL32K_XPD_FORCE_S 7 +/* RTC_CNTL_XTAL32K_AUTO_RETURN : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: xtal 32k switch back xtal when xtal is restarted.*/ +#define RTC_CNTL_XTAL32K_AUTO_RETURN (BIT(6)) +#define RTC_CNTL_XTAL32K_AUTO_RETURN_M (BIT(6)) +#define RTC_CNTL_XTAL32K_AUTO_RETURN_V 0x1 +#define RTC_CNTL_XTAL32K_AUTO_RETURN_S 6 +/* RTC_CNTL_XTAL32K_AUTO_RESTART : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: xtal 32k restart xtal when xtal is dead.*/ +#define RTC_CNTL_XTAL32K_AUTO_RESTART (BIT(5)) +#define RTC_CNTL_XTAL32K_AUTO_RESTART_M (BIT(5)) +#define RTC_CNTL_XTAL32K_AUTO_RESTART_V 0x1 +#define RTC_CNTL_XTAL32K_AUTO_RESTART_S 5 +/* RTC_CNTL_XTAL32K_AUTO_BACKUP : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: xtal 32k switch to back up clock when xtal is dead.*/ +#define RTC_CNTL_XTAL32K_AUTO_BACKUP (BIT(4)) +#define RTC_CNTL_XTAL32K_AUTO_BACKUP_M (BIT(4)) +#define RTC_CNTL_XTAL32K_AUTO_BACKUP_V 0x1 +#define RTC_CNTL_XTAL32K_AUTO_BACKUP_S 4 +/* RTC_CNTL_XTAL32K_EXT_CLK_FO : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: xtal 32k external xtal clock force on.*/ +#define RTC_CNTL_XTAL32K_EXT_CLK_FO (BIT(3)) +#define RTC_CNTL_XTAL32K_EXT_CLK_FO_M (BIT(3)) +#define RTC_CNTL_XTAL32K_EXT_CLK_FO_V 0x1 +#define RTC_CNTL_XTAL32K_EXT_CLK_FO_S 3 +/* RTC_CNTL_XTAL32K_WDT_RESET : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: xtal 32k watch dog sw reset.*/ +#define RTC_CNTL_XTAL32K_WDT_RESET (BIT(2)) +#define RTC_CNTL_XTAL32K_WDT_RESET_M (BIT(2)) +#define RTC_CNTL_XTAL32K_WDT_RESET_V 0x1 +#define RTC_CNTL_XTAL32K_WDT_RESET_S 2 +/* RTC_CNTL_XTAL32K_WDT_CLK_FO : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: xtal 32k watch dog clock force on.*/ +#define RTC_CNTL_XTAL32K_WDT_CLK_FO (BIT(1)) +#define RTC_CNTL_XTAL32K_WDT_CLK_FO_M (BIT(1)) +#define RTC_CNTL_XTAL32K_WDT_CLK_FO_V 0x1 +#define RTC_CNTL_XTAL32K_WDT_CLK_FO_S 1 +/* RTC_CNTL_XTAL32K_WDT_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: xtal 32k watch dog enable.*/ +#define RTC_CNTL_XTAL32K_WDT_EN (BIT(0)) +#define RTC_CNTL_XTAL32K_WDT_EN_M (BIT(0)) +#define RTC_CNTL_XTAL32K_WDT_EN_V 0x1 +#define RTC_CNTL_XTAL32K_WDT_EN_S 0 + +#define RTC_CNTL_EXT_WAKEUP_CONF_REG (DR_REG_RTCCNTL_BASE + 0x64) +/* RTC_CNTL_EXT_WAKEUP1_LV : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_EXT_WAKEUP1_LV (BIT(31)) +#define RTC_CNTL_EXT_WAKEUP1_LV_M (BIT(31)) +#define RTC_CNTL_EXT_WAKEUP1_LV_V 0x1 +#define RTC_CNTL_EXT_WAKEUP1_LV_S 31 +/* RTC_CNTL_EXT_WAKEUP0_LV : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: 0: external wakeup at low level.*/ +#define RTC_CNTL_EXT_WAKEUP0_LV (BIT(30)) +#define RTC_CNTL_EXT_WAKEUP0_LV_M (BIT(30)) +#define RTC_CNTL_EXT_WAKEUP0_LV_V 0x1 +#define RTC_CNTL_EXT_WAKEUP0_LV_S 30 +/* RTC_CNTL_GPIO_WAKEUP_FILTER : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: enable filter for gpio wakeup event.*/ +#define RTC_CNTL_GPIO_WAKEUP_FILTER (BIT(29)) +#define RTC_CNTL_GPIO_WAKEUP_FILTER_M (BIT(29)) +#define RTC_CNTL_GPIO_WAKEUP_FILTER_V 0x1 +#define RTC_CNTL_GPIO_WAKEUP_FILTER_S 29 + +#define RTC_CNTL_SLP_REJECT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x68) +/* RTC_CNTL_DEEP_SLP_REJECT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: enable reject for deep sleep.*/ +#define RTC_CNTL_DEEP_SLP_REJECT_EN (BIT(31)) +#define RTC_CNTL_DEEP_SLP_REJECT_EN_M (BIT(31)) +#define RTC_CNTL_DEEP_SLP_REJECT_EN_V 0x1 +#define RTC_CNTL_DEEP_SLP_REJECT_EN_S 31 +/* RTC_CNTL_LIGHT_SLP_REJECT_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: enable reject for light sleep.*/ +#define RTC_CNTL_LIGHT_SLP_REJECT_EN (BIT(30)) +#define RTC_CNTL_LIGHT_SLP_REJECT_EN_M (BIT(30)) +#define RTC_CNTL_LIGHT_SLP_REJECT_EN_V 0x1 +#define RTC_CNTL_LIGHT_SLP_REJECT_EN_S 30 +/* RTC_CNTL_SLEEP_REJECT_ENA : R/W ;bitpos:[29:12] ;default: 17'd0 ; */ +/*description: sleep reject enable.*/ +#define RTC_CNTL_SLEEP_REJECT_ENA 0x0003FFFF +#define RTC_CNTL_SLEEP_REJECT_ENA_M ((RTC_CNTL_SLEEP_REJECT_ENA_V)<<(RTC_CNTL_SLEEP_REJECT_ENA_S)) +#define RTC_CNTL_SLEEP_REJECT_ENA_V 0x3FFFF +#define RTC_CNTL_SLEEP_REJECT_ENA_S 12 + +#define RTC_CNTL_CPU_PERIOD_CONF_REG (DR_REG_RTCCNTL_BASE + 0x6C) +/* RTC_CNTL_CPUPERIOD_SEL : R/W ;bitpos:[31:30] ;default: 2'b00 ; */ +/*description: .*/ +#define RTC_CNTL_CPUPERIOD_SEL 0x00000003 +#define RTC_CNTL_CPUPERIOD_SEL_M ((RTC_CNTL_CPUPERIOD_SEL_V)<<(RTC_CNTL_CPUPERIOD_SEL_S)) +#define RTC_CNTL_CPUPERIOD_SEL_V 0x3 +#define RTC_CNTL_CPUPERIOD_SEL_S 30 +/* RTC_CNTL_CPUSEL_CONF : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: CPU sel option.*/ +#define RTC_CNTL_CPUSEL_CONF (BIT(29)) +#define RTC_CNTL_CPUSEL_CONF_M (BIT(29)) +#define RTC_CNTL_CPUSEL_CONF_V 0x1 +#define RTC_CNTL_CPUSEL_CONF_S 29 + +#define RTC_CNTL_SDIO_ACT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x70) +/* RTC_CNTL_SDIO_ACT_DNUM : R/W ;bitpos:[31:22] ;default: 10'b0 ; */ +/*description: .*/ +#define RTC_CNTL_SDIO_ACT_DNUM 0x000003FF +#define RTC_CNTL_SDIO_ACT_DNUM_M ((RTC_CNTL_SDIO_ACT_DNUM_V)<<(RTC_CNTL_SDIO_ACT_DNUM_S)) +#define RTC_CNTL_SDIO_ACT_DNUM_V 0x3FF +#define RTC_CNTL_SDIO_ACT_DNUM_S 22 + +#define RTC_CNTL_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x74) +/* RTC_CNTL_ANA_CLK_RTC_SEL : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ +/*description: .*/ +#define RTC_CNTL_ANA_CLK_RTC_SEL 0x00000003 +#define RTC_CNTL_ANA_CLK_RTC_SEL_M ((RTC_CNTL_ANA_CLK_RTC_SEL_V)<<(RTC_CNTL_ANA_CLK_RTC_SEL_S)) +#define RTC_CNTL_ANA_CLK_RTC_SEL_V 0x3 +#define RTC_CNTL_ANA_CLK_RTC_SEL_S 30 +/* RTC_CNTL_FAST_CLK_RTC_SEL : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: fast_clk_rtc sel. 0: XTAL div 2.*/ +#define RTC_CNTL_FAST_CLK_RTC_SEL (BIT(29)) +#define RTC_CNTL_FAST_CLK_RTC_SEL_M (BIT(29)) +#define RTC_CNTL_FAST_CLK_RTC_SEL_V 0x1 +#define RTC_CNTL_FAST_CLK_RTC_SEL_S 29 +/* RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING : R/W ;bitpos:[28] ;default: 1'b1 ; */ +/*description: .*/ +#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING (BIT(28)) +#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_M (BIT(28)) +#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_V 0x1 +#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_S 28 +/* RTC_CNTL_XTAL_GLOBAL_FORCE_GATING : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING (BIT(27)) +#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_M (BIT(27)) +#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_V 0x1 +#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_S 27 +/* RTC_CNTL_CK8M_FORCE_PU : R/W ;bitpos:[26] ;default: 1'd0 ; */ +/*description: CK8M force power up.*/ +#define RTC_CNTL_CK8M_FORCE_PU (BIT(26)) +#define RTC_CNTL_CK8M_FORCE_PU_M (BIT(26)) +#define RTC_CNTL_CK8M_FORCE_PU_V 0x1 +#define RTC_CNTL_CK8M_FORCE_PU_S 26 +/* RTC_CNTL_CK8M_FORCE_PD : R/W ;bitpos:[25] ;default: 1'd0 ; */ +/*description: CK8M force power down.*/ +#define RTC_CNTL_CK8M_FORCE_PD (BIT(25)) +#define RTC_CNTL_CK8M_FORCE_PD_M (BIT(25)) +#define RTC_CNTL_CK8M_FORCE_PD_V 0x1 +#define RTC_CNTL_CK8M_FORCE_PD_S 25 +/* RTC_CNTL_CK8M_DFREQ : R/W ;bitpos:[24:17] ;default: 8'd172 ; */ +/*description: CK8M_DFREQ.*/ +#define RTC_CNTL_CK8M_DFREQ 0x000000FF +#define RTC_CNTL_CK8M_DFREQ_M ((RTC_CNTL_CK8M_DFREQ_V)<<(RTC_CNTL_CK8M_DFREQ_S)) +#define RTC_CNTL_CK8M_DFREQ_V 0xFF +#define RTC_CNTL_CK8M_DFREQ_S 17 +/* RTC_CNTL_CK8M_FORCE_NOGATING : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: CK8M force no gating during sleep.*/ +#define RTC_CNTL_CK8M_FORCE_NOGATING (BIT(16)) +#define RTC_CNTL_CK8M_FORCE_NOGATING_M (BIT(16)) +#define RTC_CNTL_CK8M_FORCE_NOGATING_V 0x1 +#define RTC_CNTL_CK8M_FORCE_NOGATING_S 16 +/* RTC_CNTL_XTAL_FORCE_NOGATING : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: XTAL force no gating during sleep.*/ +#define RTC_CNTL_XTAL_FORCE_NOGATING (BIT(15)) +#define RTC_CNTL_XTAL_FORCE_NOGATING_M (BIT(15)) +#define RTC_CNTL_XTAL_FORCE_NOGATING_V 0x1 +#define RTC_CNTL_XTAL_FORCE_NOGATING_S 15 +/* RTC_CNTL_CK8M_DIV_SEL : R/W ;bitpos:[14:12] ;default: 3'd3 ; */ +/*description: divider = reg_ck8m_div_sel + 1.*/ +#define RTC_CNTL_CK8M_DIV_SEL 0x00000007 +#define RTC_CNTL_CK8M_DIV_SEL_M ((RTC_CNTL_CK8M_DIV_SEL_V)<<(RTC_CNTL_CK8M_DIV_SEL_S)) +#define RTC_CNTL_CK8M_DIV_SEL_V 0x7 +#define RTC_CNTL_CK8M_DIV_SEL_S 12 +/* RTC_CNTL_DIG_CLK8M_EN : R/W ;bitpos:[10] ;default: 1'd0 ; */ +/*description: enable CK8M for digital core (no relationship with RTC core).*/ +#define RTC_CNTL_DIG_CLK8M_EN (BIT(10)) +#define RTC_CNTL_DIG_CLK8M_EN_M (BIT(10)) +#define RTC_CNTL_DIG_CLK8M_EN_V 0x1 +#define RTC_CNTL_DIG_CLK8M_EN_S 10 +/* RTC_CNTL_DIG_CLK8M_D256_EN : R/W ;bitpos:[9] ;default: 1'd1 ; */ +/*description: enable CK8M_D256_OUT for digital core (no relationship with RTC core).*/ +#define RTC_CNTL_DIG_CLK8M_D256_EN (BIT(9)) +#define RTC_CNTL_DIG_CLK8M_D256_EN_M (BIT(9)) +#define RTC_CNTL_DIG_CLK8M_D256_EN_V 0x1 +#define RTC_CNTL_DIG_CLK8M_D256_EN_S 9 +/* RTC_CNTL_DIG_XTAL32K_EN : R/W ;bitpos:[8] ;default: 1'd0 ; */ +/*description: enable CK_XTAL_32K for digital core (no relationship with RTC core).*/ +#define RTC_CNTL_DIG_XTAL32K_EN (BIT(8)) +#define RTC_CNTL_DIG_XTAL32K_EN_M (BIT(8)) +#define RTC_CNTL_DIG_XTAL32K_EN_V 0x1 +#define RTC_CNTL_DIG_XTAL32K_EN_S 8 +/* RTC_CNTL_ENB_CK8M_DIV : R/W ;bitpos:[7] ;default: 1'd0 ; */ +/*description: 1: CK8M_D256_OUT is actually CK8M.*/ +#define RTC_CNTL_ENB_CK8M_DIV (BIT(7)) +#define RTC_CNTL_ENB_CK8M_DIV_M (BIT(7)) +#define RTC_CNTL_ENB_CK8M_DIV_V 0x1 +#define RTC_CNTL_ENB_CK8M_DIV_S 7 +/* RTC_CNTL_ENB_CK8M : R/W ;bitpos:[6] ;default: 1'd0 ; */ +/*description: disable CK8M and CK8M_D256_OUT.*/ +#define RTC_CNTL_ENB_CK8M (BIT(6)) +#define RTC_CNTL_ENB_CK8M_M (BIT(6)) +#define RTC_CNTL_ENB_CK8M_V 0x1 +#define RTC_CNTL_ENB_CK8M_S 6 +/* RTC_CNTL_CK8M_DIV : R/W ;bitpos:[5:4] ;default: 2'b01 ; */ +/*description: CK8M_D256_OUT divider. 00: div128.*/ +#define RTC_CNTL_CK8M_DIV 0x00000003 +#define RTC_CNTL_CK8M_DIV_M ((RTC_CNTL_CK8M_DIV_V)<<(RTC_CNTL_CK8M_DIV_S)) +#define RTC_CNTL_CK8M_DIV_V 0x3 +#define RTC_CNTL_CK8M_DIV_S 4 +/* RTC_CNTL_CK8M_DIV_SEL_VLD : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel.*/ +#define RTC_CNTL_CK8M_DIV_SEL_VLD (BIT(3)) +#define RTC_CNTL_CK8M_DIV_SEL_VLD_M (BIT(3)) +#define RTC_CNTL_CK8M_DIV_SEL_VLD_V 0x1 +#define RTC_CNTL_CK8M_DIV_SEL_VLD_S 3 +/* RTC_CNTL_EFUSE_CLK_FORCE_NOGATING : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: .*/ +#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING (BIT(2)) +#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_M (BIT(2)) +#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_V 0x1 +#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_S 2 +/* RTC_CNTL_EFUSE_CLK_FORCE_GATING : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_EFUSE_CLK_FORCE_GATING (BIT(1)) +#define RTC_CNTL_EFUSE_CLK_FORCE_GATING_M (BIT(1)) +#define RTC_CNTL_EFUSE_CLK_FORCE_GATING_V 0x1 +#define RTC_CNTL_EFUSE_CLK_FORCE_GATING_S 1 + +#define RTC_CNTL_SLOW_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x78) +/* RTC_CNTL_SLOW_CLK_NEXT_EDGE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_SLOW_CLK_NEXT_EDGE (BIT(31)) +#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_M (BIT(31)) +#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_V 0x1 +#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_S 31 +/* RTC_CNTL_ANA_CLK_DIV : R/W ;bitpos:[30:23] ;default: 8'd0 ; */ +/*description: .*/ +#define RTC_CNTL_ANA_CLK_DIV 0x000000FF +#define RTC_CNTL_ANA_CLK_DIV_M ((RTC_CNTL_ANA_CLK_DIV_V)<<(RTC_CNTL_ANA_CLK_DIV_S)) +#define RTC_CNTL_ANA_CLK_DIV_V 0xFF +#define RTC_CNTL_ANA_CLK_DIV_S 23 +/* RTC_CNTL_ANA_CLK_DIV_VLD : R/W ;bitpos:[22] ;default: 1'b1 ; */ +/*description: used to sync div bus. clear vld before set reg_rtc_ana_clk_div.*/ +#define RTC_CNTL_ANA_CLK_DIV_VLD (BIT(22)) +#define RTC_CNTL_ANA_CLK_DIV_VLD_M (BIT(22)) +#define RTC_CNTL_ANA_CLK_DIV_VLD_V 0x1 +#define RTC_CNTL_ANA_CLK_DIV_VLD_S 22 + +#define RTC_CNTL_SDIO_CONF_REG (DR_REG_RTCCNTL_BASE + 0x7C) +/* RTC_CNTL_XPD_SDIO_REG : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: .*/ +#define RTC_CNTL_XPD_SDIO_REG (BIT(31)) +#define RTC_CNTL_XPD_SDIO_REG_M (BIT(31)) +#define RTC_CNTL_XPD_SDIO_REG_V 0x1 +#define RTC_CNTL_XPD_SDIO_REG_S 31 +/* RTC_CNTL_DREFH_SDIO : R/W ;bitpos:[30:29] ;default: 2'b00 ; */ +/*description: SW option for DREFH_SDIO. Only active when reg_sdio_force = 1.*/ +#define RTC_CNTL_DREFH_SDIO 0x00000003 +#define RTC_CNTL_DREFH_SDIO_M ((RTC_CNTL_DREFH_SDIO_V)<<(RTC_CNTL_DREFH_SDIO_S)) +#define RTC_CNTL_DREFH_SDIO_V 0x3 +#define RTC_CNTL_DREFH_SDIO_S 29 +/* RTC_CNTL_DREFM_SDIO : R/W ;bitpos:[28:27] ;default: 2'b01 ; */ +/*description: SW option for DREFM_SDIO. Only active when reg_sdio_force = 1.*/ +#define RTC_CNTL_DREFM_SDIO 0x00000003 +#define RTC_CNTL_DREFM_SDIO_M ((RTC_CNTL_DREFM_SDIO_V)<<(RTC_CNTL_DREFM_SDIO_S)) +#define RTC_CNTL_DREFM_SDIO_V 0x3 +#define RTC_CNTL_DREFM_SDIO_S 27 +/* RTC_CNTL_DREFL_SDIO : R/W ;bitpos:[26:25] ;default: 2'b01 ; */ +/*description: SW option for DREFL_SDIO. Only active when reg_sdio_force = 1.*/ +#define RTC_CNTL_DREFL_SDIO 0x00000003 +#define RTC_CNTL_DREFL_SDIO_M ((RTC_CNTL_DREFL_SDIO_V)<<(RTC_CNTL_DREFL_SDIO_S)) +#define RTC_CNTL_DREFL_SDIO_V 0x3 +#define RTC_CNTL_DREFL_SDIO_S 25 +/* RTC_CNTL_REG1P8_READY : RO ;bitpos:[24] ;default: 1'd0 ; */ +/*description: read only register for REG1P8_READY.*/ +#define RTC_CNTL_REG1P8_READY (BIT(24)) +#define RTC_CNTL_REG1P8_READY_M (BIT(24)) +#define RTC_CNTL_REG1P8_READY_V 0x1 +#define RTC_CNTL_REG1P8_READY_S 24 +/* RTC_CNTL_SDIO_TIEH : R/W ;bitpos:[23] ;default: 1'd1 ; */ +/*description: SW option for SDIO_TIEH. Only active when reg_sdio_force = 1.*/ +#define RTC_CNTL_SDIO_TIEH (BIT(23)) +#define RTC_CNTL_SDIO_TIEH_M (BIT(23)) +#define RTC_CNTL_SDIO_TIEH_V 0x1 +#define RTC_CNTL_SDIO_TIEH_S 23 +/* RTC_CNTL_SDIO_FORCE : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: 1: use SW option to control SDIO_REG.*/ +#define RTC_CNTL_SDIO_FORCE (BIT(22)) +#define RTC_CNTL_SDIO_FORCE_M (BIT(22)) +#define RTC_CNTL_SDIO_FORCE_V 0x1 +#define RTC_CNTL_SDIO_FORCE_S 22 +/* RTC_CNTL_SDIO_PD_EN : R/W ;bitpos:[21] ;default: 1'd1 ; */ +/*description: power down SDIO_REG in sleep. Only active when reg_sdio_force = 0.*/ +#define RTC_CNTL_SDIO_PD_EN (BIT(21)) +#define RTC_CNTL_SDIO_PD_EN_M (BIT(21)) +#define RTC_CNTL_SDIO_PD_EN_V 0x1 +#define RTC_CNTL_SDIO_PD_EN_S 21 +/* RTC_CNTL_SDIO_ENCURLIM : R/W ;bitpos:[20] ;default: 1'd1 ; */ +/*description: enable current limit.*/ +#define RTC_CNTL_SDIO_ENCURLIM (BIT(20)) +#define RTC_CNTL_SDIO_ENCURLIM_M (BIT(20)) +#define RTC_CNTL_SDIO_ENCURLIM_V 0x1 +#define RTC_CNTL_SDIO_ENCURLIM_S 20 +/* RTC_CNTL_SDIO_MODECURLIM : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: select current limit mode.*/ +#define RTC_CNTL_SDIO_MODECURLIM (BIT(19)) +#define RTC_CNTL_SDIO_MODECURLIM_M (BIT(19)) +#define RTC_CNTL_SDIO_MODECURLIM_V 0x1 +#define RTC_CNTL_SDIO_MODECURLIM_S 19 +/* RTC_CNTL_SDIO_DCURLIM : R/W ;bitpos:[18:16] ;default: 3'd0 ; */ +/*description: tune current limit threshold when tieh = 0. About 800mA/(8+d).*/ +#define RTC_CNTL_SDIO_DCURLIM 0x00000007 +#define RTC_CNTL_SDIO_DCURLIM_M ((RTC_CNTL_SDIO_DCURLIM_V)<<(RTC_CNTL_SDIO_DCURLIM_S)) +#define RTC_CNTL_SDIO_DCURLIM_V 0x7 +#define RTC_CNTL_SDIO_DCURLIM_S 16 +/* RTC_CNTL_SDIO_EN_INITI : R/W ;bitpos:[15] ;default: 1'd1 ; */ +/*description: 0 to set init[1:0]=0.*/ +#define RTC_CNTL_SDIO_EN_INITI (BIT(15)) +#define RTC_CNTL_SDIO_EN_INITI_M (BIT(15)) +#define RTC_CNTL_SDIO_EN_INITI_V 0x1 +#define RTC_CNTL_SDIO_EN_INITI_S 15 +/* RTC_CNTL_SDIO_INITI : R/W ;bitpos:[14:13] ;default: 2'd1 ; */ +/*description: add resistor from ldo output to ground. 0: no res.*/ +#define RTC_CNTL_SDIO_INITI 0x00000003 +#define RTC_CNTL_SDIO_INITI_M ((RTC_CNTL_SDIO_INITI_V)<<(RTC_CNTL_SDIO_INITI_S)) +#define RTC_CNTL_SDIO_INITI_V 0x3 +#define RTC_CNTL_SDIO_INITI_S 13 +/* RTC_CNTL_SDIO_DCAP : R/W ;bitpos:[12:11] ;default: 2'b11 ; */ +/*description: ability to prevent LDO from overshoot.*/ +#define RTC_CNTL_SDIO_DCAP 0x00000003 +#define RTC_CNTL_SDIO_DCAP_M ((RTC_CNTL_SDIO_DCAP_V)<<(RTC_CNTL_SDIO_DCAP_S)) +#define RTC_CNTL_SDIO_DCAP_V 0x3 +#define RTC_CNTL_SDIO_DCAP_S 11 +/* RTC_CNTL_SDIO_DTHDRV : R/W ;bitpos:[10:9] ;default: 2'b11 ; */ +/*description: Tieh = 1 mode drive ability. Initially set to 0 to limit charge current.*/ +#define RTC_CNTL_SDIO_DTHDRV 0x00000003 +#define RTC_CNTL_SDIO_DTHDRV_M ((RTC_CNTL_SDIO_DTHDRV_V)<<(RTC_CNTL_SDIO_DTHDRV_S)) +#define RTC_CNTL_SDIO_DTHDRV_V 0x3 +#define RTC_CNTL_SDIO_DTHDRV_S 9 +/* RTC_CNTL_SDIO_TIMER_TARGET : R/W ;bitpos:[7:0] ;default: 8'd10 ; */ +/*description: timer count to apply reg_sdio_dcap after sdio power on.*/ +#define RTC_CNTL_SDIO_TIMER_TARGET 0x000000FF +#define RTC_CNTL_SDIO_TIMER_TARGET_M ((RTC_CNTL_SDIO_TIMER_TARGET_V)<<(RTC_CNTL_SDIO_TIMER_TARGET_S)) +#define RTC_CNTL_SDIO_TIMER_TARGET_V 0xFF +#define RTC_CNTL_SDIO_TIMER_TARGET_S 0 + +#define RTC_CNTL_BIAS_CONF_REG (DR_REG_RTCCNTL_BASE + 0x80) +/* RTC_CNTL_DBG_ATTEN_WAKEUP : R/W ;bitpos:[29:26] ;default: 4'd0 ; */ +/*description: .*/ +#define RTC_CNTL_DBG_ATTEN_WAKEUP 0x0000000F +#define RTC_CNTL_DBG_ATTEN_WAKEUP_M ((RTC_CNTL_DBG_ATTEN_WAKEUP_V)<<(RTC_CNTL_DBG_ATTEN_WAKEUP_S)) +#define RTC_CNTL_DBG_ATTEN_WAKEUP_V 0xF +#define RTC_CNTL_DBG_ATTEN_WAKEUP_S 26 +/* RTC_CNTL_DBG_ATTEN_MONITOR : R/W ;bitpos:[25:22] ;default: 4'd0 ; */ +/*description: DBG_ATTEN when rtc in monitor state.*/ +#define RTC_CNTL_DBG_ATTEN_MONITOR 0x0000000F +#define RTC_CNTL_DBG_ATTEN_MONITOR_M ((RTC_CNTL_DBG_ATTEN_MONITOR_V)<<(RTC_CNTL_DBG_ATTEN_MONITOR_S)) +#define RTC_CNTL_DBG_ATTEN_MONITOR_V 0xF +#define RTC_CNTL_DBG_ATTEN_MONITOR_S 22 +/* RTC_CNTL_DBG_ATTEN_DEEP_SLP : R/W ;bitpos:[21:18] ;default: 4'd0 ; */ +/*description: DBG_ATTEN when rtc in sleep state.*/ +#define RTC_CNTL_DBG_ATTEN_DEEP_SLP 0x0000000F +#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_M ((RTC_CNTL_DBG_ATTEN_DEEP_SLP_V)<<(RTC_CNTL_DBG_ATTEN_DEEP_SLP_S)) +#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_V 0xF +#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_S 18 +/* RTC_CNTL_BIAS_SLEEP_MONITOR : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: bias_sleep when rtc in monitor state.*/ +#define RTC_CNTL_BIAS_SLEEP_MONITOR (BIT(17)) +#define RTC_CNTL_BIAS_SLEEP_MONITOR_M (BIT(17)) +#define RTC_CNTL_BIAS_SLEEP_MONITOR_V 0x1 +#define RTC_CNTL_BIAS_SLEEP_MONITOR_S 17 +/* RTC_CNTL_BIAS_SLEEP_DEEP_SLP : R/W ;bitpos:[16] ;default: 1'b1 ; */ +/*description: bias_sleep when rtc in sleep_state.*/ +#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP (BIT(16)) +#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_M (BIT(16)) +#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_V 0x1 +#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_S 16 +/* RTC_CNTL_PD_CUR_MONITOR : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: xpd cur when rtc in monitor state.*/ +#define RTC_CNTL_PD_CUR_MONITOR (BIT(15)) +#define RTC_CNTL_PD_CUR_MONITOR_M (BIT(15)) +#define RTC_CNTL_PD_CUR_MONITOR_V 0x1 +#define RTC_CNTL_PD_CUR_MONITOR_S 15 +/* RTC_CNTL_PD_CUR_DEEP_SLP : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: xpd cur when rtc in sleep_state.*/ +#define RTC_CNTL_PD_CUR_DEEP_SLP (BIT(14)) +#define RTC_CNTL_PD_CUR_DEEP_SLP_M (BIT(14)) +#define RTC_CNTL_PD_CUR_DEEP_SLP_V 0x1 +#define RTC_CNTL_PD_CUR_DEEP_SLP_S 14 +/* RTC_CNTL_BIAS_BUF_MONITOR : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_BIAS_BUF_MONITOR (BIT(13)) +#define RTC_CNTL_BIAS_BUF_MONITOR_M (BIT(13)) +#define RTC_CNTL_BIAS_BUF_MONITOR_V 0x1 +#define RTC_CNTL_BIAS_BUF_MONITOR_S 13 +/* RTC_CNTL_BIAS_BUF_DEEP_SLP : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_BIAS_BUF_DEEP_SLP (BIT(12)) +#define RTC_CNTL_BIAS_BUF_DEEP_SLP_M (BIT(12)) +#define RTC_CNTL_BIAS_BUF_DEEP_SLP_V 0x1 +#define RTC_CNTL_BIAS_BUF_DEEP_SLP_S 12 +/* RTC_CNTL_BIAS_BUF_WAKE : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: .*/ +#define RTC_CNTL_BIAS_BUF_WAKE (BIT(11)) +#define RTC_CNTL_BIAS_BUF_WAKE_M (BIT(11)) +#define RTC_CNTL_BIAS_BUF_WAKE_V 0x1 +#define RTC_CNTL_BIAS_BUF_WAKE_S 11 +/* RTC_CNTL_BIAS_BUF_IDLE : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_BIAS_BUF_IDLE (BIT(10)) +#define RTC_CNTL_BIAS_BUF_IDLE_M (BIT(10)) +#define RTC_CNTL_BIAS_BUF_IDLE_V 0x1 +#define RTC_CNTL_BIAS_BUF_IDLE_S 10 + +#define RTC_CNTL_REG (DR_REG_RTCCNTL_BASE + 0x84) +/* RTC_CNTL_REGULATOR_FORCE_PU : R/W ;bitpos:[31] ;default: 1'd1 ; */ +/*description: .*/ +#define RTC_CNTL_REGULATOR_FORCE_PU (BIT(31)) +#define RTC_CNTL_REGULATOR_FORCE_PU_M (BIT(31)) +#define RTC_CNTL_REGULATOR_FORCE_PU_V 0x1 +#define RTC_CNTL_REGULATOR_FORCE_PU_S 31 +/* RTC_CNTL_REGULATOR_FORCE_PD : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0 +.8v or lower ).*/ +#define RTC_CNTL_REGULATOR_FORCE_PD (BIT(30)) +#define RTC_CNTL_REGULATOR_FORCE_PD_M (BIT(30)) +#define RTC_CNTL_REGULATOR_FORCE_PD_V 0x1 +#define RTC_CNTL_REGULATOR_FORCE_PD_S 30 +/* RTC_CNTL_DBOOST_FORCE_PU : R/W ;bitpos:[29] ;default: 1'd1 ; */ +/*description: RTC_DBOOST force power up.*/ +#define RTC_CNTL_DBOOST_FORCE_PU (BIT(29)) +#define RTC_CNTL_DBOOST_FORCE_PU_M (BIT(29)) +#define RTC_CNTL_DBOOST_FORCE_PU_V 0x1 +#define RTC_CNTL_DBOOST_FORCE_PU_S 29 +/* RTC_CNTL_DBOOST_FORCE_PD : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: RTC_DBOOST force power down.*/ +#define RTC_CNTL_DBOOST_FORCE_PD (BIT(28)) +#define RTC_CNTL_DBOOST_FORCE_PD_M (BIT(28)) +#define RTC_CNTL_DBOOST_FORCE_PD_V 0x1 +#define RTC_CNTL_DBOOST_FORCE_PD_S 28 +/* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP, + * RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values. + * Valid if RTC_CNTL_DBG_ATTEN is 0. + */ +#define RTC_CNTL_DIG_DBIAS_0V85 0 +#define RTC_CNTL_DIG_DBIAS_0V90 1 +#define RTC_CNTL_DIG_DBIAS_0V95 2 +#define RTC_CNTL_DIG_DBIAS_1V00 3 +#define RTC_CNTL_DIG_DBIAS_1V05 4 +#define RTC_CNTL_DIG_DBIAS_1V10 5 +#define RTC_CNTL_DIG_DBIAS_1V15 6 +#define RTC_CNTL_DIG_DBIAS_1V20 7 + +/* RTC_CNTL_SCK_DCAP : R/W ;bitpos:[21:14] ;default: 8'd0 ; */ +/*description: SCK_DCAP.*/ +#define RTC_CNTL_SCK_DCAP 0x000000FF +#define RTC_CNTL_SCK_DCAP_M ((RTC_CNTL_SCK_DCAP_V)<<(RTC_CNTL_SCK_DCAP_S)) +#define RTC_CNTL_SCK_DCAP_V 0xFF +#define RTC_CNTL_SCK_DCAP_S 14 +/* RTC_CNTL_DIG_CAL_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_DIG_CAL_EN (BIT(7)) +#define RTC_CNTL_DIG_CAL_EN_M (BIT(7)) +#define RTC_CNTL_DIG_CAL_EN_V 0x1 +#define RTC_CNTL_DIG_CAL_EN_S 7 + +#define RTC_CNTL_PWC_REG (DR_REG_RTCCNTL_BASE + 0x88) +/* RTC_CNTL_PAD_FORCE_HOLD : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: rtc pad force hold.*/ +#define RTC_CNTL_PAD_FORCE_HOLD (BIT(21)) +#define RTC_CNTL_PAD_FORCE_HOLD_M (BIT(21)) +#define RTC_CNTL_PAD_FORCE_HOLD_V 0x1 +#define RTC_CNTL_PAD_FORCE_HOLD_S 21 +/* RTC_CNTL_PD_EN : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: enable power down rtc_peri in sleep .*/ +#define RTC_CNTL_PD_EN (BIT(20)) +#define RTC_CNTL_PD_EN_M (BIT(20)) +#define RTC_CNTL_PD_EN_V 0x1 +#define RTC_CNTL_PD_EN_S 20 +/* RTC_CNTL_FORCE_PU : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: rtc_peri force power up.*/ +#define RTC_CNTL_FORCE_PU (BIT(19)) +#define RTC_CNTL_FORCE_PU_M (BIT(19)) +#define RTC_CNTL_FORCE_PU_V 0x1 +#define RTC_CNTL_FORCE_PU_S 19 +/* RTC_CNTL_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: rtc_peri force power down.*/ +#define RTC_CNTL_FORCE_PD (BIT(18)) +#define RTC_CNTL_FORCE_PD_M (BIT(18)) +#define RTC_CNTL_FORCE_PD_V 0x1 +#define RTC_CNTL_FORCE_PD_S 18 +/* RTC_CNTL_SLOWMEM_FORCE_LPU : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: RTC memory force no PD.*/ +#define RTC_CNTL_SLOWMEM_FORCE_LPU (BIT(11)) +#define RTC_CNTL_SLOWMEM_FORCE_LPU_M (BIT(11)) +#define RTC_CNTL_SLOWMEM_FORCE_LPU_V 0x1 +#define RTC_CNTL_SLOWMEM_FORCE_LPU_S 11 +/* RTC_CNTL_SLOWMEM_FORCE_LPD : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: RTC memory force PD.*/ +#define RTC_CNTL_SLOWMEM_FORCE_LPD (BIT(10)) +#define RTC_CNTL_SLOWMEM_FORCE_LPD_M (BIT(10)) +#define RTC_CNTL_SLOWMEM_FORCE_LPD_V 0x1 +#define RTC_CNTL_SLOWMEM_FORCE_LPD_S 10 +/* RTC_CNTL_SLOWMEM_FOLW_CPU : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: 1: RTC memory PD following CPU.*/ +#define RTC_CNTL_SLOWMEM_FOLW_CPU (BIT(9)) +#define RTC_CNTL_SLOWMEM_FOLW_CPU_M (BIT(9)) +#define RTC_CNTL_SLOWMEM_FOLW_CPU_V 0x1 +#define RTC_CNTL_SLOWMEM_FOLW_CPU_S 9 +/* RTC_CNTL_FASTMEM_FORCE_LPU : R/W ;bitpos:[8] ;default: 1'b1 ; */ +/*description: Fast RTC memory force no PD.*/ +#define RTC_CNTL_FASTMEM_FORCE_LPU (BIT(8)) +#define RTC_CNTL_FASTMEM_FORCE_LPU_M (BIT(8)) +#define RTC_CNTL_FASTMEM_FORCE_LPU_V 0x1 +#define RTC_CNTL_FASTMEM_FORCE_LPU_S 8 +/* RTC_CNTL_FASTMEM_FORCE_LPD : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Fast RTC memory force PD.*/ +#define RTC_CNTL_FASTMEM_FORCE_LPD (BIT(7)) +#define RTC_CNTL_FASTMEM_FORCE_LPD_M (BIT(7)) +#define RTC_CNTL_FASTMEM_FORCE_LPD_V 0x1 +#define RTC_CNTL_FASTMEM_FORCE_LPD_S 7 +/* RTC_CNTL_FASTMEM_FOLW_CPU : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: 1: Fast RTC memory PD following CPU.*/ +#define RTC_CNTL_FASTMEM_FOLW_CPU (BIT(6)) +#define RTC_CNTL_FASTMEM_FOLW_CPU_M (BIT(6)) +#define RTC_CNTL_FASTMEM_FOLW_CPU_V 0x1 +#define RTC_CNTL_FASTMEM_FOLW_CPU_S 6 +/* RTC_CNTL_FORCE_NOISO : R/W ;bitpos:[5] ;default: 1'd1 ; */ +/*description: rtc_peri force no ISO.*/ +#define RTC_CNTL_FORCE_NOISO (BIT(5)) +#define RTC_CNTL_FORCE_NOISO_M (BIT(5)) +#define RTC_CNTL_FORCE_NOISO_V 0x1 +#define RTC_CNTL_FORCE_NOISO_S 5 +/* RTC_CNTL_FORCE_ISO : R/W ;bitpos:[4] ;default: 1'd0 ; */ +/*description: rtc_peri force ISO.*/ +#define RTC_CNTL_FORCE_ISO (BIT(4)) +#define RTC_CNTL_FORCE_ISO_M (BIT(4)) +#define RTC_CNTL_FORCE_ISO_V 0x1 +#define RTC_CNTL_FORCE_ISO_S 4 +/* RTC_CNTL_SLOWMEM_FORCE_ISO : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: RTC memory force ISO.*/ +#define RTC_CNTL_SLOWMEM_FORCE_ISO (BIT(3)) +#define RTC_CNTL_SLOWMEM_FORCE_ISO_M (BIT(3)) +#define RTC_CNTL_SLOWMEM_FORCE_ISO_V 0x1 +#define RTC_CNTL_SLOWMEM_FORCE_ISO_S 3 +/* RTC_CNTL_SLOWMEM_FORCE_NOISO : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: RTC memory force no ISO.*/ +#define RTC_CNTL_SLOWMEM_FORCE_NOISO (BIT(2)) +#define RTC_CNTL_SLOWMEM_FORCE_NOISO_M (BIT(2)) +#define RTC_CNTL_SLOWMEM_FORCE_NOISO_V 0x1 +#define RTC_CNTL_SLOWMEM_FORCE_NOISO_S 2 +/* RTC_CNTL_FASTMEM_FORCE_ISO : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Fast RTC memory force ISO.*/ +#define RTC_CNTL_FASTMEM_FORCE_ISO (BIT(1)) +#define RTC_CNTL_FASTMEM_FORCE_ISO_M (BIT(1)) +#define RTC_CNTL_FASTMEM_FORCE_ISO_V 0x1 +#define RTC_CNTL_FASTMEM_FORCE_ISO_S 1 +/* RTC_CNTL_FASTMEM_FORCE_NOISO : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: Fast RTC memory force no ISO.*/ +#define RTC_CNTL_FASTMEM_FORCE_NOISO (BIT(0)) +#define RTC_CNTL_FASTMEM_FORCE_NOISO_M (BIT(0)) +#define RTC_CNTL_FASTMEM_FORCE_NOISO_V 0x1 +#define RTC_CNTL_FASTMEM_FORCE_NOISO_S 0 + +#define RTC_CNTL_REGULATOR_DRV_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x8C) +/* RTC_CNTL_DG_VDD_DRV_B_MONITOR : R/W ;bitpos:[27:20] ;default: 8'h0 ; */ +/*description: .*/ +#define RTC_CNTL_DG_VDD_DRV_B_MONITOR 0x000000FF +#define RTC_CNTL_DG_VDD_DRV_B_MONITOR_M ((RTC_CNTL_DG_VDD_DRV_B_MONITOR_V)<<(RTC_CNTL_DG_VDD_DRV_B_MONITOR_S)) +#define RTC_CNTL_DG_VDD_DRV_B_MONITOR_V 0xFF +#define RTC_CNTL_DG_VDD_DRV_B_MONITOR_S 20 +/* RTC_CNTL_DG_VDD_DRV_B_SLP : R/W ;bitpos:[19:12] ;default: 8'h0 ; */ +/*description: .*/ +#define RTC_CNTL_DG_VDD_DRV_B_SLP 0x000000FF +#define RTC_CNTL_DG_VDD_DRV_B_SLP_M ((RTC_CNTL_DG_VDD_DRV_B_SLP_V)<<(RTC_CNTL_DG_VDD_DRV_B_SLP_S)) +#define RTC_CNTL_DG_VDD_DRV_B_SLP_V 0xFF +#define RTC_CNTL_DG_VDD_DRV_B_SLP_S 12 +/* RTC_CNTL_REGULATOR_DRV_B_SLP : R/W ;bitpos:[11:6] ;default: 6'b0 ; */ +/*description: .*/ +#define RTC_CNTL_REGULATOR_DRV_B_SLP 0x0000003F +#define RTC_CNTL_REGULATOR_DRV_B_SLP_M ((RTC_CNTL_REGULATOR_DRV_B_SLP_V)<<(RTC_CNTL_REGULATOR_DRV_B_SLP_S)) +#define RTC_CNTL_REGULATOR_DRV_B_SLP_V 0x3F +#define RTC_CNTL_REGULATOR_DRV_B_SLP_S 6 +/* RTC_CNTL_REGULATOR_DRV_B_MONITOR : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: .*/ +#define RTC_CNTL_REGULATOR_DRV_B_MONITOR 0x0000003F +#define RTC_CNTL_REGULATOR_DRV_B_MONITOR_M ((RTC_CNTL_REGULATOR_DRV_B_MONITOR_V)<<(RTC_CNTL_REGULATOR_DRV_B_MONITOR_S)) +#define RTC_CNTL_REGULATOR_DRV_B_MONITOR_V 0x3F +#define RTC_CNTL_REGULATOR_DRV_B_MONITOR_S 0 + +#define RTC_CNTL_DIG_PWC_REG (DR_REG_RTCCNTL_BASE + 0x90) +/* RTC_CNTL_DG_WRAP_PD_EN : R/W ;bitpos:[31] ;default: 0 ; */ +/*description: .*/ +#define RTC_CNTL_DG_WRAP_PD_EN (BIT(31)) +#define RTC_CNTL_DG_WRAP_PD_EN_M (BIT(31)) +#define RTC_CNTL_DG_WRAP_PD_EN_V 0x1 +#define RTC_CNTL_DG_WRAP_PD_EN_S 31 +/* RTC_CNTL_WIFI_PD_EN : R/W ;bitpos:[30] ;default: 0 ; */ +/*description: enable power down wifi in sleep.*/ +#define RTC_CNTL_WIFI_PD_EN (BIT(30)) +#define RTC_CNTL_WIFI_PD_EN_M (BIT(30)) +#define RTC_CNTL_WIFI_PD_EN_V 0x1 +#define RTC_CNTL_WIFI_PD_EN_S 30 +/* RTC_CNTL_CPU_TOP_PD_EN : R/W ;bitpos:[29] ;default: 0 ; */ +/*description: enable power down internal SRAM 4 in sleep.*/ +#define RTC_CNTL_CPU_TOP_PD_EN (BIT(29)) +#define RTC_CNTL_CPU_TOP_PD_EN_M (BIT(29)) +#define RTC_CNTL_CPU_TOP_PD_EN_V 0x1 +#define RTC_CNTL_CPU_TOP_PD_EN_S 29 +/* RTC_CNTL_DG_PERI_PD_EN : R/W ;bitpos:[28] ;default: 0 ; */ +/*description: enable power down internal SRAM 3 in sleep.*/ +#define RTC_CNTL_DG_PERI_PD_EN (BIT(28)) +#define RTC_CNTL_DG_PERI_PD_EN_M (BIT(28)) +#define RTC_CNTL_DG_PERI_PD_EN_V 0x1 +#define RTC_CNTL_DG_PERI_PD_EN_S 28 +/* RTC_CNTL_CPU_TOP_FORCE_PU : R/W ;bitpos:[22] ;default: 1'd1 ; */ +/*description: digital dcdc force power up.*/ +#define RTC_CNTL_CPU_TOP_FORCE_PU (BIT(22)) +#define RTC_CNTL_CPU_TOP_FORCE_PU_M (BIT(22)) +#define RTC_CNTL_CPU_TOP_FORCE_PU_V 0x1 +#define RTC_CNTL_CPU_TOP_FORCE_PU_S 22 +/* RTC_CNTL_CPU_TOP_FORCE_PD : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: digital dcdc force power down.*/ +#define RTC_CNTL_CPU_TOP_FORCE_PD (BIT(21)) +#define RTC_CNTL_CPU_TOP_FORCE_PD_M (BIT(21)) +#define RTC_CNTL_CPU_TOP_FORCE_PD_V 0x1 +#define RTC_CNTL_CPU_TOP_FORCE_PD_S 21 +/* RTC_CNTL_DG_WRAP_FORCE_PU : R/W ;bitpos:[20] ;default: 1'd1 ; */ +/*description: digital core force power up.*/ +#define RTC_CNTL_DG_WRAP_FORCE_PU (BIT(20)) +#define RTC_CNTL_DG_WRAP_FORCE_PU_M (BIT(20)) +#define RTC_CNTL_DG_WRAP_FORCE_PU_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_PU_S 20 +/* RTC_CNTL_DG_WRAP_FORCE_PD : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: digital core force power down.*/ +#define RTC_CNTL_DG_WRAP_FORCE_PD (BIT(19)) +#define RTC_CNTL_DG_WRAP_FORCE_PD_M (BIT(19)) +#define RTC_CNTL_DG_WRAP_FORCE_PD_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_PD_S 19 +/* RTC_CNTL_WIFI_FORCE_PU : R/W ;bitpos:[18] ;default: 1'd1 ; */ +/*description: wifi force power up.*/ +#define RTC_CNTL_WIFI_FORCE_PU (BIT(18)) +#define RTC_CNTL_WIFI_FORCE_PU_M (BIT(18)) +#define RTC_CNTL_WIFI_FORCE_PU_V 0x1 +#define RTC_CNTL_WIFI_FORCE_PU_S 18 +/* RTC_CNTL_WIFI_FORCE_PD : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: wifi force power down.*/ +#define RTC_CNTL_WIFI_FORCE_PD (BIT(17)) +#define RTC_CNTL_WIFI_FORCE_PD_M (BIT(17)) +#define RTC_CNTL_WIFI_FORCE_PD_V 0x1 +#define RTC_CNTL_WIFI_FORCE_PD_S 17 +/* RTC_CNTL_DG_PERI_FORCE_PU : R/W ;bitpos:[14] ;default: 1'd1 ; */ +/*description: internal SRAM 3 force power up.*/ +#define RTC_CNTL_DG_PERI_FORCE_PU (BIT(14)) +#define RTC_CNTL_DG_PERI_FORCE_PU_M (BIT(14)) +#define RTC_CNTL_DG_PERI_FORCE_PU_V 0x1 +#define RTC_CNTL_DG_PERI_FORCE_PU_S 14 +/* RTC_CNTL_DG_PERI_FORCE_PD : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: internal SRAM 3 force power down.*/ +#define RTC_CNTL_DG_PERI_FORCE_PD (BIT(13)) +#define RTC_CNTL_DG_PERI_FORCE_PD_M (BIT(13)) +#define RTC_CNTL_DG_PERI_FORCE_PD_V 0x1 +#define RTC_CNTL_DG_PERI_FORCE_PD_S 13 +/* RTC_CNTL_BT_FORCE_PU : R/W ;bitpos:[12] ;default: 1'd1 ; */ +/*description: internal SRAM 2 force power up.*/ +#define RTC_CNTL_BT_FORCE_PU (BIT(12)) +#define RTC_CNTL_BT_FORCE_PU_M (BIT(12)) +#define RTC_CNTL_BT_FORCE_PU_V 0x1 +#define RTC_CNTL_BT_FORCE_PU_S 12 +/* RTC_CNTL_BT_FORCE_PD : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: internal SRAM 2 force power down.*/ +#define RTC_CNTL_BT_FORCE_PD (BIT(11)) +#define RTC_CNTL_BT_FORCE_PD_M (BIT(11)) +#define RTC_CNTL_BT_FORCE_PD_V 0x1 +#define RTC_CNTL_BT_FORCE_PD_S 11 +/* RTC_CNTL_LSLP_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: memories in digital core force no PD in sleep.*/ +#define RTC_CNTL_LSLP_MEM_FORCE_PU (BIT(4)) +#define RTC_CNTL_LSLP_MEM_FORCE_PU_M (BIT(4)) +#define RTC_CNTL_LSLP_MEM_FORCE_PU_V 0x1 +#define RTC_CNTL_LSLP_MEM_FORCE_PU_S 4 +/* RTC_CNTL_LSLP_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: memories in digital core force PD in sleep.*/ +#define RTC_CNTL_LSLP_MEM_FORCE_PD (BIT(3)) +#define RTC_CNTL_LSLP_MEM_FORCE_PD_M (BIT(3)) +#define RTC_CNTL_LSLP_MEM_FORCE_PD_V 0x1 +#define RTC_CNTL_LSLP_MEM_FORCE_PD_S 3 + +#define RTC_CNTL_DIG_ISO_REG (DR_REG_RTCCNTL_BASE + 0x94) +/* RTC_CNTL_DG_WRAP_FORCE_NOISO : R/W ;bitpos:[31] ;default: 1'd1 ; */ +/*description: .*/ +#define RTC_CNTL_DG_WRAP_FORCE_NOISO (BIT(31)) +#define RTC_CNTL_DG_WRAP_FORCE_NOISO_M (BIT(31)) +#define RTC_CNTL_DG_WRAP_FORCE_NOISO_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_NOISO_S 31 +/* RTC_CNTL_DG_WRAP_FORCE_ISO : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: digital core force ISO.*/ +#define RTC_CNTL_DG_WRAP_FORCE_ISO (BIT(30)) +#define RTC_CNTL_DG_WRAP_FORCE_ISO_M (BIT(30)) +#define RTC_CNTL_DG_WRAP_FORCE_ISO_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_ISO_S 30 +/* RTC_CNTL_WIFI_FORCE_NOISO : R/W ;bitpos:[29] ;default: 1'd1 ; */ +/*description: wifi force no ISO.*/ +#define RTC_CNTL_WIFI_FORCE_NOISO (BIT(29)) +#define RTC_CNTL_WIFI_FORCE_NOISO_M (BIT(29)) +#define RTC_CNTL_WIFI_FORCE_NOISO_V 0x1 +#define RTC_CNTL_WIFI_FORCE_NOISO_S 29 +/* RTC_CNTL_WIFI_FORCE_ISO : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: wifi force ISO.*/ +#define RTC_CNTL_WIFI_FORCE_ISO (BIT(28)) +#define RTC_CNTL_WIFI_FORCE_ISO_M (BIT(28)) +#define RTC_CNTL_WIFI_FORCE_ISO_V 0x1 +#define RTC_CNTL_WIFI_FORCE_ISO_S 28 +/* RTC_CNTL_CPU_TOP_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */ +/*description: internal SRAM 4 force no ISO.*/ +#define RTC_CNTL_CPU_TOP_FORCE_NOISO (BIT(27)) +#define RTC_CNTL_CPU_TOP_FORCE_NOISO_M (BIT(27)) +#define RTC_CNTL_CPU_TOP_FORCE_NOISO_V 0x1 +#define RTC_CNTL_CPU_TOP_FORCE_NOISO_S 27 +/* RTC_CNTL_CPU_TOP_FORCE_ISO : R/W ;bitpos:[26] ;default: 1'd0 ; */ +/*description: internal SRAM 4 force ISO.*/ +#define RTC_CNTL_CPU_TOP_FORCE_ISO (BIT(26)) +#define RTC_CNTL_CPU_TOP_FORCE_ISO_M (BIT(26)) +#define RTC_CNTL_CPU_TOP_FORCE_ISO_V 0x1 +#define RTC_CNTL_CPU_TOP_FORCE_ISO_S 26 +/* RTC_CNTL_DG_PERI_FORCE_NOISO : R/W ;bitpos:[25] ;default: 1'd1 ; */ +/*description: internal SRAM 3 force no ISO.*/ +#define RTC_CNTL_DG_PERI_FORCE_NOISO (BIT(25)) +#define RTC_CNTL_DG_PERI_FORCE_NOISO_M (BIT(25)) +#define RTC_CNTL_DG_PERI_FORCE_NOISO_V 0x1 +#define RTC_CNTL_DG_PERI_FORCE_NOISO_S 25 +/* RTC_CNTL_DG_PERI_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */ +/*description: internal SRAM 3 force ISO.*/ +#define RTC_CNTL_DG_PERI_FORCE_ISO (BIT(24)) +#define RTC_CNTL_DG_PERI_FORCE_ISO_M (BIT(24)) +#define RTC_CNTL_DG_PERI_FORCE_ISO_V 0x1 +#define RTC_CNTL_DG_PERI_FORCE_ISO_S 24 +/* RTC_CNTL_BT_FORCE_NOISO : R/W ;bitpos:[23] ;default: 1'd1 ; */ +/*description: internal SRAM 2 force no ISO.*/ +#define RTC_CNTL_BT_FORCE_NOISO (BIT(23)) +#define RTC_CNTL_BT_FORCE_NOISO_M (BIT(23)) +#define RTC_CNTL_BT_FORCE_NOISO_V 0x1 +#define RTC_CNTL_BT_FORCE_NOISO_S 23 +/* RTC_CNTL_BT_FORCE_ISO : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: internal SRAM 2 force ISO.*/ +#define RTC_CNTL_BT_FORCE_ISO (BIT(22)) +#define RTC_CNTL_BT_FORCE_ISO_M (BIT(22)) +#define RTC_CNTL_BT_FORCE_ISO_V 0x1 +#define RTC_CNTL_BT_FORCE_ISO_S 22 +/* RTC_CNTL_DG_PAD_FORCE_HOLD : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: digital pad force hold.*/ +#define RTC_CNTL_DG_PAD_FORCE_HOLD (BIT(15)) +#define RTC_CNTL_DG_PAD_FORCE_HOLD_M (BIT(15)) +#define RTC_CNTL_DG_PAD_FORCE_HOLD_V 0x1 +#define RTC_CNTL_DG_PAD_FORCE_HOLD_S 15 +/* RTC_CNTL_DG_PAD_FORCE_UNHOLD : R/W ;bitpos:[14] ;default: 1'd1 ; */ +/*description: digital pad force un-hold.*/ +#define RTC_CNTL_DG_PAD_FORCE_UNHOLD (BIT(14)) +#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_M (BIT(14)) +#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_V 0x1 +#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_S 14 +/* RTC_CNTL_DG_PAD_FORCE_ISO : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: digital pad force ISO.*/ +#define RTC_CNTL_DG_PAD_FORCE_ISO (BIT(13)) +#define RTC_CNTL_DG_PAD_FORCE_ISO_M (BIT(13)) +#define RTC_CNTL_DG_PAD_FORCE_ISO_V 0x1 +#define RTC_CNTL_DG_PAD_FORCE_ISO_S 13 +/* RTC_CNTL_DG_PAD_FORCE_NOISO : R/W ;bitpos:[12] ;default: 1'd1 ; */ +/*description: digital pad force no ISO.*/ +#define RTC_CNTL_DG_PAD_FORCE_NOISO (BIT(12)) +#define RTC_CNTL_DG_PAD_FORCE_NOISO_M (BIT(12)) +#define RTC_CNTL_DG_PAD_FORCE_NOISO_V 0x1 +#define RTC_CNTL_DG_PAD_FORCE_NOISO_S 12 +/* RTC_CNTL_DG_PAD_AUTOHOLD_EN : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: digital pad enable auto-hold.*/ +#define RTC_CNTL_DG_PAD_AUTOHOLD_EN (BIT(11)) +#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_M (BIT(11)) +#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_V 0x1 +#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_S 11 +/* RTC_CNTL_CLR_DG_PAD_AUTOHOLD : WO ;bitpos:[10] ;default: 1'd0 ; */ +/*description: wtite only register to clear digital pad auto-hold.*/ +#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD (BIT(10)) +#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_M (BIT(10)) +#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_V 0x1 +#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_S 10 +/* RTC_CNTL_DG_PAD_AUTOHOLD : RO ;bitpos:[9] ;default: 1'd0 ; */ +/*description: read only register to indicate digital pad auto-hold status.*/ +#define RTC_CNTL_DG_PAD_AUTOHOLD (BIT(9)) +#define RTC_CNTL_DG_PAD_AUTOHOLD_M (BIT(9)) +#define RTC_CNTL_DG_PAD_AUTOHOLD_V 0x1 +#define RTC_CNTL_DG_PAD_AUTOHOLD_S 9 +/* RTC_CNTL_DIG_ISO_FORCE_ON : R/W ;bitpos:[8] ;default: 1'd0 ; */ +/*description: .*/ +#define RTC_CNTL_DIG_ISO_FORCE_ON (BIT(8)) +#define RTC_CNTL_DIG_ISO_FORCE_ON_M (BIT(8)) +#define RTC_CNTL_DIG_ISO_FORCE_ON_V 0x1 +#define RTC_CNTL_DIG_ISO_FORCE_ON_S 8 +/* RTC_CNTL_DIG_ISO_FORCE_OFF : R/W ;bitpos:[7] ;default: 1'd1 ; */ +/*description: .*/ +#define RTC_CNTL_DIG_ISO_FORCE_OFF (BIT(7)) +#define RTC_CNTL_DIG_ISO_FORCE_OFF_M (BIT(7)) +#define RTC_CNTL_DIG_ISO_FORCE_OFF_V 0x1 +#define RTC_CNTL_DIG_ISO_FORCE_OFF_S 7 + +#define RTC_CNTL_WDTCONFIG0_REG (DR_REG_RTCCNTL_BASE + 0x98) +/* RTC_CNTL_WDT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: .*/ +#define RTC_CNTL_WDT_EN (BIT(31)) +#define RTC_CNTL_WDT_EN_M (BIT(31)) +#define RTC_CNTL_WDT_EN_V 0x1 +#define RTC_CNTL_WDT_EN_S 31 +/* RTC_CNTL_WDT_STG0 : R/W ;bitpos:[30:28] ;default: 3'h0 ; */ +/*description: 1: interrupt stage en.*/ +#define RTC_CNTL_WDT_STG0 0x00000007 +#define RTC_CNTL_WDT_STG0_M ((RTC_CNTL_WDT_STG0_V)<<(RTC_CNTL_WDT_STG0_S)) +#define RTC_CNTL_WDT_STG0_V 0x7 +#define RTC_CNTL_WDT_STG0_S 28 +/* RTC_CNTL_WDT_STG1 : R/W ;bitpos:[27:25] ;default: 3'h0 ; */ +/*description: 1: interrupt stage en.*/ +#define RTC_CNTL_WDT_STG1 0x00000007 +#define RTC_CNTL_WDT_STG1_M ((RTC_CNTL_WDT_STG1_V)<<(RTC_CNTL_WDT_STG1_S)) +#define RTC_CNTL_WDT_STG1_V 0x7 +#define RTC_CNTL_WDT_STG1_S 25 +/* RTC_CNTL_WDT_STG2 : R/W ;bitpos:[24:22] ;default: 3'h0 ; */ +/*description: 1: interrupt stage en.*/ +#define RTC_CNTL_WDT_STG2 0x00000007 +#define RTC_CNTL_WDT_STG2_M ((RTC_CNTL_WDT_STG2_V)<<(RTC_CNTL_WDT_STG2_S)) +#define RTC_CNTL_WDT_STG2_V 0x7 +#define RTC_CNTL_WDT_STG2_S 22 +/* RTC_CNTL_WDT_STG3 : R/W ;bitpos:[21:19] ;default: 3'h0 ; */ +/*description: 1: interrupt stage en.*/ +#define RTC_CNTL_WDT_STG3 0x00000007 +#define RTC_CNTL_WDT_STG3_M ((RTC_CNTL_WDT_STG3_V)<<(RTC_CNTL_WDT_STG3_S)) +#define RTC_CNTL_WDT_STG3_V 0x7 +#define RTC_CNTL_WDT_STG3_S 19 + +/* RTC_CNTL_WDT_CPU_RESET_LENGTH : R/W ;bitpos:[18:16] ;default: 3'h1 ; */ +/*description: CPU reset counter length.*/ +#define RTC_CNTL_WDT_CPU_RESET_LENGTH 0x00000007 +#define RTC_CNTL_WDT_CPU_RESET_LENGTH_M ((RTC_CNTL_WDT_CPU_RESET_LENGTH_V)<<(RTC_CNTL_WDT_CPU_RESET_LENGTH_S)) +#define RTC_CNTL_WDT_CPU_RESET_LENGTH_V 0x7 +#define RTC_CNTL_WDT_CPU_RESET_LENGTH_S 16 +/* RTC_CNTL_WDT_SYS_RESET_LENGTH : R/W ;bitpos:[15:13] ;default: 3'h1 ; */ +/*description: system reset counter length.*/ +#define RTC_CNTL_WDT_SYS_RESET_LENGTH 0x00000007 +#define RTC_CNTL_WDT_SYS_RESET_LENGTH_M ((RTC_CNTL_WDT_SYS_RESET_LENGTH_V)<<(RTC_CNTL_WDT_SYS_RESET_LENGTH_S)) +#define RTC_CNTL_WDT_SYS_RESET_LENGTH_V 0x7 +#define RTC_CNTL_WDT_SYS_RESET_LENGTH_S 13 +/* RTC_CNTL_WDT_FLASHBOOT_MOD_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */ +/*description: enable WDT in flash boot.*/ +#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN (BIT(12)) +#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_M (BIT(12)) +#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_V 0x1 +#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_S 12 +/* RTC_CNTL_WDT_PROCPU_RESET_EN : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: enable WDT reset PRO CPU.*/ +#define RTC_CNTL_WDT_PROCPU_RESET_EN (BIT(11)) +#define RTC_CNTL_WDT_PROCPU_RESET_EN_M (BIT(11)) +#define RTC_CNTL_WDT_PROCPU_RESET_EN_V 0x1 +#define RTC_CNTL_WDT_PROCPU_RESET_EN_S 11 +/* RTC_CNTL_WDT_APPCPU_RESET_EN : R/W ;bitpos:[10] ;default: 1'd0 ; */ +/*description: enable WDT reset APP CPU.*/ +#define RTC_CNTL_WDT_APPCPU_RESET_EN (BIT(10)) +#define RTC_CNTL_WDT_APPCPU_RESET_EN_M (BIT(10)) +#define RTC_CNTL_WDT_APPCPU_RESET_EN_V 0x1 +#define RTC_CNTL_WDT_APPCPU_RESET_EN_S 10 +/* RTC_CNTL_WDT_PAUSE_IN_SLP : R/W ;bitpos:[9] ;default: 1'd1 ; */ +/*description: pause WDT in sleep.*/ +#define RTC_CNTL_WDT_PAUSE_IN_SLP (BIT(9)) +#define RTC_CNTL_WDT_PAUSE_IN_SLP_M (BIT(9)) +#define RTC_CNTL_WDT_PAUSE_IN_SLP_V 0x1 +#define RTC_CNTL_WDT_PAUSE_IN_SLP_S 9 +/* RTC_CNTL_WDT_CHIP_RESET_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: wdt reset whole chip enable.*/ +#define RTC_CNTL_WDT_CHIP_RESET_EN (BIT(8)) +#define RTC_CNTL_WDT_CHIP_RESET_EN_M (BIT(8)) +#define RTC_CNTL_WDT_CHIP_RESET_EN_V 0x1 +#define RTC_CNTL_WDT_CHIP_RESET_EN_S 8 +/* RTC_CNTL_WDT_CHIP_RESET_WIDTH : R/W ;bitpos:[7:0] ;default: 8'd20 ; */ +/*description: chip reset siginal pulse width.*/ +#define RTC_CNTL_WDT_CHIP_RESET_WIDTH 0x000000FF +#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_M ((RTC_CNTL_WDT_CHIP_RESET_WIDTH_V)<<(RTC_CNTL_WDT_CHIP_RESET_WIDTH_S)) +#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_V 0xFF +#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_S 0 + +#define RTC_CNTL_WDTCONFIG1_REG (DR_REG_RTCCNTL_BASE + 0x9C) +/* RTC_CNTL_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd200000 ; */ +/*description: .*/ +#define RTC_CNTL_WDT_STG0_HOLD 0xFFFFFFFF +#define RTC_CNTL_WDT_STG0_HOLD_M ((RTC_CNTL_WDT_STG0_HOLD_V)<<(RTC_CNTL_WDT_STG0_HOLD_S)) +#define RTC_CNTL_WDT_STG0_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_WDT_STG0_HOLD_S 0 + +#define RTC_CNTL_WDTCONFIG2_REG (DR_REG_RTCCNTL_BASE + 0xA0) +/* RTC_CNTL_WDT_STG1_HOLD : R/W ;bitpos:[31:0] ;default: 32'd80000 ; */ +/*description: .*/ +#define RTC_CNTL_WDT_STG1_HOLD 0xFFFFFFFF +#define RTC_CNTL_WDT_STG1_HOLD_M ((RTC_CNTL_WDT_STG1_HOLD_V)<<(RTC_CNTL_WDT_STG1_HOLD_S)) +#define RTC_CNTL_WDT_STG1_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_WDT_STG1_HOLD_S 0 + +#define RTC_CNTL_WDTCONFIG3_REG (DR_REG_RTCCNTL_BASE + 0xA4) +/* RTC_CNTL_WDT_STG2_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */ +/*description: .*/ +#define RTC_CNTL_WDT_STG2_HOLD 0xFFFFFFFF +#define RTC_CNTL_WDT_STG2_HOLD_M ((RTC_CNTL_WDT_STG2_HOLD_V)<<(RTC_CNTL_WDT_STG2_HOLD_S)) +#define RTC_CNTL_WDT_STG2_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_WDT_STG2_HOLD_S 0 + +#define RTC_CNTL_WDTCONFIG4_REG (DR_REG_RTCCNTL_BASE + 0xA8) +/* RTC_CNTL_WDT_STG3_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */ +/*description: .*/ +#define RTC_CNTL_WDT_STG3_HOLD 0xFFFFFFFF +#define RTC_CNTL_WDT_STG3_HOLD_M ((RTC_CNTL_WDT_STG3_HOLD_V)<<(RTC_CNTL_WDT_STG3_HOLD_S)) +#define RTC_CNTL_WDT_STG3_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_WDT_STG3_HOLD_S 0 + +#define RTC_CNTL_WDTFEED_REG (DR_REG_RTCCNTL_BASE + 0xAC) +/* RTC_CNTL_WDT_FEED : WO ;bitpos:[31] ;default: 1'd0 ; */ +/*description: .*/ +#define RTC_CNTL_WDT_FEED (BIT(31)) +#define RTC_CNTL_WDT_FEED_M (BIT(31)) +#define RTC_CNTL_WDT_FEED_V 0x1 +#define RTC_CNTL_WDT_FEED_S 31 + +#define RTC_CNTL_WDTWPROTECT_REG (DR_REG_RTCCNTL_BASE + 0xB0) +/* RTC_CNTL_WDT_WKEY : R/W ;bitpos:[31:0] ;default: 32'h50d83aa1 ; */ +/*description: .*/ +#define RTC_CNTL_WDT_WKEY 0xFFFFFFFF +#define RTC_CNTL_WDT_WKEY_M ((RTC_CNTL_WDT_WKEY_V)<<(RTC_CNTL_WDT_WKEY_S)) +#define RTC_CNTL_WDT_WKEY_V 0xFFFFFFFF +#define RTC_CNTL_WDT_WKEY_S 0 + +#define RTC_CNTL_SWD_CONF_REG (DR_REG_RTCCNTL_BASE + 0xB4) +/* RTC_CNTL_SWD_AUTO_FEED_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: automatically feed swd when int comes.*/ +#define RTC_CNTL_SWD_AUTO_FEED_EN (BIT(31)) +#define RTC_CNTL_SWD_AUTO_FEED_EN_M (BIT(31)) +#define RTC_CNTL_SWD_AUTO_FEED_EN_V 0x1 +#define RTC_CNTL_SWD_AUTO_FEED_EN_S 31 +/* RTC_CNTL_SWD_DISABLE : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: disable SWD.*/ +#define RTC_CNTL_SWD_DISABLE (BIT(30)) +#define RTC_CNTL_SWD_DISABLE_M (BIT(30)) +#define RTC_CNTL_SWD_DISABLE_V 0x1 +#define RTC_CNTL_SWD_DISABLE_S 30 +/* RTC_CNTL_SWD_FEED : WO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: Sw feed swd.*/ +#define RTC_CNTL_SWD_FEED (BIT(29)) +#define RTC_CNTL_SWD_FEED_M (BIT(29)) +#define RTC_CNTL_SWD_FEED_V 0x1 +#define RTC_CNTL_SWD_FEED_S 29 +/* RTC_CNTL_SWD_RST_FLAG_CLR : WO ;bitpos:[28] ;default: 1'b0 ; */ +/*description: reset swd reset flag.*/ +#define RTC_CNTL_SWD_RST_FLAG_CLR (BIT(28)) +#define RTC_CNTL_SWD_RST_FLAG_CLR_M (BIT(28)) +#define RTC_CNTL_SWD_RST_FLAG_CLR_V 0x1 +#define RTC_CNTL_SWD_RST_FLAG_CLR_S 28 +/* RTC_CNTL_SWD_SIGNAL_WIDTH : R/W ;bitpos:[27:18] ;default: 10'd300 ; */ +/*description: adjust signal width send to swd.*/ +#define RTC_CNTL_SWD_SIGNAL_WIDTH 0x000003FF +#define RTC_CNTL_SWD_SIGNAL_WIDTH_M ((RTC_CNTL_SWD_SIGNAL_WIDTH_V)<<(RTC_CNTL_SWD_SIGNAL_WIDTH_S)) +#define RTC_CNTL_SWD_SIGNAL_WIDTH_V 0x3FF +#define RTC_CNTL_SWD_SIGNAL_WIDTH_S 18 +/* RTC_CNTL_SWD_BYPASS_RST : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_SWD_BYPASS_RST (BIT(17)) +#define RTC_CNTL_SWD_BYPASS_RST_M (BIT(17)) +#define RTC_CNTL_SWD_BYPASS_RST_V 0x1 +#define RTC_CNTL_SWD_BYPASS_RST_S 17 +/* RTC_CNTL_SWD_FEED_INT : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: swd interrupt for feeding.*/ +#define RTC_CNTL_SWD_FEED_INT (BIT(1)) +#define RTC_CNTL_SWD_FEED_INT_M (BIT(1)) +#define RTC_CNTL_SWD_FEED_INT_V 0x1 +#define RTC_CNTL_SWD_FEED_INT_S 1 +/* RTC_CNTL_SWD_RESET_FLAG : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: swd reset flag.*/ +#define RTC_CNTL_SWD_RESET_FLAG (BIT(0)) +#define RTC_CNTL_SWD_RESET_FLAG_M (BIT(0)) +#define RTC_CNTL_SWD_RESET_FLAG_V 0x1 +#define RTC_CNTL_SWD_RESET_FLAG_S 0 + +#define RTC_CNTL_SWD_WPROTECT_REG (DR_REG_RTCCNTL_BASE + 0xB8) +/* RTC_CNTL_SWD_WKEY : R/W ;bitpos:[31:0] ;default: 32'h8f1d312a ; */ +/*description: .*/ +#define RTC_CNTL_SWD_WKEY 0xFFFFFFFF +#define RTC_CNTL_SWD_WKEY_M ((RTC_CNTL_SWD_WKEY_V)<<(RTC_CNTL_SWD_WKEY_S)) +#define RTC_CNTL_SWD_WKEY_V 0xFFFFFFFF +#define RTC_CNTL_SWD_WKEY_S 0 + +#define RTC_CNTL_SW_CPU_STALL_REG (DR_REG_RTCCNTL_BASE + 0xBC) +/* RTC_CNTL_SW_STALL_PROCPU_C1 : R/W ;bitpos:[31:26] ;default: 6'b0 ; */ +/*description: .*/ +#define RTC_CNTL_SW_STALL_PROCPU_C1 0x0000003F +#define RTC_CNTL_SW_STALL_PROCPU_C1_M ((RTC_CNTL_SW_STALL_PROCPU_C1_V)<<(RTC_CNTL_SW_STALL_PROCPU_C1_S)) +#define RTC_CNTL_SW_STALL_PROCPU_C1_V 0x3F +#define RTC_CNTL_SW_STALL_PROCPU_C1_S 26 +/* RTC_CNTL_SW_STALL_APPCPU_C1 : R/W ;bitpos:[25:20] ;default: 6'b0 ; */ +/*description: {reg_sw_stall_appcpu_c1[5:0].*/ +#define RTC_CNTL_SW_STALL_APPCPU_C1 0x0000003F +#define RTC_CNTL_SW_STALL_APPCPU_C1_M ((RTC_CNTL_SW_STALL_APPCPU_C1_V)<<(RTC_CNTL_SW_STALL_APPCPU_C1_S)) +#define RTC_CNTL_SW_STALL_APPCPU_C1_V 0x3F +#define RTC_CNTL_SW_STALL_APPCPU_C1_S 20 + +#define RTC_CNTL_STORE4_REG (DR_REG_RTCCNTL_BASE + 0xC0) +/* RTC_CNTL_SCRATCH4 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: .*/ +#define RTC_CNTL_SCRATCH4 0xFFFFFFFF +#define RTC_CNTL_SCRATCH4_M ((RTC_CNTL_SCRATCH4_V)<<(RTC_CNTL_SCRATCH4_S)) +#define RTC_CNTL_SCRATCH4_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH4_S 0 + +#define RTC_CNTL_STORE5_REG (DR_REG_RTCCNTL_BASE + 0xC4) +/* RTC_CNTL_SCRATCH5 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: .*/ +#define RTC_CNTL_SCRATCH5 0xFFFFFFFF +#define RTC_CNTL_SCRATCH5_M ((RTC_CNTL_SCRATCH5_V)<<(RTC_CNTL_SCRATCH5_S)) +#define RTC_CNTL_SCRATCH5_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH5_S 0 + +#define RTC_CNTL_STORE6_REG (DR_REG_RTCCNTL_BASE + 0xC8) +/* RTC_CNTL_SCRATCH6 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: .*/ +#define RTC_CNTL_SCRATCH6 0xFFFFFFFF +#define RTC_CNTL_SCRATCH6_M ((RTC_CNTL_SCRATCH6_V)<<(RTC_CNTL_SCRATCH6_S)) +#define RTC_CNTL_SCRATCH6_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH6_S 0 + +#define RTC_CNTL_STORE7_REG (DR_REG_RTCCNTL_BASE + 0xCC) +/* RTC_CNTL_SCRATCH7 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: .*/ +#define RTC_CNTL_SCRATCH7 0xFFFFFFFF +#define RTC_CNTL_SCRATCH7_M ((RTC_CNTL_SCRATCH7_V)<<(RTC_CNTL_SCRATCH7_S)) +#define RTC_CNTL_SCRATCH7_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH7_S 0 + +#define RTC_CNTL_LOW_POWER_ST_REG (DR_REG_RTCCNTL_BASE + 0xD0) +/* RTC_CNTL_MAIN_STATE : RO ;bitpos:[31:28] ;default: 4'd0 ; */ +/*description: rtc main state machine status.*/ +#define RTC_CNTL_MAIN_STATE 0x0000000F +#define RTC_CNTL_MAIN_STATE_M ((RTC_CNTL_MAIN_STATE_V)<<(RTC_CNTL_MAIN_STATE_S)) +#define RTC_CNTL_MAIN_STATE_V 0xF +#define RTC_CNTL_MAIN_STATE_S 28 +/* RTC_CNTL_MAIN_STATE_IN_IDLE : RO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: rtc main state machine is in idle state.*/ +#define RTC_CNTL_MAIN_STATE_IN_IDLE (BIT(27)) +#define RTC_CNTL_MAIN_STATE_IN_IDLE_M (BIT(27)) +#define RTC_CNTL_MAIN_STATE_IN_IDLE_V 0x1 +#define RTC_CNTL_MAIN_STATE_IN_IDLE_S 27 +/* RTC_CNTL_MAIN_STATE_IN_SLP : RO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: rtc main state machine is in sleep state.*/ +#define RTC_CNTL_MAIN_STATE_IN_SLP (BIT(26)) +#define RTC_CNTL_MAIN_STATE_IN_SLP_M (BIT(26)) +#define RTC_CNTL_MAIN_STATE_IN_SLP_V 0x1 +#define RTC_CNTL_MAIN_STATE_IN_SLP_S 26 +/* RTC_CNTL_MAIN_STATE_IN_WAIT_XTL : RO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: rtc main state machine is in wait xtal state.*/ +#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL (BIT(25)) +#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_M (BIT(25)) +#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_V 0x1 +#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_S 25 +/* RTC_CNTL_MAIN_STATE_IN_WAIT_PLL : RO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: rtc main state machine is in wait pll state.*/ +#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL (BIT(24)) +#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_M (BIT(24)) +#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_V 0x1 +#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_S 24 +/* RTC_CNTL_MAIN_STATE_IN_WAIT_8M : RO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: rtc main state machine is in wait 8m state.*/ +#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M (BIT(23)) +#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_M (BIT(23)) +#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_V 0x1 +#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_S 23 +/* RTC_CNTL_IN_LOW_POWER_STATE : RO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: rtc main state machine is in the states of low power.*/ +#define RTC_CNTL_IN_LOW_POWER_STATE (BIT(22)) +#define RTC_CNTL_IN_LOW_POWER_STATE_M (BIT(22)) +#define RTC_CNTL_IN_LOW_POWER_STATE_V 0x1 +#define RTC_CNTL_IN_LOW_POWER_STATE_S 22 +/* RTC_CNTL_IN_WAKEUP_STATE : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: rtc main state machine is in the states of wakeup process.*/ +#define RTC_CNTL_IN_WAKEUP_STATE (BIT(21)) +#define RTC_CNTL_IN_WAKEUP_STATE_M (BIT(21)) +#define RTC_CNTL_IN_WAKEUP_STATE_V 0x1 +#define RTC_CNTL_IN_WAKEUP_STATE_S 21 +/* RTC_CNTL_MAIN_STATE_WAIT_END : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: rtc main state machine has been waited for some cycles.*/ +#define RTC_CNTL_MAIN_STATE_WAIT_END (BIT(20)) +#define RTC_CNTL_MAIN_STATE_WAIT_END_M (BIT(20)) +#define RTC_CNTL_MAIN_STATE_WAIT_END_V 0x1 +#define RTC_CNTL_MAIN_STATE_WAIT_END_S 20 +/* RTC_CNTL_RDY_FOR_WAKEUP : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: rtc is ready to receive wake up trigger from wake up source.*/ +#define RTC_CNTL_RDY_FOR_WAKEUP (BIT(19)) +#define RTC_CNTL_RDY_FOR_WAKEUP_M (BIT(19)) +#define RTC_CNTL_RDY_FOR_WAKEUP_V 0x1 +#define RTC_CNTL_RDY_FOR_WAKEUP_S 19 +/* RTC_CNTL_MAIN_STATE_PLL_ON : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: rtc main state machine is in states that pll should be running.*/ +#define RTC_CNTL_MAIN_STATE_PLL_ON (BIT(18)) +#define RTC_CNTL_MAIN_STATE_PLL_ON_M (BIT(18)) +#define RTC_CNTL_MAIN_STATE_PLL_ON_V 0x1 +#define RTC_CNTL_MAIN_STATE_PLL_ON_S 18 +/* RTC_CNTL_MAIN_STATE_XTAL_ISO : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: no use any more.*/ +#define RTC_CNTL_MAIN_STATE_XTAL_ISO (BIT(17)) +#define RTC_CNTL_MAIN_STATE_XTAL_ISO_M (BIT(17)) +#define RTC_CNTL_MAIN_STATE_XTAL_ISO_V 0x1 +#define RTC_CNTL_MAIN_STATE_XTAL_ISO_S 17 +/* RTC_CNTL_COCPU_STATE_DONE : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: ulp/cocpu is done.*/ +#define RTC_CNTL_COCPU_STATE_DONE (BIT(16)) +#define RTC_CNTL_COCPU_STATE_DONE_M (BIT(16)) +#define RTC_CNTL_COCPU_STATE_DONE_V 0x1 +#define RTC_CNTL_COCPU_STATE_DONE_S 16 +/* RTC_CNTL_COCPU_STATE_SLP : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: ulp/cocpu is in sleep state.*/ +#define RTC_CNTL_COCPU_STATE_SLP (BIT(15)) +#define RTC_CNTL_COCPU_STATE_SLP_M (BIT(15)) +#define RTC_CNTL_COCPU_STATE_SLP_V 0x1 +#define RTC_CNTL_COCPU_STATE_SLP_S 15 +/* RTC_CNTL_COCPU_STATE_SWITCH : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: ulp/cocpu is about to working. Switch rtc main state.*/ +#define RTC_CNTL_COCPU_STATE_SWITCH (BIT(14)) +#define RTC_CNTL_COCPU_STATE_SWITCH_M (BIT(14)) +#define RTC_CNTL_COCPU_STATE_SWITCH_V 0x1 +#define RTC_CNTL_COCPU_STATE_SWITCH_S 14 +/* RTC_CNTL_COCPU_STATE_START : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: ulp/cocpu should start to work.*/ +#define RTC_CNTL_COCPU_STATE_START (BIT(13)) +#define RTC_CNTL_COCPU_STATE_START_M (BIT(13)) +#define RTC_CNTL_COCPU_STATE_START_V 0x1 +#define RTC_CNTL_COCPU_STATE_START_S 13 +/* RTC_CNTL_TOUCH_STATE_DONE : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: touch is done.*/ +#define RTC_CNTL_TOUCH_STATE_DONE (BIT(12)) +#define RTC_CNTL_TOUCH_STATE_DONE_M (BIT(12)) +#define RTC_CNTL_TOUCH_STATE_DONE_V 0x1 +#define RTC_CNTL_TOUCH_STATE_DONE_S 12 +/* RTC_CNTL_TOUCH_STATE_SLP : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: touch is in sleep state.*/ +#define RTC_CNTL_TOUCH_STATE_SLP (BIT(11)) +#define RTC_CNTL_TOUCH_STATE_SLP_M (BIT(11)) +#define RTC_CNTL_TOUCH_STATE_SLP_V 0x1 +#define RTC_CNTL_TOUCH_STATE_SLP_S 11 +/* RTC_CNTL_TOUCH_STATE_SWITCH : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: touch is about to working. Switch rtc main state.*/ +#define RTC_CNTL_TOUCH_STATE_SWITCH (BIT(10)) +#define RTC_CNTL_TOUCH_STATE_SWITCH_M (BIT(10)) +#define RTC_CNTL_TOUCH_STATE_SWITCH_V 0x1 +#define RTC_CNTL_TOUCH_STATE_SWITCH_S 10 +/* RTC_CNTL_TOUCH_STATE_START : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: touch should start to work.*/ +#define RTC_CNTL_TOUCH_STATE_START (BIT(9)) +#define RTC_CNTL_TOUCH_STATE_START_M (BIT(9)) +#define RTC_CNTL_TOUCH_STATE_START_V 0x1 +#define RTC_CNTL_TOUCH_STATE_START_S 9 +/* RTC_CNTL_XPD_DIG : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: digital wrap power down.*/ +#define RTC_CNTL_XPD_DIG (BIT(8)) +#define RTC_CNTL_XPD_DIG_M (BIT(8)) +#define RTC_CNTL_XPD_DIG_V 0x1 +#define RTC_CNTL_XPD_DIG_S 8 +/* RTC_CNTL_DIG_ISO : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: digital wrap iso.*/ +#define RTC_CNTL_DIG_ISO (BIT(7)) +#define RTC_CNTL_DIG_ISO_M (BIT(7)) +#define RTC_CNTL_DIG_ISO_V 0x1 +#define RTC_CNTL_DIG_ISO_S 7 +/* RTC_CNTL_XPD_WIFI : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: wifi wrap power down.*/ +#define RTC_CNTL_XPD_WIFI (BIT(6)) +#define RTC_CNTL_XPD_WIFI_M (BIT(6)) +#define RTC_CNTL_XPD_WIFI_V 0x1 +#define RTC_CNTL_XPD_WIFI_S 6 +/* RTC_CNTL_WIFI_ISO : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: wifi iso.*/ +#define RTC_CNTL_WIFI_ISO (BIT(5)) +#define RTC_CNTL_WIFI_ISO_M (BIT(5)) +#define RTC_CNTL_WIFI_ISO_V 0x1 +#define RTC_CNTL_WIFI_ISO_S 5 +/* RTC_CNTL_XPD_RTC_PERI : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: rtc peripheral power down .*/ +#define RTC_CNTL_XPD_RTC_PERI (BIT(4)) +#define RTC_CNTL_XPD_RTC_PERI_M (BIT(4)) +#define RTC_CNTL_XPD_RTC_PERI_V 0x1 +#define RTC_CNTL_XPD_RTC_PERI_S 4 +/* RTC_CNTL_PERI_ISO : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: rtc peripheral iso.*/ +#define RTC_CNTL_PERI_ISO (BIT(3)) +#define RTC_CNTL_PERI_ISO_M (BIT(3)) +#define RTC_CNTL_PERI_ISO_V 0x1 +#define RTC_CNTL_PERI_ISO_S 3 +/* RTC_CNTL_XPD_DIG_DCDC : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: External DCDC power down.*/ +#define RTC_CNTL_XPD_DIG_DCDC (BIT(2)) +#define RTC_CNTL_XPD_DIG_DCDC_M (BIT(2)) +#define RTC_CNTL_XPD_DIG_DCDC_V 0x1 +#define RTC_CNTL_XPD_DIG_DCDC_S 2 +/* RTC_CNTL_XPD_ROM0 : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: rom0 power down.*/ +#define RTC_CNTL_XPD_ROM0 (BIT(0)) +#define RTC_CNTL_XPD_ROM0_M (BIT(0)) +#define RTC_CNTL_XPD_ROM0_V 0x1 +#define RTC_CNTL_XPD_ROM0_S 0 + +#define RTC_CNTL_DIAG0_REG (DR_REG_RTCCNTL_BASE + 0xD4) +/* RTC_CNTL_LOW_POWER_DIAG1 : RO ;bitpos:[31:0] ;default: 0 ; */ +/*description: .*/ +#define RTC_CNTL_LOW_POWER_DIAG1 0xFFFFFFFF +#define RTC_CNTL_LOW_POWER_DIAG1_M ((RTC_CNTL_LOW_POWER_DIAG1_V)<<(RTC_CNTL_LOW_POWER_DIAG1_S)) +#define RTC_CNTL_LOW_POWER_DIAG1_V 0xFFFFFFFF +#define RTC_CNTL_LOW_POWER_DIAG1_S 0 + +#define RTC_CNTL_PAD_HOLD_REG (DR_REG_RTCCNTL_BASE + 0xD8) +/* RTC_CNTL_PAD21_HOLD : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_PAD21_HOLD (BIT(21)) +#define RTC_CNTL_PAD21_HOLD_M (BIT(21)) +#define RTC_CNTL_PAD21_HOLD_V 0x1 +#define RTC_CNTL_PAD21_HOLD_S 21 +/* RTC_CNTL_PAD20_HOLD : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_PAD20_HOLD (BIT(20)) +#define RTC_CNTL_PAD20_HOLD_M (BIT(20)) +#define RTC_CNTL_PAD20_HOLD_V 0x1 +#define RTC_CNTL_PAD20_HOLD_S 20 +/* RTC_CNTL_PAD19_HOLD : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_PAD19_HOLD (BIT(19)) +#define RTC_CNTL_PAD19_HOLD_M (BIT(19)) +#define RTC_CNTL_PAD19_HOLD_V 0x1 +#define RTC_CNTL_PAD19_HOLD_S 19 +/* RTC_CNTL_PDAC2_HOLD : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_PDAC2_HOLD (BIT(18)) +#define RTC_CNTL_PDAC2_HOLD_M (BIT(18)) +#define RTC_CNTL_PDAC2_HOLD_V 0x1 +#define RTC_CNTL_PDAC2_HOLD_S 18 +/* RTC_CNTL_PDAC1_HOLD : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_PDAC1_HOLD (BIT(17)) +#define RTC_CNTL_PDAC1_HOLD_M (BIT(17)) +#define RTC_CNTL_PDAC1_HOLD_V 0x1 +#define RTC_CNTL_PDAC1_HOLD_S 17 +/* RTC_CNTL_X32N_HOLD : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_X32N_HOLD (BIT(16)) +#define RTC_CNTL_X32N_HOLD_M (BIT(16)) +#define RTC_CNTL_X32N_HOLD_V 0x1 +#define RTC_CNTL_X32N_HOLD_S 16 +/* RTC_CNTL_X32P_HOLD : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_X32P_HOLD (BIT(15)) +#define RTC_CNTL_X32P_HOLD_M (BIT(15)) +#define RTC_CNTL_X32P_HOLD_V 0x1 +#define RTC_CNTL_X32P_HOLD_S 15 +/* RTC_CNTL_TOUCH_PAD14_HOLD : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD14_HOLD (BIT(14)) +#define RTC_CNTL_TOUCH_PAD14_HOLD_M (BIT(14)) +#define RTC_CNTL_TOUCH_PAD14_HOLD_V 0x1 +#define RTC_CNTL_TOUCH_PAD14_HOLD_S 14 +/* RTC_CNTL_TOUCH_PAD13_HOLD : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD13_HOLD (BIT(13)) +#define RTC_CNTL_TOUCH_PAD13_HOLD_M (BIT(13)) +#define RTC_CNTL_TOUCH_PAD13_HOLD_V 0x1 +#define RTC_CNTL_TOUCH_PAD13_HOLD_S 13 +/* RTC_CNTL_TOUCH_PAD12_HOLD : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD12_HOLD (BIT(12)) +#define RTC_CNTL_TOUCH_PAD12_HOLD_M (BIT(12)) +#define RTC_CNTL_TOUCH_PAD12_HOLD_V 0x1 +#define RTC_CNTL_TOUCH_PAD12_HOLD_S 12 +/* RTC_CNTL_TOUCH_PAD11_HOLD : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD11_HOLD (BIT(11)) +#define RTC_CNTL_TOUCH_PAD11_HOLD_M (BIT(11)) +#define RTC_CNTL_TOUCH_PAD11_HOLD_V 0x1 +#define RTC_CNTL_TOUCH_PAD11_HOLD_S 11 +/* RTC_CNTL_TOUCH_PAD10_HOLD : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD10_HOLD (BIT(10)) +#define RTC_CNTL_TOUCH_PAD10_HOLD_M (BIT(10)) +#define RTC_CNTL_TOUCH_PAD10_HOLD_V 0x1 +#define RTC_CNTL_TOUCH_PAD10_HOLD_S 10 +/* RTC_CNTL_TOUCH_PAD9_HOLD : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD9_HOLD (BIT(9)) +#define RTC_CNTL_TOUCH_PAD9_HOLD_M (BIT(9)) +#define RTC_CNTL_TOUCH_PAD9_HOLD_V 0x1 +#define RTC_CNTL_TOUCH_PAD9_HOLD_S 9 +/* RTC_CNTL_TOUCH_PAD8_HOLD : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD8_HOLD (BIT(8)) +#define RTC_CNTL_TOUCH_PAD8_HOLD_M (BIT(8)) +#define RTC_CNTL_TOUCH_PAD8_HOLD_V 0x1 +#define RTC_CNTL_TOUCH_PAD8_HOLD_S 8 +/* RTC_CNTL_TOUCH_PAD7_HOLD : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD7_HOLD (BIT(7)) +#define RTC_CNTL_TOUCH_PAD7_HOLD_M (BIT(7)) +#define RTC_CNTL_TOUCH_PAD7_HOLD_V 0x1 +#define RTC_CNTL_TOUCH_PAD7_HOLD_S 7 +/* RTC_CNTL_TOUCH_PAD6_HOLD : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD6_HOLD (BIT(6)) +#define RTC_CNTL_TOUCH_PAD6_HOLD_M (BIT(6)) +#define RTC_CNTL_TOUCH_PAD6_HOLD_V 0x1 +#define RTC_CNTL_TOUCH_PAD6_HOLD_S 6 +/* RTC_CNTL_TOUCH_PAD5_HOLD : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD5_HOLD (BIT(5)) +#define RTC_CNTL_TOUCH_PAD5_HOLD_M (BIT(5)) +#define RTC_CNTL_TOUCH_PAD5_HOLD_V 0x1 +#define RTC_CNTL_TOUCH_PAD5_HOLD_S 5 +/* RTC_CNTL_TOUCH_PAD4_HOLD : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD4_HOLD (BIT(4)) +#define RTC_CNTL_TOUCH_PAD4_HOLD_M (BIT(4)) +#define RTC_CNTL_TOUCH_PAD4_HOLD_V 0x1 +#define RTC_CNTL_TOUCH_PAD4_HOLD_S 4 +/* RTC_CNTL_TOUCH_PAD3_HOLD : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD3_HOLD (BIT(3)) +#define RTC_CNTL_TOUCH_PAD3_HOLD_M (BIT(3)) +#define RTC_CNTL_TOUCH_PAD3_HOLD_V 0x1 +#define RTC_CNTL_TOUCH_PAD3_HOLD_S 3 +/* RTC_CNTL_TOUCH_PAD2_HOLD : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD2_HOLD (BIT(2)) +#define RTC_CNTL_TOUCH_PAD2_HOLD_M (BIT(2)) +#define RTC_CNTL_TOUCH_PAD2_HOLD_V 0x1 +#define RTC_CNTL_TOUCH_PAD2_HOLD_S 2 +/* RTC_CNTL_TOUCH_PAD1_HOLD : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD1_HOLD (BIT(1)) +#define RTC_CNTL_TOUCH_PAD1_HOLD_M (BIT(1)) +#define RTC_CNTL_TOUCH_PAD1_HOLD_V 0x1 +#define RTC_CNTL_TOUCH_PAD1_HOLD_S 1 +/* RTC_CNTL_TOUCH_PAD0_HOLD : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD0_HOLD (BIT(0)) +#define RTC_CNTL_TOUCH_PAD0_HOLD_M (BIT(0)) +#define RTC_CNTL_TOUCH_PAD0_HOLD_V 0x1 +#define RTC_CNTL_TOUCH_PAD0_HOLD_S 0 + +#define RTC_CNTL_DIG_PAD_HOLD_REG (DR_REG_RTCCNTL_BASE + 0xDC) +/* RTC_CNTL_DIG_PAD_HOLD : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: .*/ +#define RTC_CNTL_DIG_PAD_HOLD 0xFFFFFFFF +#define RTC_CNTL_DIG_PAD_HOLD_M ((RTC_CNTL_DIG_PAD_HOLD_V)<<(RTC_CNTL_DIG_PAD_HOLD_S)) +#define RTC_CNTL_DIG_PAD_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_DIG_PAD_HOLD_S 0 + +#define RTC_CNTL_EXT_WAKEUP1_REG (DR_REG_RTCCNTL_BASE + 0xE0) +/* RTC_CNTL_EXT_WAKEUP1_STATUS_CLR : WO ;bitpos:[22] ;default: 1'd0 ; */ +/*description: clear ext wakeup1 status.*/ +#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR (BIT(22)) +#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_M (BIT(22)) +#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_V 0x1 +#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_S 22 +/* RTC_CNTL_EXT_WAKEUP1_SEL : R/W ;bitpos:[21:0] ;default: 22'd0 ; */ +/*description: Bitmap to select RTC pads for ext wakeup1.*/ +#define RTC_CNTL_EXT_WAKEUP1_SEL 0x003FFFFF +#define RTC_CNTL_EXT_WAKEUP1_SEL_M ((RTC_CNTL_EXT_WAKEUP1_SEL_V)<<(RTC_CNTL_EXT_WAKEUP1_SEL_S)) +#define RTC_CNTL_EXT_WAKEUP1_SEL_V 0x3FFFFF +#define RTC_CNTL_EXT_WAKEUP1_SEL_S 0 + +#define RTC_CNTL_EXT_WAKEUP1_STATUS_REG (DR_REG_RTCCNTL_BASE + 0xE4) +/* RTC_CNTL_EXT_WAKEUP1_STATUS : RO ;bitpos:[21:0] ;default: 22'd0 ; */ +/*description: ext wakeup1 status.*/ +#define RTC_CNTL_EXT_WAKEUP1_STATUS 0x003FFFFF +#define RTC_CNTL_EXT_WAKEUP1_STATUS_M ((RTC_CNTL_EXT_WAKEUP1_STATUS_V)<<(RTC_CNTL_EXT_WAKEUP1_STATUS_S)) +#define RTC_CNTL_EXT_WAKEUP1_STATUS_V 0x3FFFFF +#define RTC_CNTL_EXT_WAKEUP1_STATUS_S 0 + +#define RTC_CNTL_BROWN_OUT_REG (DR_REG_RTCCNTL_BASE + 0xE8) +/* RTC_CNTL_BROWN_OUT_DET : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_BROWN_OUT_DET (BIT(31)) +#define RTC_CNTL_BROWN_OUT_DET_M (BIT(31)) +#define RTC_CNTL_BROWN_OUT_DET_V 0x1 +#define RTC_CNTL_BROWN_OUT_DET_S 31 +/* RTC_CNTL_BROWN_OUT_ENA : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: enable brown out.*/ +#define RTC_CNTL_BROWN_OUT_ENA (BIT(30)) +#define RTC_CNTL_BROWN_OUT_ENA_M (BIT(30)) +#define RTC_CNTL_BROWN_OUT_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_ENA_S 30 +/* RTC_CNTL_BROWN_OUT_CNT_CLR : WO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: clear brown out counter.*/ +#define RTC_CNTL_BROWN_OUT_CNT_CLR (BIT(29)) +#define RTC_CNTL_BROWN_OUT_CNT_CLR_M (BIT(29)) +#define RTC_CNTL_BROWN_OUT_CNT_CLR_V 0x1 +#define RTC_CNTL_BROWN_OUT_CNT_CLR_S 29 +/* RTC_CNTL_BROWN_OUT_ANA_RST_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_BROWN_OUT_ANA_RST_EN (BIT(28)) +#define RTC_CNTL_BROWN_OUT_ANA_RST_EN_M (BIT(28)) +#define RTC_CNTL_BROWN_OUT_ANA_RST_EN_V 0x1 +#define RTC_CNTL_BROWN_OUT_ANA_RST_EN_S 28 +/* RTC_CNTL_BROWN_OUT_RST_SEL : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: 1: 4-pos reset.*/ +#define RTC_CNTL_BROWN_OUT_RST_SEL (BIT(27)) +#define RTC_CNTL_BROWN_OUT_RST_SEL_M (BIT(27)) +#define RTC_CNTL_BROWN_OUT_RST_SEL_V 0x1 +#define RTC_CNTL_BROWN_OUT_RST_SEL_S 27 +/* RTC_CNTL_BROWN_OUT_RST_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: enable brown out reset.*/ +#define RTC_CNTL_BROWN_OUT_RST_ENA (BIT(26)) +#define RTC_CNTL_BROWN_OUT_RST_ENA_M (BIT(26)) +#define RTC_CNTL_BROWN_OUT_RST_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_RST_ENA_S 26 +/* RTC_CNTL_BROWN_OUT_RST_WAIT : R/W ;bitpos:[25:16] ;default: 10'h3ff ; */ +/*description: brown out reset wait cycles.*/ +#define RTC_CNTL_BROWN_OUT_RST_WAIT 0x000003FF +#define RTC_CNTL_BROWN_OUT_RST_WAIT_M ((RTC_CNTL_BROWN_OUT_RST_WAIT_V)<<(RTC_CNTL_BROWN_OUT_RST_WAIT_S)) +#define RTC_CNTL_BROWN_OUT_RST_WAIT_V 0x3FF +#define RTC_CNTL_BROWN_OUT_RST_WAIT_S 16 +/* RTC_CNTL_BROWN_OUT_PD_RF_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: enable power down RF when brown out happens.*/ +#define RTC_CNTL_BROWN_OUT_PD_RF_ENA (BIT(15)) +#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_M (BIT(15)) +#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_S 15 +/* RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: enable close flash when brown out happens.*/ +#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA (BIT(14)) +#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_M (BIT(14)) +#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_S 14 +/* RTC_CNTL_BROWN_OUT_INT_WAIT : R/W ;bitpos:[13:4] ;default: 10'h1 ; */ +/*description: brown out interrupt wait cycles.*/ +#define RTC_CNTL_BROWN_OUT_INT_WAIT 0x000003FF +#define RTC_CNTL_BROWN_OUT_INT_WAIT_M ((RTC_CNTL_BROWN_OUT_INT_WAIT_V)<<(RTC_CNTL_BROWN_OUT_INT_WAIT_S)) +#define RTC_CNTL_BROWN_OUT_INT_WAIT_V 0x3FF +#define RTC_CNTL_BROWN_OUT_INT_WAIT_S 4 + +#define RTC_CNTL_TIME_LOW1_REG (DR_REG_RTCCNTL_BASE + 0xEC) +/* RTC_CNTL_TIMER_VALUE1_LOW : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: RTC timer low 32 bits.*/ +#define RTC_CNTL_TIMER_VALUE1_LOW 0xFFFFFFFF +#define RTC_CNTL_TIMER_VALUE1_LOW_M ((RTC_CNTL_TIMER_VALUE1_LOW_V)<<(RTC_CNTL_TIMER_VALUE1_LOW_S)) +#define RTC_CNTL_TIMER_VALUE1_LOW_V 0xFFFFFFFF +#define RTC_CNTL_TIMER_VALUE1_LOW_S 0 + +#define RTC_CNTL_TIME_HIGH1_REG (DR_REG_RTCCNTL_BASE + 0xF0) +/* RTC_CNTL_TIMER_VALUE1_HIGH : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: RTC timer high 16 bits.*/ +#define RTC_CNTL_TIMER_VALUE1_HIGH 0x0000FFFF +#define RTC_CNTL_TIMER_VALUE1_HIGH_M ((RTC_CNTL_TIMER_VALUE1_HIGH_V)<<(RTC_CNTL_TIMER_VALUE1_HIGH_S)) +#define RTC_CNTL_TIMER_VALUE1_HIGH_V 0xFFFF +#define RTC_CNTL_TIMER_VALUE1_HIGH_S 0 + +#define RTC_CNTL_XTAL32K_CLK_FACTOR_REG (DR_REG_RTCCNTL_BASE + 0xF4) +/* RTC_CNTL_XTAL32K_CLK_FACTOR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: xtal 32k watch dog backup clock factor.*/ +#define RTC_CNTL_XTAL32K_CLK_FACTOR 0xFFFFFFFF +#define RTC_CNTL_XTAL32K_CLK_FACTOR_M ((RTC_CNTL_XTAL32K_CLK_FACTOR_V)<<(RTC_CNTL_XTAL32K_CLK_FACTOR_S)) +#define RTC_CNTL_XTAL32K_CLK_FACTOR_V 0xFFFFFFFF +#define RTC_CNTL_XTAL32K_CLK_FACTOR_S 0 + +#define RTC_CNTL_XTAL32K_CONF_REG (DR_REG_RTCCNTL_BASE + 0xF8) +/* RTC_CNTL_XTAL32K_STABLE_THRES : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ +/*description: if restarted xtal32k period is smaller than this.*/ +#define RTC_CNTL_XTAL32K_STABLE_THRES 0x0000000F +#define RTC_CNTL_XTAL32K_STABLE_THRES_M ((RTC_CNTL_XTAL32K_STABLE_THRES_V)<<(RTC_CNTL_XTAL32K_STABLE_THRES_S)) +#define RTC_CNTL_XTAL32K_STABLE_THRES_V 0xF +#define RTC_CNTL_XTAL32K_STABLE_THRES_S 28 +/* RTC_CNTL_XTAL32K_WDT_TIMEOUT : R/W ;bitpos:[27:20] ;default: 8'hff ; */ +/*description: If no clock detected for this amount of time.*/ +#define RTC_CNTL_XTAL32K_WDT_TIMEOUT 0x000000FF +#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_M ((RTC_CNTL_XTAL32K_WDT_TIMEOUT_V)<<(RTC_CNTL_XTAL32K_WDT_TIMEOUT_S)) +#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_V 0xFF +#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_S 20 +/* RTC_CNTL_XTAL32K_RESTART_WAIT : R/W ;bitpos:[19:4] ;default: 16'h0 ; */ +/*description: cycles to wait to repower on xtal 32k.*/ +#define RTC_CNTL_XTAL32K_RESTART_WAIT 0x0000FFFF +#define RTC_CNTL_XTAL32K_RESTART_WAIT_M ((RTC_CNTL_XTAL32K_RESTART_WAIT_V)<<(RTC_CNTL_XTAL32K_RESTART_WAIT_S)) +#define RTC_CNTL_XTAL32K_RESTART_WAIT_V 0xFFFF +#define RTC_CNTL_XTAL32K_RESTART_WAIT_S 4 +/* RTC_CNTL_XTAL32K_RETURN_WAIT : R/W ;bitpos:[3:0] ;default: 4'h0 ; */ +/*description: cycles to wait to return normal xtal 32k.*/ +#define RTC_CNTL_XTAL32K_RETURN_WAIT 0x0000000F +#define RTC_CNTL_XTAL32K_RETURN_WAIT_M ((RTC_CNTL_XTAL32K_RETURN_WAIT_V)<<(RTC_CNTL_XTAL32K_RETURN_WAIT_S)) +#define RTC_CNTL_XTAL32K_RETURN_WAIT_V 0xF +#define RTC_CNTL_XTAL32K_RETURN_WAIT_S 0 + +#define RTC_CNTL_ULP_CP_TIMER_REG (DR_REG_RTCCNTL_BASE + 0xFC) +/* RTC_CNTL_ULP_CP_SLP_TIMER_EN : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: ULP-coprocessor timer enable bit.*/ +#define RTC_CNTL_ULP_CP_SLP_TIMER_EN (BIT(31)) +#define RTC_CNTL_ULP_CP_SLP_TIMER_EN_M (BIT(31)) +#define RTC_CNTL_ULP_CP_SLP_TIMER_EN_V 0x1 +#define RTC_CNTL_ULP_CP_SLP_TIMER_EN_S 31 +/* RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR : WO ;bitpos:[30] ;default: 1'd0 ; */ +/*description: ULP-coprocessor wakeup by GPIO state clear.*/ +#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR (BIT(30)) +#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_M (BIT(30)) +#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_V 0x1 +#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_S 30 +/* RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: ULP-coprocessor wakeup by GPIO enable.*/ +#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA (BIT(29)) +#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_M (BIT(29)) +#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_V 0x1 +#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_S 29 +/* RTC_CNTL_ULP_CP_PC_INIT : R/W ;bitpos:[10:0] ;default: 11'b0 ; */ +/*description: ULP-coprocessor PC initial address.*/ +#define RTC_CNTL_ULP_CP_PC_INIT 0x000007FF +#define RTC_CNTL_ULP_CP_PC_INIT_M ((RTC_CNTL_ULP_CP_PC_INIT_V)<<(RTC_CNTL_ULP_CP_PC_INIT_S)) +#define RTC_CNTL_ULP_CP_PC_INIT_V 0x7FF +#define RTC_CNTL_ULP_CP_PC_INIT_S 0 + +#define RTC_CNTL_ULP_CP_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x100) +/* RTC_CNTL_ULP_CP_START_TOP : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: Write 1 to start ULP-coprocessor.*/ +#define RTC_CNTL_ULP_CP_START_TOP (BIT(31)) +#define RTC_CNTL_ULP_CP_START_TOP_M (BIT(31)) +#define RTC_CNTL_ULP_CP_START_TOP_V 0x1 +#define RTC_CNTL_ULP_CP_START_TOP_S 31 +/* RTC_CNTL_ULP_CP_FORCE_START_TOP : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: 1: ULP-coprocessor is started by SW.*/ +#define RTC_CNTL_ULP_CP_FORCE_START_TOP (BIT(30)) +#define RTC_CNTL_ULP_CP_FORCE_START_TOP_M (BIT(30)) +#define RTC_CNTL_ULP_CP_FORCE_START_TOP_V 0x1 +#define RTC_CNTL_ULP_CP_FORCE_START_TOP_S 30 +/* RTC_CNTL_ULP_CP_RESET : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: ulp coprocessor clk software reset.*/ +#define RTC_CNTL_ULP_CP_RESET (BIT(29)) +#define RTC_CNTL_ULP_CP_RESET_M (BIT(29)) +#define RTC_CNTL_ULP_CP_RESET_V 0x1 +#define RTC_CNTL_ULP_CP_RESET_S 29 +/* RTC_CNTL_ULP_CP_CLK_FO : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: ulp coprocessor clk force on.*/ +#define RTC_CNTL_ULP_CP_CLK_FO (BIT(28)) +#define RTC_CNTL_ULP_CP_CLK_FO_M (BIT(28)) +#define RTC_CNTL_ULP_CP_CLK_FO_V 0x1 +#define RTC_CNTL_ULP_CP_CLK_FO_S 28 +/* RTC_CNTL_ULP_CP_MEM_OFFST_CLR : WO ;bitpos:[22] ;default: 1'd0 ; */ +/*description: .*/ +#define RTC_CNTL_ULP_CP_MEM_OFFST_CLR (BIT(22)) +#define RTC_CNTL_ULP_CP_MEM_OFFST_CLR_M (BIT(22)) +#define RTC_CNTL_ULP_CP_MEM_OFFST_CLR_V 0x1 +#define RTC_CNTL_ULP_CP_MEM_OFFST_CLR_S 22 +/* RTC_CNTL_ULP_CP_MEM_ADDR_SIZE : R/W ;bitpos:[21:11] ;default: 11'd512 ; */ +/*description: .*/ +#define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE 0x000007FF +#define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_M ((RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_V)<<(RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_S)) +#define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_V 0x7FF +#define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_S 11 +/* RTC_CNTL_ULP_CP_MEM_ADDR_INIT : R/W ;bitpos:[10:0] ;default: 11'd512 ; */ +/*description: .*/ +#define RTC_CNTL_ULP_CP_MEM_ADDR_INIT 0x000007FF +#define RTC_CNTL_ULP_CP_MEM_ADDR_INIT_M ((RTC_CNTL_ULP_CP_MEM_ADDR_INIT_V)<<(RTC_CNTL_ULP_CP_MEM_ADDR_INIT_S)) +#define RTC_CNTL_ULP_CP_MEM_ADDR_INIT_V 0x7FF +#define RTC_CNTL_ULP_CP_MEM_ADDR_INIT_S 0 + +#define RTC_CNTL_COCPU_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x104) +/* RTC_CNTL_COCPU_CLKGATE_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_COCPU_CLKGATE_EN (BIT(27)) +#define RTC_CNTL_COCPU_CLKGATE_EN_M (BIT(27)) +#define RTC_CNTL_COCPU_CLKGATE_EN_V 0x1 +#define RTC_CNTL_COCPU_CLKGATE_EN_S 27 +/* RTC_CNTL_COCPU_SW_INT_TRIGGER : WO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: trigger cocpu register interrupt.*/ +#define RTC_CNTL_COCPU_SW_INT_TRIGGER (BIT(26)) +#define RTC_CNTL_COCPU_SW_INT_TRIGGER_M (BIT(26)) +#define RTC_CNTL_COCPU_SW_INT_TRIGGER_V 0x1 +#define RTC_CNTL_COCPU_SW_INT_TRIGGER_S 26 +/* RTC_CNTL_COCPU_DONE : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: done signal used by riscv to control timer. .*/ +#define RTC_CNTL_COCPU_DONE (BIT(25)) +#define RTC_CNTL_COCPU_DONE_M (BIT(25)) +#define RTC_CNTL_COCPU_DONE_V 0x1 +#define RTC_CNTL_COCPU_DONE_S 25 +/* RTC_CNTL_COCPU_DONE_FORCE : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: 1: select riscv done 0: select ulp done.*/ +#define RTC_CNTL_COCPU_DONE_FORCE (BIT(24)) +#define RTC_CNTL_COCPU_DONE_FORCE_M (BIT(24)) +#define RTC_CNTL_COCPU_DONE_FORCE_V 0x1 +#define RTC_CNTL_COCPU_DONE_FORCE_S 24 +/* RTC_CNTL_COCPU_SEL : R/W ;bitpos:[23] ;default: 1'b1 ; */ +/*description: 1: old ULP 0: new riscV.*/ +#define RTC_CNTL_COCPU_SEL (BIT(23)) +#define RTC_CNTL_COCPU_SEL_M (BIT(23)) +#define RTC_CNTL_COCPU_SEL_V 0x1 +#define RTC_CNTL_COCPU_SEL_S 23 +/* RTC_CNTL_COCPU_SHUT_RESET_EN : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: to reset cocpu.*/ +#define RTC_CNTL_COCPU_SHUT_RESET_EN (BIT(22)) +#define RTC_CNTL_COCPU_SHUT_RESET_EN_M (BIT(22)) +#define RTC_CNTL_COCPU_SHUT_RESET_EN_V 0x1 +#define RTC_CNTL_COCPU_SHUT_RESET_EN_S 22 +/* RTC_CNTL_COCPU_SHUT_2_CLK_DIS : R/W ;bitpos:[21:14] ;default: 8'd40 ; */ +/*description: time from shut cocpu to disable clk.*/ +#define RTC_CNTL_COCPU_SHUT_2_CLK_DIS 0x000000FF +#define RTC_CNTL_COCPU_SHUT_2_CLK_DIS_M ((RTC_CNTL_COCPU_SHUT_2_CLK_DIS_V)<<(RTC_CNTL_COCPU_SHUT_2_CLK_DIS_S)) +#define RTC_CNTL_COCPU_SHUT_2_CLK_DIS_V 0xFF +#define RTC_CNTL_COCPU_SHUT_2_CLK_DIS_S 14 +/* RTC_CNTL_COCPU_SHUT : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: to shut cocpu.*/ +#define RTC_CNTL_COCPU_SHUT (BIT(13)) +#define RTC_CNTL_COCPU_SHUT_M (BIT(13)) +#define RTC_CNTL_COCPU_SHUT_V 0x1 +#define RTC_CNTL_COCPU_SHUT_S 13 +/* RTC_CNTL_COCPU_START_2_INTR_EN : R/W ;bitpos:[12:7] ;default: 6'd16 ; */ +/*description: time from start cocpu to give start interrupt.*/ +#define RTC_CNTL_COCPU_START_2_INTR_EN 0x0000003F +#define RTC_CNTL_COCPU_START_2_INTR_EN_M ((RTC_CNTL_COCPU_START_2_INTR_EN_V)<<(RTC_CNTL_COCPU_START_2_INTR_EN_S)) +#define RTC_CNTL_COCPU_START_2_INTR_EN_V 0x3F +#define RTC_CNTL_COCPU_START_2_INTR_EN_S 7 +/* RTC_CNTL_COCPU_START_2_RESET_DIS : R/W ;bitpos:[6:1] ;default: 6'd8 ; */ +/*description: time from start cocpu to pull down reset.*/ +#define RTC_CNTL_COCPU_START_2_RESET_DIS 0x0000003F +#define RTC_CNTL_COCPU_START_2_RESET_DIS_M ((RTC_CNTL_COCPU_START_2_RESET_DIS_V)<<(RTC_CNTL_COCPU_START_2_RESET_DIS_S)) +#define RTC_CNTL_COCPU_START_2_RESET_DIS_V 0x3F +#define RTC_CNTL_COCPU_START_2_RESET_DIS_S 1 +/* RTC_CNTL_COCPU_CLK_FO : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: cocpu clk force on.*/ +#define RTC_CNTL_COCPU_CLK_FO (BIT(0)) +#define RTC_CNTL_COCPU_CLK_FO_M (BIT(0)) +#define RTC_CNTL_COCPU_CLK_FO_V 0x1 +#define RTC_CNTL_COCPU_CLK_FO_S 0 + +#define RTC_CNTL_TOUCH_CTRL1_REG (DR_REG_RTCCNTL_BASE + 0x108) +/* RTC_CNTL_TOUCH_MEAS_NUM : R/W ;bitpos:[31:16] ;default: 16'h1000 ; */ +/*description: the meas length (in 8MHz).*/ +#define RTC_CNTL_TOUCH_MEAS_NUM 0x0000FFFF +#define RTC_CNTL_TOUCH_MEAS_NUM_M ((RTC_CNTL_TOUCH_MEAS_NUM_V)<<(RTC_CNTL_TOUCH_MEAS_NUM_S)) +#define RTC_CNTL_TOUCH_MEAS_NUM_V 0xFFFF +#define RTC_CNTL_TOUCH_MEAS_NUM_S 16 +/* RTC_CNTL_TOUCH_SLEEP_CYCLES : R/W ;bitpos:[15:0] ;default: 16'h100 ; */ +/*description: sleep cycles for timer.*/ +#define RTC_CNTL_TOUCH_SLEEP_CYCLES 0x0000FFFF +#define RTC_CNTL_TOUCH_SLEEP_CYCLES_M ((RTC_CNTL_TOUCH_SLEEP_CYCLES_V)<<(RTC_CNTL_TOUCH_SLEEP_CYCLES_S)) +#define RTC_CNTL_TOUCH_SLEEP_CYCLES_V 0xFFFF +#define RTC_CNTL_TOUCH_SLEEP_CYCLES_S 0 + +#define RTC_CNTL_TOUCH_CTRL2_REG (DR_REG_RTCCNTL_BASE + 0x10C) +/* RTC_CNTL_TOUCH_CLKGATE_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: touch clock enable.*/ +#define RTC_CNTL_TOUCH_CLKGATE_EN (BIT(31)) +#define RTC_CNTL_TOUCH_CLKGATE_EN_M (BIT(31)) +#define RTC_CNTL_TOUCH_CLKGATE_EN_V 0x1 +#define RTC_CNTL_TOUCH_CLKGATE_EN_S 31 +/* RTC_CNTL_TOUCH_CLK_FO : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: touch clock force on.*/ +#define RTC_CNTL_TOUCH_CLK_FO (BIT(30)) +#define RTC_CNTL_TOUCH_CLK_FO_M (BIT(30)) +#define RTC_CNTL_TOUCH_CLK_FO_V 0x1 +#define RTC_CNTL_TOUCH_CLK_FO_S 30 +/* RTC_CNTL_TOUCH_RESET : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: reset upgrade touch.*/ +#define RTC_CNTL_TOUCH_RESET (BIT(29)) +#define RTC_CNTL_TOUCH_RESET_M (BIT(29)) +#define RTC_CNTL_TOUCH_RESET_V 0x1 +#define RTC_CNTL_TOUCH_RESET_S 29 +/* RTC_CNTL_TOUCH_TIMER_FORCE_DONE : R/W ;bitpos:[28:27] ;default: 2'b0 ; */ +/*description: force touch timer done.*/ +#define RTC_CNTL_TOUCH_TIMER_FORCE_DONE 0x00000003 +#define RTC_CNTL_TOUCH_TIMER_FORCE_DONE_M ((RTC_CNTL_TOUCH_TIMER_FORCE_DONE_V)<<(RTC_CNTL_TOUCH_TIMER_FORCE_DONE_S)) +#define RTC_CNTL_TOUCH_TIMER_FORCE_DONE_V 0x3 +#define RTC_CNTL_TOUCH_TIMER_FORCE_DONE_S 27 +/* RTC_CNTL_TOUCH_SLP_CYC_DIV : R/W ;bitpos:[26:25] ;default: 2'd0 ; */ +/*description: when a touch pad is active.*/ +#define RTC_CNTL_TOUCH_SLP_CYC_DIV 0x00000003 +#define RTC_CNTL_TOUCH_SLP_CYC_DIV_M ((RTC_CNTL_TOUCH_SLP_CYC_DIV_V)<<(RTC_CNTL_TOUCH_SLP_CYC_DIV_S)) +#define RTC_CNTL_TOUCH_SLP_CYC_DIV_V 0x3 +#define RTC_CNTL_TOUCH_SLP_CYC_DIV_S 25 +/* RTC_CNTL_TOUCH_XPD_WAIT : R/W ;bitpos:[24:17] ;default: 8'h4 ; */ +/*description: the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD.*/ +#define RTC_CNTL_TOUCH_XPD_WAIT 0x000000FF +#define RTC_CNTL_TOUCH_XPD_WAIT_M ((RTC_CNTL_TOUCH_XPD_WAIT_V)<<(RTC_CNTL_TOUCH_XPD_WAIT_S)) +#define RTC_CNTL_TOUCH_XPD_WAIT_V 0xFF +#define RTC_CNTL_TOUCH_XPD_WAIT_S 17 +/* RTC_CNTL_TOUCH_START_FORCE : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: 1: to start touch fsm by SW.*/ +#define RTC_CNTL_TOUCH_START_FORCE (BIT(16)) +#define RTC_CNTL_TOUCH_START_FORCE_M (BIT(16)) +#define RTC_CNTL_TOUCH_START_FORCE_V 0x1 +#define RTC_CNTL_TOUCH_START_FORCE_S 16 +/* RTC_CNTL_TOUCH_START_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: 1: start touch fsm.*/ +#define RTC_CNTL_TOUCH_START_EN (BIT(15)) +#define RTC_CNTL_TOUCH_START_EN_M (BIT(15)) +#define RTC_CNTL_TOUCH_START_EN_V 0x1 +#define RTC_CNTL_TOUCH_START_EN_S 15 +/* RTC_CNTL_TOUCH_START_FSM_EN : R/W ;bitpos:[14] ;default: 1'b1 ; */ +/*description: 1: TOUCH_START & TOUCH_XPD is controlled by touch fsm.*/ +#define RTC_CNTL_TOUCH_START_FSM_EN (BIT(14)) +#define RTC_CNTL_TOUCH_START_FSM_EN_M (BIT(14)) +#define RTC_CNTL_TOUCH_START_FSM_EN_V 0x1 +#define RTC_CNTL_TOUCH_START_FSM_EN_S 14 +/* RTC_CNTL_TOUCH_SLP_TIMER_EN : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: touch timer enable bit.*/ +#define RTC_CNTL_TOUCH_SLP_TIMER_EN (BIT(13)) +#define RTC_CNTL_TOUCH_SLP_TIMER_EN_M (BIT(13)) +#define RTC_CNTL_TOUCH_SLP_TIMER_EN_V 0x1 +#define RTC_CNTL_TOUCH_SLP_TIMER_EN_S 13 +/* RTC_CNTL_TOUCH_DBIAS : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: 1:use self bias 0:use bandgap bias.*/ +#define RTC_CNTL_TOUCH_DBIAS (BIT(12)) +#define RTC_CNTL_TOUCH_DBIAS_M (BIT(12)) +#define RTC_CNTL_TOUCH_DBIAS_V 0x1 +#define RTC_CNTL_TOUCH_DBIAS_S 12 +/* RTC_CNTL_TOUCH_REFC : R/W ;bitpos:[11:9] ;default: 3'h0 ; */ +/*description: TOUCH pad0 reference cap.*/ +#define RTC_CNTL_TOUCH_REFC 0x00000007 +#define RTC_CNTL_TOUCH_REFC_M ((RTC_CNTL_TOUCH_REFC_V)<<(RTC_CNTL_TOUCH_REFC_S)) +#define RTC_CNTL_TOUCH_REFC_V 0x7 +#define RTC_CNTL_TOUCH_REFC_S 9 +/* RTC_CNTL_TOUCH_XPD_BIAS : R/W ;bitpos:[8] ;default: 1'd0 ; */ +/*description: TOUCH_XPD_BIAS.*/ +#define RTC_CNTL_TOUCH_XPD_BIAS (BIT(8)) +#define RTC_CNTL_TOUCH_XPD_BIAS_M (BIT(8)) +#define RTC_CNTL_TOUCH_XPD_BIAS_V 0x1 +#define RTC_CNTL_TOUCH_XPD_BIAS_S 8 +/* RTC_CNTL_TOUCH_DREFH : R/W ;bitpos:[7:6] ;default: 2'b11 ; */ +/*description: TOUCH_DREFH.*/ +#define RTC_CNTL_TOUCH_DREFH 0x00000003 +#define RTC_CNTL_TOUCH_DREFH_M ((RTC_CNTL_TOUCH_DREFH_V)<<(RTC_CNTL_TOUCH_DREFH_S)) +#define RTC_CNTL_TOUCH_DREFH_V 0x3 +#define RTC_CNTL_TOUCH_DREFH_S 6 +/* RTC_CNTL_TOUCH_DREFL : R/W ;bitpos:[5:4] ;default: 2'b00 ; */ +/*description: TOUCH_DREFL.*/ +#define RTC_CNTL_TOUCH_DREFL 0x00000003 +#define RTC_CNTL_TOUCH_DREFL_M ((RTC_CNTL_TOUCH_DREFL_V)<<(RTC_CNTL_TOUCH_DREFL_S)) +#define RTC_CNTL_TOUCH_DREFL_V 0x3 +#define RTC_CNTL_TOUCH_DREFL_S 4 +/* RTC_CNTL_TOUCH_DRANGE : R/W ;bitpos:[3:2] ;default: 2'b11 ; */ +/*description: TOUCH_DRANGE.*/ +#define RTC_CNTL_TOUCH_DRANGE 0x00000003 +#define RTC_CNTL_TOUCH_DRANGE_M ((RTC_CNTL_TOUCH_DRANGE_V)<<(RTC_CNTL_TOUCH_DRANGE_S)) +#define RTC_CNTL_TOUCH_DRANGE_V 0x3 +#define RTC_CNTL_TOUCH_DRANGE_S 2 + +#define RTC_CNTL_TOUCH_SCAN_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x110) +/* RTC_CNTL_TOUCH_OUT_RING : R/W ;bitpos:[31:28] ;default: 4'hf ; */ +/*description: select out ring pad.*/ +#define RTC_CNTL_TOUCH_OUT_RING 0x0000000F +#define RTC_CNTL_TOUCH_OUT_RING_M ((RTC_CNTL_TOUCH_OUT_RING_V)<<(RTC_CNTL_TOUCH_OUT_RING_S)) +#define RTC_CNTL_TOUCH_OUT_RING_V 0xF +#define RTC_CNTL_TOUCH_OUT_RING_S 28 +/* RTC_CNTL_TOUCH_BUFDRV : R/W ;bitpos:[27:25] ;default: 3'h0 ; */ +/*description: touch7 buffer driver strength.*/ +#define RTC_CNTL_TOUCH_BUFDRV 0x00000007 +#define RTC_CNTL_TOUCH_BUFDRV_M ((RTC_CNTL_TOUCH_BUFDRV_V)<<(RTC_CNTL_TOUCH_BUFDRV_S)) +#define RTC_CNTL_TOUCH_BUFDRV_V 0x7 +#define RTC_CNTL_TOUCH_BUFDRV_S 25 +/* RTC_CNTL_TOUCH_SCAN_PAD_MAP : R/W ;bitpos:[24:10] ;default: 15'h0 ; */ +/*description: touch scan mode pad enable map.*/ +#define RTC_CNTL_TOUCH_SCAN_PAD_MAP 0x00007FFF +#define RTC_CNTL_TOUCH_SCAN_PAD_MAP_M ((RTC_CNTL_TOUCH_SCAN_PAD_MAP_V)<<(RTC_CNTL_TOUCH_SCAN_PAD_MAP_S)) +#define RTC_CNTL_TOUCH_SCAN_PAD_MAP_V 0x7FFF +#define RTC_CNTL_TOUCH_SCAN_PAD_MAP_S 10 +/* RTC_CNTL_TOUCH_SHIELD_PAD_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: touch pad14 will be used as shield.*/ +#define RTC_CNTL_TOUCH_SHIELD_PAD_EN (BIT(9)) +#define RTC_CNTL_TOUCH_SHIELD_PAD_EN_M (BIT(9)) +#define RTC_CNTL_TOUCH_SHIELD_PAD_EN_V 0x1 +#define RTC_CNTL_TOUCH_SHIELD_PAD_EN_S 9 +/* RTC_CNTL_TOUCH_INACTIVE_CONNECTION : R/W ;bitpos:[8] ;default: 1'b1 ; */ +/*description: inactive touch pads connect to 1: gnd 0: HighZ.*/ +#define RTC_CNTL_TOUCH_INACTIVE_CONNECTION (BIT(8)) +#define RTC_CNTL_TOUCH_INACTIVE_CONNECTION_M (BIT(8)) +#define RTC_CNTL_TOUCH_INACTIVE_CONNECTION_V 0x1 +#define RTC_CNTL_TOUCH_INACTIVE_CONNECTION_S 8 +/* RTC_CNTL_TOUCH_DENOISE_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: touch pad0 will be used to de-noise.*/ +#define RTC_CNTL_TOUCH_DENOISE_EN (BIT(2)) +#define RTC_CNTL_TOUCH_DENOISE_EN_M (BIT(2)) +#define RTC_CNTL_TOUCH_DENOISE_EN_V 0x1 +#define RTC_CNTL_TOUCH_DENOISE_EN_S 2 +/* RTC_CNTL_TOUCH_DENOISE_RES : R/W ;bitpos:[1:0] ;default: 2'd2 ; */ +/*description: De-noise resolution: 12/10/8/4 bit.*/ +#define RTC_CNTL_TOUCH_DENOISE_RES 0x00000003 +#define RTC_CNTL_TOUCH_DENOISE_RES_M ((RTC_CNTL_TOUCH_DENOISE_RES_V)<<(RTC_CNTL_TOUCH_DENOISE_RES_S)) +#define RTC_CNTL_TOUCH_DENOISE_RES_V 0x3 +#define RTC_CNTL_TOUCH_DENOISE_RES_S 0 + +#define RTC_CNTL_TOUCH_SLP_THRES_REG (DR_REG_RTCCNTL_BASE + 0x114) +/* RTC_CNTL_TOUCH_SLP_PAD : R/W ;bitpos:[31:27] ;default: 4'hf ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_SLP_PAD 0x0000001F +#define RTC_CNTL_TOUCH_SLP_PAD_M ((RTC_CNTL_TOUCH_SLP_PAD_V)<<(RTC_CNTL_TOUCH_SLP_PAD_S)) +#define RTC_CNTL_TOUCH_SLP_PAD_V 0x1F +#define RTC_CNTL_TOUCH_SLP_PAD_S 27 +/* RTC_CNTL_TOUCH_SLP_APPROACH_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: sleep pad approach function enable.*/ +#define RTC_CNTL_TOUCH_SLP_APPROACH_EN (BIT(26)) +#define RTC_CNTL_TOUCH_SLP_APPROACH_EN_M (BIT(26)) +#define RTC_CNTL_TOUCH_SLP_APPROACH_EN_V 0x1 +#define RTC_CNTL_TOUCH_SLP_APPROACH_EN_S 26 +/* RTC_CNTL_TOUCH_SLP_TH : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: the threshold for sleep touch pad.*/ +#define RTC_CNTL_TOUCH_SLP_TH 0x003FFFFF +#define RTC_CNTL_TOUCH_SLP_TH_M ((RTC_CNTL_TOUCH_SLP_TH_V)<<(RTC_CNTL_TOUCH_SLP_TH_S)) +#define RTC_CNTL_TOUCH_SLP_TH_V 0x3FFFFF +#define RTC_CNTL_TOUCH_SLP_TH_S 0 + +#define RTC_CNTL_TOUCH_APPROACH_REG (DR_REG_RTCCNTL_BASE + 0x118) +/* RTC_CNTL_TOUCH_APPROACH_MEAS_TIME : R/W ;bitpos:[31:24] ;default: 8'd80 ; */ +/*description: approach pads total meas times.*/ +#define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME 0x000000FF +#define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_M ((RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_V)<<(RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_S)) +#define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_V 0xFF +#define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_S 24 +/* RTC_CNTL_TOUCH_SLP_CHANNEL_CLR : WO ;bitpos:[23] ;default: 1'd0 ; */ +/*description: clear touch slp channel.*/ +#define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR (BIT(23)) +#define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_M (BIT(23)) +#define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_V 0x1 +#define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_S 23 + +#define RTC_CNTL_TOUCH_FILTER_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x11C) +/* RTC_CNTL_TOUCH_FILTER_EN : R/W ;bitpos:[31] ;default: 1'b1 ; */ +/*description: touch filter enable.*/ +#define RTC_CNTL_TOUCH_FILTER_EN (BIT(31)) +#define RTC_CNTL_TOUCH_FILTER_EN_M (BIT(31)) +#define RTC_CNTL_TOUCH_FILTER_EN_V 0x1 +#define RTC_CNTL_TOUCH_FILTER_EN_S 31 +/* RTC_CNTL_TOUCH_FILTER_MODE : R/W ;bitpos:[30:28] ;default: 3'd1 ; */ +/*description: 0: IIR ? 1: IIR ? 2: IIR 1/8 3: Jitter.*/ +#define RTC_CNTL_TOUCH_FILTER_MODE 0x00000007 +#define RTC_CNTL_TOUCH_FILTER_MODE_M ((RTC_CNTL_TOUCH_FILTER_MODE_V)<<(RTC_CNTL_TOUCH_FILTER_MODE_S)) +#define RTC_CNTL_TOUCH_FILTER_MODE_V 0x7 +#define RTC_CNTL_TOUCH_FILTER_MODE_S 28 +/* RTC_CNTL_TOUCH_DEBOUNCE : R/W ;bitpos:[27:25] ;default: 3'd3 ; */ +/*description: debounce counter.*/ +#define RTC_CNTL_TOUCH_DEBOUNCE 0x00000007 +#define RTC_CNTL_TOUCH_DEBOUNCE_M ((RTC_CNTL_TOUCH_DEBOUNCE_V)<<(RTC_CNTL_TOUCH_DEBOUNCE_S)) +#define RTC_CNTL_TOUCH_DEBOUNCE_V 0x7 +#define RTC_CNTL_TOUCH_DEBOUNCE_S 25 +/* RTC_CNTL_TOUCH_CONFIG3 : R/W ;bitpos:[24:23] ;default: 2'd1 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_CONFIG3 0x00000003 +#define RTC_CNTL_TOUCH_CONFIG3_M ((RTC_CNTL_TOUCH_CONFIG3_V) << (RTC_CNTL_TOUCH_CONFIG3_S)) +#define RTC_CNTL_TOUCH_CONFIG3_V 0x3 +#define RTC_CNTL_TOUCH_CONFIG3_S 23 +/* RTC_CNTL_TOUCH_NOISE_THRES : R/W ;bitpos:[22:21] ;default: 2'd1 ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_NOISE_THRES 0x00000003 +#define RTC_CNTL_TOUCH_NOISE_THRES_M ((RTC_CNTL_TOUCH_NOISE_THRES_V)<<(RTC_CNTL_TOUCH_NOISE_THRES_S)) +#define RTC_CNTL_TOUCH_NOISE_THRES_V 0x3 +#define RTC_CNTL_TOUCH_NOISE_THRES_S 21 +/* RTC_CNTL_TOUCH_CONFIG2 : R/W ;bitpos:[20:19] ;default: 2'd1 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_CONFIG2 0x00000003 +#define RTC_CNTL_TOUCH_CONFIG2_M ((RTC_CNTL_TOUCH_CONFIG2_V) << (RTC_CNTL_TOUCH_CONFIG2_S)) +#define RTC_CNTL_TOUCH_CONFIG2_V 0x3 +#define RTC_CNTL_TOUCH_CONFIG2_S 19 +/* RTC_CNTL_TOUCH_CONFIG1 : R/W ;bitpos:[18:15] ;default: 4'd5 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_CONFIG1 0x0000000F +#define RTC_CNTL_TOUCH_CONFIG1_M ((RTC_CNTL_TOUCH_CONFIG1_V) << (RTC_CNTL_TOUCH_CONFIG1_S)) +#define RTC_CNTL_TOUCH_CONFIG1_V 0xF +#define RTC_CNTL_TOUCH_CONFIG1_S 15 +/* RTC_CNTL_TOUCH_JITTER_STEP : R/W ;bitpos:[14:11] ;default: 4'd1 ; */ +/*description: touch jitter step.*/ +#define RTC_CNTL_TOUCH_JITTER_STEP 0x0000000F +#define RTC_CNTL_TOUCH_JITTER_STEP_M ((RTC_CNTL_TOUCH_JITTER_STEP_V)<<(RTC_CNTL_TOUCH_JITTER_STEP_S)) +#define RTC_CNTL_TOUCH_JITTER_STEP_V 0xF +#define RTC_CNTL_TOUCH_JITTER_STEP_S 11 +/* RTC_CNTL_TOUCH_SMOOTH_LVL : R/W ;bitpos:[10:9] ;default: 2'd0 ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_SMOOTH_LVL 0x00000003 +#define RTC_CNTL_TOUCH_SMOOTH_LVL_M ((RTC_CNTL_TOUCH_SMOOTH_LVL_V)<<(RTC_CNTL_TOUCH_SMOOTH_LVL_S)) +#define RTC_CNTL_TOUCH_SMOOTH_LVL_V 0x3 +#define RTC_CNTL_TOUCH_SMOOTH_LVL_S 9 +/* RTC_CNTL_TOUCH_BYPASS_NOISE_THRES : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_BYPASS_NOISE_THRES (BIT(8)) +#define RTC_CNTL_TOUCH_BYPASS_NOISE_THRES_M (BIT(8)) +#define RTC_CNTL_TOUCH_BYPASS_NOISE_THRES_V 0x1 +#define RTC_CNTL_TOUCH_BYPASS_NOISE_THRES_S 8 +/* RTC_CNTL_TOUCH_BYPASS_NN_THRES : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_BYPASS_NN_THRES (BIT(7)) +#define RTC_CNTL_TOUCH_BYPASS_NN_THRES_M (BIT(7)) +#define RTC_CNTL_TOUCH_BYPASS_NN_THRES_V 0x1 +#define RTC_CNTL_TOUCH_BYPASS_NN_THRES_S 7 + +#define RTC_CNTL_USB_CONF_REG (DR_REG_RTCCNTL_BASE + 0x120) +/* RTC_CNTL_SW_HW_USB_PHY_SEL : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_SW_HW_USB_PHY_SEL (BIT(20)) +#define RTC_CNTL_SW_HW_USB_PHY_SEL_M (BIT(20)) +#define RTC_CNTL_SW_HW_USB_PHY_SEL_V 0x1 +#define RTC_CNTL_SW_HW_USB_PHY_SEL_S 20 +/* RTC_CNTL_SW_USB_PHY_SEL : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_SW_USB_PHY_SEL (BIT(19)) +#define RTC_CNTL_SW_USB_PHY_SEL_M (BIT(19)) +#define RTC_CNTL_SW_USB_PHY_SEL_V 0x1 +#define RTC_CNTL_SW_USB_PHY_SEL_S 19 +/* RTC_CNTL_IO_MUX_RESET_DISABLE : R/W ;bitpos:[18] ;default: 1'd0 ; */ +/*description: .*/ +#define RTC_CNTL_IO_MUX_RESET_DISABLE (BIT(18)) +#define RTC_CNTL_IO_MUX_RESET_DISABLE_M (BIT(18)) +#define RTC_CNTL_IO_MUX_RESET_DISABLE_V 0x1 +#define RTC_CNTL_IO_MUX_RESET_DISABLE_S 18 +/* RTC_CNTL_USB_RESET_DISABLE : R/W ;bitpos:[17] ;default: 1'd0 ; */ +/*description: .*/ +#define RTC_CNTL_USB_RESET_DISABLE (BIT(17)) +#define RTC_CNTL_USB_RESET_DISABLE_M (BIT(17)) +#define RTC_CNTL_USB_RESET_DISABLE_V 0x1 +#define RTC_CNTL_USB_RESET_DISABLE_S 17 +/* RTC_CNTL_USB_TX_EN_OVERRIDE : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: .*/ +#define RTC_CNTL_USB_TX_EN_OVERRIDE (BIT(16)) +#define RTC_CNTL_USB_TX_EN_OVERRIDE_M (BIT(16)) +#define RTC_CNTL_USB_TX_EN_OVERRIDE_V 0x1 +#define RTC_CNTL_USB_TX_EN_OVERRIDE_S 16 +/* RTC_CNTL_USB_TX_EN : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: .*/ +#define RTC_CNTL_USB_TX_EN (BIT(15)) +#define RTC_CNTL_USB_TX_EN_M (BIT(15)) +#define RTC_CNTL_USB_TX_EN_V 0x1 +#define RTC_CNTL_USB_TX_EN_S 15 +/* RTC_CNTL_USB_TXP : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: .*/ +#define RTC_CNTL_USB_TXP (BIT(14)) +#define RTC_CNTL_USB_TXP_M (BIT(14)) +#define RTC_CNTL_USB_TXP_V 0x1 +#define RTC_CNTL_USB_TXP_S 14 +/* RTC_CNTL_USB_TXM : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: .*/ +#define RTC_CNTL_USB_TXM (BIT(13)) +#define RTC_CNTL_USB_TXM_M (BIT(13)) +#define RTC_CNTL_USB_TXM_V 0x1 +#define RTC_CNTL_USB_TXM_S 13 +/* RTC_CNTL_USB_PAD_ENABLE : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: .*/ +#define RTC_CNTL_USB_PAD_ENABLE (BIT(12)) +#define RTC_CNTL_USB_PAD_ENABLE_M (BIT(12)) +#define RTC_CNTL_USB_PAD_ENABLE_V 0x1 +#define RTC_CNTL_USB_PAD_ENABLE_S 12 +/* RTC_CNTL_USB_PAD_ENABLE_OVERRIDE : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: .*/ +#define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE (BIT(11)) +#define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_M (BIT(11)) +#define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_V 0x1 +#define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_S 11 +/* RTC_CNTL_USB_PULLUP_VALUE : R/W ;bitpos:[10] ;default: 1'd0 ; */ +/*description: .*/ +#define RTC_CNTL_USB_PULLUP_VALUE (BIT(10)) +#define RTC_CNTL_USB_PULLUP_VALUE_M (BIT(10)) +#define RTC_CNTL_USB_PULLUP_VALUE_V 0x1 +#define RTC_CNTL_USB_PULLUP_VALUE_S 10 +/* RTC_CNTL_USB_DM_PULLDOWN : R/W ;bitpos:[9] ;default: 1'd0 ; */ +/*description: .*/ +#define RTC_CNTL_USB_DM_PULLDOWN (BIT(9)) +#define RTC_CNTL_USB_DM_PULLDOWN_M (BIT(9)) +#define RTC_CNTL_USB_DM_PULLDOWN_V 0x1 +#define RTC_CNTL_USB_DM_PULLDOWN_S 9 +/* RTC_CNTL_USB_DM_PULLUP : R/W ;bitpos:[8] ;default: 1'd0 ; */ +/*description: .*/ +#define RTC_CNTL_USB_DM_PULLUP (BIT(8)) +#define RTC_CNTL_USB_DM_PULLUP_M (BIT(8)) +#define RTC_CNTL_USB_DM_PULLUP_V 0x1 +#define RTC_CNTL_USB_DM_PULLUP_S 8 +/* RTC_CNTL_USB_DP_PULLDOWN : R/W ;bitpos:[7] ;default: 1'd0 ; */ +/*description: .*/ +#define RTC_CNTL_USB_DP_PULLDOWN (BIT(7)) +#define RTC_CNTL_USB_DP_PULLDOWN_M (BIT(7)) +#define RTC_CNTL_USB_DP_PULLDOWN_V 0x1 +#define RTC_CNTL_USB_DP_PULLDOWN_S 7 +/* RTC_CNTL_USB_DP_PULLUP : R/W ;bitpos:[6] ;default: 1'd0 ; */ +/*description: .*/ +#define RTC_CNTL_USB_DP_PULLUP (BIT(6)) +#define RTC_CNTL_USB_DP_PULLUP_M (BIT(6)) +#define RTC_CNTL_USB_DP_PULLUP_V 0x1 +#define RTC_CNTL_USB_DP_PULLUP_S 6 +/* RTC_CNTL_USB_PAD_PULL_OVERRIDE : R/W ;bitpos:[5] ;default: 1'd0 ; */ +/*description: .*/ +#define RTC_CNTL_USB_PAD_PULL_OVERRIDE (BIT(5)) +#define RTC_CNTL_USB_PAD_PULL_OVERRIDE_M (BIT(5)) +#define RTC_CNTL_USB_PAD_PULL_OVERRIDE_V 0x1 +#define RTC_CNTL_USB_PAD_PULL_OVERRIDE_S 5 +/* RTC_CNTL_USB_VREF_OVERRIDE : R/W ;bitpos:[4] ;default: 1'd0 ; */ +/*description: .*/ +#define RTC_CNTL_USB_VREF_OVERRIDE (BIT(4)) +#define RTC_CNTL_USB_VREF_OVERRIDE_M (BIT(4)) +#define RTC_CNTL_USB_VREF_OVERRIDE_V 0x1 +#define RTC_CNTL_USB_VREF_OVERRIDE_S 4 +/* RTC_CNTL_USB_VREFL : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ +/*description: .*/ +#define RTC_CNTL_USB_VREFL 0x00000003 +#define RTC_CNTL_USB_VREFL_M ((RTC_CNTL_USB_VREFL_V)<<(RTC_CNTL_USB_VREFL_S)) +#define RTC_CNTL_USB_VREFL_V 0x3 +#define RTC_CNTL_USB_VREFL_S 2 +/* RTC_CNTL_USB_VREFH : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: .*/ +#define RTC_CNTL_USB_VREFH 0x00000003 +#define RTC_CNTL_USB_VREFH_M ((RTC_CNTL_USB_VREFH_V)<<(RTC_CNTL_USB_VREFH_S)) +#define RTC_CNTL_USB_VREFH_V 0x3 +#define RTC_CNTL_USB_VREFH_S 0 + +#define RTC_CNTL_TOUCH_TIMEOUT_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x124) +/* RTC_CNTL_TOUCH_TIMEOUT_EN : R/W ;bitpos:[22] ;default: 1'b1 ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_TIMEOUT_EN (BIT(22)) +#define RTC_CNTL_TOUCH_TIMEOUT_EN_M (BIT(22)) +#define RTC_CNTL_TOUCH_TIMEOUT_EN_V 0x1 +#define RTC_CNTL_TOUCH_TIMEOUT_EN_S 22 +/* RTC_CNTL_TOUCH_TIMEOUT_NUM : R/W ;bitpos:[21:0] ;default: 22'h3fffff ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_TIMEOUT_NUM 0x003FFFFF +#define RTC_CNTL_TOUCH_TIMEOUT_NUM_M ((RTC_CNTL_TOUCH_TIMEOUT_NUM_V)<<(RTC_CNTL_TOUCH_TIMEOUT_NUM_S)) +#define RTC_CNTL_TOUCH_TIMEOUT_NUM_V 0x3FFFFF +#define RTC_CNTL_TOUCH_TIMEOUT_NUM_S 0 + +#define RTC_CNTL_SLP_REJECT_CAUSE_REG (DR_REG_RTCCNTL_BASE + 0x128) +/* RTC_CNTL_REJECT_CAUSE : RO ;bitpos:[17:0] ;default: 18'd0 ; */ +/*description: sleep reject cause.*/ +#define RTC_CNTL_REJECT_CAUSE 0x0003FFFF +#define RTC_CNTL_REJECT_CAUSE_M ((RTC_CNTL_REJECT_CAUSE_V)<<(RTC_CNTL_REJECT_CAUSE_S)) +#define RTC_CNTL_REJECT_CAUSE_V 0x3FFFF +#define RTC_CNTL_REJECT_CAUSE_S 0 + +#define RTC_CNTL_OPTION1_REG (DR_REG_RTCCNTL_BASE + 0x12C) +/* RTC_CNTL_FORCE_DOWNLOAD_BOOT : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: .*/ +#define RTC_CNTL_FORCE_DOWNLOAD_BOOT (BIT(0)) +#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_M (BIT(0)) +#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_V 0x1 +#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_S 0 + +#define RTC_CNTL_SLP_WAKEUP_CAUSE_REG (DR_REG_RTCCNTL_BASE + 0x130) +/* RTC_CNTL_WAKEUP_CAUSE : RO ;bitpos:[16:0] ;default: 17'd0 ; */ +/*description: sleep wakeup cause.*/ +#define RTC_CNTL_WAKEUP_CAUSE 0x0001FFFF +#define RTC_CNTL_WAKEUP_CAUSE_M ((RTC_CNTL_WAKEUP_CAUSE_V)<<(RTC_CNTL_WAKEUP_CAUSE_S)) +#define RTC_CNTL_WAKEUP_CAUSE_V 0x1FFFF +#define RTC_CNTL_WAKEUP_CAUSE_S 0 + +#define RTC_CNTL_ULP_CP_TIMER_1_REG (DR_REG_RTCCNTL_BASE + 0x134) +/* RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE : R/W ;bitpos:[31:8] ;default: 24'd200 ; */ +/*description: sleep cycles for ULP-coprocessor timer.*/ +#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE 0x00FFFFFF +#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_M ((RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V)<<(RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S)) +#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V 0xFFFFFF +#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S 8 + +#define RTC_CNTL_INT_ENA_W1TS_REG (DR_REG_RTCCNTL_BASE + 0x138) +/* RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS : WO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS (BIT(20)) +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_M (BIT(20)) +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_S 20 +/* RTC_CNTL_GLITCH_DET_INT_ENA_W1TS : WO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: enable gitch det interrupt.*/ +#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_M (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_S 19 +/* RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TS : WO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: enable touch timeout interrupt.*/ +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TS (BIT(18)) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TS_M (BIT(18)) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TS_S 18 +/* RTC_CNTL_COCPU_TRAP_INT_ENA_W1TS : WO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: enable cocpu trap interrupt.*/ +#define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TS (BIT(17)) +#define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TS_M (BIT(17)) +#define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TS_S 17 +/* RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: enable xtal32k_dead interrupt.*/ +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_M (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_S 16 +/* RTC_CNTL_SWD_INT_ENA_W1TS : WO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: enable super watch dog interrupt.*/ +#define RTC_CNTL_SWD_INT_ENA_W1TS (BIT(15)) +#define RTC_CNTL_SWD_INT_ENA_W1TS_M (BIT(15)) +#define RTC_CNTL_SWD_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_SWD_INT_ENA_W1TS_S 15 +/* RTC_CNTL_SARADC2_INT_ENA_W1TS : WO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: enable saradc2 interrupt.*/ +#define RTC_CNTL_SARADC2_INT_ENA_W1TS (BIT(14)) +#define RTC_CNTL_SARADC2_INT_ENA_W1TS_M (BIT(14)) +#define RTC_CNTL_SARADC2_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_SARADC2_INT_ENA_W1TS_S 14 +/* RTC_CNTL_COCPU_INT_ENA_W1TS : WO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: enable riscV cocpu interrupt.*/ +#define RTC_CNTL_COCPU_INT_ENA_W1TS (BIT(13)) +#define RTC_CNTL_COCPU_INT_ENA_W1TS_M (BIT(13)) +#define RTC_CNTL_COCPU_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_COCPU_INT_ENA_W1TS_S 13 +/* RTC_CNTL_TSENS_INT_ENA_W1TS : WO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: enable tsens interrupt.*/ +#define RTC_CNTL_TSENS_INT_ENA_W1TS (BIT(12)) +#define RTC_CNTL_TSENS_INT_ENA_W1TS_M (BIT(12)) +#define RTC_CNTL_TSENS_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_TSENS_INT_ENA_W1TS_S 12 +/* RTC_CNTL_SARADC1_INT_ENA_W1TS : WO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: enable saradc1 interrupt.*/ +#define RTC_CNTL_SARADC1_INT_ENA_W1TS (BIT(11)) +#define RTC_CNTL_SARADC1_INT_ENA_W1TS_M (BIT(11)) +#define RTC_CNTL_SARADC1_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_SARADC1_INT_ENA_W1TS_S 11 +/* RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS : WO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: enable RTC main timer interrupt.*/ +#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_M (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_S 10 +/* RTC_CNTL_BROWN_OUT_INT_ENA_W1TS : WO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: enable brown out interrupt.*/ +#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_M (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_S 9 +/* RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TS : WO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: enable touch inactive interrupt.*/ +#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TS (BIT(8)) +#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TS_M (BIT(8)) +#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TS_S 8 +/* RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TS : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: enable touch active interrupt.*/ +#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TS (BIT(7)) +#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TS_M (BIT(7)) +#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TS_S 7 +/* RTC_CNTL_TOUCH_DONE_INT_ENA_W1TS : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: enable touch done interrupt.*/ +#define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TS (BIT(6)) +#define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TS_M (BIT(6)) +#define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TS_S 6 +/* RTC_CNTL_ULP_CP_INT_ENA_W1TS : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: enable ULP-coprocessor interrupt.*/ +#define RTC_CNTL_ULP_CP_INT_ENA_W1TS (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_ENA_W1TS_M (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_ULP_CP_INT_ENA_W1TS_S 5 +/* RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TS : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: enable touch scan done interrupt.*/ +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TS (BIT(4)) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TS_M (BIT(4)) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TS_S 4 +/* RTC_CNTL_WDT_INT_ENA_W1TS : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: enable RTC WDT interrupt.*/ +#define RTC_CNTL_WDT_INT_ENA_W1TS (BIT(3)) +#define RTC_CNTL_WDT_INT_ENA_W1TS_M (BIT(3)) +#define RTC_CNTL_WDT_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_WDT_INT_ENA_W1TS_S 3 +/* RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: enable SDIO idle interrupt.*/ +#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS_M (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS_S 2 +/* RTC_CNTL_SLP_REJECT_INT_ENA_W1TS : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: enable sleep reject interrupt.*/ +#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_S 1 +/* RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: enable sleep wakeup interrupt.*/ +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_S 0 + +#define RTC_CNTL_INT_ENA_W1TC_REG (DR_REG_RTCCNTL_BASE + 0x13C) +/* RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC : WO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC (BIT(20)) +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_M (BIT(20)) +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_S 20 +/* RTC_CNTL_GLITCH_DET_INT_ENA_W1TC : WO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: enable gitch det interrupt.*/ +#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_M (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_S 19 +/* RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TC : WO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: enable touch timeout interrupt.*/ +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TC (BIT(18)) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TC_M (BIT(18)) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TC_S 18 +/* RTC_CNTL_COCPU_TRAP_INT_ENA_W1TC : WO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: enable cocpu trap interrupt.*/ +#define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TC (BIT(17)) +#define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TC_M (BIT(17)) +#define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TC_S 17 +/* RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: enable xtal32k_dead interrupt.*/ +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_M (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_S 16 +/* RTC_CNTL_SWD_INT_ENA_W1TC : WO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: enable super watch dog interrupt.*/ +#define RTC_CNTL_SWD_INT_ENA_W1TC (BIT(15)) +#define RTC_CNTL_SWD_INT_ENA_W1TC_M (BIT(15)) +#define RTC_CNTL_SWD_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_SWD_INT_ENA_W1TC_S 15 +/* RTC_CNTL_SARADC2_INT_ENA_W1TC : WO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: enable saradc2 interrupt.*/ +#define RTC_CNTL_SARADC2_INT_ENA_W1TC (BIT(14)) +#define RTC_CNTL_SARADC2_INT_ENA_W1TC_M (BIT(14)) +#define RTC_CNTL_SARADC2_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_SARADC2_INT_ENA_W1TC_S 14 +/* RTC_CNTL_COCPU_INT_ENA_W1TC : WO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: enable riscV cocpu interrupt.*/ +#define RTC_CNTL_COCPU_INT_ENA_W1TC (BIT(13)) +#define RTC_CNTL_COCPU_INT_ENA_W1TC_M (BIT(13)) +#define RTC_CNTL_COCPU_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_COCPU_INT_ENA_W1TC_S 13 +/* RTC_CNTL_TSENS_INT_ENA_W1TC : WO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: enable tsens interrupt.*/ +#define RTC_CNTL_TSENS_INT_ENA_W1TC (BIT(12)) +#define RTC_CNTL_TSENS_INT_ENA_W1TC_M (BIT(12)) +#define RTC_CNTL_TSENS_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_TSENS_INT_ENA_W1TC_S 12 +/* RTC_CNTL_SARADC1_INT_ENA_W1TC : WO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: enable saradc1 interrupt.*/ +#define RTC_CNTL_SARADC1_INT_ENA_W1TC (BIT(11)) +#define RTC_CNTL_SARADC1_INT_ENA_W1TC_M (BIT(11)) +#define RTC_CNTL_SARADC1_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_SARADC1_INT_ENA_W1TC_S 11 +/* RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC : WO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: enable RTC main timer interrupt.*/ +#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_M (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_S 10 +/* RTC_CNTL_BROWN_OUT_INT_ENA_W1TC : WO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: enable brown out interrupt.*/ +#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_M (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_S 9 +/* RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TC : WO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: enable touch inactive interrupt.*/ +#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TC (BIT(8)) +#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TC_M (BIT(8)) +#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TC_S 8 +/* RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TC : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: enable touch active interrupt.*/ +#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TC (BIT(7)) +#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TC_M (BIT(7)) +#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TC_S 7 +/* RTC_CNTL_TOUCH_DONE_INT_ENA_W1TC : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: enable touch done interrupt.*/ +#define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TC (BIT(6)) +#define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TC_M (BIT(6)) +#define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TC_S 6 +/* RTC_CNTL_ULP_CP_INT_ENA_W1TC : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: enable ULP-coprocessor interrupt.*/ +#define RTC_CNTL_ULP_CP_INT_ENA_W1TC (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_ENA_W1TC_M (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_ULP_CP_INT_ENA_W1TC_S 5 +/* RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TC : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: enable touch scan done interrupt.*/ +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TC (BIT(4)) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TC_M (BIT(4)) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TC_S 4 +/* RTC_CNTL_WDT_INT_ENA_W1TC : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: enable RTC WDT interrupt.*/ +#define RTC_CNTL_WDT_INT_ENA_W1TC (BIT(3)) +#define RTC_CNTL_WDT_INT_ENA_W1TC_M (BIT(3)) +#define RTC_CNTL_WDT_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_WDT_INT_ENA_W1TC_S 3 +/* RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: enable SDIO idle interrupt.*/ +#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC_M (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC_S 2 +/* RTC_CNTL_SLP_REJECT_INT_ENA_W1TC : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: enable sleep reject interrupt.*/ +#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_S 1 +/* RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: enable sleep wakeup interrupt.*/ +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_S 0 + +#define RTC_CNTL_RETENTION_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x140) +/* RTC_CNTL_RETENTION_WAIT : R/W ;bitpos:[31:25] ;default: 7'd20 ; */ +/*description: wait cycles for rention operation.*/ +#define RTC_CNTL_RETENTION_WAIT 0x0000007F +#define RTC_CNTL_RETENTION_WAIT_M ((RTC_CNTL_RETENTION_WAIT_V)<<(RTC_CNTL_RETENTION_WAIT_S)) +#define RTC_CNTL_RETENTION_WAIT_V 0x7F +#define RTC_CNTL_RETENTION_WAIT_S 25 +/* RTC_CNTL_RETENTION_EN : R/W ;bitpos:[24] ;default: 1'd0 ; */ +/*description: .*/ +#define RTC_CNTL_RETENTION_EN (BIT(24)) +#define RTC_CNTL_RETENTION_EN_M (BIT(24)) +#define RTC_CNTL_RETENTION_EN_V 0x1 +#define RTC_CNTL_RETENTION_EN_S 24 +/* RTC_CNTL_RETENTION_CLKOFF_WAIT : R/W ;bitpos:[23:20] ;default: 4'd3 ; */ +/*description: .*/ +#define RTC_CNTL_RETENTION_CLKOFF_WAIT 0x0000000F +#define RTC_CNTL_RETENTION_CLKOFF_WAIT_M ((RTC_CNTL_RETENTION_CLKOFF_WAIT_V)<<(RTC_CNTL_RETENTION_CLKOFF_WAIT_S)) +#define RTC_CNTL_RETENTION_CLKOFF_WAIT_V 0xF +#define RTC_CNTL_RETENTION_CLKOFF_WAIT_S 20 +/* RTC_CNTL_RETENTION_DONE_WAIT : R/W ;bitpos:[19:17] ;default: 3'd2 ; */ +/*description: .*/ +#define RTC_CNTL_RETENTION_DONE_WAIT 0x00000007 +#define RTC_CNTL_RETENTION_DONE_WAIT_M ((RTC_CNTL_RETENTION_DONE_WAIT_V)<<(RTC_CNTL_RETENTION_DONE_WAIT_S)) +#define RTC_CNTL_RETENTION_DONE_WAIT_V 0x7 +#define RTC_CNTL_RETENTION_DONE_WAIT_S 17 +/* RTC_CNTL_RETENTION_CLK_SEL : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_RETENTION_CLK_SEL (BIT(16)) +#define RTC_CNTL_RETENTION_CLK_SEL_M (BIT(16)) +#define RTC_CNTL_RETENTION_CLK_SEL_V 0x1 +#define RTC_CNTL_RETENTION_CLK_SEL_S 16 +/* RTC_CNTL_RETENTION_TARGET : R/W ;bitpos:[15:14] ;default: 2'b0 ; */ +/*description: .*/ +#define RTC_CNTL_RETENTION_TARGET 0x00000003 +#define RTC_CNTL_RETENTION_TARGET_M ((RTC_CNTL_RETENTION_TARGET_V)<<(RTC_CNTL_RETENTION_TARGET_S)) +#define RTC_CNTL_RETENTION_TARGET_V 0x3 +#define RTC_CNTL_RETENTION_TARGET_S 14 +/* RTC_CNTL_RETENTION_TAG_MODE : R/W ;bitpos:[13:10] ;default: 4'd0 ; */ +/*description: .*/ +#define RTC_CNTL_RETENTION_TAG_MODE 0x0000000F +#define RTC_CNTL_RETENTION_TAG_MODE_M ((RTC_CNTL_RETENTION_TAG_MODE_V)<<(RTC_CNTL_RETENTION_TAG_MODE_S)) +#define RTC_CNTL_RETENTION_TAG_MODE_V 0xF +#define RTC_CNTL_RETENTION_TAG_MODE_S 10 + +#define RTC_CNTL_PG_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x144) +/* RTC_CNTL_POWER_GLITCH_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_POWER_GLITCH_EN (BIT(31)) +#define RTC_CNTL_POWER_GLITCH_EN_M (BIT(31)) +#define RTC_CNTL_POWER_GLITCH_EN_V 0x1 +#define RTC_CNTL_POWER_GLITCH_EN_S 31 +/* RTC_CNTL_POWER_GLITCH_EFUSE_SEL : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: select use analog fib signal.*/ +#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL (BIT(30)) +#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL_M (BIT(30)) +#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL_V 0x1 +#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL_S 30 +/* RTC_CNTL_POWER_GLITCH_FORCE_PU : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_POWER_GLITCH_FORCE_PU (BIT(29)) +#define RTC_CNTL_POWER_GLITCH_FORCE_PU_M (BIT(29)) +#define RTC_CNTL_POWER_GLITCH_FORCE_PU_V 0x1 +#define RTC_CNTL_POWER_GLITCH_FORCE_PU_S 29 +/* RTC_CNTL_POWER_GLITCH_FORCE_PD : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_POWER_GLITCH_FORCE_PD (BIT(28)) +#define RTC_CNTL_POWER_GLITCH_FORCE_PD_M (BIT(28)) +#define RTC_CNTL_POWER_GLITCH_FORCE_PD_V 0x1 +#define RTC_CNTL_POWER_GLITCH_FORCE_PD_S 28 +/* RTC_CNTL_POWER_GLITCH_DSENSE : R/W ;bitpos:[27:26] ;default: 2'b0 ; */ +/*description: .*/ +#define RTC_CNTL_POWER_GLITCH_DSENSE 0x00000003 +#define RTC_CNTL_POWER_GLITCH_DSENSE_M ((RTC_CNTL_POWER_GLITCH_DSENSE_V)<<(RTC_CNTL_POWER_GLITCH_DSENSE_S)) +#define RTC_CNTL_POWER_GLITCH_DSENSE_V 0x3 +#define RTC_CNTL_POWER_GLITCH_DSENSE_S 26 + +#define RTC_CNTL_FIB_SEL_REG (DR_REG_RTCCNTL_BASE + 0x148) +/* RTC_CNTL_FIB_SEL : R/W ;bitpos:[2:0] ;default: 3'd7 ; */ +/*description: .*/ +#define RTC_CNTL_FIB_SEL 0x00000007 +#define RTC_CNTL_FIB_SEL_M ((RTC_CNTL_FIB_SEL_V)<<(RTC_CNTL_FIB_SEL_S)) +#define RTC_CNTL_FIB_SEL_V 0x7 +#define RTC_CNTL_FIB_SEL_S 0 + +#define RTC_CNTL_FIB_GLITCH_RST BIT(0) +#define RTC_CNTL_FIB_BOD_RST BIT(1) +#define RTC_CNTL_FIB_SUPER_WDT_RST BIT(2) + +#define RTC_CNTL_TOUCH_DAC_REG (DR_REG_RTCCNTL_BASE + 0x14C) +/* RTC_CNTL_TOUCH_PAD0_DAC : R/W ;bitpos:[31:29] ;default: 3'd0 ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD0_DAC 0x00000007 +#define RTC_CNTL_TOUCH_PAD0_DAC_M ((RTC_CNTL_TOUCH_PAD0_DAC_V)<<(RTC_CNTL_TOUCH_PAD0_DAC_S)) +#define RTC_CNTL_TOUCH_PAD0_DAC_V 0x7 +#define RTC_CNTL_TOUCH_PAD0_DAC_S 29 +/* RTC_CNTL_TOUCH_PAD1_DAC : R/W ;bitpos:[28:26] ;default: 3'd0 ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD1_DAC 0x00000007 +#define RTC_CNTL_TOUCH_PAD1_DAC_M ((RTC_CNTL_TOUCH_PAD1_DAC_V)<<(RTC_CNTL_TOUCH_PAD1_DAC_S)) +#define RTC_CNTL_TOUCH_PAD1_DAC_V 0x7 +#define RTC_CNTL_TOUCH_PAD1_DAC_S 26 +/* RTC_CNTL_TOUCH_PAD2_DAC : R/W ;bitpos:[25:23] ;default: 3'd0 ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD2_DAC 0x00000007 +#define RTC_CNTL_TOUCH_PAD2_DAC_M ((RTC_CNTL_TOUCH_PAD2_DAC_V)<<(RTC_CNTL_TOUCH_PAD2_DAC_S)) +#define RTC_CNTL_TOUCH_PAD2_DAC_V 0x7 +#define RTC_CNTL_TOUCH_PAD2_DAC_S 23 +/* RTC_CNTL_TOUCH_PAD3_DAC : R/W ;bitpos:[22:20] ;default: 3'd0 ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD3_DAC 0x00000007 +#define RTC_CNTL_TOUCH_PAD3_DAC_M ((RTC_CNTL_TOUCH_PAD3_DAC_V)<<(RTC_CNTL_TOUCH_PAD3_DAC_S)) +#define RTC_CNTL_TOUCH_PAD3_DAC_V 0x7 +#define RTC_CNTL_TOUCH_PAD3_DAC_S 20 +/* RTC_CNTL_TOUCH_PAD4_DAC : R/W ;bitpos:[19:17] ;default: 3'd0 ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD4_DAC 0x00000007 +#define RTC_CNTL_TOUCH_PAD4_DAC_M ((RTC_CNTL_TOUCH_PAD4_DAC_V)<<(RTC_CNTL_TOUCH_PAD4_DAC_S)) +#define RTC_CNTL_TOUCH_PAD4_DAC_V 0x7 +#define RTC_CNTL_TOUCH_PAD4_DAC_S 17 +/* RTC_CNTL_TOUCH_PAD5_DAC : R/W ;bitpos:[16:14] ;default: 3'd0 ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD5_DAC 0x00000007 +#define RTC_CNTL_TOUCH_PAD5_DAC_M ((RTC_CNTL_TOUCH_PAD5_DAC_V)<<(RTC_CNTL_TOUCH_PAD5_DAC_S)) +#define RTC_CNTL_TOUCH_PAD5_DAC_V 0x7 +#define RTC_CNTL_TOUCH_PAD5_DAC_S 14 +/* RTC_CNTL_TOUCH_PAD6_DAC : R/W ;bitpos:[13:11] ;default: 3'd0 ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD6_DAC 0x00000007 +#define RTC_CNTL_TOUCH_PAD6_DAC_M ((RTC_CNTL_TOUCH_PAD6_DAC_V)<<(RTC_CNTL_TOUCH_PAD6_DAC_S)) +#define RTC_CNTL_TOUCH_PAD6_DAC_V 0x7 +#define RTC_CNTL_TOUCH_PAD6_DAC_S 11 +/* RTC_CNTL_TOUCH_PAD7_DAC : R/W ;bitpos:[10:8] ;default: 3'd0 ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD7_DAC 0x00000007 +#define RTC_CNTL_TOUCH_PAD7_DAC_M ((RTC_CNTL_TOUCH_PAD7_DAC_V)<<(RTC_CNTL_TOUCH_PAD7_DAC_S)) +#define RTC_CNTL_TOUCH_PAD7_DAC_V 0x7 +#define RTC_CNTL_TOUCH_PAD7_DAC_S 8 +/* RTC_CNTL_TOUCH_PAD8_DAC : R/W ;bitpos:[7:5] ;default: 3'd0 ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD8_DAC 0x00000007 +#define RTC_CNTL_TOUCH_PAD8_DAC_M ((RTC_CNTL_TOUCH_PAD8_DAC_V)<<(RTC_CNTL_TOUCH_PAD8_DAC_S)) +#define RTC_CNTL_TOUCH_PAD8_DAC_V 0x7 +#define RTC_CNTL_TOUCH_PAD8_DAC_S 5 +/* RTC_CNTL_TOUCH_PAD9_DAC : R/W ;bitpos:[4:2] ;default: 3'd0 ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD9_DAC 0x00000007 +#define RTC_CNTL_TOUCH_PAD9_DAC_M ((RTC_CNTL_TOUCH_PAD9_DAC_V)<<(RTC_CNTL_TOUCH_PAD9_DAC_S)) +#define RTC_CNTL_TOUCH_PAD9_DAC_V 0x7 +#define RTC_CNTL_TOUCH_PAD9_DAC_S 2 + +#define RTC_CNTL_TOUCH_DAC1_REG (DR_REG_RTCCNTL_BASE + 0x150) +/* RTC_CNTL_TOUCH_PAD10_DAC : R/W ;bitpos:[31:29] ;default: 3'd0 ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD10_DAC 0x00000007 +#define RTC_CNTL_TOUCH_PAD10_DAC_M ((RTC_CNTL_TOUCH_PAD10_DAC_V)<<(RTC_CNTL_TOUCH_PAD10_DAC_S)) +#define RTC_CNTL_TOUCH_PAD10_DAC_V 0x7 +#define RTC_CNTL_TOUCH_PAD10_DAC_S 29 +/* RTC_CNTL_TOUCH_PAD11_DAC : R/W ;bitpos:[28:26] ;default: 3'd0 ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD11_DAC 0x00000007 +#define RTC_CNTL_TOUCH_PAD11_DAC_M ((RTC_CNTL_TOUCH_PAD11_DAC_V)<<(RTC_CNTL_TOUCH_PAD11_DAC_S)) +#define RTC_CNTL_TOUCH_PAD11_DAC_V 0x7 +#define RTC_CNTL_TOUCH_PAD11_DAC_S 26 +/* RTC_CNTL_TOUCH_PAD12_DAC : R/W ;bitpos:[25:23] ;default: 3'd0 ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD12_DAC 0x00000007 +#define RTC_CNTL_TOUCH_PAD12_DAC_M ((RTC_CNTL_TOUCH_PAD12_DAC_V)<<(RTC_CNTL_TOUCH_PAD12_DAC_S)) +#define RTC_CNTL_TOUCH_PAD12_DAC_V 0x7 +#define RTC_CNTL_TOUCH_PAD12_DAC_S 23 +/* RTC_CNTL_TOUCH_PAD13_DAC : R/W ;bitpos:[22:20] ;default: 3'd0 ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD13_DAC 0x00000007 +#define RTC_CNTL_TOUCH_PAD13_DAC_M ((RTC_CNTL_TOUCH_PAD13_DAC_V)<<(RTC_CNTL_TOUCH_PAD13_DAC_S)) +#define RTC_CNTL_TOUCH_PAD13_DAC_V 0x7 +#define RTC_CNTL_TOUCH_PAD13_DAC_S 20 +/* RTC_CNTL_TOUCH_PAD14_DAC : R/W ;bitpos:[19:17] ;default: 3'd0 ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD14_DAC 0x00000007 +#define RTC_CNTL_TOUCH_PAD14_DAC_M ((RTC_CNTL_TOUCH_PAD14_DAC_V)<<(RTC_CNTL_TOUCH_PAD14_DAC_S)) +#define RTC_CNTL_TOUCH_PAD14_DAC_V 0x7 +#define RTC_CNTL_TOUCH_PAD14_DAC_S 17 + +#define RTC_CNTL_COCPU_DISABLE_REG (DR_REG_RTCCNTL_BASE + 0x154) +/* RTC_CNTL_DISABLE_RTC_CPU : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_DISABLE_RTC_CPU (BIT(31)) +#define RTC_CNTL_DISABLE_RTC_CPU_M (BIT(31)) +#define RTC_CNTL_DISABLE_RTC_CPU_V 0x1 +#define RTC_CNTL_DISABLE_RTC_CPU_S 31 + +/* +Due to the LDO slaves, RTC_CNTL_DATE_REG[18:13] can only be used for LDO adjustment. +*/ +#define RTC_CNTL_DATE_REG (DR_REG_RTCCNTL_BASE + 0x1FC) +/* RTC_CNTL_DATE : R/W ;bitpos:[27:0] ;default: 28'h2101271 ; */ +/*description: .*/ +#define RTC_CNTL_DATE 0x0FFFFFFF +#define RTC_CNTL_DATE_M ((RTC_CNTL_DATE_V)<<(RTC_CNTL_DATE_S)) +#define RTC_CNTL_DATE_V 0xFFFFFFF +#define RTC_CNTL_DATE_S 0 +/*LDO SLAVE : R/W ;bitpos:[18:13] ; default: 6'd0 ;*/ +/*description: .*/ +#define RTC_CNTL_SLAVE_PD 0x0000003F +#define RTC_CNTL_SLAVE_PD_M ((RTC_CNTL_SLAVE_PD_V)<<(RTC_CNTL_SLAVE_PD_S)) +#define RTC_CNTL_SLAVE_PD_V 0x3F +#define RTC_CNTL_SLAVE_PD_S 13 + +#ifdef __cplusplus +} +#endif + +#endif /*_SOC_RTC_CNTL_REG_H_ */ diff --git a/src/target/esp32s3/include/soc/system_reg.h b/src/target/esp32s3/include/soc/system_reg.h new file mode 100644 index 0000000..f1581e0 --- /dev/null +++ b/src/target/esp32s3/include/soc/system_reg.h @@ -0,0 +1,1078 @@ +/* + * SPDX-FileCopyrightText: 2017-2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 OR MIT + */ +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#define SYSTEM_CORE_1_CONTROL_0_REG (DR_REG_SYSTEM_BASE + 0x0) +/* SYSTEM_CONTROL_CORE_1_RESETING : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: .*/ +#define SYSTEM_CONTROL_CORE_1_RESETING (BIT(2)) +#define SYSTEM_CONTROL_CORE_1_RESETING_M (BIT(2)) +#define SYSTEM_CONTROL_CORE_1_RESETING_V 0x1 +#define SYSTEM_CONTROL_CORE_1_RESETING_S 2 +/* SYSTEM_CONTROL_CORE_1_CLKGATE_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_CONTROL_CORE_1_CLKGATE_EN (BIT(1)) +#define SYSTEM_CONTROL_CORE_1_CLKGATE_EN_M (BIT(1)) +#define SYSTEM_CONTROL_CORE_1_CLKGATE_EN_V 0x1 +#define SYSTEM_CONTROL_CORE_1_CLKGATE_EN_S 1 +/* SYSTEM_CONTROL_CORE_1_RUNSTALL : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_CONTROL_CORE_1_RUNSTALL (BIT(0)) +#define SYSTEM_CONTROL_CORE_1_RUNSTALL_M (BIT(0)) +#define SYSTEM_CONTROL_CORE_1_RUNSTALL_V 0x1 +#define SYSTEM_CONTROL_CORE_1_RUNSTALL_S 0 + +#define SYSTEM_CORE_1_CONTROL_1_REG (DR_REG_SYSTEM_BASE + 0x4) +/* SYSTEM_CONTROL_CORE_1_MESSAGE : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: .*/ +#define SYSTEM_CONTROL_CORE_1_MESSAGE 0xFFFFFFFF +#define SYSTEM_CONTROL_CORE_1_MESSAGE_M ((SYSTEM_CONTROL_CORE_1_MESSAGE_V)<<(SYSTEM_CONTROL_CORE_1_MESSAGE_S)) +#define SYSTEM_CONTROL_CORE_1_MESSAGE_V 0xFFFFFFFF +#define SYSTEM_CONTROL_CORE_1_MESSAGE_S 0 + +#define SYSTEM_CPU_PERI_CLK_EN_REG (DR_REG_SYSTEM_BASE + 0x8) +/* SYSTEM_CLK_EN_DEDICATED_GPIO : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_CLK_EN_DEDICATED_GPIO (BIT(7)) +#define SYSTEM_CLK_EN_DEDICATED_GPIO_M (BIT(7)) +#define SYSTEM_CLK_EN_DEDICATED_GPIO_V 0x1 +#define SYSTEM_CLK_EN_DEDICATED_GPIO_S 7 +/* SYSTEM_CLK_EN_ASSIST_DEBUG : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_CLK_EN_ASSIST_DEBUG (BIT(6)) +#define SYSTEM_CLK_EN_ASSIST_DEBUG_M (BIT(6)) +#define SYSTEM_CLK_EN_ASSIST_DEBUG_V 0x1 +#define SYSTEM_CLK_EN_ASSIST_DEBUG_S 6 + +#define SYSTEM_CPU_PERI_RST_EN_REG (DR_REG_SYSTEM_BASE + 0xC) +/* SYSTEM_RST_EN_DEDICATED_GPIO : R/W ;bitpos:[7] ;default: 1'b1 ; */ +/*description: .*/ +#define SYSTEM_RST_EN_DEDICATED_GPIO (BIT(7)) +#define SYSTEM_RST_EN_DEDICATED_GPIO_M (BIT(7)) +#define SYSTEM_RST_EN_DEDICATED_GPIO_V 0x1 +#define SYSTEM_RST_EN_DEDICATED_GPIO_S 7 +/* SYSTEM_RST_EN_ASSIST_DEBUG : R/W ;bitpos:[6] ;default: 1'b1 ; */ +/*description: .*/ +#define SYSTEM_RST_EN_ASSIST_DEBUG (BIT(6)) +#define SYSTEM_RST_EN_ASSIST_DEBUG_M (BIT(6)) +#define SYSTEM_RST_EN_ASSIST_DEBUG_V 0x1 +#define SYSTEM_RST_EN_ASSIST_DEBUG_S 6 + +#define SYSTEM_CPU_PER_CONF_REG (DR_REG_SYSTEM_BASE + 0x10) +/* SYSTEM_CPU_WAITI_DELAY_NUM : R/W ;bitpos:[7:4] ;default: 4'h0 ; */ +/*description: .*/ +#define SYSTEM_CPU_WAITI_DELAY_NUM 0x0000000F +#define SYSTEM_CPU_WAITI_DELAY_NUM_M ((SYSTEM_CPU_WAITI_DELAY_NUM_V)<<(SYSTEM_CPU_WAITI_DELAY_NUM_S)) +#define SYSTEM_CPU_WAITI_DELAY_NUM_V 0xF +#define SYSTEM_CPU_WAITI_DELAY_NUM_S 4 +/* SYSTEM_CPU_WAIT_MODE_FORCE_ON : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: .*/ +#define SYSTEM_CPU_WAIT_MODE_FORCE_ON (BIT(3)) +#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_M (BIT(3)) +#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_V 0x1 +#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_S 3 +/* SYSTEM_PLL_FREQ_SEL : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: .*/ +#define SYSTEM_PLL_FREQ_SEL (BIT(2)) +#define SYSTEM_PLL_FREQ_SEL_M (BIT(2)) +#define SYSTEM_PLL_FREQ_SEL_V 0x1 +#define SYSTEM_PLL_FREQ_SEL_S 2 +/* SYSTEM_CPUPERIOD_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: .*/ +#define SYSTEM_CPUPERIOD_SEL 0x00000003 +#define SYSTEM_CPUPERIOD_SEL_M ((SYSTEM_CPUPERIOD_SEL_V)<<(SYSTEM_CPUPERIOD_SEL_S)) +#define SYSTEM_CPUPERIOD_SEL_V 0x3 +#define SYSTEM_CPUPERIOD_SEL_S 0 + +#define SYSTEM_MEM_PD_MASK_REG (DR_REG_SYSTEM_BASE + 0x14) +/* SYSTEM_LSLP_MEM_PD_MASK : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: .*/ +#define SYSTEM_LSLP_MEM_PD_MASK (BIT(0)) +#define SYSTEM_LSLP_MEM_PD_MASK_M (BIT(0)) +#define SYSTEM_LSLP_MEM_PD_MASK_V 0x1 +#define SYSTEM_LSLP_MEM_PD_MASK_S 0 + +#define SYSTEM_PERIP_CLK_EN0_REG (DR_REG_SYSTEM_BASE + 0x18) +/* SYSTEM_SPI4_CLK_EN : R/W ;bitpos:[31] ;default: 1'h1 ; */ +/*description: .*/ +#define SYSTEM_SPI4_CLK_EN (BIT(31)) +#define SYSTEM_SPI4_CLK_EN_M (BIT(31)) +#define SYSTEM_SPI4_CLK_EN_V 0x1 +#define SYSTEM_SPI4_CLK_EN_S 31 +/* SYSTEM_ADC2_ARB_CLK_EN : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: .*/ +#define SYSTEM_ADC2_ARB_CLK_EN (BIT(30)) +#define SYSTEM_ADC2_ARB_CLK_EN_M (BIT(30)) +#define SYSTEM_ADC2_ARB_CLK_EN_V 0x1 +#define SYSTEM_ADC2_ARB_CLK_EN_S 30 +/* SYSTEM_SYSTIMER_CLK_EN : R/W ;bitpos:[29] ;default: 1'b1 ; */ +/*description: .*/ +#define SYSTEM_SYSTIMER_CLK_EN (BIT(29)) +#define SYSTEM_SYSTIMER_CLK_EN_M (BIT(29)) +#define SYSTEM_SYSTIMER_CLK_EN_V 0x1 +#define SYSTEM_SYSTIMER_CLK_EN_S 29 +/* SYSTEM_APB_SARADC_CLK_EN : R/W ;bitpos:[28] ;default: 1'b1 ; */ +/*description: .*/ +#define SYSTEM_APB_SARADC_CLK_EN (BIT(28)) +#define SYSTEM_APB_SARADC_CLK_EN_M (BIT(28)) +#define SYSTEM_APB_SARADC_CLK_EN_V 0x1 +#define SYSTEM_APB_SARADC_CLK_EN_S 28 +/* SYSTEM_SPI3_DMA_CLK_EN : R/W ;bitpos:[27] ;default: 1'b1 ; */ +/*description: .*/ +#define SYSTEM_SPI3_DMA_CLK_EN (BIT(27)) +#define SYSTEM_SPI3_DMA_CLK_EN_M (BIT(27)) +#define SYSTEM_SPI3_DMA_CLK_EN_V 0x1 +#define SYSTEM_SPI3_DMA_CLK_EN_S 27 +/* SYSTEM_PWM3_CLK_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_PWM3_CLK_EN (BIT(26)) +#define SYSTEM_PWM3_CLK_EN_M (BIT(26)) +#define SYSTEM_PWM3_CLK_EN_V 0x1 +#define SYSTEM_PWM3_CLK_EN_S 26 +/* SYSTEM_PWM2_CLK_EN : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_PWM2_CLK_EN (BIT(25)) +#define SYSTEM_PWM2_CLK_EN_M (BIT(25)) +#define SYSTEM_PWM2_CLK_EN_V 0x1 +#define SYSTEM_PWM2_CLK_EN_S 25 +/* SYSTEM_UART_MEM_CLK_EN : R/W ;bitpos:[24] ;default: 1'b1 ; */ +/*description: .*/ +#define SYSTEM_UART_MEM_CLK_EN (BIT(24)) +#define SYSTEM_UART_MEM_CLK_EN_M (BIT(24)) +#define SYSTEM_UART_MEM_CLK_EN_V 0x1 +#define SYSTEM_UART_MEM_CLK_EN_S 24 +/* SYSTEM_USB_CLK_EN : R/W ;bitpos:[23] ;default: 1'b1 ; */ +/*description: .*/ +#define SYSTEM_USB_CLK_EN (BIT(23)) +#define SYSTEM_USB_CLK_EN_M (BIT(23)) +#define SYSTEM_USB_CLK_EN_V 0x1 +#define SYSTEM_USB_CLK_EN_S 23 +/* SYSTEM_SPI2_DMA_CLK_EN : R/W ;bitpos:[22] ;default: 1'b1 ; */ +/*description: .*/ +#define SYSTEM_SPI2_DMA_CLK_EN (BIT(22)) +#define SYSTEM_SPI2_DMA_CLK_EN_M (BIT(22)) +#define SYSTEM_SPI2_DMA_CLK_EN_V 0x1 +#define SYSTEM_SPI2_DMA_CLK_EN_S 22 +/* SYSTEM_I2S1_CLK_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_I2S1_CLK_EN (BIT(21)) +#define SYSTEM_I2S1_CLK_EN_M (BIT(21)) +#define SYSTEM_I2S1_CLK_EN_V 0x1 +#define SYSTEM_I2S1_CLK_EN_S 21 +/* SYSTEM_PWM1_CLK_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_PWM1_CLK_EN (BIT(20)) +#define SYSTEM_PWM1_CLK_EN_M (BIT(20)) +#define SYSTEM_PWM1_CLK_EN_V 0x1 +#define SYSTEM_PWM1_CLK_EN_S 20 +/* SYSTEM_TWAI_CLK_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_TWAI_CLK_EN (BIT(19)) +#define SYSTEM_TWAI_CLK_EN_M (BIT(19)) +#define SYSTEM_TWAI_CLK_EN_V 0x1 +#define SYSTEM_TWAI_CLK_EN_S 19 +/* SYSTEM_I2C_EXT1_CLK_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_I2C_EXT1_CLK_EN (BIT(18)) +#define SYSTEM_I2C_EXT1_CLK_EN_M (BIT(18)) +#define SYSTEM_I2C_EXT1_CLK_EN_V 0x1 +#define SYSTEM_I2C_EXT1_CLK_EN_S 18 +/* SYSTEM_PWM0_CLK_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_PWM0_CLK_EN (BIT(17)) +#define SYSTEM_PWM0_CLK_EN_M (BIT(17)) +#define SYSTEM_PWM0_CLK_EN_V 0x1 +#define SYSTEM_PWM0_CLK_EN_S 17 +/* SYSTEM_SPI3_CLK_EN : R/W ;bitpos:[16] ;default: 1'b1 ; */ +/*description: .*/ +#define SYSTEM_SPI3_CLK_EN (BIT(16)) +#define SYSTEM_SPI3_CLK_EN_M (BIT(16)) +#define SYSTEM_SPI3_CLK_EN_V 0x1 +#define SYSTEM_SPI3_CLK_EN_S 16 +/* SYSTEM_TIMERGROUP1_CLK_EN : R/W ;bitpos:[15] ;default: 1'b1 ; */ +/*description: .*/ +#define SYSTEM_TIMERGROUP1_CLK_EN (BIT(15)) +#define SYSTEM_TIMERGROUP1_CLK_EN_M (BIT(15)) +#define SYSTEM_TIMERGROUP1_CLK_EN_V 0x1 +#define SYSTEM_TIMERGROUP1_CLK_EN_S 15 +/* SYSTEM_EFUSE_CLK_EN : R/W ;bitpos:[14] ;default: 1'b1 ; */ +/*description: .*/ +#define SYSTEM_EFUSE_CLK_EN (BIT(14)) +#define SYSTEM_EFUSE_CLK_EN_M (BIT(14)) +#define SYSTEM_EFUSE_CLK_EN_V 0x1 +#define SYSTEM_EFUSE_CLK_EN_S 14 +/* SYSTEM_TIMERGROUP_CLK_EN : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: .*/ +#define SYSTEM_TIMERGROUP_CLK_EN (BIT(13)) +#define SYSTEM_TIMERGROUP_CLK_EN_M (BIT(13)) +#define SYSTEM_TIMERGROUP_CLK_EN_V 0x1 +#define SYSTEM_TIMERGROUP_CLK_EN_S 13 +/* SYSTEM_UHCI1_CLK_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_UHCI1_CLK_EN (BIT(12)) +#define SYSTEM_UHCI1_CLK_EN_M (BIT(12)) +#define SYSTEM_UHCI1_CLK_EN_V 0x1 +#define SYSTEM_UHCI1_CLK_EN_S 12 +/* SYSTEM_LEDC_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_LEDC_CLK_EN (BIT(11)) +#define SYSTEM_LEDC_CLK_EN_M (BIT(11)) +#define SYSTEM_LEDC_CLK_EN_V 0x1 +#define SYSTEM_LEDC_CLK_EN_S 11 +/* SYSTEM_PCNT_CLK_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_PCNT_CLK_EN (BIT(10)) +#define SYSTEM_PCNT_CLK_EN_M (BIT(10)) +#define SYSTEM_PCNT_CLK_EN_V 0x1 +#define SYSTEM_PCNT_CLK_EN_S 10 +/* SYSTEM_RMT_CLK_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_RMT_CLK_EN (BIT(9)) +#define SYSTEM_RMT_CLK_EN_M (BIT(9)) +#define SYSTEM_RMT_CLK_EN_V 0x1 +#define SYSTEM_RMT_CLK_EN_S 9 +/* SYSTEM_UHCI0_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_UHCI0_CLK_EN (BIT(8)) +#define SYSTEM_UHCI0_CLK_EN_M (BIT(8)) +#define SYSTEM_UHCI0_CLK_EN_V 0x1 +#define SYSTEM_UHCI0_CLK_EN_S 8 +/* SYSTEM_I2C_EXT0_CLK_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_I2C_EXT0_CLK_EN (BIT(7)) +#define SYSTEM_I2C_EXT0_CLK_EN_M (BIT(7)) +#define SYSTEM_I2C_EXT0_CLK_EN_V 0x1 +#define SYSTEM_I2C_EXT0_CLK_EN_S 7 +/* SYSTEM_SPI2_CLK_EN : R/W ;bitpos:[6] ;default: 1'b1 ; */ +/*description: .*/ +#define SYSTEM_SPI2_CLK_EN (BIT(6)) +#define SYSTEM_SPI2_CLK_EN_M (BIT(6)) +#define SYSTEM_SPI2_CLK_EN_V 0x1 +#define SYSTEM_SPI2_CLK_EN_S 6 +/* SYSTEM_UART1_CLK_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: .*/ +#define SYSTEM_UART1_CLK_EN (BIT(5)) +#define SYSTEM_UART1_CLK_EN_M (BIT(5)) +#define SYSTEM_UART1_CLK_EN_V 0x1 +#define SYSTEM_UART1_CLK_EN_S 5 +/* SYSTEM_I2S0_CLK_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_I2S0_CLK_EN (BIT(4)) +#define SYSTEM_I2S0_CLK_EN_M (BIT(4)) +#define SYSTEM_I2S0_CLK_EN_V 0x1 +#define SYSTEM_I2S0_CLK_EN_S 4 +/* SYSTEM_WDG_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: .*/ +#define SYSTEM_WDG_CLK_EN (BIT(3)) +#define SYSTEM_WDG_CLK_EN_M (BIT(3)) +#define SYSTEM_WDG_CLK_EN_V 0x1 +#define SYSTEM_WDG_CLK_EN_S 3 +/* SYSTEM_UART_CLK_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: .*/ +#define SYSTEM_UART_CLK_EN (BIT(2)) +#define SYSTEM_UART_CLK_EN_M (BIT(2)) +#define SYSTEM_UART_CLK_EN_V 0x1 +#define SYSTEM_UART_CLK_EN_S 2 +/* SYSTEM_SPI01_CLK_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: .*/ +#define SYSTEM_SPI01_CLK_EN (BIT(1)) +#define SYSTEM_SPI01_CLK_EN_M (BIT(1)) +#define SYSTEM_SPI01_CLK_EN_V 0x1 +#define SYSTEM_SPI01_CLK_EN_S 1 +/* SYSTEM_TIMERS_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: .*/ +#define SYSTEM_TIMERS_CLK_EN (BIT(0)) +#define SYSTEM_TIMERS_CLK_EN_M (BIT(0)) +#define SYSTEM_TIMERS_CLK_EN_V 0x1 +#define SYSTEM_TIMERS_CLK_EN_S 0 + +#define SYSTEM_PERIP_CLK_EN1_REG (DR_REG_SYSTEM_BASE + 0x1C) +/* SYSTEM_USB_DEVICE_CLK_EN : R/W ;bitpos:[10] ;default: 1'b1 ; */ +/*description: .*/ +#define SYSTEM_USB_DEVICE_CLK_EN (BIT(10)) +#define SYSTEM_USB_DEVICE_CLK_EN_M (BIT(10)) +#define SYSTEM_USB_DEVICE_CLK_EN_V 0x1 +#define SYSTEM_USB_DEVICE_CLK_EN_S 10 +/* SYSTEM_UART2_CLK_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */ +/*description: .*/ +#define SYSTEM_UART2_CLK_EN (BIT(9)) +#define SYSTEM_UART2_CLK_EN_M (BIT(9)) +#define SYSTEM_UART2_CLK_EN_V 0x1 +#define SYSTEM_UART2_CLK_EN_S 9 +/* SYSTEM_LCD_CAM_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_LCD_CAM_CLK_EN (BIT(8)) +#define SYSTEM_LCD_CAM_CLK_EN_M (BIT(8)) +#define SYSTEM_LCD_CAM_CLK_EN_V 0x1 +#define SYSTEM_LCD_CAM_CLK_EN_S 8 +/* SYSTEM_SDIO_HOST_CLK_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_SDIO_HOST_CLK_EN (BIT(7)) +#define SYSTEM_SDIO_HOST_CLK_EN_M (BIT(7)) +#define SYSTEM_SDIO_HOST_CLK_EN_V 0x1 +#define SYSTEM_SDIO_HOST_CLK_EN_S 7 +/* SYSTEM_DMA_CLK_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_DMA_CLK_EN (BIT(6)) +#define SYSTEM_DMA_CLK_EN_M (BIT(6)) +#define SYSTEM_DMA_CLK_EN_V 0x1 +#define SYSTEM_DMA_CLK_EN_S 6 +/* SYSTEM_CRYPTO_HMAC_CLK_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_CRYPTO_HMAC_CLK_EN (BIT(5)) +#define SYSTEM_CRYPTO_HMAC_CLK_EN_M (BIT(5)) +#define SYSTEM_CRYPTO_HMAC_CLK_EN_V 0x1 +#define SYSTEM_CRYPTO_HMAC_CLK_EN_S 5 +/* SYSTEM_CRYPTO_DS_CLK_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_CRYPTO_DS_CLK_EN (BIT(4)) +#define SYSTEM_CRYPTO_DS_CLK_EN_M (BIT(4)) +#define SYSTEM_CRYPTO_DS_CLK_EN_V 0x1 +#define SYSTEM_CRYPTO_DS_CLK_EN_S 4 +/* SYSTEM_CRYPTO_RSA_CLK_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_CRYPTO_RSA_CLK_EN (BIT(3)) +#define SYSTEM_CRYPTO_RSA_CLK_EN_M (BIT(3)) +#define SYSTEM_CRYPTO_RSA_CLK_EN_V 0x1 +#define SYSTEM_CRYPTO_RSA_CLK_EN_S 3 +/* SYSTEM_CRYPTO_SHA_CLK_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_CRYPTO_SHA_CLK_EN (BIT(2)) +#define SYSTEM_CRYPTO_SHA_CLK_EN_M (BIT(2)) +#define SYSTEM_CRYPTO_SHA_CLK_EN_V 0x1 +#define SYSTEM_CRYPTO_SHA_CLK_EN_S 2 +/* SYSTEM_CRYPTO_AES_CLK_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_CRYPTO_AES_CLK_EN (BIT(1)) +#define SYSTEM_CRYPTO_AES_CLK_EN_M (BIT(1)) +#define SYSTEM_CRYPTO_AES_CLK_EN_V 0x1 +#define SYSTEM_CRYPTO_AES_CLK_EN_S 1 +/* SYSTEM_PERI_BACKUP_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_PERI_BACKUP_CLK_EN (BIT(0)) +#define SYSTEM_PERI_BACKUP_CLK_EN_M (BIT(0)) +#define SYSTEM_PERI_BACKUP_CLK_EN_V 0x1 +#define SYSTEM_PERI_BACKUP_CLK_EN_S 0 + +#define SYSTEM_PERIP_RST_EN0_REG (DR_REG_SYSTEM_BASE + 0x20) +/* SYSTEM_SPI4_RST : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: .*/ +#define SYSTEM_SPI4_RST (BIT(31)) +#define SYSTEM_SPI4_RST_M (BIT(31)) +#define SYSTEM_SPI4_RST_V 0x1 +#define SYSTEM_SPI4_RST_S 31 +/* SYSTEM_ADC2_ARB_RST : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_ADC2_ARB_RST (BIT(30)) +#define SYSTEM_ADC2_ARB_RST_M (BIT(30)) +#define SYSTEM_ADC2_ARB_RST_V 0x1 +#define SYSTEM_ADC2_ARB_RST_S 30 +/* SYSTEM_SYSTIMER_RST : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_SYSTIMER_RST (BIT(29)) +#define SYSTEM_SYSTIMER_RST_M (BIT(29)) +#define SYSTEM_SYSTIMER_RST_V 0x1 +#define SYSTEM_SYSTIMER_RST_S 29 +/* SYSTEM_APB_SARADC_RST : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_APB_SARADC_RST (BIT(28)) +#define SYSTEM_APB_SARADC_RST_M (BIT(28)) +#define SYSTEM_APB_SARADC_RST_V 0x1 +#define SYSTEM_APB_SARADC_RST_S 28 +/* SYSTEM_SPI3_DMA_RST : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_SPI3_DMA_RST (BIT(27)) +#define SYSTEM_SPI3_DMA_RST_M (BIT(27)) +#define SYSTEM_SPI3_DMA_RST_V 0x1 +#define SYSTEM_SPI3_DMA_RST_S 27 +/* SYSTEM_PWM3_RST : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_PWM3_RST (BIT(26)) +#define SYSTEM_PWM3_RST_M (BIT(26)) +#define SYSTEM_PWM3_RST_V 0x1 +#define SYSTEM_PWM3_RST_S 26 +/* SYSTEM_PWM2_RST : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_PWM2_RST (BIT(25)) +#define SYSTEM_PWM2_RST_M (BIT(25)) +#define SYSTEM_PWM2_RST_V 0x1 +#define SYSTEM_PWM2_RST_S 25 +/* SYSTEM_UART_MEM_RST : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_UART_MEM_RST (BIT(24)) +#define SYSTEM_UART_MEM_RST_M (BIT(24)) +#define SYSTEM_UART_MEM_RST_V 0x1 +#define SYSTEM_UART_MEM_RST_S 24 +/* SYSTEM_USB_RST : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_USB_RST (BIT(23)) +#define SYSTEM_USB_RST_M (BIT(23)) +#define SYSTEM_USB_RST_V 0x1 +#define SYSTEM_USB_RST_S 23 +/* SYSTEM_SPI2_DMA_RST : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_SPI2_DMA_RST (BIT(22)) +#define SYSTEM_SPI2_DMA_RST_M (BIT(22)) +#define SYSTEM_SPI2_DMA_RST_V 0x1 +#define SYSTEM_SPI2_DMA_RST_S 22 +/* SYSTEM_I2S1_RST : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_I2S1_RST (BIT(21)) +#define SYSTEM_I2S1_RST_M (BIT(21)) +#define SYSTEM_I2S1_RST_V 0x1 +#define SYSTEM_I2S1_RST_S 21 +/* SYSTEM_PWM1_RST : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_PWM1_RST (BIT(20)) +#define SYSTEM_PWM1_RST_M (BIT(20)) +#define SYSTEM_PWM1_RST_V 0x1 +#define SYSTEM_PWM1_RST_S 20 +/* SYSTEM_TWAI_RST : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_TWAI_RST (BIT(19)) +#define SYSTEM_TWAI_RST_M (BIT(19)) +#define SYSTEM_TWAI_RST_V 0x1 +#define SYSTEM_TWAI_RST_S 19 +/* SYSTEM_I2C_EXT1_RST : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_I2C_EXT1_RST (BIT(18)) +#define SYSTEM_I2C_EXT1_RST_M (BIT(18)) +#define SYSTEM_I2C_EXT1_RST_V 0x1 +#define SYSTEM_I2C_EXT1_RST_S 18 +/* SYSTEM_PWM0_RST : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_PWM0_RST (BIT(17)) +#define SYSTEM_PWM0_RST_M (BIT(17)) +#define SYSTEM_PWM0_RST_V 0x1 +#define SYSTEM_PWM0_RST_S 17 +/* SYSTEM_SPI3_RST : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_SPI3_RST (BIT(16)) +#define SYSTEM_SPI3_RST_M (BIT(16)) +#define SYSTEM_SPI3_RST_V 0x1 +#define SYSTEM_SPI3_RST_S 16 +/* SYSTEM_TIMERGROUP1_RST : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_TIMERGROUP1_RST (BIT(15)) +#define SYSTEM_TIMERGROUP1_RST_M (BIT(15)) +#define SYSTEM_TIMERGROUP1_RST_V 0x1 +#define SYSTEM_TIMERGROUP1_RST_S 15 +/* SYSTEM_EFUSE_RST : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_EFUSE_RST (BIT(14)) +#define SYSTEM_EFUSE_RST_M (BIT(14)) +#define SYSTEM_EFUSE_RST_V 0x1 +#define SYSTEM_EFUSE_RST_S 14 +/* SYSTEM_TIMERGROUP_RST : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_TIMERGROUP_RST (BIT(13)) +#define SYSTEM_TIMERGROUP_RST_M (BIT(13)) +#define SYSTEM_TIMERGROUP_RST_V 0x1 +#define SYSTEM_TIMERGROUP_RST_S 13 +/* SYSTEM_UHCI1_RST : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_UHCI1_RST (BIT(12)) +#define SYSTEM_UHCI1_RST_M (BIT(12)) +#define SYSTEM_UHCI1_RST_V 0x1 +#define SYSTEM_UHCI1_RST_S 12 +/* SYSTEM_LEDC_RST : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_LEDC_RST (BIT(11)) +#define SYSTEM_LEDC_RST_M (BIT(11)) +#define SYSTEM_LEDC_RST_V 0x1 +#define SYSTEM_LEDC_RST_S 11 +/* SYSTEM_PCNT_RST : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_PCNT_RST (BIT(10)) +#define SYSTEM_PCNT_RST_M (BIT(10)) +#define SYSTEM_PCNT_RST_V 0x1 +#define SYSTEM_PCNT_RST_S 10 +/* SYSTEM_RMT_RST : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_RMT_RST (BIT(9)) +#define SYSTEM_RMT_RST_M (BIT(9)) +#define SYSTEM_RMT_RST_V 0x1 +#define SYSTEM_RMT_RST_S 9 +/* SYSTEM_UHCI0_RST : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_UHCI0_RST (BIT(8)) +#define SYSTEM_UHCI0_RST_M (BIT(8)) +#define SYSTEM_UHCI0_RST_V 0x1 +#define SYSTEM_UHCI0_RST_S 8 +/* SYSTEM_I2C_EXT0_RST : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_I2C_EXT0_RST (BIT(7)) +#define SYSTEM_I2C_EXT0_RST_M (BIT(7)) +#define SYSTEM_I2C_EXT0_RST_V 0x1 +#define SYSTEM_I2C_EXT0_RST_S 7 +/* SYSTEM_SPI2_RST : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_SPI2_RST (BIT(6)) +#define SYSTEM_SPI2_RST_M (BIT(6)) +#define SYSTEM_SPI2_RST_V 0x1 +#define SYSTEM_SPI2_RST_S 6 +/* SYSTEM_UART1_RST : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_UART1_RST (BIT(5)) +#define SYSTEM_UART1_RST_M (BIT(5)) +#define SYSTEM_UART1_RST_V 0x1 +#define SYSTEM_UART1_RST_S 5 +/* SYSTEM_I2S0_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_I2S0_RST (BIT(4)) +#define SYSTEM_I2S0_RST_M (BIT(4)) +#define SYSTEM_I2S0_RST_V 0x1 +#define SYSTEM_I2S0_RST_S 4 +/* SYSTEM_WDG_RST : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_WDG_RST (BIT(3)) +#define SYSTEM_WDG_RST_M (BIT(3)) +#define SYSTEM_WDG_RST_V 0x1 +#define SYSTEM_WDG_RST_S 3 +/* SYSTEM_UART_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_UART_RST (BIT(2)) +#define SYSTEM_UART_RST_M (BIT(2)) +#define SYSTEM_UART_RST_V 0x1 +#define SYSTEM_UART_RST_S 2 +/* SYSTEM_SPI01_RST : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_SPI01_RST (BIT(1)) +#define SYSTEM_SPI01_RST_M (BIT(1)) +#define SYSTEM_SPI01_RST_V 0x1 +#define SYSTEM_SPI01_RST_S 1 +/* SYSTEM_TIMERS_RST : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_TIMERS_RST (BIT(0)) +#define SYSTEM_TIMERS_RST_M (BIT(0)) +#define SYSTEM_TIMERS_RST_V 0x1 +#define SYSTEM_TIMERS_RST_S 0 + +#define SYSTEM_PERIP_RST_EN1_REG (DR_REG_SYSTEM_BASE + 0x24) +/* SYSTEM_USB_DEVICE_RST : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_USB_DEVICE_RST (BIT(10)) +#define SYSTEM_USB_DEVICE_RST_M (BIT(10)) +#define SYSTEM_USB_DEVICE_RST_V 0x1 +#define SYSTEM_USB_DEVICE_RST_S 10 +/* SYSTEM_UART2_RST : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_UART2_RST (BIT(9)) +#define SYSTEM_UART2_RST_M (BIT(9)) +#define SYSTEM_UART2_RST_V 0x1 +#define SYSTEM_UART2_RST_S 9 +/* SYSTEM_LCD_CAM_RST : R/W ;bitpos:[8] ;default: 1'b1 ; */ +/*description: .*/ +#define SYSTEM_LCD_CAM_RST (BIT(8)) +#define SYSTEM_LCD_CAM_RST_M (BIT(8)) +#define SYSTEM_LCD_CAM_RST_V 0x1 +#define SYSTEM_LCD_CAM_RST_S 8 +/* SYSTEM_SDIO_HOST_RST : R/W ;bitpos:[7] ;default: 1'b1 ; */ +/*description: .*/ +#define SYSTEM_SDIO_HOST_RST (BIT(7)) +#define SYSTEM_SDIO_HOST_RST_M (BIT(7)) +#define SYSTEM_SDIO_HOST_RST_V 0x1 +#define SYSTEM_SDIO_HOST_RST_S 7 +/* SYSTEM_DMA_RST : R/W ;bitpos:[6] ;default: 1'b1 ; */ +/*description: .*/ +#define SYSTEM_DMA_RST (BIT(6)) +#define SYSTEM_DMA_RST_M (BIT(6)) +#define SYSTEM_DMA_RST_V 0x1 +#define SYSTEM_DMA_RST_S 6 +/* SYSTEM_CRYPTO_HMAC_RST : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: .*/ +#define SYSTEM_CRYPTO_HMAC_RST (BIT(5)) +#define SYSTEM_CRYPTO_HMAC_RST_M (BIT(5)) +#define SYSTEM_CRYPTO_HMAC_RST_V 0x1 +#define SYSTEM_CRYPTO_HMAC_RST_S 5 +/* SYSTEM_CRYPTO_DS_RST : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: .*/ +#define SYSTEM_CRYPTO_DS_RST (BIT(4)) +#define SYSTEM_CRYPTO_DS_RST_M (BIT(4)) +#define SYSTEM_CRYPTO_DS_RST_V 0x1 +#define SYSTEM_CRYPTO_DS_RST_S 4 +/* SYSTEM_CRYPTO_RSA_RST : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: .*/ +#define SYSTEM_CRYPTO_RSA_RST (BIT(3)) +#define SYSTEM_CRYPTO_RSA_RST_M (BIT(3)) +#define SYSTEM_CRYPTO_RSA_RST_V 0x1 +#define SYSTEM_CRYPTO_RSA_RST_S 3 +/* SYSTEM_CRYPTO_SHA_RST : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: .*/ +#define SYSTEM_CRYPTO_SHA_RST (BIT(2)) +#define SYSTEM_CRYPTO_SHA_RST_M (BIT(2)) +#define SYSTEM_CRYPTO_SHA_RST_V 0x1 +#define SYSTEM_CRYPTO_SHA_RST_S 2 +/* SYSTEM_CRYPTO_AES_RST : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: .*/ +#define SYSTEM_CRYPTO_AES_RST (BIT(1)) +#define SYSTEM_CRYPTO_AES_RST_M (BIT(1)) +#define SYSTEM_CRYPTO_AES_RST_V 0x1 +#define SYSTEM_CRYPTO_AES_RST_S 1 +/* SYSTEM_PERI_BACKUP_RST : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_PERI_BACKUP_RST (BIT(0)) +#define SYSTEM_PERI_BACKUP_RST_M (BIT(0)) +#define SYSTEM_PERI_BACKUP_RST_V 0x1 +#define SYSTEM_PERI_BACKUP_RST_S 0 + +#define SYSTEM_BT_LPCK_DIV_INT_REG (DR_REG_SYSTEM_BASE + 0x28) +/* SYSTEM_BT_LPCK_DIV_NUM : R/W ;bitpos:[11:0] ;default: 12'd255 ; */ +/*description: .*/ +#define SYSTEM_BT_LPCK_DIV_NUM 0x00000FFF +#define SYSTEM_BT_LPCK_DIV_NUM_M ((SYSTEM_BT_LPCK_DIV_NUM_V)<<(SYSTEM_BT_LPCK_DIV_NUM_S)) +#define SYSTEM_BT_LPCK_DIV_NUM_V 0xFFF +#define SYSTEM_BT_LPCK_DIV_NUM_S 0 + +#define SYSTEM_BT_LPCK_DIV_FRAC_REG (DR_REG_SYSTEM_BASE + 0x2C) +/* SYSTEM_LPCLK_RTC_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_LPCLK_RTC_EN (BIT(28)) +#define SYSTEM_LPCLK_RTC_EN_M (BIT(28)) +#define SYSTEM_LPCLK_RTC_EN_V 0x1 +#define SYSTEM_LPCLK_RTC_EN_S 28 +/* SYSTEM_LPCLK_SEL_XTAL32K : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_LPCLK_SEL_XTAL32K (BIT(27)) +#define SYSTEM_LPCLK_SEL_XTAL32K_M (BIT(27)) +#define SYSTEM_LPCLK_SEL_XTAL32K_V 0x1 +#define SYSTEM_LPCLK_SEL_XTAL32K_S 27 +/* SYSTEM_LPCLK_SEL_XTAL : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_LPCLK_SEL_XTAL (BIT(26)) +#define SYSTEM_LPCLK_SEL_XTAL_M (BIT(26)) +#define SYSTEM_LPCLK_SEL_XTAL_V 0x1 +#define SYSTEM_LPCLK_SEL_XTAL_S 26 +/* SYSTEM_LPCLK_SEL_8M : R/W ;bitpos:[25] ;default: 1'b1 ; */ +/*description: .*/ +#define SYSTEM_LPCLK_SEL_8M (BIT(25)) +#define SYSTEM_LPCLK_SEL_8M_M (BIT(25)) +#define SYSTEM_LPCLK_SEL_8M_V 0x1 +#define SYSTEM_LPCLK_SEL_8M_S 25 +/* SYSTEM_LPCLK_SEL_RTC_SLOW : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_LPCLK_SEL_RTC_SLOW (BIT(24)) +#define SYSTEM_LPCLK_SEL_RTC_SLOW_M (BIT(24)) +#define SYSTEM_LPCLK_SEL_RTC_SLOW_V 0x1 +#define SYSTEM_LPCLK_SEL_RTC_SLOW_S 24 +/* SYSTEM_BT_LPCK_DIV_A : R/W ;bitpos:[23:12] ;default: 12'd1 ; */ +/*description: .*/ +#define SYSTEM_BT_LPCK_DIV_A 0x00000FFF +#define SYSTEM_BT_LPCK_DIV_A_M ((SYSTEM_BT_LPCK_DIV_A_V)<<(SYSTEM_BT_LPCK_DIV_A_S)) +#define SYSTEM_BT_LPCK_DIV_A_V 0xFFF +#define SYSTEM_BT_LPCK_DIV_A_S 12 +/* SYSTEM_BT_LPCK_DIV_B : R/W ;bitpos:[11:0] ;default: 12'd1 ; */ +/*description: .*/ +#define SYSTEM_BT_LPCK_DIV_B 0x00000FFF +#define SYSTEM_BT_LPCK_DIV_B_M ((SYSTEM_BT_LPCK_DIV_B_V)<<(SYSTEM_BT_LPCK_DIV_B_S)) +#define SYSTEM_BT_LPCK_DIV_B_V 0xFFF +#define SYSTEM_BT_LPCK_DIV_B_S 0 + +#define SYSTEM_CPU_INTR_FROM_CPU_0_REG (DR_REG_SYSTEM_BASE + 0x30) +/* SYSTEM_CPU_INTR_FROM_CPU_0 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_CPU_INTR_FROM_CPU_0 (BIT(0)) +#define SYSTEM_CPU_INTR_FROM_CPU_0_M (BIT(0)) +#define SYSTEM_CPU_INTR_FROM_CPU_0_V 0x1 +#define SYSTEM_CPU_INTR_FROM_CPU_0_S 0 + +#define SYSTEM_CPU_INTR_FROM_CPU_1_REG (DR_REG_SYSTEM_BASE + 0x34) +/* SYSTEM_CPU_INTR_FROM_CPU_1 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_CPU_INTR_FROM_CPU_1 (BIT(0)) +#define SYSTEM_CPU_INTR_FROM_CPU_1_M (BIT(0)) +#define SYSTEM_CPU_INTR_FROM_CPU_1_V 0x1 +#define SYSTEM_CPU_INTR_FROM_CPU_1_S 0 + +#define SYSTEM_CPU_INTR_FROM_CPU_2_REG (DR_REG_SYSTEM_BASE + 0x38) +/* SYSTEM_CPU_INTR_FROM_CPU_2 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_CPU_INTR_FROM_CPU_2 (BIT(0)) +#define SYSTEM_CPU_INTR_FROM_CPU_2_M (BIT(0)) +#define SYSTEM_CPU_INTR_FROM_CPU_2_V 0x1 +#define SYSTEM_CPU_INTR_FROM_CPU_2_S 0 + +#define SYSTEM_CPU_INTR_FROM_CPU_3_REG (DR_REG_SYSTEM_BASE + 0x3C) +/* SYSTEM_CPU_INTR_FROM_CPU_3 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_CPU_INTR_FROM_CPU_3 (BIT(0)) +#define SYSTEM_CPU_INTR_FROM_CPU_3_M (BIT(0)) +#define SYSTEM_CPU_INTR_FROM_CPU_3_V 0x1 +#define SYSTEM_CPU_INTR_FROM_CPU_3_S 0 + +#define SYSTEM_RSA_PD_CTRL_REG (DR_REG_SYSTEM_BASE + 0x40) +/* SYSTEM_RSA_MEM_FORCE_PD : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_RSA_MEM_FORCE_PD (BIT(2)) +#define SYSTEM_RSA_MEM_FORCE_PD_M (BIT(2)) +#define SYSTEM_RSA_MEM_FORCE_PD_V 0x1 +#define SYSTEM_RSA_MEM_FORCE_PD_S 2 +/* SYSTEM_RSA_MEM_FORCE_PU : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_RSA_MEM_FORCE_PU (BIT(1)) +#define SYSTEM_RSA_MEM_FORCE_PU_M (BIT(1)) +#define SYSTEM_RSA_MEM_FORCE_PU_V 0x1 +#define SYSTEM_RSA_MEM_FORCE_PU_S 1 +/* SYSTEM_RSA_MEM_PD : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: .*/ +#define SYSTEM_RSA_MEM_PD (BIT(0)) +#define SYSTEM_RSA_MEM_PD_M (BIT(0)) +#define SYSTEM_RSA_MEM_PD_V 0x1 +#define SYSTEM_RSA_MEM_PD_S 0 + +#define SYSTEM_EDMA_CTRL_REG (DR_REG_SYSTEM_BASE + 0x44) +/* SYSTEM_EDMA_RESET : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_EDMA_RESET (BIT(1)) +#define SYSTEM_EDMA_RESET_M (BIT(1)) +#define SYSTEM_EDMA_RESET_V 0x1 +#define SYSTEM_EDMA_RESET_S 1 +/* SYSTEM_EDMA_CLK_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: .*/ +#define SYSTEM_EDMA_CLK_ON (BIT(0)) +#define SYSTEM_EDMA_CLK_ON_M (BIT(0)) +#define SYSTEM_EDMA_CLK_ON_V 0x1 +#define SYSTEM_EDMA_CLK_ON_S 0 + +#define SYSTEM_CACHE_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x48) +/* SYSTEM_DCACHE_RESET : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_DCACHE_RESET (BIT(3)) +#define SYSTEM_DCACHE_RESET_M (BIT(3)) +#define SYSTEM_DCACHE_RESET_V 0x1 +#define SYSTEM_DCACHE_RESET_S 3 +/* SYSTEM_DCACHE_CLK_ON : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: .*/ +#define SYSTEM_DCACHE_CLK_ON (BIT(2)) +#define SYSTEM_DCACHE_CLK_ON_M (BIT(2)) +#define SYSTEM_DCACHE_CLK_ON_V 0x1 +#define SYSTEM_DCACHE_CLK_ON_S 2 +/* SYSTEM_ICACHE_RESET : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_ICACHE_RESET (BIT(1)) +#define SYSTEM_ICACHE_RESET_M (BIT(1)) +#define SYSTEM_ICACHE_RESET_V 0x1 +#define SYSTEM_ICACHE_RESET_S 1 +/* SYSTEM_ICACHE_CLK_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: .*/ +#define SYSTEM_ICACHE_CLK_ON (BIT(0)) +#define SYSTEM_ICACHE_CLK_ON_M (BIT(0)) +#define SYSTEM_ICACHE_CLK_ON_V 0x1 +#define SYSTEM_ICACHE_CLK_ON_S 0 + +#define SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x4C) +/* SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT (BIT(3)) +#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_M (BIT(3)) +#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V 0x1 +#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S 3 +/* SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT (BIT(2)) +#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_M (BIT(2)) +#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V 0x1 +#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S 2 +/* SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT (BIT(1)) +#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_M (BIT(1)) +#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V 0x1 +#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S 1 +/* SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT (BIT(0)) +#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_M (BIT(0)) +#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V 0x1 +#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S 0 + +#define SYSTEM_RTC_FASTMEM_CONFIG_REG (DR_REG_SYSTEM_BASE + 0x50) +/* SYSTEM_RTC_MEM_CRC_FINISH : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_RTC_MEM_CRC_FINISH (BIT(31)) +#define SYSTEM_RTC_MEM_CRC_FINISH_M (BIT(31)) +#define SYSTEM_RTC_MEM_CRC_FINISH_V 0x1 +#define SYSTEM_RTC_MEM_CRC_FINISH_S 31 +/* SYSTEM_RTC_MEM_CRC_LEN : R/W ;bitpos:[30:20] ;default: 11'h7ff ; */ +/*description: .*/ +#define SYSTEM_RTC_MEM_CRC_LEN 0x000007FF +#define SYSTEM_RTC_MEM_CRC_LEN_M ((SYSTEM_RTC_MEM_CRC_LEN_V)<<(SYSTEM_RTC_MEM_CRC_LEN_S)) +#define SYSTEM_RTC_MEM_CRC_LEN_V 0x7FF +#define SYSTEM_RTC_MEM_CRC_LEN_S 20 +/* SYSTEM_RTC_MEM_CRC_ADDR : R/W ;bitpos:[19:9] ;default: 11'h0 ; */ +/*description: .*/ +#define SYSTEM_RTC_MEM_CRC_ADDR 0x000007FF +#define SYSTEM_RTC_MEM_CRC_ADDR_M ((SYSTEM_RTC_MEM_CRC_ADDR_V)<<(SYSTEM_RTC_MEM_CRC_ADDR_S)) +#define SYSTEM_RTC_MEM_CRC_ADDR_V 0x7FF +#define SYSTEM_RTC_MEM_CRC_ADDR_S 9 +/* SYSTEM_RTC_MEM_CRC_START : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_RTC_MEM_CRC_START (BIT(8)) +#define SYSTEM_RTC_MEM_CRC_START_M (BIT(8)) +#define SYSTEM_RTC_MEM_CRC_START_V 0x1 +#define SYSTEM_RTC_MEM_CRC_START_S 8 + +#define SYSTEM_RTC_FASTMEM_CRC_REG (DR_REG_SYSTEM_BASE + 0x54) +/* SYSTEM_RTC_MEM_CRC_RES : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: .*/ +#define SYSTEM_RTC_MEM_CRC_RES 0xFFFFFFFF +#define SYSTEM_RTC_MEM_CRC_RES_M ((SYSTEM_RTC_MEM_CRC_RES_V)<<(SYSTEM_RTC_MEM_CRC_RES_S)) +#define SYSTEM_RTC_MEM_CRC_RES_V 0xFFFFFFFF +#define SYSTEM_RTC_MEM_CRC_RES_S 0 + +#define SYSTEM_REDUNDANT_ECO_CTRL_REG (DR_REG_SYSTEM_BASE + 0x58) +/* SYSTEM_REDUNDANT_ECO_RESULT : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_REDUNDANT_ECO_RESULT (BIT(1)) +#define SYSTEM_REDUNDANT_ECO_RESULT_M (BIT(1)) +#define SYSTEM_REDUNDANT_ECO_RESULT_V 0x1 +#define SYSTEM_REDUNDANT_ECO_RESULT_S 1 +/* SYSTEM_REDUNDANT_ECO_DRIVE : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_REDUNDANT_ECO_DRIVE (BIT(0)) +#define SYSTEM_REDUNDANT_ECO_DRIVE_M (BIT(0)) +#define SYSTEM_REDUNDANT_ECO_DRIVE_V 0x1 +#define SYSTEM_REDUNDANT_ECO_DRIVE_S 0 + +#define SYSTEM_CLOCK_GATE_REG (DR_REG_SYSTEM_BASE + 0x5C) +/* SYSTEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: .*/ +#define SYSTEM_CLK_EN (BIT(0)) +#define SYSTEM_CLK_EN_M (BIT(0)) +#define SYSTEM_CLK_EN_V 0x1 +#define SYSTEM_CLK_EN_S 0 + +#define SYSTEM_SYSCLK_CONF_REG (DR_REG_SYSTEM_BASE + 0x60) +/* SYSTEM_CLK_DIV_EN : RO ;bitpos:[19] ;default: 1'd0 ; */ +/*description: .*/ +#define SYSTEM_CLK_DIV_EN (BIT(19)) +#define SYSTEM_CLK_DIV_EN_M (BIT(19)) +#define SYSTEM_CLK_DIV_EN_V 0x1 +#define SYSTEM_CLK_DIV_EN_S 19 +/* SYSTEM_CLK_XTAL_FREQ : RO ;bitpos:[18:12] ;default: 7'd0 ; */ +/*description: .*/ +#define SYSTEM_CLK_XTAL_FREQ 0x0000007F +#define SYSTEM_CLK_XTAL_FREQ_M ((SYSTEM_CLK_XTAL_FREQ_V)<<(SYSTEM_CLK_XTAL_FREQ_S)) +#define SYSTEM_CLK_XTAL_FREQ_V 0x7F +#define SYSTEM_CLK_XTAL_FREQ_S 12 +/* SYSTEM_SOC_CLK_SEL : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ +/*description: .*/ +#define SYSTEM_SOC_CLK_SEL 0x00000003 +#define SYSTEM_SOC_CLK_SEL_M ((SYSTEM_SOC_CLK_SEL_V)<<(SYSTEM_SOC_CLK_SEL_S)) +#define SYSTEM_SOC_CLK_SEL_V 0x3 +#define SYSTEM_SOC_CLK_SEL_S 10 +/* SYSTEM_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */ +/*description: .*/ +#define SYSTEM_PRE_DIV_CNT 0x000003FF +#define SYSTEM_PRE_DIV_CNT_M ((SYSTEM_PRE_DIV_CNT_V)<<(SYSTEM_PRE_DIV_CNT_S)) +#define SYSTEM_PRE_DIV_CNT_V 0x3FF +#define SYSTEM_PRE_DIV_CNT_S 0 + +#define SYSTEM_MEM_PVT_REG (DR_REG_SYSTEM_BASE + 0x64) +/* SYSTEM_MEM_VT_SEL : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: .*/ +#define SYSTEM_MEM_VT_SEL 0x00000003 +#define SYSTEM_MEM_VT_SEL_M ((SYSTEM_MEM_VT_SEL_V)<<(SYSTEM_MEM_VT_SEL_S)) +#define SYSTEM_MEM_VT_SEL_V 0x3 +#define SYSTEM_MEM_VT_SEL_S 22 +/* SYSTEM_MEM_TIMING_ERR_CNT : RO ;bitpos:[21:6] ;default: 16'h0 ; */ +/*description: .*/ +#define SYSTEM_MEM_TIMING_ERR_CNT 0x0000FFFF +#define SYSTEM_MEM_TIMING_ERR_CNT_M ((SYSTEM_MEM_TIMING_ERR_CNT_V)<<(SYSTEM_MEM_TIMING_ERR_CNT_S)) +#define SYSTEM_MEM_TIMING_ERR_CNT_V 0xFFFF +#define SYSTEM_MEM_TIMING_ERR_CNT_S 6 +/* SYSTEM_MEM_PVT_MONITOR_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_MEM_PVT_MONITOR_EN (BIT(5)) +#define SYSTEM_MEM_PVT_MONITOR_EN_M (BIT(5)) +#define SYSTEM_MEM_PVT_MONITOR_EN_V 0x1 +#define SYSTEM_MEM_PVT_MONITOR_EN_S 5 +/* SYSTEM_MEM_ERR_CNT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_MEM_ERR_CNT_CLR (BIT(4)) +#define SYSTEM_MEM_ERR_CNT_CLR_M (BIT(4)) +#define SYSTEM_MEM_ERR_CNT_CLR_V 0x1 +#define SYSTEM_MEM_ERR_CNT_CLR_S 4 +/* SYSTEM_MEM_PATH_LEN : R/W ;bitpos:[3:0] ;default: 4'h3 ; */ +/*description: .*/ +#define SYSTEM_MEM_PATH_LEN 0x0000000F +#define SYSTEM_MEM_PATH_LEN_M ((SYSTEM_MEM_PATH_LEN_V)<<(SYSTEM_MEM_PATH_LEN_S)) +#define SYSTEM_MEM_PATH_LEN_V 0xF +#define SYSTEM_MEM_PATH_LEN_S 0 + +#define SYSTEM_COMB_PVT_LVT_CONF_REG (DR_REG_SYSTEM_BASE + 0x68) +/* SYSTEM_COMB_PVT_MONITOR_EN_LVT : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_COMB_PVT_MONITOR_EN_LVT (BIT(6)) +#define SYSTEM_COMB_PVT_MONITOR_EN_LVT_M (BIT(6)) +#define SYSTEM_COMB_PVT_MONITOR_EN_LVT_V 0x1 +#define SYSTEM_COMB_PVT_MONITOR_EN_LVT_S 6 +/* SYSTEM_COMB_ERR_CNT_CLR_LVT : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_COMB_ERR_CNT_CLR_LVT (BIT(5)) +#define SYSTEM_COMB_ERR_CNT_CLR_LVT_M (BIT(5)) +#define SYSTEM_COMB_ERR_CNT_CLR_LVT_V 0x1 +#define SYSTEM_COMB_ERR_CNT_CLR_LVT_S 5 +/* SYSTEM_COMB_PATH_LEN_LVT : R/W ;bitpos:[4:0] ;default: 5'h3 ; */ +/*description: .*/ +#define SYSTEM_COMB_PATH_LEN_LVT 0x0000001F +#define SYSTEM_COMB_PATH_LEN_LVT_M ((SYSTEM_COMB_PATH_LEN_LVT_V)<<(SYSTEM_COMB_PATH_LEN_LVT_S)) +#define SYSTEM_COMB_PATH_LEN_LVT_V 0x1F +#define SYSTEM_COMB_PATH_LEN_LVT_S 0 + +#define SYSTEM_COMB_PVT_NVT_CONF_REG (DR_REG_SYSTEM_BASE + 0x6C) +/* SYSTEM_COMB_PVT_MONITOR_EN_NVT : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_COMB_PVT_MONITOR_EN_NVT (BIT(6)) +#define SYSTEM_COMB_PVT_MONITOR_EN_NVT_M (BIT(6)) +#define SYSTEM_COMB_PVT_MONITOR_EN_NVT_V 0x1 +#define SYSTEM_COMB_PVT_MONITOR_EN_NVT_S 6 +/* SYSTEM_COMB_ERR_CNT_CLR_NVT : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_COMB_ERR_CNT_CLR_NVT (BIT(5)) +#define SYSTEM_COMB_ERR_CNT_CLR_NVT_M (BIT(5)) +#define SYSTEM_COMB_ERR_CNT_CLR_NVT_V 0x1 +#define SYSTEM_COMB_ERR_CNT_CLR_NVT_S 5 +/* SYSTEM_COMB_PATH_LEN_NVT : R/W ;bitpos:[4:0] ;default: 5'h3 ; */ +/*description: .*/ +#define SYSTEM_COMB_PATH_LEN_NVT 0x0000001F +#define SYSTEM_COMB_PATH_LEN_NVT_M ((SYSTEM_COMB_PATH_LEN_NVT_V)<<(SYSTEM_COMB_PATH_LEN_NVT_S)) +#define SYSTEM_COMB_PATH_LEN_NVT_V 0x1F +#define SYSTEM_COMB_PATH_LEN_NVT_S 0 + +#define SYSTEM_COMB_PVT_HVT_CONF_REG (DR_REG_SYSTEM_BASE + 0x70) +/* SYSTEM_COMB_PVT_MONITOR_EN_HVT : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_COMB_PVT_MONITOR_EN_HVT (BIT(6)) +#define SYSTEM_COMB_PVT_MONITOR_EN_HVT_M (BIT(6)) +#define SYSTEM_COMB_PVT_MONITOR_EN_HVT_V 0x1 +#define SYSTEM_COMB_PVT_MONITOR_EN_HVT_S 6 +/* SYSTEM_COMB_ERR_CNT_CLR_HVT : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_COMB_ERR_CNT_CLR_HVT (BIT(5)) +#define SYSTEM_COMB_ERR_CNT_CLR_HVT_M (BIT(5)) +#define SYSTEM_COMB_ERR_CNT_CLR_HVT_V 0x1 +#define SYSTEM_COMB_ERR_CNT_CLR_HVT_S 5 +/* SYSTEM_COMB_PATH_LEN_HVT : R/W ;bitpos:[4:0] ;default: 5'h3 ; */ +/*description: .*/ +#define SYSTEM_COMB_PATH_LEN_HVT 0x0000001F +#define SYSTEM_COMB_PATH_LEN_HVT_M ((SYSTEM_COMB_PATH_LEN_HVT_V)<<(SYSTEM_COMB_PATH_LEN_HVT_S)) +#define SYSTEM_COMB_PATH_LEN_HVT_V 0x1F +#define SYSTEM_COMB_PATH_LEN_HVT_S 0 + +#define SYSTEM_COMB_PVT_ERR_LVT_SITE0_REG (DR_REG_SYSTEM_BASE + 0x74) +/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: .*/ +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0 0x0000FFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_M ((SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_S)) +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_V 0xFFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_S 0 + +#define SYSTEM_COMB_PVT_ERR_NVT_SITE0_REG (DR_REG_SYSTEM_BASE + 0x78) +/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: .*/ +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0 0x0000FFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_M ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_S)) +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_V 0xFFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_S 0 + +#define SYSTEM_COMB_PVT_ERR_HVT_SITE0_REG (DR_REG_SYSTEM_BASE + 0x7C) +/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: .*/ +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0 0x0000FFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_M ((SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_S)) +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_V 0xFFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_S 0 + +#define SYSTEM_COMB_PVT_ERR_LVT_SITE1_REG (DR_REG_SYSTEM_BASE + 0x80) +/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: .*/ +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1 0x0000FFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_M ((SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_S)) +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_V 0xFFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_S 0 + +#define SYSTEM_COMB_PVT_ERR_NVT_SITE1_REG (DR_REG_SYSTEM_BASE + 0x84) +/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: .*/ +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1 0x0000FFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_M ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_S)) +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_V 0xFFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_S 0 + +#define SYSTEM_COMB_PVT_ERR_HVT_SITE1_REG (DR_REG_SYSTEM_BASE + 0x88) +/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: .*/ +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1 0x0000FFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_M ((SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_S)) +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_V 0xFFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_S 0 + +#define SYSTEM_COMB_PVT_ERR_LVT_SITE2_REG (DR_REG_SYSTEM_BASE + 0x8C) +/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: .*/ +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2 0x0000FFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_M ((SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_S)) +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_V 0xFFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_S 0 + +#define SYSTEM_COMB_PVT_ERR_NVT_SITE2_REG (DR_REG_SYSTEM_BASE + 0x90) +/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: .*/ +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2 0x0000FFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_M ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_S)) +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_V 0xFFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_S 0 + +#define SYSTEM_COMB_PVT_ERR_HVT_SITE2_REG (DR_REG_SYSTEM_BASE + 0x94) +/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: .*/ +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2 0x0000FFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_M ((SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_S)) +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_V 0xFFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_S 0 + +#define SYSTEM_COMB_PVT_ERR_LVT_SITE3_REG (DR_REG_SYSTEM_BASE + 0x98) +/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: .*/ +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3 0x0000FFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_M ((SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_S)) +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_V 0xFFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_S 0 + +#define SYSTEM_COMB_PVT_ERR_NVT_SITE3_REG (DR_REG_SYSTEM_BASE + 0x9C) +/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: .*/ +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3 0x0000FFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_M ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_S)) +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_V 0xFFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_S 0 + +#define SYSTEM_COMB_PVT_ERR_HVT_SITE3_REG (DR_REG_SYSTEM_BASE + 0xA0) +/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: .*/ +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3 0x0000FFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_M ((SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_S)) +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_V 0xFFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_S 0 + +#define SYSTEM_DATE_REG (DR_REG_SYSTEM_BASE + 0xFFC) +/* SYSTEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2101220 ; */ +/*description: .*/ +#define SYSTEM_DATE 0x0FFFFFFF +#define SYSTEM_DATE_M ((SYSTEM_DATE_V)<<(SYSTEM_DATE_S)) +#define SYSTEM_DATE_V 0xFFFFFFF +#define SYSTEM_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/src/target/esp32s3/ld/esp32s3.rom.api.ld b/src/target/esp32s3/ld/esp32s3.rom.api.ld index 350a6ea..dd6edf8 100644 --- a/src/target/esp32s3/ld/esp32s3.rom.api.ld +++ b/src/target/esp32s3/ld/esp32s3.rom.api.ld @@ -31,7 +31,6 @@ PROVIDE ( esp_rom_uart_putc = ets_write_char_uart ); PROVIDE ( esp_rom_uart_attach = uartAttach ); PROVIDE ( esp_rom_uart_init = Uart_Init ); PROVIDE ( esp_rom_uart_div_modify = uart_div_modify ); -PROVIDE ( esp_rom_get_apb_freq = ets_get_apb_freq ); PROVIDE ( esp_rom_get_uart_device = GetUartDevice ); PROVIDE ( esp_rom_output_flush_tx = uart_tx_flush ); @@ -59,6 +58,7 @@ PROVIDE ( esp_rom_isr_attach = ets_isr_attach ); PROVIDE ( esp_rom_isr_unmask = ets_isr_unmask ); PROVIDE ( esp_rom_get_cpu_ticks_per_us = ets_get_cpu_frequency ); PROVIDE ( esp_rom_set_cpu_ticks_per_us = ets_update_cpu_frequency ); +PROVIDE ( esp_rom_get_xtal_freq = ets_get_xtal_freq ); PROVIDE ( esp_rom_spiflash_attach = spi_flash_attach ); PROVIDE ( esp_rom_spiflash_clear_bp = esp_rom_spiflash_unlock ); diff --git a/src/target/esp32s3/src/clock.c b/src/target/esp32s3/src/clock.c new file mode 100644 index 0000000..210af80 --- /dev/null +++ b/src/target/esp32s3/src/clock.c @@ -0,0 +1,46 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 OR MIT + */ + +#include +#include +#include +#include +#include +#include + +#define MHZ 1000000U + +extern uint32_t esp_rom_get_cpu_ticks_per_us(void); +extern void esp_rom_set_cpu_ticks_per_us(uint32_t ticks_per_us); +extern uint32_t esp_rom_get_xtal_freq(void); + +static uint32_t s_cpu_freq = 0; + +void stub_target_clock_init(void) +{ + // TODO: Increase DBIAS voltage before clock increase, + // not that simple for esp32s3 as ESP-IDF reads it from eFuse. + // Without it there were stability issues. + // https://github.com/espressif/esptool/issues/832, https://github.com/espressif/esptool/issues/808 + s_cpu_freq = 40U * MHZ; + esp_rom_set_cpu_ticks_per_us(s_cpu_freq / MHZ); +} + +uint32_t stub_target_get_cpu_freq(void) +{ + if (s_cpu_freq == 0) { + return esp_rom_get_cpu_ticks_per_us() * MHZ; + } + return s_cpu_freq; +} + +uint32_t stub_target_get_apb_freq(void) +{ + if (REG_GET_FIELD(SYSTEM_CPU_PER_CONF_REG, SYSTEM_PLL_FREQ_SEL) == 1) { + return 80U * MHZ; + } + return esp_rom_get_xtal_freq(); +} diff --git a/src/target/esp32s3/src/uart.c b/src/target/esp32s3/src/uart.c index 43ff228..a904919 100644 --- a/src/target/esp32s3/src/uart.c +++ b/src/target/esp32s3/src/uart.c @@ -8,21 +8,19 @@ #include #include #include +#include +#include #include #include // These functions are defined in the ROM extern void esp_rom_uart_attach(void *rxBuffer); extern void esp_rom_uart_init(uint8_t uart_no, uint32_t clock); -extern uint32_t esp_rom_get_apb_freq(void); -extern void esp_rom_set_cpu_ticks_per_us(uint32_t ticks_per_us); extern void esp_rom_uart_set_as_console(uint8_t uart_no); extern void esp_rom_uart_div_modify(uint8_t uart_no, uint32_t divisor); extern void esp_rom_isr_attach(int int_num, void *handler, void *arg); extern void esp_rom_isr_unmask(int int_num); -#define UART_CLK_FREQ_ROM (40 * 1000000) - void stub_target_rom_uart_attach(void *rxBuffer) { esp_rom_uart_attach(rxBuffer); @@ -36,18 +34,20 @@ void stub_target_rom_uart_init(uint8_t uart_no, uint32_t clock) void stub_target_uart_init(uint8_t uart_num) { extern bool g_uart_print; - esp_rom_set_cpu_ticks_per_us(esp_rom_get_apb_freq() / 1000000); stub_target_rom_uart_attach(NULL); - stub_target_rom_uart_init(uart_num, UART_CLK_FREQ_ROM); + uint32_t clock = stub_target_get_apb_freq(); + stub_target_rom_uart_init(uart_num, clock); esp_rom_uart_set_as_console(uart_num); g_uart_print = true; } void stub_target_uart_rominit_set_baudrate(uint8_t uart_num, uint32_t baudrate) { - uint32_t clock = esp_rom_get_apb_freq() << 4; - uint32_t divisor = clock / baudrate; + stub_lib_delay_us(5 * 1000); + + uint32_t clk_div = (stub_target_get_apb_freq() << 4) / baudrate; stub_target_uart_wait_idle(uart_num); - esp_rom_uart_div_modify(uart_num, divisor); - // TODO: Consider decimal part + esp_rom_uart_div_modify(uart_num, clk_div); + + stub_lib_delay_us(5 * 1000); } diff --git a/src/target/esp8266/CMakeLists.txt b/src/target/esp8266/CMakeLists.txt index 481e849..81fcb8e 100644 --- a/src/target/esp8266/CMakeLists.txt +++ b/src/target/esp8266/CMakeLists.txt @@ -3,6 +3,7 @@ set(srcs src/rom-patched.c src/security.c src/flash.c + src/clock.c ) add_library(${ESP_TARGET_LIB} STATIC ${srcs}) diff --git a/src/target/esp8266/include/soc/uart_reg.h b/src/target/esp8266/include/soc/uart_reg.h index 905ac19..127c799 100644 --- a/src/target/esp8266/include/soc/uart_reg.h +++ b/src/target/esp8266/include/soc/uart_reg.h @@ -95,7 +95,7 @@ extern "C" { #define UART_CLKDIV_REG(i) (REG_UART_BASE(i) + 0x14) #define UART_CLKDIV_M (UART_CLKDIV_V << UART_CLKDIV_S) -#define UART_CLKDIV_CNT_V 0x000FFFFF +#define UART_CLKDIV_V 0x000FFFFF #define UART_CLKDIV_S 0 #define UART_AUTOBAUD_REG(i) (REG_UART_BASE(i) + 0x18) diff --git a/src/target/esp8266/src/clock.c b/src/target/esp8266/src/clock.c new file mode 100644 index 0000000..e25036f --- /dev/null +++ b/src/target/esp8266/src/clock.c @@ -0,0 +1,21 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 OR MIT + */ + +#include +#include +#include +#include +#include + +#define MHZ 1000000 + +extern uint32_t esp_rom_get_cpu_ticks_per_us(void); +extern void esp_rom_set_cpu_ticks_per_us(uint32_t ticks_per_us); + +void stub_target_clock_init(void) +{ + esp_rom_set_cpu_ticks_per_us(52); +} diff --git a/src/target/esp8266/src/uart.c b/src/target/esp8266/src/uart.c index 5d30fbd..b269822 100644 --- a/src/target/esp8266/src/uart.c +++ b/src/target/esp8266/src/uart.c @@ -6,7 +6,9 @@ #include #include +#include #include +#include #include #include @@ -17,10 +19,7 @@ extern void esp_rom_uart_rx_intr_handler(void *para); extern void esp_rom_isr_attach(int int_num, void *handler, void *arg); extern void esp_rom_isr_unmask(int int_num); extern void esp_rom_uart_div_modify(uint8_t uart_no, uint32_t divisor); -extern uint32_t ets_get_detected_xtal_freq(void); -extern uint32_t esp_rom_get_cpu_ticks_per_us(void); -extern void esp_rom_set_cpu_ticks_per_us(uint32_t ticks_per_us); -extern uint32_t g_ticks_per_us; +extern uint32_t esp_rom_get_xtal_freq(void); void stub_target_rom_uart_attach(void *rxBuffer) { @@ -52,10 +51,16 @@ void stub_target_uart_init(uint8_t uart_num) void stub_target_uart_rominit_set_baudrate(uint8_t uart_num, uint32_t baudrate) { - uint32_t xtal_freq = g_ticks_per_us * 1000000; - uint32_t clock = xtal_freq << 4; - uint32_t divisor = clock / baudrate; - esp_rom_uart_div_modify(uart_num, divisor); + stub_lib_delay_us(5 * 1000); + + uint32_t uart_reg_value = READ_PERI_REG(UART_CLKDIV_REG(uart_num)); + uint32_t clk_div = uart_reg_value & UART_CLKDIV_M; + + uint32_t new_clk_div = clk_div * 115200 / baudrate; + stub_target_uart_wait_idle(uart_num); + esp_rom_uart_div_modify(uart_num, new_clk_div); + + stub_lib_delay_us(5 * 1000); } void stub_target_uart_tx_flush(uint8_t uart_no)