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chenqian
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[Pass] add more examples in RISCVIntLoopUnrollAndRemainder
1 parent 7062d3e commit 199f819

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llvm/lib/Target/RISCV/CMakeLists.txt

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@@ -45,6 +45,7 @@ add_llvm_target(RISCVCodeGen
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RISCVLoopUnrollAndRemainder.cpp
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RISCVEsp32P4MemIntrin.cpp
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RISCVIndirectBranchTracking.cpp
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RISCVIntLoopUnrollAndRemainder.cpp
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RISCVInsertReadWriteCSR.cpp
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RISCVInsertVSETVLI.cpp
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RISCVInsertWriteVXRM.cpp

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