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sstefan1gerekon
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[RISCV][ESP32P4] Don't yet consider v16i8 and v4i32 legal
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llvm/lib/Target/RISCV/RISCVISelLowering.cpp

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@@ -118,12 +118,6 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
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// Set up the register classes.
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addRegisterClass(XLenVT, &RISCV::GPRRegClass);
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if (Subtarget.hasVendorXesppie()) {
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static const MVT::SimpleValueType QRVec[] = {MVT::v16i8, MVT::v4i32};
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for (auto st : QRVec)
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addRegisterClass(st, &RISCV::QRRegClass);
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}
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if (Subtarget.hasStdExtZfhmin())
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addRegisterClass(MVT::f16, &RISCV::FPR16RegClass);
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if (Subtarget.hasStdExtZfbfmin())

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