Skip to content

Commit 3fdfd75

Browse files
sstefan1gerekon
sstefan1
authored and
gerekon
committed
[ESP32H4] Implement support for custom dsp instructions.
1 parent bebe49b commit 3fdfd75

File tree

19 files changed

+2464
-2
lines changed

19 files changed

+2464
-2
lines changed

‎clang/include/clang/Basic/BuiltinsRISCV.td‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -154,6 +154,7 @@ let Features = "zihintpause", Attributes = [NoThrow] in
154154
def pause : RISCVBuiltin<"void()">;
155155

156156
include "BuiltinsRISCVESP32P4.td"
157+
include "BuiltinsRISCVESP32H4.td"
157158

158159
//===----------------------------------------------------------------------===//
159160
// XCV extensions.

‎clang/include/clang/Basic/BuiltinsRISCVESP32H4.td‎

Lines changed: 52 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,52 @@
1+
let Features = "xespdsp" in {
2+
def esp_muls16ix2 : RISCVBuiltin<"void(unsigned int, unsigned int, unsigned int, unsigned int, unsigned int)">;
3+
def esp_muls16x2 : RISCVBuiltin<"void(unsigned int, unsigned int, unsigned int, unsigned int)">;
4+
def esp_muls32i : RISCVBuiltin<"int(unsigned int, unsigned int, unsigned int)">;
5+
def esp_muls32 : RISCVBuiltin<"int(unsigned int, unsigned int)">;
6+
def esp_shl : RISCVBuiltin<"int(unsigned int, unsigned int)">;
7+
def esp_shr : RISCVBuiltin<"int(unsigned int, unsigned int)">;
8+
def esp_abs : RISCVBuiltin<"int(unsigned int)">;
9+
def esp_movr_xacc : RISCVBuiltin<"int(unsigned int)">;
10+
def esp_min : RISCVBuiltin<"int(unsigned int, unsigned int)">;
11+
def esp_max : RISCVBuiltin<"int(unsigned int, unsigned int)">;
12+
def esp_clzs : RISCVBuiltin<"int(unsigned int)">;
13+
def esp_flw_ip : RISCVBuiltin<"float(unsigned int, unsigned int, unsigned int)">;
14+
def esp_flw_xp : RISCVBuiltin<"float(unsigned int, unsigned int)">;
15+
def esp_fsw_ip : RISCVBuiltin<"void(unsigned int, unsigned int, unsigned int, unsigned int)">;
16+
def esp_fsw_xp : RISCVBuiltin<"void(unsigned int, unsigned int, unsigned int)">;
17+
def esp_lw_ip : RISCVBuiltin<"int(unsigned int, unsigned int, unsigned int)">;
18+
def esp_lw_xp : RISCVBuiltin<"int(unsigned int, unsigned int)">;
19+
def esp_sw_ip : RISCVBuiltin<"void(unsigned int, unsigned int, unsigned int, unsigned int)">;
20+
def esp_sw_xp : RISCVBuiltin<"void(unsigned int, unsigned int, unsigned int)">;
21+
def esp_lh_ip : RISCVBuiltin<"int(unsigned int, unsigned int, unsigned int)">;
22+
def esp_lh_xp : RISCVBuiltin<"int(unsigned int, unsigned int)">;
23+
def esp_sh_ip : RISCVBuiltin<"void(unsigned int, unsigned int, unsigned int, unsigned int)">;
24+
def esp_sh_xp : RISCVBuiltin<"void(unsigned int, unsigned int, unsigned int)">;
25+
def esp_lb_ip : RISCVBuiltin<"int(unsigned int, unsigned int, unsigned int)">;
26+
def esp_lb_xp : RISCVBuiltin<"int(unsigned int, unsigned int)">;
27+
def esp_sb_ip : RISCVBuiltin<"void(unsigned int, unsigned int, unsigned int, unsigned int)">;
28+
def esp_sb_xp : RISCVBuiltin<"void(unsigned int, unsigned int, unsigned int)">;
29+
def esp_lhu_ip : RISCVBuiltin<"int(unsigned int, unsigned int, unsigned int)">;
30+
def esp_lhu_xp : RISCVBuiltin<"int(unsigned int, unsigned int)">;
31+
def esp_lbu_ip : RISCVBuiltin<"int(unsigned int, unsigned int, unsigned int)">;
32+
def esp_lbu_xp : RISCVBuiltin<"int(unsigned int, unsigned int)">;
33+
def esp_movw_xacc : RISCVBuiltin<"void(unsigned int, unsigned int)">;
34+
def esp_macs32i : RISCVBuiltin<"void(unsigned int, unsigned int, unsigned int)">;
35+
def esp_macs32 : RISCVBuiltin<"void(unsigned int, unsigned int)">;
36+
def esp_macs32_ld : RISCVBuiltin<"int(unsigned int, unsigned int, unsigned int)">;
37+
def esp_macs32_st : RISCVBuiltin<"void(unsigned int, unsigned int, unsigned int, unsigned int)">;
38+
def esp_macs16ix2 : RISCVBuiltin<"void(unsigned int, unsigned int, unsigned int)">;
39+
def esp_macs16x2 : RISCVBuiltin<"void(unsigned int, unsigned int)">;
40+
def esp_macs16x2_ld : RISCVBuiltin<"int(unsigned int, unsigned int, unsigned int)">;
41+
def esp_macs16x1_ld : RISCVBuiltin<"int(unsigned int, unsigned int, unsigned int)">;
42+
def esp_macs16x2_st : RISCVBuiltin<"void(unsigned int, unsigned int, unsigned int, unsigned int)">;
43+
def esp_msus32i : RISCVBuiltin<"void(unsigned int, unsigned int, unsigned int)">;
44+
def esp_msus32 : RISCVBuiltin<"void(unsigned int, unsigned int)">;
45+
def esp_msus32_ld : RISCVBuiltin<"int(unsigned int, unsigned int, unsigned int)">;
46+
def esp_msus32_st : RISCVBuiltin<"void(unsigned int, unsigned int, unsigned int, unsigned int)">;
47+
def esp_msus16ix2 : RISCVBuiltin<"void(unsigned int, unsigned int, unsigned int)">;
48+
def esp_msus16x2 : RISCVBuiltin<"void(unsigned int, unsigned int)">;
49+
def esp_msus16x2_ld : RISCVBuiltin<"int(unsigned int, unsigned int, unsigned int)">;
50+
def esp_msus16x1_ld : RISCVBuiltin<"int(unsigned int, unsigned int, unsigned int)">;
51+
def esp_msus16x2_st : RISCVBuiltin<"void(unsigned int, unsigned int, unsigned int, unsigned int)">;
52+
}

‎clang/include/clang/Basic/BuiltinsRISCVESP32P4.td‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -353,4 +353,4 @@ def esp_vsrd_32 : RISCVBuiltin<"void(unsigned int, unsigned int, unsigned int)">
353353
def esp_vsrd_8 : RISCVBuiltin<"void(unsigned int, unsigned int, unsigned int)">;
354354
def esp_st_s_xacc_ip : RISCVBuiltin<"int(unsigned int, int)">;
355355
def esp_st_u_xacc_ip : RISCVBuiltin<"int(unsigned int, int)">;
356-
}
356+
}

‎clang/test/CodeGen/RISCV/riscv-esp32h4.c‎

Lines changed: 231 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,231 @@
1+
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5
2+
// RUN: %clang_cc1 -triple riscv32 -target-feature +xespdsp -emit-llvm -O0 -o - %s \
3+
// RUN: | FileCheck %s
4+
5+
#include <stdint.h>
6+
7+
// CHECK-LABEL: define dso_local void @test(
8+
// CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
9+
// CHECK-NEXT: [[ENTRY:.*:]]
10+
// CHECK-NEXT: [[DATA:%.*]] = alloca i32, align 4
11+
// CHECK-NEXT: store i32 10, ptr [[DATA]], align 4
12+
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[DATA]], align 4
13+
// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[DATA]], align 4
14+
// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[DATA]], align 4
15+
// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[DATA]], align 4
16+
// CHECK-NEXT: call void @llvm.riscv.esp.muls16ix2(i32 [[TMP0]], i32 [[TMP1]], i32 29, i32 [[TMP2]], i32 [[TMP3]])
17+
// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[DATA]], align 4
18+
// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[DATA]], align 4
19+
// CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[DATA]], align 4
20+
// CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[DATA]], align 4
21+
// CHECK-NEXT: call void @llvm.riscv.esp.muls16x2(i32 [[TMP4]], i32 [[TMP5]], i32 [[TMP6]], i32 [[TMP7]])
22+
// CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[DATA]], align 4
23+
// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[DATA]], align 4
24+
// CHECK-NEXT: [[TMP10:%.*]] = call i32 @llvm.riscv.esp.muls32i(i32 [[TMP8]], i32 [[TMP9]], i32 3)
25+
// CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr [[DATA]], align 4
26+
// CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[DATA]], align 4
27+
// CHECK-NEXT: [[TMP13:%.*]] = call i32 @llvm.riscv.esp.muls32(i32 [[TMP11]], i32 [[TMP12]])
28+
// CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[DATA]], align 4
29+
// CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[DATA]], align 4
30+
// CHECK-NEXT: [[TMP16:%.*]] = call i32 @llvm.riscv.esp.shl(i32 [[TMP14]], i32 [[TMP15]])
31+
// CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[DATA]], align 4
32+
// CHECK-NEXT: [[TMP18:%.*]] = load i32, ptr [[DATA]], align 4
33+
// CHECK-NEXT: [[TMP19:%.*]] = call i32 @llvm.riscv.esp.shr(i32 [[TMP17]], i32 [[TMP18]])
34+
// CHECK-NEXT: [[TMP20:%.*]] = load i32, ptr [[DATA]], align 4
35+
// CHECK-NEXT: [[TMP21:%.*]] = call i32 @llvm.riscv.esp.abs(i32 [[TMP20]])
36+
// CHECK-NEXT: [[TMP22:%.*]] = load i32, ptr [[DATA]], align 4
37+
// CHECK-NEXT: [[TMP23:%.*]] = call i32 @llvm.riscv.esp.movr.xacc(i32 [[TMP22]])
38+
// CHECK-NEXT: [[TMP24:%.*]] = load i32, ptr [[DATA]], align 4
39+
// CHECK-NEXT: [[TMP25:%.*]] = load i32, ptr [[DATA]], align 4
40+
// CHECK-NEXT: [[TMP26:%.*]] = call i32 @llvm.riscv.esp.min(i32 [[TMP24]], i32 [[TMP25]])
41+
// CHECK-NEXT: [[TMP27:%.*]] = load i32, ptr [[DATA]], align 4
42+
// CHECK-NEXT: [[TMP28:%.*]] = load i32, ptr [[DATA]], align 4
43+
// CHECK-NEXT: [[TMP29:%.*]] = call i32 @llvm.riscv.esp.max(i32 [[TMP27]], i32 [[TMP28]])
44+
// CHECK-NEXT: [[TMP30:%.*]] = load i32, ptr [[DATA]], align 4
45+
// CHECK-NEXT: [[TMP31:%.*]] = call i32 @llvm.riscv.esp.clzs(i32 [[TMP30]])
46+
// CHECK-NEXT: [[TMP32:%.*]] = load i32, ptr [[DATA]], align 4
47+
// CHECK-NEXT: [[TMP33:%.*]] = call float @llvm.riscv.esp.flw.ip(i32 [[TMP32]], i32 -5, i32 2)
48+
// CHECK-NEXT: [[TMP34:%.*]] = load i32, ptr [[DATA]], align 4
49+
// CHECK-NEXT: [[TMP35:%.*]] = load i32, ptr [[DATA]], align 4
50+
// CHECK-NEXT: [[TMP36:%.*]] = call float @llvm.riscv.esp.flw.xp(i32 [[TMP34]], i32 [[TMP35]])
51+
// CHECK-NEXT: [[TMP37:%.*]] = load i32, ptr [[DATA]], align 4
52+
// CHECK-NEXT: [[TMP38:%.*]] = load i32, ptr [[DATA]], align 4
53+
// CHECK-NEXT: [[TMP39:%.*]] = bitcast i32 [[TMP38]] to float
54+
// CHECK-NEXT: call void @llvm.riscv.esp.fsw.ip(i32 [[TMP37]], float [[TMP39]], i32 4, i32 3)
55+
// CHECK-NEXT: [[TMP40:%.*]] = load i32, ptr [[DATA]], align 4
56+
// CHECK-NEXT: [[TMP41:%.*]] = load i32, ptr [[DATA]], align 4
57+
// CHECK-NEXT: [[TMP42:%.*]] = load i32, ptr [[DATA]], align 4
58+
// CHECK-NEXT: [[TMP43:%.*]] = bitcast i32 [[TMP42]] to float
59+
// CHECK-NEXT: call void @llvm.riscv.esp.fsw.xp(i32 [[TMP40]], i32 [[TMP41]], float [[TMP43]])
60+
// CHECK-NEXT: [[TMP44:%.*]] = load i32, ptr [[DATA]], align 4
61+
// CHECK-NEXT: [[TMP45:%.*]] = call i32 @llvm.riscv.esp.lw.ip(i32 [[TMP44]], i32 -8, i32 1)
62+
// CHECK-NEXT: [[TMP46:%.*]] = load i32, ptr [[DATA]], align 4
63+
// CHECK-NEXT: [[TMP47:%.*]] = load i32, ptr [[DATA]], align 4
64+
// CHECK-NEXT: [[TMP48:%.*]] = call i32 @llvm.riscv.esp.lw.xp(i32 [[TMP46]], i32 [[TMP47]])
65+
// CHECK-NEXT: [[TMP49:%.*]] = load i32, ptr [[DATA]], align 4
66+
// CHECK-NEXT: [[TMP50:%.*]] = load i32, ptr [[DATA]], align 4
67+
// CHECK-NEXT: call void @llvm.riscv.esp.sw.ip(i32 [[TMP49]], i32 [[TMP50]], i32 -10, i32 0)
68+
// CHECK-NEXT: [[TMP51:%.*]] = load i32, ptr [[DATA]], align 4
69+
// CHECK-NEXT: [[TMP52:%.*]] = load i32, ptr [[DATA]], align 4
70+
// CHECK-NEXT: [[TMP53:%.*]] = load i32, ptr [[DATA]], align 4
71+
// CHECK-NEXT: call void @llvm.riscv.esp.sw.xp(i32 [[TMP51]], i32 [[TMP52]], i32 [[TMP53]])
72+
// CHECK-NEXT: [[TMP54:%.*]] = load i32, ptr [[DATA]], align 4
73+
// CHECK-NEXT: [[TMP55:%.*]] = call i32 @llvm.riscv.esp.lh.ip(i32 [[TMP54]], i32 3, i32 1)
74+
// CHECK-NEXT: [[TMP56:%.*]] = load i32, ptr [[DATA]], align 4
75+
// CHECK-NEXT: [[TMP57:%.*]] = load i32, ptr [[DATA]], align 4
76+
// CHECK-NEXT: [[TMP58:%.*]] = call i32 @llvm.riscv.esp.lh.xp(i32 [[TMP56]], i32 [[TMP57]])
77+
// CHECK-NEXT: [[TMP59:%.*]] = load i32, ptr [[DATA]], align 4
78+
// CHECK-NEXT: [[TMP60:%.*]] = load i32, ptr [[DATA]], align 4
79+
// CHECK-NEXT: call void @llvm.riscv.esp.sh.ip(i32 [[TMP59]], i32 [[TMP60]], i32 14, i32 0)
80+
// CHECK-NEXT: [[TMP61:%.*]] = load i32, ptr [[DATA]], align 4
81+
// CHECK-NEXT: [[TMP62:%.*]] = load i32, ptr [[DATA]], align 4
82+
// CHECK-NEXT: [[TMP63:%.*]] = load i32, ptr [[DATA]], align 4
83+
// CHECK-NEXT: call void @llvm.riscv.esp.sh.xp(i32 [[TMP61]], i32 [[TMP62]], i32 [[TMP63]])
84+
// CHECK-NEXT: [[TMP64:%.*]] = load i32, ptr [[DATA]], align 4
85+
// CHECK-NEXT: [[TMP65:%.*]] = call i32 @llvm.riscv.esp.lb.ip(i32 [[TMP64]], i32 11, i32 0)
86+
// CHECK-NEXT: [[TMP66:%.*]] = load i32, ptr [[DATA]], align 4
87+
// CHECK-NEXT: [[TMP67:%.*]] = load i32, ptr [[DATA]], align 4
88+
// CHECK-NEXT: [[TMP68:%.*]] = call i32 @llvm.riscv.esp.lb.xp(i32 [[TMP66]], i32 [[TMP67]])
89+
// CHECK-NEXT: [[TMP69:%.*]] = load i32, ptr [[DATA]], align 4
90+
// CHECK-NEXT: [[TMP70:%.*]] = load i32, ptr [[DATA]], align 4
91+
// CHECK-NEXT: call void @llvm.riscv.esp.sb.ip(i32 [[TMP69]], i32 [[TMP70]], i32 7, i32 2)
92+
// CHECK-NEXT: [[TMP71:%.*]] = load i32, ptr [[DATA]], align 4
93+
// CHECK-NEXT: [[TMP72:%.*]] = load i32, ptr [[DATA]], align 4
94+
// CHECK-NEXT: [[TMP73:%.*]] = load i32, ptr [[DATA]], align 4
95+
// CHECK-NEXT: call void @llvm.riscv.esp.sb.xp(i32 [[TMP71]], i32 [[TMP72]], i32 [[TMP73]])
96+
// CHECK-NEXT: [[TMP74:%.*]] = load i32, ptr [[DATA]], align 4
97+
// CHECK-NEXT: [[TMP75:%.*]] = call i32 @llvm.riscv.esp.lhu.ip(i32 [[TMP74]], i32 -12, i32 2)
98+
// CHECK-NEXT: [[TMP76:%.*]] = load i32, ptr [[DATA]], align 4
99+
// CHECK-NEXT: [[TMP77:%.*]] = load i32, ptr [[DATA]], align 4
100+
// CHECK-NEXT: [[TMP78:%.*]] = call i32 @llvm.riscv.esp.lhu.xp(i32 [[TMP76]], i32 [[TMP77]])
101+
// CHECK-NEXT: [[TMP79:%.*]] = load i32, ptr [[DATA]], align 4
102+
// CHECK-NEXT: [[TMP80:%.*]] = call i32 @llvm.riscv.esp.lbu.ip(i32 [[TMP79]], i32 12, i32 2)
103+
// CHECK-NEXT: [[TMP81:%.*]] = load i32, ptr [[DATA]], align 4
104+
// CHECK-NEXT: [[TMP82:%.*]] = load i32, ptr [[DATA]], align 4
105+
// CHECK-NEXT: [[TMP83:%.*]] = call i32 @llvm.riscv.esp.lbu.xp(i32 [[TMP81]], i32 [[TMP82]])
106+
// CHECK-NEXT: [[TMP84:%.*]] = load i32, ptr [[DATA]], align 4
107+
// CHECK-NEXT: [[TMP85:%.*]] = load i32, ptr [[DATA]], align 4
108+
// CHECK-NEXT: call void @llvm.riscv.esp.movw.xacc(i32 [[TMP84]], i32 [[TMP85]])
109+
// CHECK-NEXT: [[TMP86:%.*]] = load i32, ptr [[DATA]], align 4
110+
// CHECK-NEXT: [[TMP87:%.*]] = load i32, ptr [[DATA]], align 4
111+
// CHECK-NEXT: call void @llvm.riscv.esp.macs32i(i32 [[TMP86]], i32 [[TMP87]], i32 18)
112+
// CHECK-NEXT: [[TMP88:%.*]] = load i32, ptr [[DATA]], align 4
113+
// CHECK-NEXT: [[TMP89:%.*]] = load i32, ptr [[DATA]], align 4
114+
// CHECK-NEXT: call void @llvm.riscv.esp.macs32(i32 [[TMP88]], i32 [[TMP89]])
115+
// CHECK-NEXT: [[TMP90:%.*]] = load i32, ptr [[DATA]], align 4
116+
// CHECK-NEXT: [[TMP91:%.*]] = load i32, ptr [[DATA]], align 4
117+
// CHECK-NEXT: [[TMP92:%.*]] = load i32, ptr [[DATA]], align 4
118+
// CHECK-NEXT: [[TMP93:%.*]] = call i32 @llvm.riscv.esp.macs32.ld(i32 [[TMP90]], i32 [[TMP91]], i32 [[TMP92]])
119+
// CHECK-NEXT: [[TMP94:%.*]] = load i32, ptr [[DATA]], align 4
120+
// CHECK-NEXT: [[TMP95:%.*]] = load i32, ptr [[DATA]], align 4
121+
// CHECK-NEXT: [[TMP96:%.*]] = load i32, ptr [[DATA]], align 4
122+
// CHECK-NEXT: [[TMP97:%.*]] = load i32, ptr [[DATA]], align 4
123+
// CHECK-NEXT: call void @llvm.riscv.esp.macs32.st(i32 [[TMP94]], i32 [[TMP95]], i32 [[TMP96]], i32 [[TMP97]])
124+
// CHECK-NEXT: [[TMP98:%.*]] = load i32, ptr [[DATA]], align 4
125+
// CHECK-NEXT: [[TMP99:%.*]] = load i32, ptr [[DATA]], align 4
126+
// CHECK-NEXT: call void @llvm.riscv.esp.macs16ix2(i32 [[TMP98]], i32 [[TMP99]], i32 25)
127+
// CHECK-NEXT: [[TMP100:%.*]] = load i32, ptr [[DATA]], align 4
128+
// CHECK-NEXT: [[TMP101:%.*]] = load i32, ptr [[DATA]], align 4
129+
// CHECK-NEXT: call void @llvm.riscv.esp.macs16x2(i32 [[TMP100]], i32 [[TMP101]])
130+
// CHECK-NEXT: [[TMP102:%.*]] = load i32, ptr [[DATA]], align 4
131+
// CHECK-NEXT: [[TMP103:%.*]] = load i32, ptr [[DATA]], align 4
132+
// CHECK-NEXT: [[TMP104:%.*]] = load i32, ptr [[DATA]], align 4
133+
// CHECK-NEXT: [[TMP105:%.*]] = call i32 @llvm.riscv.esp.macs16x2.ld(i32 [[TMP102]], i32 [[TMP103]], i32 [[TMP104]])
134+
// CHECK-NEXT: [[TMP106:%.*]] = load i32, ptr [[DATA]], align 4
135+
// CHECK-NEXT: [[TMP107:%.*]] = load i32, ptr [[DATA]], align 4
136+
// CHECK-NEXT: [[TMP108:%.*]] = load i32, ptr [[DATA]], align 4
137+
// CHECK-NEXT: [[TMP109:%.*]] = call i32 @llvm.riscv.esp.macs16x1.ld(i32 [[TMP106]], i32 [[TMP107]], i32 [[TMP108]])
138+
// CHECK-NEXT: [[TMP110:%.*]] = load i32, ptr [[DATA]], align 4
139+
// CHECK-NEXT: [[TMP111:%.*]] = load i32, ptr [[DATA]], align 4
140+
// CHECK-NEXT: [[TMP112:%.*]] = load i32, ptr [[DATA]], align 4
141+
// CHECK-NEXT: [[TMP113:%.*]] = load i32, ptr [[DATA]], align 4
142+
// CHECK-NEXT: call void @llvm.riscv.esp.macs16x2.st(i32 [[TMP110]], i32 [[TMP111]], i32 [[TMP112]], i32 [[TMP113]])
143+
// CHECK-NEXT: [[TMP114:%.*]] = load i32, ptr [[DATA]], align 4
144+
// CHECK-NEXT: [[TMP115:%.*]] = load i32, ptr [[DATA]], align 4
145+
// CHECK-NEXT: call void @llvm.riscv.esp.msus32i(i32 [[TMP114]], i32 [[TMP115]], i32 3)
146+
// CHECK-NEXT: [[TMP116:%.*]] = load i32, ptr [[DATA]], align 4
147+
// CHECK-NEXT: [[TMP117:%.*]] = load i32, ptr [[DATA]], align 4
148+
// CHECK-NEXT: call void @llvm.riscv.esp.msus32(i32 [[TMP116]], i32 [[TMP117]])
149+
// CHECK-NEXT: [[TMP118:%.*]] = load i32, ptr [[DATA]], align 4
150+
// CHECK-NEXT: [[TMP119:%.*]] = load i32, ptr [[DATA]], align 4
151+
// CHECK-NEXT: [[TMP120:%.*]] = load i32, ptr [[DATA]], align 4
152+
// CHECK-NEXT: [[TMP121:%.*]] = call i32 @llvm.riscv.esp.msus32.ld(i32 [[TMP118]], i32 [[TMP119]], i32 [[TMP120]])
153+
// CHECK-NEXT: [[TMP122:%.*]] = load i32, ptr [[DATA]], align 4
154+
// CHECK-NEXT: [[TMP123:%.*]] = load i32, ptr [[DATA]], align 4
155+
// CHECK-NEXT: [[TMP124:%.*]] = load i32, ptr [[DATA]], align 4
156+
// CHECK-NEXT: [[TMP125:%.*]] = load i32, ptr [[DATA]], align 4
157+
// CHECK-NEXT: call void @llvm.riscv.esp.msus32.st(i32 [[TMP122]], i32 [[TMP123]], i32 [[TMP124]], i32 [[TMP125]])
158+
// CHECK-NEXT: [[TMP126:%.*]] = load i32, ptr [[DATA]], align 4
159+
// CHECK-NEXT: [[TMP127:%.*]] = load i32, ptr [[DATA]], align 4
160+
// CHECK-NEXT: call void @llvm.riscv.esp.msus16ix2(i32 [[TMP126]], i32 [[TMP127]], i32 23)
161+
// CHECK-NEXT: [[TMP128:%.*]] = load i32, ptr [[DATA]], align 4
162+
// CHECK-NEXT: [[TMP129:%.*]] = load i32, ptr [[DATA]], align 4
163+
// CHECK-NEXT: call void @llvm.riscv.esp.msus16x2(i32 [[TMP128]], i32 [[TMP129]])
164+
// CHECK-NEXT: [[TMP130:%.*]] = load i32, ptr [[DATA]], align 4
165+
// CHECK-NEXT: [[TMP131:%.*]] = load i32, ptr [[DATA]], align 4
166+
// CHECK-NEXT: [[TMP132:%.*]] = load i32, ptr [[DATA]], align 4
167+
// CHECK-NEXT: [[TMP133:%.*]] = call i32 @llvm.riscv.esp.msus16x2.ld(i32 [[TMP130]], i32 [[TMP131]], i32 [[TMP132]])
168+
// CHECK-NEXT: [[TMP134:%.*]] = load i32, ptr [[DATA]], align 4
169+
// CHECK-NEXT: [[TMP135:%.*]] = load i32, ptr [[DATA]], align 4
170+
// CHECK-NEXT: [[TMP136:%.*]] = load i32, ptr [[DATA]], align 4
171+
// CHECK-NEXT: [[TMP137:%.*]] = call i32 @llvm.riscv.esp.msus16x1.ld(i32 [[TMP134]], i32 [[TMP135]], i32 [[TMP136]])
172+
// CHECK-NEXT: [[TMP138:%.*]] = load i32, ptr [[DATA]], align 4
173+
// CHECK-NEXT: [[TMP139:%.*]] = load i32, ptr [[DATA]], align 4
174+
// CHECK-NEXT: [[TMP140:%.*]] = load i32, ptr [[DATA]], align 4
175+
// CHECK-NEXT: [[TMP141:%.*]] = load i32, ptr [[DATA]], align 4
176+
// CHECK-NEXT: call void @llvm.riscv.esp.msus16x2.st(i32 [[TMP138]], i32 [[TMP139]], i32 [[TMP140]], i32 [[TMP141]])
177+
// CHECK-NEXT: ret void
178+
//
179+
void test() {
180+
uint32_t data = 10;
181+
__builtin_riscv_esp_muls16ix2(data, data, 29, data, data);
182+
__builtin_riscv_esp_muls16x2(data, data, data, data);
183+
__builtin_riscv_esp_muls32i(data, data, 3);
184+
__builtin_riscv_esp_muls32(data, data);
185+
__builtin_riscv_esp_shl(data, data);
186+
__builtin_riscv_esp_shr(data, data);
187+
__builtin_riscv_esp_abs(data);
188+
__builtin_riscv_esp_movr_xacc(data);
189+
__builtin_riscv_esp_min(data, data);
190+
__builtin_riscv_esp_max(data, data);
191+
__builtin_riscv_esp_clzs(data);
192+
__builtin_riscv_esp_flw_ip(data, -5, 2);
193+
__builtin_riscv_esp_flw_xp(data, data);
194+
__builtin_riscv_esp_fsw_ip(data, data, 4, 3);
195+
__builtin_riscv_esp_fsw_xp(data, data, data);
196+
__builtin_riscv_esp_lw_ip(data, -8, 1);
197+
__builtin_riscv_esp_lw_xp(data, data);
198+
__builtin_riscv_esp_sw_ip(data, data, -10, 0);
199+
__builtin_riscv_esp_sw_xp(data, data, data);
200+
__builtin_riscv_esp_lh_ip(data, 3, 1);
201+
__builtin_riscv_esp_lh_xp(data, data);
202+
__builtin_riscv_esp_sh_ip(data, data, 14, 0);
203+
__builtin_riscv_esp_sh_xp(data, data, data);
204+
__builtin_riscv_esp_lb_ip(data, 11, 0);
205+
__builtin_riscv_esp_lb_xp(data, data);
206+
__builtin_riscv_esp_sb_ip(data, data, 7, 2);
207+
__builtin_riscv_esp_sb_xp(data, data, data);
208+
__builtin_riscv_esp_lhu_ip(data, -12, 2);
209+
__builtin_riscv_esp_lhu_xp(data, data);
210+
__builtin_riscv_esp_lbu_ip(data, 12, 2);
211+
__builtin_riscv_esp_lbu_xp(data, data);
212+
__builtin_riscv_esp_movw_xacc(data, data);
213+
__builtin_riscv_esp_macs32i(data, data, 18);
214+
__builtin_riscv_esp_macs32(data, data);
215+
__builtin_riscv_esp_macs32_ld(data, data, data);
216+
__builtin_riscv_esp_macs32_st(data, data, data, data);
217+
__builtin_riscv_esp_macs16ix2(data, data, 25);
218+
__builtin_riscv_esp_macs16x2(data, data);
219+
__builtin_riscv_esp_macs16x2_ld(data, data, data);
220+
__builtin_riscv_esp_macs16x1_ld(data, data, data);
221+
__builtin_riscv_esp_macs16x2_st(data, data, data, data);
222+
__builtin_riscv_esp_msus32i(data, data, 3);
223+
__builtin_riscv_esp_msus32(data, data);
224+
__builtin_riscv_esp_msus32_ld(data, data, data);
225+
__builtin_riscv_esp_msus32_st(data, data, data, data);
226+
__builtin_riscv_esp_msus16ix2(data, data, 23);
227+
__builtin_riscv_esp_msus16x2(data, data);
228+
__builtin_riscv_esp_msus16x2_ld(data, data, data);
229+
__builtin_riscv_esp_msus16x1_ld(data, data, data);
230+
__builtin_riscv_esp_msus16x2_st(data, data, data, data);
231+
}

0 commit comments

Comments
 (0)