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[AMDGPU] Use register pair for PC spill (llvm#183146)
Change-Id: Ibedeef926f7ff235a06de65a83087c151f66a416
1 parent 3a203a5 commit 57b485f

95 files changed

Lines changed: 18153 additions & 18044 deletions

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‎llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp‎

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -285,11 +285,20 @@ bool SILowerSGPRSpills::spillCalleeSavedRegs(
285285

286286
std::vector<CalleeSavedInfo> CSI;
287287
const MCPhysReg *CSRegs = MRI.getCalleeSavedRegs();
288+
MCRegister RetAddrReg = TRI->getReturnAddressReg(MF);
289+
MCRegister RetAddrRegSub0 = TRI->getSubReg(RetAddrReg, AMDGPU::sub0);
290+
MCRegister RetAddrRegSub1 = TRI->getSubReg(RetAddrReg, AMDGPU::sub1);
291+
bool SpillRetAddrReg = false;
288292

289293
for (unsigned I = 0; CSRegs[I]; ++I) {
290294
MCRegister Reg = CSRegs[I];
291295

292296
if (SavedRegs.test(Reg)) {
297+
if (Reg == RetAddrRegSub0 || Reg == RetAddrRegSub1) {
298+
SpillRetAddrReg = true;
299+
continue;
300+
}
301+
293302
const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
294303
int JunkFI = MFI.CreateStackObject(TRI->getSpillSize(*RC),
295304
TRI->getSpillAlign(*RC), true);
@@ -299,6 +308,18 @@ bool SILowerSGPRSpills::spillCalleeSavedRegs(
299308
}
300309
}
301310

311+
// Return address uses a register pair. Add the super register to the
312+
// CSI list so that it's easier to identify the entire spill and CFI
313+
// can be emitted appropriately.
314+
if (SpillRetAddrReg) {
315+
const TargetRegisterClass *RC =
316+
TRI->getMinimalPhysRegClass(RetAddrReg, MVT::i64);
317+
int JunkFI = MFI.CreateStackObject(TRI->getSpillSize(*RC),
318+
TRI->getSpillAlign(*RC), true);
319+
CSI.push_back(CalleeSavedInfo(RetAddrReg, JunkFI));
320+
CalleeSavedFIs.push_back(JunkFI);
321+
}
322+
302323
if (!CSI.empty()) {
303324
for (MachineBasicBlock *SaveBlock : SaveBlocks)
304325
insertCSRSaves(*SaveBlock, CSI, Indexes, LIS);

‎llvm/test/CodeGen/AMDGPU/GlobalISel/assert-align.ll‎

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33

44
declare hidden ptr addrspace(1) @ext(ptr addrspace(1))
55

6-
define ptr addrspace(1) @call_assert_align() {
6+
define ptr addrspace(1) @call_assert_align() #0 {
77
; CHECK-LABEL: call_assert_align:
88
; CHECK: ; %bb.0: ; %entry
99
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -23,10 +23,10 @@ define ptr addrspace(1) @call_assert_align() {
2323
; CHECK-NEXT: v_writelane_b32 v40, s31, 1
2424
; CHECK-NEXT: s_swappc_b64 s[30:31], s[16:17]
2525
; CHECK-NEXT: v_mov_b32_e32 v2, 0
26+
; CHECK-NEXT: v_readlane_b32 s30, v40, 0
2627
; CHECK-NEXT: global_store_dword v[0:1], v2, off
2728
; CHECK-NEXT: s_waitcnt vmcnt(0)
2829
; CHECK-NEXT: v_readlane_b32 s31, v40, 1
29-
; CHECK-NEXT: v_readlane_b32 s30, v40, 0
3030
; CHECK-NEXT: s_mov_b32 s32, s33
3131
; CHECK-NEXT: v_readlane_b32 s4, v40, 2
3232
; CHECK-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -41,7 +41,7 @@ entry:
4141
ret ptr addrspace(1) %call
4242
}
4343

44-
define ptr addrspace(1) @tail_call_assert_align() {
44+
define ptr addrspace(1) @tail_call_assert_align() #0 {
4545
; CHECK-LABEL: tail_call_assert_align:
4646
; CHECK: ; %bb.0: ; %entry
4747
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -55,3 +55,5 @@ entry:
5555
%call = tail call align 4 ptr addrspace(1) @ext(ptr addrspace(1) null)
5656
ret ptr addrspace(1) %call
5757
}
58+
59+
attributes #0 = { nounwind }

‎llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -238,8 +238,8 @@ define void @func_caller_stack() #2 {
238238
; MUBUF-NEXT: v_writelane_b32 v40, s31, 1
239239
; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:16
240240
; MUBUF-NEXT: s_swappc_b64 s[30:31], s[4:5]
241-
; MUBUF-NEXT: v_readlane_b32 s31, v40, 1
242241
; MUBUF-NEXT: v_readlane_b32 s30, v40, 0
242+
; MUBUF-NEXT: v_readlane_b32 s31, v40, 1
243243
; MUBUF-NEXT: s_mov_b32 s32, s33
244244
; MUBUF-NEXT: v_readlane_b32 s4, v40, 2
245245
; MUBUF-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -277,8 +277,8 @@ define void @func_caller_stack() #2 {
277277
; FLATSCR-NEXT: s_addc_u32 s1, s1, external_void_func_v16i32_v16i32_v4i32@rel32@hi+12
278278
; FLATSCR-NEXT: v_writelane_b32 v40, s31, 1
279279
; FLATSCR-NEXT: s_swappc_b64 s[30:31], s[0:1]
280-
; FLATSCR-NEXT: v_readlane_b32 s31, v40, 1
281280
; FLATSCR-NEXT: v_readlane_b32 s30, v40, 0
281+
; FLATSCR-NEXT: v_readlane_b32 s31, v40, 1
282282
; FLATSCR-NEXT: s_mov_b32 s32, s33
283283
; FLATSCR-NEXT: v_readlane_b32 s0, v40, 2
284284
; FLATSCR-NEXT: s_or_saveexec_b64 s[2:3], -1
@@ -363,8 +363,8 @@ define void @func_caller_byval(ptr addrspace(5) %argptr) #2 {
363363
; MUBUF-NEXT: s_waitcnt vmcnt(1)
364364
; MUBUF-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:60
365365
; MUBUF-NEXT: s_swappc_b64 s[30:31], s[4:5]
366-
; MUBUF-NEXT: v_readlane_b32 s31, v40, 1
367366
; MUBUF-NEXT: v_readlane_b32 s30, v40, 0
367+
; MUBUF-NEXT: v_readlane_b32 s31, v40, 1
368368
; MUBUF-NEXT: s_mov_b32 s32, s33
369369
; MUBUF-NEXT: v_readlane_b32 s4, v40, 2
370370
; MUBUF-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -414,8 +414,8 @@ define void @func_caller_byval(ptr addrspace(5) %argptr) #2 {
414414
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
415415
; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], s32 offset:56
416416
; FLATSCR-NEXT: s_swappc_b64 s[30:31], s[0:1]
417-
; FLATSCR-NEXT: v_readlane_b32 s31, v40, 1
418417
; FLATSCR-NEXT: v_readlane_b32 s30, v40, 0
418+
; FLATSCR-NEXT: v_readlane_b32 s31, v40, 1
419419
; FLATSCR-NEXT: s_mov_b32 s32, s33
420420
; FLATSCR-NEXT: v_readlane_b32 s0, v40, 2
421421
; FLATSCR-NEXT: s_or_saveexec_b64 s[2:3], -1

‎llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -245,8 +245,8 @@ define void @sink_null_insert_pt(ptr addrspace(4) %arg0) #0 {
245245
; GFX9-NEXT: s_addk_i32 s32, 0x400
246246
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
247247
; GFX9-NEXT: s_swappc_b64 s[30:31], 0
248-
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
249248
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
249+
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
250250
; GFX9-NEXT: s_mov_b32 s32, s33
251251
; GFX9-NEXT: v_readlane_b32 s4, v40, 2
252252
; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1

‎llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -30,8 +30,8 @@ define void @parent_func_missing_inputs() #0 {
3030
; FIXEDABI-NEXT: s_addc_u32 s17, s17, requires_all_inputs@rel32@hi+12
3131
; FIXEDABI-NEXT: v_writelane_b32 v40, s31, 1
3232
; FIXEDABI-NEXT: s_swappc_b64 s[30:31], s[16:17]
33-
; FIXEDABI-NEXT: v_readlane_b32 s31, v40, 1
3433
; FIXEDABI-NEXT: v_readlane_b32 s30, v40, 0
34+
; FIXEDABI-NEXT: v_readlane_b32 s31, v40, 1
3535
; FIXEDABI-NEXT: s_mov_b32 s32, s33
3636
; FIXEDABI-NEXT: v_readlane_b32 s4, v40, 2
3737
; FIXEDABI-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -416,5 +416,5 @@ declare i1 @llvm.amdgcn.is.private(ptr)
416416
declare void @llvm.trap()
417417
declare void @llvm.debugtrap()
418418

419-
attributes #0 = { "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-queue-ptr" "amdgpu-no-work-group-id-x" "amdgpu-no-work-group-id-y" "amdgpu-no-work-group-id-z" "amdgpu-no-work-item-id-x" "amdgpu-no-work-item-id-y" "amdgpu-no-work-item-id-z" }
419+
attributes #0 = { "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-queue-ptr" "amdgpu-no-work-group-id-x" "amdgpu-no-work-group-id-y" "amdgpu-no-work-group-id-z" "amdgpu-no-work-item-id-x" "amdgpu-no-work-item-id-y" "amdgpu-no-work-item-id-z" nounwind }
420420

‎llvm/test/CodeGen/AMDGPU/amdgcn-call-whole-wave.ll‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -35,8 +35,8 @@ define amdgpu_gfx void @basic_test(i32 %x, i32 inreg %c, ptr addrspace(1) %ptr)
3535
; DAGISEL-NEXT: s_clause 0x1 ; 8-byte Folded Reload
3636
; DAGISEL-NEXT: scratch_load_b32 v41, off, s33
3737
; DAGISEL-NEXT: scratch_load_b32 v40, off, s33 offset:4
38-
; DAGISEL-NEXT: v_readlane_b32 s31, v42, 1
3938
; DAGISEL-NEXT: v_readlane_b32 s30, v42, 0
39+
; DAGISEL-NEXT: v_readlane_b32 s31, v42, 1
4040
; DAGISEL-NEXT: s_mov_b32 s32, s33
4141
; DAGISEL-NEXT: v_readlane_b32 s0, v42, 2
4242
; DAGISEL-NEXT: s_or_saveexec_b32 s1, -1
@@ -78,8 +78,8 @@ define amdgpu_gfx void @basic_test(i32 %x, i32 inreg %c, ptr addrspace(1) %ptr)
7878
; GISEL-NEXT: s_clause 0x1 ; 8-byte Folded Reload
7979
; GISEL-NEXT: scratch_load_b32 v41, off, s33
8080
; GISEL-NEXT: scratch_load_b32 v40, off, s33 offset:4
81-
; GISEL-NEXT: v_readlane_b32 s31, v42, 1
8281
; GISEL-NEXT: v_readlane_b32 s30, v42, 0
82+
; GISEL-NEXT: v_readlane_b32 s31, v42, 1
8383
; GISEL-NEXT: s_mov_b32 s32, s33
8484
; GISEL-NEXT: v_readlane_b32 s0, v42, 2
8585
; GISEL-NEXT: s_or_saveexec_b32 s1, -1
@@ -787,8 +787,8 @@ define amdgpu_gfx void @ret_void(i32 %x) #0 {
787787
; DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
788788
; DAGISEL-NEXT: s_swappc_b64 s[30:31], s[0:1]
789789
; DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
790-
; DAGISEL-NEXT: v_readlane_b32 s31, v40, 1
791790
; DAGISEL-NEXT: v_readlane_b32 s30, v40, 0
791+
; DAGISEL-NEXT: v_readlane_b32 s31, v40, 1
792792
; DAGISEL-NEXT: s_mov_b32 s32, s33
793793
; DAGISEL-NEXT: v_readlane_b32 s0, v40, 2
794794
; DAGISEL-NEXT: s_or_saveexec_b32 s1, -1
@@ -822,8 +822,8 @@ define amdgpu_gfx void @ret_void(i32 %x) #0 {
822822
; GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
823823
; GISEL-NEXT: s_swappc_b64 s[30:31], s[0:1]
824824
; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
825-
; GISEL-NEXT: v_readlane_b32 s31, v40, 1
826825
; GISEL-NEXT: v_readlane_b32 s30, v40, 0
826+
; GISEL-NEXT: v_readlane_b32 s31, v40, 1
827827
; GISEL-NEXT: s_mov_b32 s32, s33
828828
; GISEL-NEXT: v_readlane_b32 s0, v40, 2
829829
; GISEL-NEXT: s_or_saveexec_b32 s1, -1

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