Improve support for esp32s3's 128-bit QR registers in inline asm

[vxpm]

Checklist

• Checked the issue tracker for similar issues to ensure this is not a duplicate.
• Described the feature in detail and justified the reason for the request.
• Provided specific use cases and examples.

Feature description

Improve the support for esp32s3's 128-bit QR vector register class in inline assembly. Currently, they're very limited - see esp-rs/rust#265.

Use cases

Writing performant SIMD code while leaving register allocation to the compiler. The esp32s3 has an extended instruction set with a bunch of useful vector instructions that currently don't seem to get generated at all by LLVM. Plus, they are only partially supported in inline assembly since you need to manually load specific QR registers with the data you want to manipulate every time.

Alternatives

1. Keep using inline assembly as it is.
2. Add vectorization support for these instructions. It seems like even emitting clearly vectorized LLVM IR does not result in LLVM generating them (see Expose SIMD registers as a possible register class in asm macros esp-rs/rust#265 (comment)).

Additional context

I'm using rustc. I've tried implementing these changes myself - I, however, am not knowledgeable in LLVM and could only take it so far. My efforts can be seen in the following forks:

• https://github.com/vxpm/llvm-project-espressif
• https://github.com/vxpm/rust-xtensa