feature(dcd_dwc): Proceed implment cache synchronization

Author: roma-jam

src/portable/synopsys/dwc2/dcd_dwc2.c

@@ -79,10 +79,7 @@ TU_ATTR_ALWAYS_INLINE static inline dwc2_regs_t* DWC2_REG(uint8_t rhport) {
 // MACRO TYPEDEF CONSTANT ENUM
 //--------------------------------------------------------------------+
 
-#include "esp_attr.h"
-
-// static CFG_TUD_MEM_SECTION TU_ATTR_ALIGNED(4) uint32_t _setup_packet[2];
-static DRAM_DMA_ALIGNED_ATTR TU_ATTR_ALIGNED(4) uint32_t _setup_packet[2];
+static CFG_TUD_MEM_SECTION TU_ATTR_ALIGNED(4) uint32_t _setup_packet[2];
 
 typedef struct {
   uint8_t* buffer;
@@ -510,7 +507,9 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c
 
     if(dma_enabled(dwc2)) {
       dep->doepdma = (uintptr_t)xfer->buffer;
-      // dwc2_dcd_sync_cache_to_memory(xfer->buffer, total_bytes);
+      if (total_bytes != 0) {
+        dwc2_dcd_sync_cache_to_memory(xfer->buffer, total_bytes);
+      }
     }
 
     dep->doepctl |= DOEPCTL_EPENA | DOEPCTL_CNAK;
@@ -1083,7 +1082,9 @@ static void handle_epout_irq(uint8_t rhport) {
               if(epnum == 0 && xfer->total_len == 0) {
                 dma_setup_prepare(rhport);
               }
-
+              if (xfer->total_len) {
+                dwc2_dcd_sync_memory_to_cache(xfer->buffer, xfer->total_len);
+              }
               dcd_event_xfer_complete(rhport, epnum, xfer->total_len, XFER_RESULT_SUCCESS, true);
             }
           } else {

src/portable/synopsys/dwc2/dwc2_esp32.h

@@ -41,6 +41,7 @@
 
 #if TU_CHECK_MCU(OPT_MCU_ESP32P4)
 #if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
+#include "sdkconfig.h"
 #include "hal/cache_hal.h"
 #include "esp_cache.h"
 #define DWC2_ENABLE_MEM_CACHE         1
@@ -106,7 +107,7 @@ TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_update(dwc2_regs_t* dwc2, uint
 // MCU specific cache synchronization call
 TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcd_sync_cache_to_memory(void *addr, size_t size) {
 #if DWC2_ENABLE_MEM_CACHE
-  ESP_EARLY_LOGW("dwc2_esp32", "cache to mem sync, addr 0x%"PRIx32", size %d", (uintptr_t)addr, size);
+  ESP_EARLY_LOGV("dwc2_esp32", "cache to mem sync, addr 0x%"PRIx32", size %d", (uintptr_t)addr, size);
   int flags = ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_UNALIGNED;
   esp_err_t ret = esp_cache_msync(addr, size, flags);
   assert(ret == ESP_OK);
@@ -120,8 +121,9 @@ TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcd_sync_cache_to_memory(void *add
 TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcd_sync_memory_to_cache(void *addr, size_t size) {
 #if DWC2_ENABLE_MEM_CACHE
   int flags = ESP_CACHE_MSYNC_FLAG_DIR_M2C;
-  size = (size < 0x40)? 0x40 : size;
-  ESP_EARLY_LOGW("dwc2", "mem to cache sync, addr 0x%"PRIx32", size %d", (uintptr_t)addr, size);
+  ESP_EARLY_LOGV("dwc2", "mem to cache sync, addr 0x%"PRIx32", size %d", (uintptr_t)addr, size);
+  // TODO: size should be multiply of CONFIG_CACHE_L1_CACHE_LINE_SIZE?
+  size = (size < CONFIG_CACHE_L1_CACHE_LINE_SIZE)? CONFIG_CACHE_L1_CACHE_LINE_SIZE : size;
   esp_err_t ret = esp_cache_msync(addr, size, flags);
   assert(ret == ESP_OK);
 #else

src/tusb_option.h

@@ -250,7 +250,7 @@
 // For example, on Cortex-M7 the MPU region can be configured as normal
 // non-cacheable, with RASR register value: TEX=1 C=0 B=0 S=0.
 #ifndef CFG_TUD_DWC2_DMA
-  #define CFG_TUD_DWC2_DMA 1
+  #define CFG_TUD_DWC2_DMA 0
 #endif
 
 // Enable PIO-USB software host controller