change(dcd_dwc2): Small refactoring

Author: roma-jam

src/portable/synopsys/dwc2/dcd_dwc2.c

@@ -79,6 +79,7 @@ TU_ATTR_ALWAYS_INLINE static inline dwc2_regs_t* DWC2_REG(uint8_t rhport) {
 // MACRO TYPEDEF CONSTANT ENUM
 //--------------------------------------------------------------------+
 #if DWC2_ENABLE_MEM_CACHE
+
 #ifndef DWC2_MEM_CACHE_LINE_SIZE
 #warning "Cache line size not specified, use default(64b) instead"
 #    define DWC2_MEM_CACHE_LINE_SIZE 0x40
@@ -91,11 +92,11 @@ CFG_TUD_MEM_SECTION struct {
   };
 } _cache_aligned_setup_packet;
 
-#define _setup_packet          _cache_aligned_setup_packet.data
-#define _sizeof_setup_packet() DWC2_MEM_CACHE_LINE_SIZE
+#define _setup_packet                         _cache_aligned_setup_packet.data
+#define _sizeof_setup_packet()                DWC2_MEM_CACHE_LINE_SIZE
 #else
 static CFG_TUD_MEM_SECTION TU_ATTR_ALIGNED(4) uint32_t _setup_packet[2];
-#define _sizeof_setup_packet() sizeof(_setup_packet)
+#define _sizeof_setup_packet()                sizeof(_setup_packet)
 #endif // DWC2_ENABLE_MEM_CACHE
 
 typedef struct {

src/portable/synopsys/dwc2/dwc2_esp32.h

@@ -45,7 +45,7 @@
 #include "hal/cache_hal.h"
 #include "esp_cache.h"
 #include "esp_log.h"
-#define DWC2_ENABLE_MEM_CACHE         1
+#define DWC2_ENABLE_MEM_CACHE               1
 #endif // SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
 #endif // OPT_MCU_ESP32P4