add CFG_TUD_MEM_DCACHE_ENABLE, CFG_TUD_MEM_DCACHE_LINE_SIZE option

Author: hathach

src/common/tusb_mcu.h

@@ -361,6 +361,18 @@
   #define TUP_USBIP_DWC2_ESP32
   #define TUP_RHPORT_HIGHSPEED    1  // port0 FS, port1 HS
   #define TUP_DCD_ENDPOINT_MAX    16 // FS 7 ep, HS 16 ep
+
+  #if defined(CFG_TUD_DWC2_DMA_ENABLE) && CFG_TUD_DWC2_DMA_ENABLE == 1
+  #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT  1
+  #endif
+
+  #if defined(CFG_TUH_DWC2_DMA_ENABLE) && CFG_TUH_DWC2_DMA_ENABLE == 1
+  #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT 1
+  #endif
+
+  #define CFG_TUD_MEM_DCACHE_LINE_SIZE  64
+  #define CFG_TUH_MEM_DCACHE_LINE_SIZE  64
+
   #define CFG_TUH_DWC2_DMA_ENABLE_DEFAULT  0 // TODO currently have issue with buffer DMA with espressif
 
 #elif TU_CHECK_MCU(OPT_MCU_ESP32, OPT_MCU_ESP32C2, OPT_MCU_ESP32C3, OPT_MCU_ESP32C6, OPT_MCU_ESP32H2)

src/portable/synopsys/dwc2/dcd_dwc2.c

@@ -72,7 +72,7 @@ static bool _sof_en;
 //--------------------------------------------------------------------
 // DMA
 //--------------------------------------------------------------------
-#if DWC2_ENABLE_MEM_CACHE
+#if CFG_TUD_MEM_DCACHE_ENABLE
 void dcd_dcache_clean(const void* addr, uint32_t data_size) {
   if (addr && data_size) {
     dwc2_dcache_clean(addr, data_size);

src/portable/synopsys/dwc2/dwc2_esp32.h

@@ -114,14 +114,15 @@ TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_update(dwc2_regs_t* dwc2, uint
 //--------------------------------------------------------------------+
 // Data Cache
 //--------------------------------------------------------------------+
+#if CFG_TUD_DWC2_DMA_ENABLE || CFG_TUH_DWC2_DMA_ENABLE
 #if defined(SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE) && SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
-#include "sdkconfig.h"
 #include "hal/cache_hal.h"
 #include "esp_cache.h"
-#include "esp_log.h"
 
-#define DWC2_MEM_CACHE_LINE_SIZE    CONFIG_CACHE_L1_CACHE_LINE_SIZE
-#define DWC2_ENABLE_MEM_CACHE 1
+#if CFG_TUD_MEM_DCACHE_LINE_SIZE != CONFIG_CACHE_L1_CACHE_LINE_SIZE || \
+    CFG_TUH_MEM_DCACHE_LINE_SIZE != CONFIG_CACHE_L1_CACHE_LINE_SIZE
+#error "CFG_TUD/TUH_MEM_DCACHE_LINE_SIZE must match CONFIG_CACHE_L1_CACHE_LINE_SIZE"
+#endif
 
 TU_ATTR_ALWAYS_INLINE static inline uint32_t round_up_to_cache_line_size(uint32_t size) {
   if (size & (CONFIG_CACHE_L1_CACHE_LINE_SIZE-1)) {
@@ -131,29 +132,25 @@ TU_ATTR_ALWAYS_INLINE static inline uint32_t round_up_to_cache_line_size(uint32_
 }
 
 TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcache_clean(const void* addr, uint32_t data_size) {
-  // round up to cache line size
   const int flag = ESP_CACHE_MSYNC_FLAG_TYPE_DATA | ESP_CACHE_MSYNC_FLAG_DIR_C2M;
   data_size = round_up_to_cache_line_size(data_size);
-  //ESP_EARLY_LOGI("ESP32_DWC", "dcache clean, addr 0x%"PRIx32", size %d (%s)", (uintptr_t)addr, data_size);
   assert(ESP_OK == esp_cache_msync((void*)addr, data_size, flag));
 }
 
 TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcache_invalidate(const void* addr, uint32_t data_size) {
   const int flag = ESP_CACHE_MSYNC_FLAG_TYPE_DATA | ESP_CACHE_MSYNC_FLAG_DIR_M2C;
   data_size = round_up_to_cache_line_size(data_size);
-  //ESP_EARLY_LOGI("ESP32_DWC", "dcache invalidate, addr 0x%"PRIx32", size %d (%s)", (uintptr_t)addr, data_size);
   assert(ESP_OK == esp_cache_msync((void*)addr, data_size, flag));
 }
 
 TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcache_clean_invalidate(const void* addr, uint32_t data_size) {
   const int flag = ESP_CACHE_MSYNC_FLAG_TYPE_DATA | ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_DIR_M2C;
   data_size = round_up_to_cache_line_size(data_size);
-  //ESP_EARLY_LOGI("ESP32_DWC", "dcache clean_invalidate, addr 0x%"PRIx32", size %d (%s)", (uintptr_t)addr, data_size);
   assert(ESP_OK == esp_cache_msync((void*)addr, data_size, flag));
 }
 
-#endif // SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
-
+#endif
+#endif
 
 #ifdef __cplusplus
 }

src/tusb_option.h

@@ -266,6 +266,7 @@
   #ifndef CFG_TUH_DWC2_SLAVE_ENABLE_DEFAULT
   #define CFG_TUH_DWC2_SLAVE_ENABLE_DEFAULT 1
   #endif
+
   #define CFG_TUH_DWC2_SLAVE_ENABLE CFG_TUH_DWC2_SLAVE_ENABLE_DEFAULT
 #endif
 
@@ -274,6 +275,7 @@
   #ifndef CFG_TUH_DWC2_DMA_ENABLE_DEFAULT
   #define CFG_TUH_DWC2_DMA_ENABLE_DEFAULT 1
   #endif
+
   #define CFG_TUH_DWC2_DMA_ENABLE   CFG_TUH_DWC2_DMA_ENABLE_DEFAULT
 #endif
 
@@ -422,6 +424,18 @@
   #define CFG_TUD_MEM_ALIGN       CFG_TUSB_MEM_ALIGN
 #endif
 
+#ifndef CFG_TUD_MEM_DCACHE_ENABLE
+  #ifndef CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT
+  #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT  0
+  #endif
+
+  #define CFG_TUD_MEM_DCACHE_ENABLE   CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT
+#endif
+
+#ifndef CFG_TUD_MEM_DCACHE_LINE_SIZE
+  #define CFG_TUD_MEM_DCACHE_LINE_SIZE 32
+#endif
+
 #ifndef CFG_TUD_ENDPOINT0_SIZE
   #define CFG_TUD_ENDPOINT0_SIZE  64
 #endif