feature(dcd_dwc2): Covered _setup_packet with alignment, added cache hints comments

Author: roma-jam

src/portable/synopsys/dwc2/dcd_dwc2.c

@@ -78,8 +78,25 @@ TU_ATTR_ALWAYS_INLINE static inline dwc2_regs_t* DWC2_REG(uint8_t rhport) {
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM
 //--------------------------------------------------------------------+
-
+#if DWC2_ENABLE_MEM_CACHE
+#ifndef DWC2_MEM_CACHE_LINE_SIZE
+#warning "Cache line size not specified, use default(64b) instead"
+#    define DWC2_MEM_CACHE_LINE_SIZE 0x40
+#endif // DWC2_MEM_CACHE_LINE_SIZE
+
+CFG_TUD_MEM_SECTION struct {
+  union {
+    uint32_t data[2];
+    uint8_t buffer[DWC2_MEM_CACHE_LINE_SIZE];
+  };
+} _cache_aligned_setup_packet;
+
+#define _setup_packet          _cache_aligned_setup_packet.data
+#define _sizeof_setup_packet() DWC2_MEM_CACHE_LINE_SIZE
+#else
 static CFG_TUD_MEM_SECTION TU_ATTR_ALIGNED(4) uint32_t _setup_packet[2];
+#define _sizeof_setup_packet() sizeof(_setup_packet)
+#endif // DWC2_ENABLE_MEM_CACHE
 
 typedef struct {
   uint8_t* buffer;
@@ -477,6 +494,8 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c
 
     if(dma_enabled(dwc2)) {
       dep->diepdma = (uintptr_t)xfer->buffer;
+      // CACHE HINT
+      // The xfer->buffer has new data, move it to memory for DMA transfer it
       dsync_c2m(xfer->buffer, total_bytes);
       // For ISO endpoint set correct odd/even bit for next frame.
       if ((dep->diepctl & DIEPCTL_EPTYP) == DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1) {
@@ -1057,7 +1076,11 @@ static void handle_epout_irq(uint8_t rhport) {
 
         if(dma_enabled(dwc2)) {
           dma_setup_prepare(rhport);
-          dsync_m2c((uint8_t*) _setup_packet, sizeof(_setup_packet));
+          // CACHE HINT
+          // When cache is enabled, _setup_packet must have cache line size alignment
+          // and there should be no valuable data in memory after.
+          // Thus, specific struct is used as a buffer for setup packet data
+          dsync_m2c((uint8_t*) _setup_packet, _sizeof_setup_packet());
         }
 
         dcd_event_setup_received(rhport, (uint8_t*) _setup_packet, true);
@@ -1084,6 +1107,8 @@ static void handle_epout_irq(uint8_t rhport) {
               if(epnum == 0 && xfer->total_len == 0) {
                 dma_setup_prepare(rhport);
               }
+              // CACHE HINT
+              // Some data has been received by DMA, fetch the data from memory to cache
               dsync_m2c(xfer->buffer, xfer->total_len);
               dcd_event_xfer_complete(rhport, epnum, xfer->total_len, XFER_RESULT_SUCCESS, true);
             }

src/portable/synopsys/dwc2/dwc2_esp32.h

@@ -41,6 +41,7 @@
 
 #if TU_CHECK_MCU(OPT_MCU_ESP32P4)
 #if (CFG_TUD_DWC2_DMA && SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE)
+#include "sdkconfig.h"
 #include "hal/cache_hal.h"
 #include "esp_cache.h"
 #include "esp_log.h"
@@ -121,41 +122,36 @@ TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_update(dwc2_regs_t* dwc2, uint
   // maybe usb_utmi_hal_disable()
 }
 
+#if DWC2_ENABLE_MEM_CACHE
 // MCU specific cache synchronization call
 TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcd_sync_cache_to_memory(void *addr, size_t size) {
-#if DWC2_ENABLE_MEM_CACHE
-  ESP_EARLY_LOGV("dwc2_esp32", "cache to mem sync, addr 0x%"PRIx32", size %d", (uintptr_t)addr, size);
   int flags = ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_UNALIGNED;
   if (addr != NULL && size) {
+    ESP_EARLY_LOGV("dwc2_esp32", "cache to mem sync, addr 0x%"PRIx32", size %d", (uintptr_t)addr, size);
     esp_err_t ret = esp_cache_msync(addr, size, flags);
     assert(ret == ESP_OK);
   }
-#else
-  (void) addr;
-  (void) size;
-  // nothing to do
-#endif // DWC2_ENABLE_MEM_CACHE
 }
 
 TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcd_sync_memory_to_cache(void *addr, size_t size) {
-#if DWC2_ENABLE_MEM_CACHE
-  ESP_EARLY_LOGV("dwc2", "mem to cache sync, addr 0x%"PRIx32", size %d", (uintptr_t)addr, size);
   int flags = ESP_CACHE_MSYNC_FLAG_DIR_M2C;
   if (addr != NULL && size) {
+    ESP_EARLY_LOGV("dwc2", "mem to cache sync, addr 0x%"PRIx32", size %d (%s)",
+                              (uintptr_t)addr,
+                              size,
+                              (size % CONFIG_CACHE_L1_CACHE_LINE_SIZE)? "not aligned" : "aligned");
     // TODO: size should be multiply of CONFIG_CACHE_L1_CACHE_LINE_SIZE?
     size = (size < CONFIG_CACHE_L1_CACHE_LINE_SIZE)? CONFIG_CACHE_L1_CACHE_LINE_SIZE : size;
     esp_err_t ret = esp_cache_msync(addr, size, flags);
     assert(ret == ESP_OK);
   }
-#else
-  (void) addr;
-  (void) size;
-  // nothing to do
-#endif // DWC2_ENABLE_MEM_CACHE
 }
 
 #define dsync_c2m(_addr, _size)   dwc2_dcd_sync_cache_to_memory((_addr), (_size))
 #define dsync_m2c(_addr, _size)   dwc2_dcd_sync_memory_to_cache((_addr), (_size))
+#define DWC2_MEM_CACHE_LINE_SIZE  CONFIG_CACHE_L1_CACHE_LINE_SIZE
+
+#endif // DWC2_ENABLE_MEM_CACHE
 
 #ifdef __cplusplus
 }