DC entry port determination does not account for clock overflows

[jeffective]

The entry_port function attempts to determine the entry port from the available subdevice ports by using the port with the minimum timestamp.

ethercrab/src/subdevice/ports.rs

Line 137 in d4a7cfe

pub fn entry_port(&self) -> Port {

This does not account for the case of the propagation delay measurement taking place during a clock overflow.
For example:

1. frame arrives at port 0 at t = 2^32 - 10 ns
2. frame returns on port 1 at t = 230 ns

This would incorrectly assign port 1 as the entry port.

This can be fixed by assuming that the propagation delay in the network will never exceed 2^31 ns (approx. 2s), thereby grouping the timestamps before comparison.

Example:

1. port 0 entry time: 2^32 - 1000
2. port 1 entry time: 134 ns
3. port 2 entry time: 250 ns
4. port 3 inactive

by recognizing the gap between port 2 and port 0 exceeds 2^31, port 0 can be recognized as the entry port.

I reported the same issue to SOEM: OpenEtherCATsociety/SOEM#979 (comment)