Define remaining MSR bits

Related cleanup

Author: Extrems

include/ogc/machine/asm.h

@@ -335,14 +335,21 @@
 #define ECID2		926
 #define ECID3		927
 
+#define MSR_LE				0x00000001
 #define MSR_RI				0x00000002
+#define MSR_PM				0x00000004
 #define MSR_DR				0x00000010
 #define MSR_IR				0x00000020
 #define MSR_IP				0x00000040
+#define MSR_FE1				0x00000100
+#define MSR_BE				0x00000200
 #define MSR_SE				0x00000400
+#define MSR_FE0				0x00000800
 #define MSR_ME				0x00001000
 #define MSR_FP				0x00002000
+#define MSR_PR				0x00004000
 #define MSR_EE				0x00008000
+#define MSR_ILE				0x00010000
 #define MSR_POW				0x00040000
 
 #define PPC_ALIGNMENT		8

libogc/cache_asm.S

@@ -2,7 +2,7 @@
 
 cache_asm.S -- Cache interface
 
-Copyright (C) 2004 - 2025
+Copyright (C) 2004 - 2026
 Michael Wiedenbauer (shagkur)
 Dave Murphy (WinterMute)
 Extrems' Corner.org
@@ -265,7 +265,7 @@ __L2Init:
 	stw		r31,12(sp)
 	mfmsr	r31
 	sync
-	li		r3,48
+	li		r3,MSR_IR|MSR_DR
 	mtmsr	r3
 	sync
 	bl		L2Disable
@@ -346,7 +346,7 @@ L2SetWriteThrough:
 	.globl __LCEnable
 __LCEnable:
 	mfmsr	r5
-	ori		r5,r5,0x1000
+	ori		r5,r5,MSR_ME
 	mtmsr	r5
 	lis		r3,0x8000
 	li		r4,1024

libogc/system_asm.S

@@ -96,7 +96,7 @@ __configBATS:
 #endif
 
 	mfmsr	r3
-	ori		r3,r3,MSR_DR|MSR_IR
+	ori		r3,r3,MSR_IR|MSR_DR
 	mtsrr1	r3
 	mflr	r3
 	oris	r3,r3,0x8000
@@ -122,7 +122,7 @@ __configMEM1_16MB:
 	isync
 
 	mfmsr	r3
-	ori		r3,r3,MSR_DR|MSR_IR
+	ori		r3,r3,MSR_IR|MSR_DR
 	mtsrr1	r3
 	mflr	r3
 	mtsrr0	r3
@@ -161,7 +161,7 @@ __configMEM1_24MB:
 	isync
 
 	mfmsr	r3
-	ori		r3,r3,MSR_DR|MSR_IR
+	ori		r3,r3,MSR_IR|MSR_DR
 	mtsrr1	r3
 	mflr	r3
 	mtsrr0	r3
@@ -186,7 +186,7 @@ __configMEM1_32MB:
 	isync
 
 	mfmsr	r3
-	ori		r3,r3,MSR_DR|MSR_IR
+	ori		r3,r3,MSR_IR|MSR_DR
 	mtsrr1	r3
 	mflr	r3
 	mtsrr0	r3
@@ -225,7 +225,7 @@ __configMEM1_48MB:
 	isync
 
 	mfmsr	r3
-	ori		r3,r3,MSR_DR|MSR_IR
+	ori		r3,r3,MSR_IR|MSR_DR
 	mtsrr1	r3
 	mflr	r3
 	mtsrr0	r3
@@ -250,7 +250,7 @@ __configMEM1_64MB:
 	isync
 
 	mfmsr	r3
-	ori		r3,r3,MSR_DR|MSR_IR
+	ori		r3,r3,MSR_IR|MSR_DR
 	mtsrr1	r3
 	mflr	r3
 	mtsrr0	r3
@@ -286,7 +286,7 @@ __configMEM2_64MB:
 	isync
 
 	mfmsr	r3
-	ori		r3,r3,MSR_DR|MSR_IR
+	ori		r3,r3,MSR_IR|MSR_DR
 	mtsrr1	r3
 	mflr	r3
 	mtsrr0	r3
@@ -321,7 +321,7 @@ __configMEM2_128MB:
 	isync
 
 	mfmsr	r3
-	ori		r3,r3,MSR_DR|MSR_IR
+	ori		r3,r3,MSR_IR|MSR_DR
 	mtsrr1	r3
 	mflr	r3
 	mtsrr0	r3