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refactor(core): rename prop
1 parent 4b80894 commit 68a22d4

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2 files changed

+3
-3
lines changed

2 files changed

+3
-3
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src/core/bus/bus.ts

+1-1
Original file line numberDiff line numberDiff line change
@@ -29,7 +29,7 @@ export class Bus {
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readonly address$ = new BehaviorSubject(0x00)
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readonly control$ = new BehaviorSubject(initialControlLines)
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32-
readonly controlOnClockRise$: Observable<ControlLines> = this.control$.pipe(
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readonly clockRise$: Observable<ControlLines> = this.control$.pipe(
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filter((control, index) => (index && control.CLK)),
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share(),
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)

src/core/cpu/cpu.ts

+2-2
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,7 @@ export class Cpu {
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RD: 0b1,
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MREQ: 0b1,
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})
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yield this.bus.controlOnClockRise$.pipe(take(1))
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yield this.bus.clockRise$.pipe(take(1))
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this.bus.setControl({
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RD: 0b0,
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MREQ: 0b0,
@@ -37,7 +37,7 @@ export class Cpu {
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WR: 0b1,
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MREQ: 0b1,
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})
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yield this.bus.controlOnClockRise$.pipe(take(1))
40+
yield this.bus.clockRise$.pipe(take(1))
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this.bus.setControl({
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WR: 0b0,
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MREQ: 0b0,

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