Optimize cvttsd2siq

Summary:
This diff improves performance for lowering `cvttsd2siq` for Arm64. The code was found in hot code blocks in production.

Old code gen:
```
mrs x0, fpsr
and x0, x0, #0xfffffffffffffffe
msr fpsr, x0
movz x0, #0x8000000000000000
fcvtzs x1, d0
mrs x2, fpsr
tst x2, #0x1
csel x1, x0, x1, ne
movz x0, #0x8000000000000000
cmp x1, x0
b.eq  slowpath          # if equal, branch to slow path
```

New code gen:
```
ubfx x12, x26, #52, #11 # extract the exponent
cmp x12, #0x43e         # compare against 0x43e, which is 63 if unbiased by subtracting 1023
fmov d24, x26           # mov the value to a NEON register
fcvtzs x4, d24          # convert to integer in rounding to zero mode
movz x9, #0x8000000000000000 # INT64_MIN
csel x4, x9, x4, hs     # if dbl is positive, dbl >= 2^63 or is infinity or NaN, impossible to
                        # convert; if dbl is negative, dbl <= INT64_MIN or is infinity or NaN,
                        # impossible to convert except dbl == INT64_MIN. In all cases, set the
                        # the value to INT64_MIN and jump to slow path.
cmp x4, x9
b.eq  slowpath          # if equal, branch to slow path
```

The biggest difference is to not read and write fpsr (floating-point status register), which is slow on Arm64 CPUs.

Reviewed By: ottoni

Differential Revision: D92241953

fbshipit-source-id: 8448b689d48fc7406fafc85f79924cf3d03c8ea1

Author: mcfi

hphp/runtime/vm/jit/vasm-arm.cpp

@@ -450,6 +450,7 @@ struct Vgen {
   void emit(const mrs& i) { a->Mrs(X(i.r), vixl::SystemRegister(i.s.l())); }
   void emit(const msr& i) { a->Msr(vixl::SystemRegister(i.s.l()), X(i.r)); }
   void emit(const ubfmli& i) { a->ubfm(W(i.d), W(i.s), i.mr.w(), i.ms.w()); }
+  void emit(const ubfmliq& i) { a->ubfm(X(i.d), X(i.s), i.mr.l(), i.ms.l()); }
   void emit(const sbfizq& i) { a->Sbfiz(X(i.d), X(i.s), i.shift.l(), i.width.l()); }
   void emit(const storepair& i) { a->Stp(X(i.s0), X(i.s1), M(i.d)); }
   void emit(const storepairl& i) { a->Stp(W(i.s0), W(i.s1), M(i.d)); }
@@ -1857,29 +1858,38 @@ Y(incwm, incw, loadw, storew, m)
 
 void lower(const VLS& e, cvttsd2siq& i, Vlabel b, size_t idx) {
   lower_impl(e.unit, b, idx, [&] (Vout& v) {
-    // Clear FPSR IOC flag.
-    auto const tmp1 = v.makeReg();
-    auto const tmp2 = v.makeReg();
-    v << mrs{FPSR, tmp1};
-    v << andqi{~0x01, tmp1, tmp2, v.makeReg()};
-    v << msr{tmp2, FPSR};
+    // Move i.s to a GP register verbatim.
+    auto const dbl_bits = v.makeReg();
+    v << copy{i.s, dbl_bits};
 
-    // Load error value.
-    auto const err = v.makeReg();
-    v << ldimmq{0x8000000000000000, err};
+    // Extract the exponent of the double value.
+    auto const dbl_exp = v.makeReg();
+    v << ubfmliq(52, 52 + 11 - 1, dbl_bits, dbl_exp);
+
+    // Compare against 0x43e, which is 63 if unbiased (0x43e - 1023 = 63).
+    auto const sf = v.makeReg();
+    v << cmpqi(0x43e, dbl_exp, sf);
 
     // Do ARM64's double to signed int64 conversion.
     auto const res = v.makeReg();
     v << fcvtzs{i.s, res};
 
-    // Check if there was a conversion error.
-    auto const fpsr = v.makeReg();
-    auto const sf = v.makeReg();
-    v << mrs{FPSR, fpsr};
-    v << testqi{1, fpsr, sf};
+    // Load error value (-2^63)
+    auto const err = v.cns(0x8000000000000000L);
 
     // Move converted value or error.
-    v << cmovq{CC_NZ, sf, res, err, i.d};
+    // If exp < 63, the double value is finite and within the range of
+    // -2^63 and 2^63 - 1, so fcvtzs always succeeds and the value is
+    // chosen as the result.
+    // Otherwise, below are all the cases:
+    // 1. If dbl is positive, then dbl is >= 2^63, or dbl is an infinity
+    //    or NaN. Converting those values to int64 certainly fails and
+    //    we choose the error value.
+    // 2. If dbl is negative, then dbl is <= -2^63, or dbl is an infinity
+    //    or NaN. If dbl is -2^63, the converted integer value is still
+    //    -2^63, so the error value is actually correct. The other cases
+    //    will lead to conversion failure, which will pick the error value.
+    v << cmovq{CC_AE, sf, res, err, i.d};
   });
 }
 

hphp/runtime/vm/jit/vasm-info.cpp

@@ -279,6 +279,7 @@ bool effectsImpl(const Vinstr& inst, bool pure) {
     case Vinstr::testw:
     case Vinstr::testwi:
     case Vinstr::ubfmli:
+    case Vinstr::ubfmliq:
     case Vinstr::ucomisd:
     case Vinstr::unpcklpd:
     case Vinstr::xorb:

hphp/runtime/vm/jit/vasm-instr.cpp

@@ -356,6 +356,7 @@ Width width(Vinstr::Opcode op) {
     case Vinstr::sarqi:
     case Vinstr::shlqi:
     case Vinstr::shrqi:
+    case Vinstr::ubfmliq:
     case Vinstr::sbfizq:
     case Vinstr::subq:
     case Vinstr::subqi:

hphp/runtime/vm/jit/vasm-instr.h

@@ -362,6 +362,7 @@ struct Vunit;
   O(mrs, I(s), Un, D(r))\
   O(msr, I(s), U(r), Dn)\
   O(ubfmli, I(mr) I(ms), U(s), D(d))\
+  O(ubfmliq, I(mr) I(ms), U(s), D(d))\
   O(sbfizq, I(shift) I(width), U(s), D(d))\
   O(loadpair, Inone, U(s), D(d0) D(d1))\
   O(loadpairl, Inone, U(s), D(d0) D(d1))\
@@ -1281,6 +1282,7 @@ struct fcvtzs { VregDbl s; Vreg64 d;};
 struct mrs { Immed s; Vreg64 r; };
 struct msr { Vreg64 r; Immed s; };
 struct ubfmli { Immed mr, ms; Vreg32 s, d; };
+struct ubfmliq { Immed mr, ms; Vreg64 s, d; };
 struct sbfizq { Immed shift, width; Vreg64 s, d; };
 struct loadpair { Vptr128 s; Vreg64 d0, d1; };
 struct loadpairl { Vptr64 s; Vreg32 d0, d1; };

hphp/test/quick/bitwise_not.php

@@ -1,7 +1,7 @@
 <?hh
 
 <<__EntryPoint>> function foo(): void {
-  $vals = vec[1,5,2,1.54,-123.3,1256.6,null /*throws*/];
+  $vals = vec[1,5,2,1.54,-123.3,1256.6,NAN,-NAN,INF,-INF,(float)(((1<<52)-1)<<11),(float)PHP_INT_MIN,null /*throws*/];
   foreach ($vals as $v) {
     var_dump(~($v is null ? $v : (int)$v));
   }

hphp/test/quick/bitwise_not.php.expectf

@@ -4,5 +4,11 @@ int(-3)
 int(-2)
 int(122)
 int(-1257)
+int(9223372036854775807)
+int(9223372036854775807)
+int(-1)
+int(9223372036854775807)
+int(-9223372036854773761)
+int(9223372036854775807)
 
 Fatal error: Unsupported operand type for ~ in %s on line 6