Apply HHVM-specific modifications for vixl 8.0.0

Summary:
Apply HHVM-specific modifications on top of the upstream vixl 8.0.0 baseline.
This is the third diff in a stack that upgrades vixl from the old a64 version
to the new aarch64 version (8.0.0).

Changes include:

hphp/vixl (HHVM-specific adaptations of upstream vixl):
- Add BUCK build file and CMakeLists.txt for HHVM build integration
- Add hphp-compat.h compatibility header (using namespace aarch64 bridge only;
  all deprecated aliases like FPRegister removed)
- Modify vixl source files to integrate with HHVM's memory management,
  code generation, and debugging infrastructure
- Adapt test files for HHVM's test framework
- Use vixl's udf(1) for trap instruction (replacing dc32(1) workaround)
- Make EmissionCheckScope (and subclasses SingleEmissionCheckScope,
  MacroEmissionCheckScope, ExactAssemblyScope) a no-op under HPHP_VIXL
  to eliminate per-instruction overhead from scope guard
  construction/destruction and redundant assertCanEmit() buffer checks.
  This removes ~8 member stores + 1 redundant bounds check + 2-3 branches
  per instruction emission that were absent in the old vixl version.

hphp/runtime (HHVM JIT backend updates):
- Update ARM backend to use new vixl aarch64 namespace and API
  (vixl::aarch64 instead of vixl)
- Update register definitions and physical register mappings
  (FPRegister -> VRegister)
- Update instruction encoding/decoding for new vixl API
- Update disassembler integration
- Update relocation and smashable instruction handling

hphp/tools (tc-print):
- Update offline-arm-code.cpp to use new vixl aarch64 headers and API
  (hphp-compat.h, GetLiteralAddress<T>(), GetImmPCOffsetTarget())

hphp/util:
- Update data-block.h for compatibility with new vixl API

Reviewed By: ricklavoie, ottoni

Differential Revision: D94756745

fbshipit-source-id: 15fbb081ddb7ba2a281e04b5c0de4e55d07e606d

Author: mcfi

hphp/runtime/test/relocation-test.cpp

@@ -18,7 +18,7 @@
 #include "hphp/runtime/vm/jit/relocation.h"
 #include "hphp/util/arch.h"
 #include "hphp/util/data-block.h"
-#include "hphp/vixl/a64/macro-assembler-a64.h"
+#include "hphp/vixl/hphp-compat.h"
 
 #include <gtest/gtest.h>
 
@@ -89,30 +89,30 @@ TEST(Relocation, RelocateBccImm2MovzMovkBccReg) {
   // 3. Call relocate()
   RelocationInfo rel;
   AreaIndex ai = AreaIndex::Main;
-  auto instr = Instruction::Cast(end);
+  const Instruction* instr = Instruction::Cast(end);
   relocate(rel, main, start, end, main, meta, nullptr, ai);
 
   // 4. Expect !b.cc, movz/movk X and br X where with imm in X
   auto bcc = instr;
   EXPECT_TRUE(bcc->IsCondBranchImm());
   EXPECT_EQ(bcc->ConditionBranch(), InvertCondition(cond));
 
-  auto movz = bcc->NextInstruction();
+  auto movz = bcc->GetNextInstruction();
   EXPECT_TRUE(movz->IsMovz());
   const auto rd = movz->Rd();
-  uint64_t target = movz->ImmMoveWide() << (16 * movz->ShiftMoveWide());
-  instr = movz->NextInstruction();
+  uint64_t target = (uint64_t)movz->ImmMoveWide() << (16 * movz->ShiftMoveWide());
+  instr = movz->GetNextInstruction();
   while (instr->IsMovk()) {
     EXPECT_EQ(instr->Rd(), rd);
-    target |= instr->ImmMoveWide() << (16 * instr->ShiftMoveWide());
-    instr = instr->NextInstruction();
+    target |= (uint64_t)instr->ImmMoveWide() << (16 * instr->ShiftMoveWide());
+    instr = instr->GetNextInstruction();
   }
   EXPECT_EQ(Instruction::Cast(target), bccOrig->ImmPCOffsetTarget());
 
   auto br = instr;
   EXPECT_TRUE(br->IsUncondBranchReg());
   EXPECT_EQ(br->Rn(), rd);
-  EXPECT_EQ(bcc->ImmPCOffsetTarget(), br->NextInstruction());
+  EXPECT_EQ(bcc->ImmPCOffsetTarget(), br->GetNextInstruction());
 }
 
 /*
@@ -153,7 +153,7 @@ TEST(Relocation, RelocateCbz2MovzMovkCbnzReg) {
   // 3. Call relocate()
   RelocationInfo rel;
   AreaIndex ai = AreaIndex::Main;
-  auto instr = Instruction::Cast(end);
+  const Instruction* instr = Instruction::Cast(end);
   relocate(rel, main, start, end, main, meta, nullptr, ai);
 
   // 4. Expect cbnz, movz/movk X and br X where with imm in X
@@ -162,22 +162,22 @@ TEST(Relocation, RelocateCbz2MovzMovkCbnzReg) {
   const auto rt = cbnz->Rt();
   EXPECT_EQ(cbzOrig->Rt(), rt);
 
-  auto movz = cbnz->NextInstruction();
+  auto movz = cbnz->GetNextInstruction();
   EXPECT_TRUE(movz->IsMovz());
   const auto rd = movz->Rd();
-  uint64_t target = movz->ImmMoveWide() << (16 * movz->ShiftMoveWide());
-  instr = movz->NextInstruction();
+  uint64_t target = (uint64_t)movz->ImmMoveWide() << (16 * movz->ShiftMoveWide());
+  instr = movz->GetNextInstruction();
   while (instr->IsMovk()) {
     EXPECT_EQ(instr->Rd(), rd);
-    target |= instr->ImmMoveWide() << (16 * instr->ShiftMoveWide());
-    instr = instr->NextInstruction();
+    target |= (uint64_t)instr->ImmMoveWide() << (16 * instr->ShiftMoveWide());
+    instr = instr->GetNextInstruction();
   }
   EXPECT_EQ(Instruction::Cast(target), cbzOrig->ImmPCOffsetTarget());
 
   auto br = instr;
   EXPECT_TRUE(br->IsUncondBranchReg());
   EXPECT_EQ(br->Rn(), rd);
-  EXPECT_EQ(cbnz->ImmPCOffsetTarget(), br->NextInstruction());
+  EXPECT_EQ(cbnz->ImmPCOffsetTarget(), br->GetNextInstruction());
 }
 
 /*
@@ -218,7 +218,7 @@ TEST(Relocation, RelocateTbz2MovzMovkTbnzReg) {
   // 3. Call relocate()
   RelocationInfo rel;
   AreaIndex ai = AreaIndex::Main;
-  auto instr = Instruction::Cast(end);
+  const Instruction* instr = Instruction::Cast(end);
   relocate(rel, main, start, end, main, meta, nullptr, ai);
 
   // 4. Expect tbnz, movz/movk X and br X where with imm in X
@@ -229,22 +229,22 @@ TEST(Relocation, RelocateTbz2MovzMovkTbnzReg) {
   const auto bit_pos = tbnz->ImmTestBranchBit40();
   EXPECT_EQ(bit_pos, 3);
 
-  auto movz = tbnz->NextInstruction();
+  auto movz = tbnz->GetNextInstruction();
   EXPECT_TRUE(movz->IsMovz());
   const auto rd = movz->Rd();
-  uint64_t target = movz->ImmMoveWide() << (16 * movz->ShiftMoveWide());
-  instr = movz->NextInstruction();
+  uint64_t target = (uint64_t)movz->ImmMoveWide() << (16 * movz->ShiftMoveWide());
+  instr = movz->GetNextInstruction();
   while (instr->IsMovk()) {
     EXPECT_EQ(instr->Rd(), rd);
-    target |= instr->ImmMoveWide() << (16 * instr->ShiftMoveWide());
-    instr = instr->NextInstruction();
+    target |= (uint64_t)instr->ImmMoveWide() << (16 * instr->ShiftMoveWide());
+    instr = instr->GetNextInstruction();
   }
   EXPECT_EQ(Instruction::Cast(target), tbzOrig->ImmPCOffsetTarget());
 
   auto br = instr;
   EXPECT_TRUE(br->IsUncondBranchReg());
   EXPECT_EQ(br->Rn(), rd);
-  EXPECT_EQ(tbnz->ImmPCOffsetTarget(), br->NextInstruction());
+  EXPECT_EQ(tbnz->ImmPCOffsetTarget(), br->GetNextInstruction());
 }
 
 /*
@@ -275,7 +275,7 @@ TEST(Relocation, RelocateMovzMovkLdr2LdrLiteral) {
   // with this test.
   a.dc64(0xdeadbeef);
   meta.addressImmediates.insert(main.frontier());
-  a.Mov(x17, start + 4);
+  a.Mov(x17, reinterpret_cast<uint64_t>(start + 4));
 
   a.Ldr(x0, MemOperand(x17, 0));
 
@@ -284,13 +284,13 @@ TEST(Relocation, RelocateMovzMovkLdr2LdrLiteral) {
   // 3. Call relocate()
   RelocationInfo rel;
   AreaIndex ai = AreaIndex::Main;
-  auto instr = Instruction::Cast(end + 8);
+  const Instruction* instr = Instruction::Cast(end + 8);
   relocate(rel, main, start, end, main, meta, nullptr, ai);
 
   // 4. Expect a Ldr Literal to $x0 from addr
   EXPECT_TRUE(instr->IsLoadLiteral());
   EXPECT_EQ(instr->Rd(), 0);
-  EXPECT_EQ(reinterpret_cast<TCA>(instr->LiteralAddress()), end);
+  EXPECT_EQ(reinterpret_cast<TCA>(instr->GetLiteralAddress<uint8_t*>()), end);
 }
 
 /*
@@ -317,26 +317,26 @@ TEST(Relocation, RelocateAdjustedMovzMovk) {
   main.setFrontier(start + (2 << 20) + 16);
   MacroAssembler a { main };
   meta.addressImmediates.insert(main.frontier());
-  a.Mov(x17, start + 8);
+  a.Mov(x17, reinterpret_cast<uint64_t>(start + 8));
 
   auto end = main.frontier();
 
   // 3. Call relocate()
   RelocationInfo rel;
   AreaIndex ai = AreaIndex::Main;
-  auto instr = Instruction::Cast(end);
+  const Instruction* instr = Instruction::Cast(end);
   relocate(rel, main, start, end, main, meta, nullptr, ai);
 
   // 4. Expect movz/movk of new target
   auto movz = instr + (2 << 20) + 16;
   EXPECT_TRUE(movz->IsMovz());
   EXPECT_EQ(movz->Rd(), 17);
-  uint64_t target = movz->ImmMoveWide() << (16 * movz->ShiftMoveWide());
-  instr = movz->NextInstruction();
+  uint64_t target = (uint64_t)movz->ImmMoveWide() << (16 * movz->ShiftMoveWide());
+  instr = movz->GetNextInstruction();
   while (instr->IsMovk()) {
     EXPECT_EQ(instr->Rd(), 17);
-    target |= instr->ImmMoveWide() << (16 * instr->ShiftMoveWide());
-    instr = instr->NextInstruction();
+    target |= (uint64_t)instr->ImmMoveWide() << (16 * instr->ShiftMoveWide());
+    instr = instr->GetNextInstruction();
   }
   EXPECT_EQ(Instruction::Cast(target), Instruction::Cast(end + 8));
 }
@@ -367,27 +367,27 @@ TEST(Relocation, RelocateInternalAdjustedMovzMovk) {
 
   MacroAssembler a { main };
   meta.addressImmediates.insert(main.frontier());
-  a.Mov(x17, start + (2 << 20) + 16);
+  a.Mov(x17, reinterpret_cast<uint64_t>(start + (2 << 20) + 16));
   main.setFrontier(start + (4 << 20) + 32);
 
   auto end = main.frontier();
 
   // 3. Call relocate()
   RelocationInfo rel;
   AreaIndex ai = AreaIndex::Main;
-  auto instr = Instruction::Cast(end);
+  const Instruction* instr = Instruction::Cast(end);
   relocate(rel, main, start, end, main, meta, nullptr, ai);
 
   // 4. Expect movz/movk of new target
   auto movz = instr;
   EXPECT_TRUE(movz->IsMovz());
   EXPECT_EQ(movz->Rd(), 17);
-  uint64_t target = movz->ImmMoveWide() << (16 * movz->ShiftMoveWide());
-  instr = movz->NextInstruction();
+  uint64_t target = (uint64_t)movz->ImmMoveWide() << (16 * movz->ShiftMoveWide());
+  instr = movz->GetNextInstruction();
   while (instr->IsMovk()) {
     EXPECT_EQ(instr->Rd(), 17);
-    target |= instr->ImmMoveWide() << (16 * instr->ShiftMoveWide());
-    instr = instr->NextInstruction();
+    target |= (uint64_t)instr->ImmMoveWide() << (16 * instr->ShiftMoveWide());
+    instr = instr->GetNextInstruction();
   }
   EXPECT_EQ(Instruction::Cast(target), Instruction::Cast(end + (2 << 20) + 16));
 }
@@ -416,7 +416,7 @@ TEST(Relocation, AdjustMovzMovk) {
 
   MacroAssembler a { main };
   meta.addressImmediates.insert(main.frontier());
-  a.Mov(x17, orig + (2 << 20) + 16);
+  a.Mov(x17, reinterpret_cast<uint64_t>(orig + (2 << 20) + 16));
   main.setFrontier(orig + (2 << 20) + 16);
 
   auto start = main.frontier();
@@ -433,12 +433,12 @@ TEST(Relocation, AdjustMovzMovk) {
   auto movz = Instruction::Cast(orig);
   EXPECT_TRUE(movz->IsMovz());
   EXPECT_EQ(movz->Rd(), 17);
-  uint64_t target = movz->ImmMoveWide() << (16 * movz->ShiftMoveWide());
-  auto instr = movz->NextInstruction();
+  uint64_t target = (uint64_t)movz->ImmMoveWide() << (16 * movz->ShiftMoveWide());
+  auto instr = movz->GetNextInstruction();
   while (instr->IsMovk()) {
     EXPECT_EQ(instr->Rd(), 17);
-    target |= instr->ImmMoveWide() << (16 * instr->ShiftMoveWide());
-    instr = instr->NextInstruction();
+    target |= (uint64_t)instr->ImmMoveWide() << (16 * instr->ShiftMoveWide());
+    instr = instr->GetNextInstruction();
   }
   EXPECT_EQ(Instruction::Cast(target), Instruction::Cast(end));
 }

hphp/runtime/vm/jit/abi-arm.cpp

@@ -190,11 +190,11 @@ PhysReg rret_simd(size_t i) {
 
 PhysReg rarg(size_t i) {
   assertx(i < num_arg_regs());
-  return vixl::Register::XRegFromCode(i);
+  return vixl::XRegister(i);
 }
 PhysReg rarg_simd(size_t i) {
   assertx(i < num_arg_regs_simd());
-  return vixl::FPRegister::DRegFromCode(i);
+  return vixl::DRegister(i);
 }
 PhysReg rarg_ind_ret(size_t i) {
   assertx(i < num_arg_regs_ind_ret());

hphp/runtime/vm/jit/abi-arm.h

@@ -18,10 +18,10 @@
 
 #include "hphp/runtime/vm/jit/abi-regs.h"
 #include "hphp/runtime/vm/jit/phys-reg.h"
+#include "hphp/runtime/vm/jit/types.h"
 
 #include "hphp/util/asm-x64.h"
-#include "hphp/vixl/a64/assembler-a64.h"
-#include "hphp/vixl/a64/constants-a64.h"
+#include "hphp/vixl/hphp-compat.h"
 
 namespace HPHP::jit {
 
@@ -90,15 +90,17 @@ inline vixl::Register x2a(PhysReg x64reg) {
   return vixl::Register(vixl::CPURegister(x64reg));
 }
 
-inline vixl::FPRegister x2f(PhysReg x64reg) {
+inline vixl::VRegister x2f(PhysReg x64reg) {
   always_assert(x64reg.isSIMD());
-  return vixl::FPRegister(vixl::CPURegister(x64reg));
+  return vixl::VRegister(vixl::CPURegister(x64reg));
 }
 
 inline vixl::VRegister x2v(PhysReg x64reg) {
   always_assert(x64reg.isSIMD());
   auto const r = vixl::CPURegister(x64reg);
-  return vixl::VRegister(r.code(), 128);
+  // Use .16b (16 lanes of bytes) format for 128-bit vector operations.
+  // The new VIXL requires an explicit lane count for ld1/st1 encoding.
+  return vixl::VRegister(r.code(), 128, 16);
 }
 
 /*

hphp/runtime/vm/jit/align-arm.cpp

@@ -20,7 +20,7 @@
 #include "hphp/runtime/vm/jit/smashable-instr-arm.h"
 
 #include "hphp/util/data-block.h"
-#include "hphp/vixl/a64/macro-assembler-a64.h"
+#include "hphp/vixl/hphp-compat.h"
 
 #include <folly/Bits.h>
 

hphp/runtime/vm/jit/phys-reg.cpp

@@ -22,7 +22,7 @@
 
 #include "hphp/util/arch.h"
 #include "hphp/util/asm-x64.h"
-#include "hphp/vixl/a64/macro-assembler-a64.h"
+#include "hphp/vixl/hphp-compat.h"
 
 namespace HPHP::jit {
 
@@ -48,7 +48,7 @@ std::string show(PhysReg r) {
 
       return folly::to<std::string>(
         r.isGP() ? (vixl::Register(r).size() == vixl::kXRegSize ? 'x' : 'w')
-                 : (vixl::FPRegister(r).size() == vixl::kSRegSize ? 's' : 'd'),
+                 : (vixl::VRegister(r).size() == vixl::kSRegSize ? 's' : 'd'),
         ((vixl::CPURegister)r).code()
       );
   }

hphp/runtime/vm/jit/phys-reg.h

@@ -18,7 +18,7 @@
 
 #include "hphp/util/asm-x64.h"
 #include "hphp/util/bitops.h"
-#include "hphp/vixl/a64/assembler-a64.h"
+#include "hphp/vixl/hphp-compat.h"
 
 #include <type_traits>
 
@@ -39,17 +39,26 @@ struct Vout;
 struct PhysReg {
 private:
   static constexpr auto kGPOffset = 0;
-  static constexpr auto kNumGP = 48;
 
-  static constexpr auto kSIMDOffset = kNumGP;
+#ifdef __aarch64__
+  // Arm64 VIXL uses number 63 to represent SP internally, so
+  // kNumGP must be >= 64 for Arm64.
+  static constexpr auto kNumGP = 64;
+  static constexpr auto kNumSIMD = 48;
+#else
+  // TODO: Eventually, we should move to arm64 kNumGP and kNumSIMD
+  // for platform parity.
+  static constexpr auto kNumGP = 48;
   static constexpr auto kNumSIMD = 64;
+#endif
 
+  static constexpr auto kSIMDOffset = kNumGP;
   static constexpr auto kSFOffset = kNumGP + kNumSIMD;
   static constexpr auto kNumSF = 1;
 
 public:
   /*
-   * 48 GP regs + 64 SIMD regs + 1 SF reg + 15 empty == 128 regs.
+   * 64 GP regs + 48 SIMD regs + 1 SF reg + 15 empty == 128 regs.
    *
    * We can toggle these values, but they need sum to 128 so that RegSet can
    * fit into two registers.
@@ -70,7 +79,7 @@ struct PhysReg {
   explicit constexpr PhysReg(Reg8 r) : n(int(r)) {}
 
   constexpr /* implicit */ PhysReg(vixl::Register r) : n(r.code()) {}
-  constexpr /* implicit */ PhysReg(vixl::FPRegister r)
+  constexpr /* implicit */ PhysReg(vixl::VRegister r)
     : n(r.code() + kSIMDOffset) {}
 
   /* implicit */ operator Reg64() const {
@@ -95,7 +104,7 @@ struct PhysReg {
                                  vixl::CPURegister::kRegister);
       } else if (isSIMD()) {
         return vixl::CPURegister(n - kSIMDOffset, vixl::kDRegSize,
-                                 vixl::CPURegister::kFPRegister);
+                                 vixl::CPURegister::kVRegister);
       } else {
         assertx(isSF());
         return vixl::NoCPUReg;
@@ -111,6 +120,10 @@ struct PhysReg {
   }
   bool isGP() const {
     static_assert(kGPOffset == 0, "kGPOffset is expected to be zero.");
+  #if defined(__aarch64__)
+    if (n == vixl::kSPRegInternalCode) return true;
+    if (n > vixl::kSpRegCode && n < vixl::kSPRegInternalCode) return false;
+  #endif
     return n < kGPOffset+numGP();
   }
   bool isSIMD() const { return n >= kSIMDOffset && n < kSIMDOffset+numSIMD(); }