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[swift] Fix translation error with expect builtin
Summary: We were not adding the accumulator instructions in this case. This solves a translation error. Reviewed By: davidpichardie Differential Revision: D90867637 Privacy Context Container: L1208441 fbshipit-source-id: ed88ca4aac57b5700b79ea5832f40b19604dd23c
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infer/src/llvm/Llair2Textual.ml

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -835,7 +835,7 @@ let cmnd_to_instrs ~(proc_state : ProcState.t) block =
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| None ->
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Some (Var.add_fresh_id ~proc_state ())
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in
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Textual.Instr.Let {id; exp; loc} :: exp_instrs
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Textual.Instr.Let {id; exp; loc} :: (exp_instrs @ textual_instrs)
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| _ ->
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assert false )
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| Builtin {reg; name; args; loc} ->

infer/tests/codetoanalyze/swift/frontend/base.swift.sil

Lines changed: 8 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -56,7 +56,9 @@ define $ss7UnicodeO6ScalarV17withUTF8CodeUnitsyxxSRys5UInt8VGKXEKlFxSPys6UInt64V
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_ = $ss18_fatalErrorMessage__4file4line5flagss5NeverOs12StaticStringV_A2HSus6UInt32VtF(__sil_cast(<int>, "Fatal error"), 11, 2, __sil_cast(<int>, "self must be a properly aligned pointer for types Pointee and T"), 63, 2, __sil_cast(<int>, "Swift/arm64-apple-ios-simulator.swiftinterface"), 46, 2, 31972, 0) @[465:0]
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jmp $ss18_fatalErrorMessage__4file4line5flagss5NeverOs12StaticStringV_A2HSus6UInt32VtF::void::ret @[466:0]
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59-
#13: @[469:0]
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#13: @[468:0]
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n23 = load &var5 @[468:0]
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n22 = load n23.__infer_swift_type<TSi>.rawValue @[468:0]
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n26 = __sil_lt(n22, 0) @[469:0]
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if n26 then jmp 26 else jmp 19 @[470:0]
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@@ -710,7 +712,11 @@ define .plain_name = "init" $s5Hello8TestSizeV4size4modeACSgSo6CGSizeV_AA0C4Mode
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n28 = __sil_bxor(__sil_lt(n24, 4.89090919532e+18), 1) @[41:22]
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if n28 then jmp 104 else jmp 31 @[41:22]
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#31: @[42:23]
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#31: @[41:20]
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n31 = load &self @[41:20]
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n32 = load n31.__infer_swift_type<T5Hello8TestSizeV,TestSize>.width @[41:20]
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n29 = load &var2 @[41:20]
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store n32.__infer_swift_type<TSi>.rawValue <- __sil_cast(<int>, n29) @[41:20]
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n33 = load &var3 @[42:23]
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n42 = __sil_bxor(__sil_lt(__sil_land(__sil_shiftrt(__sil_cast(<int>, n33), 52), 2047), 2047), 1) @[42:23]
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if n42 then jmp 105 else jmp 41 @[42:23]

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