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yosemite4n: linux-nuvoton: Add kernel driver patches
Summary: Add kernel driver patches that are still under upstream review. Test Plan: bitbake yosemite4n-image - Build Pass Signed-off-by: Marvin Lin <[email protected]>
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‎common/recipes-kernel/linux/linux-nuvoton_%.bbappend

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FILESEXTRAPATHS:prepend := "${THISDIR}/6.6:"
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LINUX_NUVOTON_PATCHES_INC ?= ""
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LINUX_NUVOTON_PATCHES_INC:openbmc-fb-lf = "linux-patches-6.6.inc"
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include ${LINUX_NUVOTON_PATCHES_INC}

‎meta-facebook/meta-yosemite4/meta-yosemite4n/recipes-kernel/linux/linux-nuvoton/1000-dt-bindings-clock-npcm845-Add-reference-25m-clock-pr.patch

+89
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From 9f903328f2169a1d058418a2e49cbe164584b9d9 Mon Sep 17 00:00:00 2001
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From: Tomer Maimon <[email protected]>
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Date: Mon, 1 Jul 2024 10:10:44 +0300
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Subject: [PATCH] dt-bindings: clock: npcm845: Add reference 25m clock property
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The NPCM8XX clock driver uses a 25Mhz external clock, therefore adding
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clock property.
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The new required clock property does not break the NPCM8XX clock ABI
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since the NPCM8XX clock driver hasn't merged yet to the Linux vanilla.
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This change was pushed upstream and under reviewing:
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https://lore.kernel.org/all/[email protected]/
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Signed-off-by: Tomer Maimon <[email protected]>
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---
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arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi | 9 +++++----
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arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts | 7 +++++++
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2 files changed, 12 insertions(+), 4 deletions(-)
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diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
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index ecd171b2feba..41d345448430 100644
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--- a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
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+++ b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
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@@ -52,6 +52,7 @@ rstc: reset-controller@f0801000 {
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reg = <0x0 0xf0801000 0x0 0x78>;
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#reset-cells = <2>;
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nuvoton,sysgcr = <&gcr>;
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+ clocks = <&refclk>;
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};
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clk: clock-controller@f0801000 {
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@@ -81,7 +82,7 @@ timer0: timer@8000 {
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compatible = "nuvoton,npcm845-timer";
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x8000 0x1C>;
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- clocks = <&clk NPCM8XX_CLK_REFCLK>;
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+ clocks = <&refclk>;
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clock-names = "refclk";
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};
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@@ -153,7 +154,7 @@ watchdog0: watchdog@801c {
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interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x801c 0x4>;
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status = "disabled";
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- clocks = <&clk NPCM8XX_CLK_REFCLK>;
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+ clocks = <&refclk>;
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syscon = <&gcr>;
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};
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@@ -162,7 +163,7 @@ watchdog1: watchdog@901c {
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interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x901c 0x4>;
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status = "disabled";
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- clocks = <&clk NPCM8XX_CLK_REFCLK>;
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+ clocks = <&refclk>;
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syscon = <&gcr>;
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};
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@@ -171,7 +172,7 @@ watchdog2: watchdog@a01c {
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interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xa01c 0x4>;
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status = "disabled";
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- clocks = <&clk NPCM8XX_CLK_REFCLK>;
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+ clocks = <&refclk>;
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syscon = <&gcr>;
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};
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};
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diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts
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index a5ab2bc0f835..83c2f4e138e5 100644
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--- a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts
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+++ b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts
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@@ -19,6 +19,13 @@ chosen {
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memory {
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reg = <0x0 0x0 0x0 0x40000000>;
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};
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+
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+ refclk: refclk-25mhz {
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+ compatible = "fixed-clock";
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+ clock-output-names = "ref";
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+ clock-frequency = <25000000>;
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+ #clock-cells = <0>;
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+ };
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};
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&serial0 {
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--
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2.34.1
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‎meta-facebook/meta-yosemite4/meta-yosemite4n/recipes-kernel/linux/linux-nuvoton/1001-arm64-dts-modify-clock-property-in-modules-node.patch

+136
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From 7ada4b7e39819f2cc765b27f3fc1ad38ece3278f Mon Sep 17 00:00:00 2001
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From: Tomer Maimon <[email protected]>
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Date: Mon, 1 Jul 2024 10:10:46 +0300
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Subject: [PATCH] arm64: dts: modify clock property in modules node
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Modify clock property handler in UART, CPU, PECI modules to reset
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controller.
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This change was pushed upstream and under reviewing:
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https://lore.kernel.org/all/[email protected]/
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Signed-off-by: Tomer Maimon <[email protected]>
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---
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.../boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi | 16 ++++++++--------
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arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi | 8 ++++----
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2 files changed, 12 insertions(+), 12 deletions(-)
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diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
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index 41d345448430..92e3b0fe746f 100644
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--- a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
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+++ b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
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@@ -73,7 +73,7 @@ peci: peci-controller@100000 {
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compatible = "nuvoton,npcm845-peci";
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reg = <0x100000 0x1000>;
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interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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- clocks = <&clk NPCM8XX_CLK_APB3>;
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+ clocks = <&rstc NPCM8XX_CLK_APB3>;
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cmd-timeout-ms = <1000>;
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status = "disabled";
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};
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@@ -89,7 +89,7 @@ timer0: timer@8000 {
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serial0: serial@0 {
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compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
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reg = <0x0 0x1000>;
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- clocks = <&clk NPCM8XX_CLK_UART>;
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+ clocks = <&rstc NPCM8XX_CLK_UART>;
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interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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status = "disabled";
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@@ -98,7 +98,7 @@ serial0: serial@0 {
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serial1: serial@1000 {
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compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
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reg = <0x1000 0x1000>;
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- clocks = <&clk NPCM8XX_CLK_UART>;
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+ clocks = <&rstc NPCM8XX_CLK_UART>;
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interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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status = "disabled";
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@@ -107,7 +107,7 @@ serial1: serial@1000 {
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serial2: serial@2000 {
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compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
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reg = <0x2000 0x1000>;
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- clocks = <&clk NPCM8XX_CLK_UART>;
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+ clocks = <&rstc NPCM8XX_CLK_UART>;
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interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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status = "disabled";
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@@ -116,7 +116,7 @@ serial2: serial@2000 {
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serial3: serial@3000 {
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compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
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reg = <0x3000 0x1000>;
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- clocks = <&clk NPCM8XX_CLK_UART>;
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+ clocks = <&rstc NPCM8XX_CLK_UART>;
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interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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status = "disabled";
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@@ -125,7 +125,7 @@ serial3: serial@3000 {
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serial4: serial@4000 {
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compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
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reg = <0x4000 0x1000>;
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- clocks = <&clk NPCM8XX_CLK_UART>;
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+ clocks = <&rstc NPCM8XX_CLK_UART>;
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interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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status = "disabled";
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@@ -134,7 +134,7 @@ serial4: serial@4000 {
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serial5: serial@5000 {
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compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
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reg = <0x5000 0x1000>;
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- clocks = <&clk NPCM8XX_CLK_UART>;
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+ clocks = <&rstc NPCM8XX_CLK_UART>;
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interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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status = "disabled";
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@@ -143,7 +143,7 @@ serial5: serial@5000 {
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serial6: serial@6000 {
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compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
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reg = <0x6000 0x1000>;
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- clocks = <&clk NPCM8XX_CLK_UART>;
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+ clocks = <&rstc NPCM8XX_CLK_UART2>;
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interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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status = "disabled";
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diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi
95+
index 383938dcd3ce..3cbcea65eba2 100644
96+
--- a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi
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+++ b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi
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@@ -14,7 +14,7 @@ cpus {
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a35";
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- clocks = <&clk NPCM8XX_CLK_CPU>;
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+ clocks = <&rstc NPCM8XX_CLK_CPU>;
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reg = <0x0 0x0>;
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next-level-cache = <&l2>;
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enable-method = "psci";
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@@ -23,7 +23,7 @@ cpu0: cpu@0 {
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a35";
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- clocks = <&clk NPCM8XX_CLK_CPU>;
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+ clocks = <&rstc NPCM8XX_CLK_CPU>;
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reg = <0x0 0x1>;
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next-level-cache = <&l2>;
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enable-method = "psci";
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@@ -32,7 +32,7 @@ cpu1: cpu@1 {
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a35";
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- clocks = <&clk NPCM8XX_CLK_CPU>;
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+ clocks = <&rstc NPCM8XX_CLK_CPU>;
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reg = <0x0 0x2>;
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next-level-cache = <&l2>;
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enable-method = "psci";
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@@ -41,7 +41,7 @@ cpu2: cpu@2 {
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a35";
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- clocks = <&clk NPCM8XX_CLK_CPU>;
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+ clocks = <&rstc NPCM8XX_CLK_CPU>;
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reg = <0x0 0x3>;
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next-level-cache = <&l2>;
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enable-method = "psci";
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--
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2.34.1
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‎meta-facebook/meta-yosemite4/meta-yosemite4n/recipes-kernel/linux/linux-nuvoton/1002-arm64-dts-npmc8xx-move-the-clk-handler-node-to-the-r.patch

+44
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From d197b1fdad05c195a1f40c4575d9b9b802e7ced1 Mon Sep 17 00:00:00 2001
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From: Tomer Maimon <[email protected]>
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Date: Mon, 1 Jul 2024 10:10:45 +0300
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Subject: [PATCH] arm64: dts: npmc8xx: move the clk handler node to the reset
5+
node
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Add clk handler node to the reset node and removing the clock node
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driver since the reset driver is register the NPCM8xx clock controller
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aux device.
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We will push this change upstream for reviewing soon.
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Signed-off-by: Tomer Maimon <[email protected]>
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---
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arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi | 7 +------
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1 file changed, 1 insertion(+), 6 deletions(-)
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diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
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index 92e3b0fe746f..01daf0615ccc 100644
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--- a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
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+++ b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
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@@ -47,18 +47,13 @@ ahb {
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interrupt-parent = <&gic>;
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ranges;
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- rstc: reset-controller@f0801000 {
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+ clk: rstc: reset-controller@f0801000 {
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compatible = "nuvoton,npcm845-reset";
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reg = <0x0 0xf0801000 0x0 0x78>;
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#reset-cells = <2>;
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nuvoton,sysgcr = <&gcr>;
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clocks = <&refclk>;
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- };
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-
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- clk: clock-controller@f0801000 {
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- compatible = "nuvoton,npcm845-clk";
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#clock-cells = <1>;
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- reg = <0x0 0xf0801000 0x0 0x1000>;
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};
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apb {
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--
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2.34.1
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