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yosemite4: Initial commit for meta-yosemite4n
Summary: - Add the meta-yosemite4n layer for Nuvoton management board. This is a Linux Foundation-based machine and already upstream. - Add a u-boot patch for factory memory testing purpose. - Add kernel driver patches that are still under upstream review. - cpld-fw-handler: enable the update-ebr-init Test Plan: bitbake yosemite4n-image - Build Pass Signed-off-by: Joseph Liu <[email protected]> Signed-off-by: Marvin Lin <[email protected]>
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‎meta-facebook/meta-yosemite4/meta-yosemite4n/conf/layer.conf

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# We have a conf and classes directory, add to BBPATH
2+
BBPATH .= ":${LAYERDIR}"
3+
4+
# We have recipes-* directories, add to BBFILES
5+
BBFILES += "${LAYERDIR}/recipes-*/*/*.bb \
6+
${LAYERDIR}/recipes-*/*/*.bbappend"
7+
8+
# Ignore bbappend related to ASPEED in meta-yosemite4
9+
BBMASK += ".*aspeed.*\.bbappend"
10+
11+
BBFILE_COLLECTIONS += "fb-yosemite4n-layer"
12+
BBFILE_PATTERN_fb-yosemite4n-layer := "^${LAYERDIR}/"
13+
LAYERVERSION_fb-yosemite4n-layer = "1"
14+
LAYERSERIES_COMPAT_fb-yosemite4n-layer = "scarthgap nanbield kirkstone"

‎meta-facebook/meta-yosemite4/meta-yosemite4n/conf/machine/yosemite4n.conf

Whitespace-only changes.

‎meta-facebook/meta-yosemite4/meta-yosemite4n/conf/templates/default/bblayers.conf.sample

+25
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# LAYER_CONF_VERSION is increased each time build/conf/bblayers.conf
2+
# changes incompatibly
3+
LCONF_VERSION = "8"
4+
5+
BBPATH = "${TOPDIR}"
6+
BBFILES ?= ""
7+
8+
BBLAYERS ?= " \
9+
##OEROOT##/meta \
10+
##OEROOT##/meta-openembedded/meta-oe \
11+
##OEROOT##/meta-openembedded/meta-networking \
12+
##OEROOT##/meta-openembedded/meta-python \
13+
##OEROOT##/meta-security/meta-tpm \
14+
##OEROOT##/meta-phosphor \
15+
##OEROOT##/meta-arm/meta-arm \
16+
##OEROOT##/meta-arm/meta-arm-toolchain \
17+
##OEROOT##/meta-nuvoton \
18+
##OEROOT##/meta-facebook \
19+
##OEROOT##/meta-facebook/meta-yosemite4 \
20+
##OEROOT##/meta-facebook/meta-yosemite4/meta-yosemite4n \
21+
##OEROOT##/../.. \
22+
##OEROOT##/../../meta-facebook \
23+
##OEROOT##/../../meta-facebook/meta-yosemite4 \
24+
##OEROOT##/../../meta-facebook/meta-yosemite4/meta-yosemite4n \
25+
"

‎meta-facebook/meta-yosemite4/meta-yosemite4n/conf/templates/default/conf-notes.txt

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1+
Common targets are:
2+
yosemite4n-image

‎meta-facebook/meta-yosemite4/meta-yosemite4n/conf/templates/default/local.conf.sample

+5
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#
2+
# Local configuration file for building the OpenBMC image.
3+
#
4+
MACHINE ??= "yosemite4n"
5+
DISTRO ?= "openbmc-fb-lf"

‎meta-facebook/meta-yosemite4/meta-yosemite4n/recipes-bsp/u-boot/u-boot-nuvoton/0003-cmd-mem-set-test-result-of-mtest-to-enviroment-varia.patch

+46
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1+
From fd6c1631c9075161df703e7928063f4acf498113 Mon Sep 17 00:00:00 2001
2+
From: RickyWu-wiwynn <[email protected]>
3+
Date: Mon, 8 Apr 2024 18:07:34 +0800
4+
Subject: [PATCH] cmd: mem: set test result of mtest to enviroment variable
5+
6+
---
7+
cmd/mem.c | 16 ++++++++++++++++
8+
1 file changed, 16 insertions(+)
9+
10+
diff --git a/cmd/mem.c b/cmd/mem.c
11+
index 5f4e865462..4dee413fea 100644
12+
--- a/cmd/mem.c
13+
+++ b/cmd/mem.c
14+
@@ -1204,6 +1204,15 @@ static ulong mem_test_quick(vu_long *buf, ulong start_addr, ulong end_addr,
15+
static int do_mem_mtest(struct cmd_tbl *cmdtp, int flag, int argc,
16+
char *const argv[])
17+
{
18+
+ char *is_done;
19+
+ is_done = env_get("memtest_result");
20+
+ if (is_done != NULL) {
21+
+ env_set("memtest_result", "");
22+
+ env_set("preboot", "");
23+
+ env_save();
24+
+ return 0;
25+
+ }
26+
+
27+
ulong start, end;
28+
vu_long scratch_space;
29+
vu_long *buf, *dummy = &scratch_space;
30+
@@ -1273,6 +1282,13 @@ static int do_mem_mtest(struct cmd_tbl *cmdtp, int flag, int argc,
31+
32+
printf("\nTested %d iteration(s) with %lu errors.\n", iteration, count);
33+
34+
+ if (errs == 0) {
35+
+ env_set("memtest_result", "pass");
36+
+ } else {
37+
+ env_set("memtest_result", "fail");
38+
+ }
39+
+ env_save();
40+
+
41+
return errs != 0;
42+
}
43+
#endif /* CONFIG_CMD_MEMTEST */
44+
--
45+
2.25.1
46+

‎meta-facebook/meta-yosemite4/meta-yosemite4n/recipes-bsp/u-boot/u-boot-nuvoton_%bbappend

+4
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FILESEXTRAPATHS:prepend := "${THISDIR}/${PN}:"
2+
3+
SRC_URI:append = " file://0003-cmd-mem-set-test-result-of-mtest-to-enviroment-varia.patch"
4+

‎meta-facebook/meta-yosemite4/meta-yosemite4n/recipes-core/images/yosemite4n-image.bb

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1+
require recipes-core/images/yosemite4-image.bb
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3+
IMAGE_INSTALL:remove = " packagegroup-openbmc-tests2"

‎meta-facebook/meta-yosemite4/meta-yosemite4n/recipes-facebook/cpld-fw-handler/cpld-fw-handler_%.bbappend

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EXTRA_OEMESON:append = " -Dupdate-ebr-init=enabled"
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‎meta-facebook/meta-yosemite4/meta-yosemite4n/recipes-kernel/linux/linux-nuvoton/1000-dt-bindings-clock-npcm845-Add-reference-25m-clock-pr.patch

+89
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From 9f903328f2169a1d058418a2e49cbe164584b9d9 Mon Sep 17 00:00:00 2001
2+
From: Tomer Maimon <[email protected]>
3+
Date: Mon, 1 Jul 2024 10:10:44 +0300
4+
Subject: [PATCH] dt-bindings: clock: npcm845: Add reference 25m clock property
5+
6+
The NPCM8XX clock driver uses a 25Mhz external clock, therefore adding
7+
clock property.
8+
9+
The new required clock property does not break the NPCM8XX clock ABI
10+
since the NPCM8XX clock driver hasn't merged yet to the Linux vanilla.
11+
12+
This change is also contributing to lf-openbmc upstream for reviewing.
13+
Lore Link: https://lore.kernel.org/all/[email protected]/
14+
15+
Signed-off-by: Tomer Maimon <[email protected]>
16+
---
17+
arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi | 9 +++++----
18+
arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts | 7 +++++++
19+
2 files changed, 12 insertions(+), 4 deletions(-)
20+
21+
diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
22+
index ecd171b2feba..41d345448430 100644
23+
--- a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
24+
+++ b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
25+
@@ -52,6 +52,7 @@ rstc: reset-controller@f0801000 {
26+
reg = <0x0 0xf0801000 0x0 0x78>;
27+
#reset-cells = <2>;
28+
nuvoton,sysgcr = <&gcr>;
29+
+ clocks = <&refclk>;
30+
};
31+
32+
clk: clock-controller@f0801000 {
33+
@@ -81,7 +82,7 @@ timer0: timer@8000 {
34+
compatible = "nuvoton,npcm845-timer";
35+
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
36+
reg = <0x8000 0x1C>;
37+
- clocks = <&clk NPCM8XX_CLK_REFCLK>;
38+
+ clocks = <&refclk>;
39+
clock-names = "refclk";
40+
};
41+
42+
@@ -153,7 +154,7 @@ watchdog0: watchdog@801c {
43+
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
44+
reg = <0x801c 0x4>;
45+
status = "disabled";
46+
- clocks = <&clk NPCM8XX_CLK_REFCLK>;
47+
+ clocks = <&refclk>;
48+
syscon = <&gcr>;
49+
};
50+
51+
@@ -162,7 +163,7 @@ watchdog1: watchdog@901c {
52+
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
53+
reg = <0x901c 0x4>;
54+
status = "disabled";
55+
- clocks = <&clk NPCM8XX_CLK_REFCLK>;
56+
+ clocks = <&refclk>;
57+
syscon = <&gcr>;
58+
};
59+
60+
@@ -171,7 +172,7 @@ watchdog2: watchdog@a01c {
61+
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
62+
reg = <0xa01c 0x4>;
63+
status = "disabled";
64+
- clocks = <&clk NPCM8XX_CLK_REFCLK>;
65+
+ clocks = <&refclk>;
66+
syscon = <&gcr>;
67+
};
68+
};
69+
diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts
70+
index a5ab2bc0f835..83c2f4e138e5 100644
71+
--- a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts
72+
+++ b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts
73+
@@ -19,6 +19,13 @@ chosen {
74+
memory {
75+
reg = <0x0 0x0 0x0 0x40000000>;
76+
};
77+
+
78+
+ refclk: refclk-25mhz {
79+
+ compatible = "fixed-clock";
80+
+ clock-output-names = "ref";
81+
+ clock-frequency = <25000000>;
82+
+ #clock-cells = <0>;
83+
+ };
84+
};
85+
86+
&serial0 {
87+
--
88+
2.34.1
89+

‎meta-facebook/meta-yosemite4/meta-yosemite4n/recipes-kernel/linux/linux-nuvoton/1001-arm64-dts-modify-clock-property-in-modules-node.patch

+136
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@@ -0,0 +1,136 @@
1+
From 7ada4b7e39819f2cc765b27f3fc1ad38ece3278f Mon Sep 17 00:00:00 2001
2+
From: Tomer Maimon <[email protected]>
3+
Date: Mon, 1 Jul 2024 10:10:46 +0300
4+
Subject: [PATCH] arm64: dts: modify clock property in modules node
5+
6+
Modify clock property handler in UART, CPU, PECI modules to reset
7+
controller.
8+
9+
This change is also contributing to lf-openbmc upstream for reviewing.
10+
Lore Link: https://lore.kernel.org/all/[email protected]/
11+
12+
Signed-off-by: Tomer Maimon <[email protected]>
13+
---
14+
.../boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi | 16 ++++++++--------
15+
arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi | 8 ++++----
16+
2 files changed, 12 insertions(+), 12 deletions(-)
17+
18+
diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
19+
index 41d345448430..92e3b0fe746f 100644
20+
--- a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
21+
+++ b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
22+
@@ -73,7 +73,7 @@ peci: peci-controller@100000 {
23+
compatible = "nuvoton,npcm845-peci";
24+
reg = <0x100000 0x1000>;
25+
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
26+
- clocks = <&clk NPCM8XX_CLK_APB3>;
27+
+ clocks = <&rstc NPCM8XX_CLK_APB3>;
28+
cmd-timeout-ms = <1000>;
29+
status = "disabled";
30+
};
31+
@@ -89,7 +89,7 @@ timer0: timer@8000 {
32+
serial0: serial@0 {
33+
compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
34+
reg = <0x0 0x1000>;
35+
- clocks = <&clk NPCM8XX_CLK_UART>;
36+
+ clocks = <&rstc NPCM8XX_CLK_UART>;
37+
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
38+
reg-shift = <2>;
39+
status = "disabled";
40+
@@ -98,7 +98,7 @@ serial0: serial@0 {
41+
serial1: serial@1000 {
42+
compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
43+
reg = <0x1000 0x1000>;
44+
- clocks = <&clk NPCM8XX_CLK_UART>;
45+
+ clocks = <&rstc NPCM8XX_CLK_UART>;
46+
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
47+
reg-shift = <2>;
48+
status = "disabled";
49+
@@ -107,7 +107,7 @@ serial1: serial@1000 {
50+
serial2: serial@2000 {
51+
compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
52+
reg = <0x2000 0x1000>;
53+
- clocks = <&clk NPCM8XX_CLK_UART>;
54+
+ clocks = <&rstc NPCM8XX_CLK_UART>;
55+
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
56+
reg-shift = <2>;
57+
status = "disabled";
58+
@@ -116,7 +116,7 @@ serial2: serial@2000 {
59+
serial3: serial@3000 {
60+
compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
61+
reg = <0x3000 0x1000>;
62+
- clocks = <&clk NPCM8XX_CLK_UART>;
63+
+ clocks = <&rstc NPCM8XX_CLK_UART>;
64+
interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
65+
reg-shift = <2>;
66+
status = "disabled";
67+
@@ -125,7 +125,7 @@ serial3: serial@3000 {
68+
serial4: serial@4000 {
69+
compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
70+
reg = <0x4000 0x1000>;
71+
- clocks = <&clk NPCM8XX_CLK_UART>;
72+
+ clocks = <&rstc NPCM8XX_CLK_UART>;
73+
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
74+
reg-shift = <2>;
75+
status = "disabled";
76+
@@ -134,7 +134,7 @@ serial4: serial@4000 {
77+
serial5: serial@5000 {
78+
compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
79+
reg = <0x5000 0x1000>;
80+
- clocks = <&clk NPCM8XX_CLK_UART>;
81+
+ clocks = <&rstc NPCM8XX_CLK_UART>;
82+
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
83+
reg-shift = <2>;
84+
status = "disabled";
85+
@@ -143,7 +143,7 @@ serial5: serial@5000 {
86+
serial6: serial@6000 {
87+
compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
88+
reg = <0x6000 0x1000>;
89+
- clocks = <&clk NPCM8XX_CLK_UART>;
90+
+ clocks = <&rstc NPCM8XX_CLK_UART2>;
91+
interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
92+
reg-shift = <2>;
93+
status = "disabled";
94+
diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi
95+
index 383938dcd3ce..3cbcea65eba2 100644
96+
--- a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi
97+
+++ b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi
98+
@@ -14,7 +14,7 @@ cpus {
99+
cpu0: cpu@0 {
100+
device_type = "cpu";
101+
compatible = "arm,cortex-a35";
102+
- clocks = <&clk NPCM8XX_CLK_CPU>;
103+
+ clocks = <&rstc NPCM8XX_CLK_CPU>;
104+
reg = <0x0 0x0>;
105+
next-level-cache = <&l2>;
106+
enable-method = "psci";
107+
@@ -23,7 +23,7 @@ cpu0: cpu@0 {
108+
cpu1: cpu@1 {
109+
device_type = "cpu";
110+
compatible = "arm,cortex-a35";
111+
- clocks = <&clk NPCM8XX_CLK_CPU>;
112+
+ clocks = <&rstc NPCM8XX_CLK_CPU>;
113+
reg = <0x0 0x1>;
114+
next-level-cache = <&l2>;
115+
enable-method = "psci";
116+
@@ -32,7 +32,7 @@ cpu1: cpu@1 {
117+
cpu2: cpu@2 {
118+
device_type = "cpu";
119+
compatible = "arm,cortex-a35";
120+
- clocks = <&clk NPCM8XX_CLK_CPU>;
121+
+ clocks = <&rstc NPCM8XX_CLK_CPU>;
122+
reg = <0x0 0x2>;
123+
next-level-cache = <&l2>;
124+
enable-method = "psci";
125+
@@ -41,7 +41,7 @@ cpu2: cpu@2 {
126+
cpu3: cpu@3 {
127+
device_type = "cpu";
128+
compatible = "arm,cortex-a35";
129+
- clocks = <&clk NPCM8XX_CLK_CPU>;
130+
+ clocks = <&rstc NPCM8XX_CLK_CPU>;
131+
reg = <0x0 0x3>;
132+
next-level-cache = <&l2>;
133+
enable-method = "psci";
134+
--
135+
2.34.1
136+

‎meta-facebook/meta-yosemite4/meta-yosemite4n/recipes-kernel/linux/linux-nuvoton/1002-arm64-dts-npmc8xx-move-the-clk-handler-node-to-the-r.patch

+44
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@@ -0,0 +1,44 @@
1+
From d197b1fdad05c195a1f40c4575d9b9b802e7ced1 Mon Sep 17 00:00:00 2001
2+
From: Tomer Maimon <[email protected]>
3+
Date: Mon, 1 Jul 2024 10:10:45 +0300
4+
Subject: [PATCH] arm64: dts: npmc8xx: move the clk handler node to the reset
5+
node
6+
7+
Add clk handler node to the reset node and removing the clock node
8+
driver since the reset driver is register the NPCM8xx clock controller
9+
aux device.
10+
11+
We will contribute to lf-openbmc upstream for reviewing.
12+
13+
Signed-off-by: Tomer Maimon <[email protected]>
14+
---
15+
arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi | 7 +------
16+
1 file changed, 1 insertion(+), 6 deletions(-)
17+
18+
diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
19+
index 92e3b0fe746f..01daf0615ccc 100644
20+
--- a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
21+
+++ b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
22+
@@ -47,18 +47,13 @@ ahb {
23+
interrupt-parent = <&gic>;
24+
ranges;
25+
26+
- rstc: reset-controller@f0801000 {
27+
+ clk: rstc: reset-controller@f0801000 {
28+
compatible = "nuvoton,npcm845-reset";
29+
reg = <0x0 0xf0801000 0x0 0x78>;
30+
#reset-cells = <2>;
31+
nuvoton,sysgcr = <&gcr>;
32+
clocks = <&refclk>;
33+
- };
34+
-
35+
- clk: clock-controller@f0801000 {
36+
- compatible = "nuvoton,npcm845-clk";
37+
#clock-cells = <1>;
38+
- reg = <0x0 0xf0801000 0x0 0x1000>;
39+
};
40+
41+
apb {
42+
--
43+
2.34.1
44+

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