Add a LoadPair LIR instruction

Summary:
Adds `kLoadPair`, the load-side counterpart to the existing `kStorePair`, so
adjacent 64-bit loads can be emitted as a single `ldp`. It takes the same
(offset, base) shape as `kStorePair`, with the first destination as the output
and the second as an extra input. On x86 it lowers to two `mov`s.

The first user is `PopulateEntryBlock`, which loads the vectorcall arguments
from consecutive slots of the argument array on every JIT function entry:

```
mov x10, x1              mov x10, x1
ldr x1, [x10]            ldp x1, x2, [x10]
ldr x2, [x10, #8]    ->  ldp x3, x4, [x10, #0x10]
ldr x3, [x10, #0x10]     ldp x5, x6, [x10, #0x20]
ldr x4, [x10, #0x18]
ldr x5, [x10, #0x20]
ldr x6, [x10, #0x28]
```

One important caveat about this - we have no support for instructions w/ multiple outputs. So this instruction is only available after register allocation where we've previously allocated the output register as part of a load instruction. The current usage runs after register allocation and the next diff adds a post-alloc pass as well.

Pairing is limited to aarch64 so x86 output is unchanged.

Reviewed By: alexmalyshev

Differential Revision: D114969843

fbshipit-source-id: 6f77f125a67b19201aac2d52dbcace9fc8bc3837

Author: DinoV

cinderx/Jit/codegen/autogen.cpp

@@ -1527,6 +1527,35 @@ void translateStorePair(Environ* env, const Instruction* instr) {
 #endif
 }
 
+void translateLoadPair(Environ* env, const Instruction* instr) {
+  arch::Builder* as = env->as;
+  JIT_DCHECK(
+      instr->getNumInputs() == 3,
+      "LoadPair expects exactly 3 inputs (offset, base, dst1)");
+  int32_t offset = static_cast<int32_t>(instr->getInput(0)->getConstant());
+  auto base_reg = instr->getInput(1)->getPhyRegister();
+  auto dst0_loc = instr->output()->getPhyRegister();
+  auto dst1_loc = instr->getInput(2)->getPhyRegister();
+
+#if defined(CINDER_X86_64)
+  auto base = x86::gpq(base_reg.loc);
+  as->mov(x86::gpq(dst0_loc.loc), x86::qword_ptr(base, offset));
+  as->mov(x86::gpq(dst1_loc.loc), x86::qword_ptr(base, offset + kPointerSize));
+#elif defined(CINDER_AARCH64)
+  auto dst0 = a64::x(dst0_loc.loc);
+  auto dst1 = a64::x(dst1_loc.loc);
+
+  if (auto ptr = getPairPtr(env, base_reg, offset)) {
+    as->ldp(dst0, dst1, *ptr);
+  } else {
+    as->ldr(dst0, getPairElementPtr(env, base_reg, offset));
+    as->ldr(dst1, getPairElementPtr(env, base_reg, offset + kPointerSize));
+  }
+#else
+  CINDER_UNSUPPORTED
+#endif
+}
+
 // Tear down the frame. On x86, this executes 'leave' (mov rsp, rbp; pop rbp).
 // On aarch64, this restores sp from fp and pops the frame record (fp + lr).
 //
@@ -3225,6 +3254,9 @@ void AutoTranslator::translateInstr(Environ* env, const Instruction* instr)
     case Instruction::kStorePair:
       translateStorePair(env, instr);
       return;
+    case Instruction::kLoadPair:
+      translateLoadPair(env, instr);
+      return;
     case Instruction::kLeave:
       translateLeave(env);
       return;
@@ -3503,6 +3535,9 @@ void AutoTranslator::translateInstr(Environ* env, const Instruction* instr)
     case Instruction::kStorePair:
       translateStorePair(env, instr);
       return;
+    case Instruction::kLoadPair:
+      translateLoadPair(env, instr);
+      return;
     case Instruction::kLeave:
       translateLeave(env);
       return;

cinderx/Jit/lir/generator.cpp

@@ -586,28 +586,79 @@ void PopulateEntryBlock(
   auto kPointerSize = static_cast<int32_t>(sizeof(void*));
 
   bool has_extra_args = false;
+
+  // Consecutive general-purpose arguments live in adjacent slots, so they can
+  // be loaded a pair at a time. This block is built after the post-allocation
+  // pairing pass has run, so the pairs are formed here instead. A double
+  // argument, a gap left by an overflow argument, or a destination that would
+  // clobber the array pointer ends the run.
+#if defined(CINDER_AARCH64)
+  constexpr bool kCanPairArgLoads = true;
+#else
+  constexpr bool kCanPairArgLoads = false;
+#endif
+
+  std::optional<std::pair<int32_t, PhyLocation>> pending;
+  auto flushPending = [&]() {
+    if (!pending.has_value()) {
+      return;
+    }
+    entry_block->allocateInstr(
+        Instruction::kMove,
+        nullptr,
+        OutPhyReg(pending->second),
+        Ind(args_reg, pending->first));
+    pending.reset();
+  };
+
   for (size_t i = 0; i < arg_locations.size(); i++) {
     PhyLocation arg = arg_locations[i];
     if (arg == PhyLocation::REG_INVALID) {
       has_extra_args = true;
+      flushPending();
       continue;
     }
-    if (arg.isGpRegister()) {
+
+    auto offset = static_cast<int32_t>(i * kPointerSize);
+
+    if (!arg.isGpRegister()) {
+      flushPending();
       entry_block->allocateInstr(
           Instruction::kMove,
           nullptr,
-          OutPhyReg(arg),
-          Ind(args_reg, static_cast<int32_t>(i * kPointerSize)));
-    } else {
+          OutPhyReg(arg, Operand::kDouble),
+          Ind(args_reg, offset, Operand::kDouble));
+      continue;
+    }
+
+    // ldp with a destination that is also its base is unpredictable, and any
+    // following load would be reading through a clobbered pointer anyway.
+    if (arg == args_reg) {
+      flushPending();
       entry_block->allocateInstr(
-          Instruction::kMove,
+          Instruction::kMove, nullptr, OutPhyReg(arg), Ind(args_reg, offset));
+      continue;
+    }
+
+    if (kCanPairArgLoads && pending.has_value() && pending->second != arg) {
+      JIT_DCHECK(
+          offset == pending->first + kPointerSize,
+          "pending arg load should be for the preceding slot");
+      entry_block->allocateInstr(
+          Instruction::kLoadPair,
           nullptr,
-          OutPhyReg(arg, Operand::kDouble),
-          Ind(args_reg,
-              static_cast<int32_t>(i * kPointerSize),
-              Operand::kDouble));
+          OutPhyReg(pending->second),
+          Imm{static_cast<uint64_t>(pending->first)},
+          PhyReg{args_reg},
+          PhyReg{arg});
+      pending.reset();
+      continue;
     }
+
+    flushPending();
+    pending = std::make_pair(offset, arg);
   }
+  flushPending();
   if (has_extra_args) {
     // Point extra_args register past the register-bound args to the
     // start of the overflow args in the vectorcall array.

cinderx/Jit/lir/instruction.h

@@ -153,6 +153,7 @@ enum OperandSizeType {
   X(SetupFrame, false, FlagEffects::kInvalidate, kDefault, 0, {}, 1)          \
   X(VariadicPush, false, FlagEffects::kNone, kDefault, 0, {}, 1)              \
   X(StorePair, false, FlagEffects::kNone, kDefault, 0, {0, 1, 1, 1}, 1)       \
+  X(LoadPair, false, FlagEffects::kNone, kDefault, 1, {0, 1, 1}, 1)           \
   X(Leave, false, FlagEffects::kInvalidate, kDefault, 0, {}, 1)               \
   X(Ret, false, FlagEffects::kInvalidate, kDefault, 0, {}, 1)                 \
   X(CmpBranchZero, false, FlagEffects::kNone, kDefault, 0, {1}, 1)            \

cinderx/Jit/lir/linear_scan.cpp

@@ -469,6 +469,9 @@ void LinearScanAllocator::calculateLiveIntervals() {
         continue;
       }
 
+      JIT_DCHECK(
+          instr_opcode != Instruction::kLoadPair,
+          "load pair can only be generated after register allocation");
       // output
       auto output_opnd = instr->output();
       if (output_opnd->isVreg()) {

cinderx/Jit/lir/postalloc.cpp

@@ -1151,6 +1151,7 @@ RewriteResult rewriteMemoryInputsToReg(instr_iter_t instr_iter) {
     case Instruction::kReserveStack:
     case Instruction::kVariadicPush:
     case Instruction::kStorePair:
+    case Instruction::kLoadPair:
     case Instruction::kLeave:
     case Instruction::kRet:
     case Instruction::kCmpBranchZero:

cinderx/Jit/lir/spill_alloc.cpp

@@ -174,6 +174,10 @@ void SpillAllocator::rewriteInstr(BasicBlock* block, instr_iter_t iter) {
     return;
   }
 
+  JIT_DCHECK(
+      !instr->isLoadPair(),
+      "load pair can only be generated after register allocation");
+
   // Generator frame migration: a Move into the frame-pointer register swaps the
   // frame pointer between the machine stack and the heap-allocated generator
   // data.  Handle values that must cross the switch, then fall through so the