Fix FP register encoding and stack alignment in codegen

Summary:
Fix two AArch64 code generation bugs:

1. In generatePrologue, FP argument loading used a64::d(arg.loc) directly, but arg.loc includes the VECD_REG_BASE offset (e.g., 32 for D0). This produced invalid register IDs like d32 instead of d0. Fix by subtracting VECD_REG_BASE, consistent with all other FP register construction in the codebase.

2. In rewriteRegularFunction, the stack argument buffer size was not aligned to kStackAlign (16 bytes). When a regular function call had an odd number of stack-spilled arguments, the unaligned size triggered an assertion failure in generatePrologue on AArch64 where the stack pointer must always be 16-byte aligned. Fix by rounding up the buffer size, consistent with prepareArgsArray which already does this for vectorcall paths.

Reviewed By: kddnewton

Differential Revision: D93875144

fbshipit-source-id: 9454441b7941572f98f318a43ba508803f318885

Author: DinoV

cinderx/Jit/codegen/gen_asm.cpp

@@ -1694,7 +1694,7 @@ void NativeGenerator::generatePrologue(
               as_, kArgsReg, i * sizeof(void*), arch::reg_scratch_0));
     } else {
       as_->ldr(
-          a64::d(arg.loc),
+          a64::d(arg.loc - VECD_REG_BASE),
           arch::ptr_resolve(
               as_, kArgsReg, i * sizeof(void*), arch::reg_scratch_0));
     }

cinderx/Jit/lir/postalloc.cpp

@@ -147,6 +147,10 @@ int rewriteRegularFunction(instr_iter_t instr_iter) {
     }
   }
 
+  // Align to kStackAlign for AArch64 stack pointer alignment requirements.
+  if (stack_arg_size % kStackAlign != 0) {
+    stack_arg_size += kStackAlign - (stack_arg_size % kStackAlign);
+  }
   return stack_arg_size;
 }