Keep 32 -> 64 bit zero-extends as MovZX in LIR

Summary:
`PostRegAllocRewrite` used to rewrite a 32 -> 64 bit `Zext` into a
32-bit `Move`, because that is how x86-64 spells the zero-extend, there
is no `movzx r64, r/m32`.  Doing that in LIR means the opcode no longer
says what the instruction is for, and it needs the output operand to be
narrowed to 32 bits, which then disagrees with the value the instruction
actually produces.

Leave it as a `MovZX` and let codegen pick the encoding, matching how
`MovSX` now handles the same width.

Reviewed By: yoney

Differential Revision: D116029617

fbshipit-source-id: 28f21003d34d9c497ed3f3434d549d3d87b5390e

Author: alexmalyshev

cinderx/Jit/codegen/autogen.cpp

@@ -2576,6 +2576,27 @@ void AutoTranslator::translateInstr(Environ* env, const Instruction* instr)
       auto* output = instr->output();
       auto* input = instr->getInput(0);
 
+      // x86-64 has no `movzx r64, r/m32`; writing a 32-bit register already
+      // zeroes the upper half of its 64-bit counterpart, so a plain MOV between
+      // the 32-bit halves is the zero-extend.  This stays a MOV even when the
+      // source and destination registers are the same, as the upper half is not
+      // known to be clear.
+      if (input->sizeInBits() == 32) {
+        JIT_THROW_IF(
+            output->sizeInBits() != 64,
+            "Zero-extend from 32-bits should always go to 64-bits, got '{}' "
+            "instead",
+            *instr);
+
+        auto output_reg = asmjit::x86::gpd(output->getPhyRegister().loc);
+        if (input->isReg()) {
+          env->as->mov(output_reg, getReg(instr, input));
+        } else {
+          env->as->mov(output_reg, getMem(instr, input));
+        }
+        return;
+      }
+
       if (input->isReg()) {
         env->as->movzx(getReg(instr, output), getReg(instr, input));
       } else {

cinderx/Jit/lir/postalloc.cpp

@@ -562,17 +562,8 @@ RewriteResult rewriteBitExtensionInstrs(instr_iter_t instr_iter) {
   switch (in_size) {
     case Operand::k8bit:
     case Operand::k16bit:
-      instr->setOpcode(is_sext ? Opcode::kMovSX : Opcode::kMovZX);
-      break;
     case Operand::k32bit:
-      if (is_sext) {
-        instr->setOpcode(Opcode::kMovSX);
-      } else {
-        // must be unsigned extension from 32 bits to 64 bits.
-        // in this case, a 32-bit move will do the work.
-        instr->setOpcode(Opcode::kMove);
-        instr->output()->setDataType(lir::Operand::k32bit);
-      }
+      instr->setOpcode(is_sext ? Opcode::kMovSX : Opcode::kMovZX);
       break;
     case Operand::k64bit:
     case Operand::kObject:

cinderx/RuntimeTests/backend_test.cpp

@@ -1451,9 +1451,9 @@ BB %1
   }
 }
 
-// Sign-extending 32 bits to 64 has to fill the upper half of the destination
-// with the sign bit.  x86-64 spells that `movsxd` rather than the `movsx` used
-// for narrower widths, so it gets its own codegen path.
+// Widening 32 bits to 64 has to reach the upper half of the destination: Zext
+// must clear it and Sext must fill it with the sign bit.  Neither lowers to the
+// movzx/movsx that the narrower widths use, so both get their own codegen path.
 TEST_F(BackendTest, Extend32BitsTo64Bits) {
   auto compile = [this](Opcode extend) {
     auto lirfunc = std::make_unique<Function>();
@@ -1480,6 +1480,11 @@ TEST_F(BackendTest, Extend32BitsTo64Bits) {
         SimpleCompile(lirfunc.get()));
   };
 
+  auto zext = compile(Opcode::kZext);
+  ASSERT_NE(zext, nullptr);
+  EXPECT_EQ(zext(0xDEADBEEFCAFEBABEULL), 0x00000000CAFEBABEULL);
+  EXPECT_EQ(zext(0xDEADBEEF0000002AULL), 0x000000000000002AULL);
+
   auto sext = compile(Opcode::kSext);
   ASSERT_NE(sext, nullptr);
   EXPECT_EQ(sext(0xDEADBEEFCAFEBABEULL), 0xFFFFFFFFCAFEBABEULL);