Use kObject for address loads in rewriteMoveAbsoluteAddress

Summary: The `rewriteMoveAbsoluteAddress` postgen pass on AArch64 lowers absolute memory address operands into a two-instruction sequence: first loading the address into a virtual register, then using an indirect load through that register. Previously the intermediate `Move(Imm → vreg)` used `DataType::k64bit`, which meant the branch relaxation pass did not recognize it as a pointer-width operand and could not select optimal instruction sequences (e.g. `adr`/`adrp+add`/`ldr` instead of `movz+movk` chains). Changing to `DataType::kObject` allows the value to flow through branch relaxation correctly, since the relaxation pass keys on the data type to determine whether an immediate load is a candidate for address-relative encoding.

Reviewed By: alexmalyshev

Differential Revision: D103072904

fbshipit-source-id: cb00a2fecccfe8adee41ece6294d2b770793de56

Author: kddnewton

cinderx/Jit/lir/postgen.cpp

@@ -697,8 +697,8 @@ RewriteResult rewriteMoveAbsoluteAddress(instr_iter_t instr_iter) {
   auto addr_move = block->allocateInstrBefore(
       instr_iter,
       Instruction::kMove,
-      OutVReg{DataType::k64bit},
-      Imm{addr, DataType::k64bit});
+      OutVReg{DataType::kObject},
+      Imm{addr, DataType::kObject});
 
   // Replace the Mem input with Ind{addr_vreg, offset=0}. For a simple
   // Ind with no index and offset 0, ptrIndirect resolves to ptr(base)

cinderx/RuntimeTests/lir_postgen_test.cpp

@@ -150,4 +150,24 @@ BB %6
   EXPECT_EQ(runPostGenRewrite(lir_input_str), expected_lir_str.c_str());
 }
 
+#if defined(CINDER_AARCH64)
+TEST_F(LIRPostGenerationRewriteTest, MoveAbsoluteAddressUsesObjectDataType) {
+  const char* lir_input_str = R"(Function:
+BB %0
+  %10:Object = Move [0x12345]
+  Return %10
+)";
+
+  const char* expected_lir_str = R"(Function:
+BB %0
+      %12:Object = Move 74565(0x12345):Object
+      %10:Object = Move [%12:Object]:Object
+                   Return %10:Object
+
+)";
+
+  EXPECT_EQ(runPostGenRewrite(lir_input_str), expected_lir_str);
+}
+#endif
+
 } // namespace jit::lir